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authorMichael Hennerich <michael.hennerich@analog.com>2010-02-19 15:09:10 +0000
committerMike Frysinger <vapier@gentoo.org>2010-03-09 00:30:52 -0500
commitaec59c911307639c77076bdc9d9b546a4a767a73 (patch)
tree84dea13756d7a2093322dc25f6e2efda2c10f169 /arch/blackfin/mach-bf537
parentb2740801457b2fbbe14812c0fda24bd689025886 (diff)
downloadlinux-2.6.34-ux500-aec59c911307639c77076bdc9d9b546a4a767a73.tar.gz
Blackfin: add support for the on-chip MAC status interrupts
This patch provides infrastructure for MAC Wake-On-Lan and PHYINT use in phylib. New Interrupts added: IRQ_MAC_PHYINT /* PHY_INT Interrupt */ IRQ_MAC_MMCINT /* MMC Counter Interrupt */ IRQ_MAC_RXFSINT /* RX Frame-Status Interrupt */ IRQ_MAC_TXFSINT /* TX Frame-Status Interrupt */ IRQ_MAC_WAKEDET /* Wake-Up Interrupt */ IRQ_MAC_RXDMAERR /* RX DMA Direction Error Interrupt */ IRQ_MAC_TXDMAERR /* TX DMA Direction Error Interrupt */ IRQ_MAC_STMDONE /* Station Mgt. Transfer Done Interrupt */ On BF537/6 the implementation is not straight forward since there are now two chained chained_handlers. A cleaner approach would have been to add latter IRQs to the demux of IRQ_GENERIC_ERROR. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf537')
-rw-r--r--arch/blackfin/mach-bf537/include/mach/irq.h11
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
index 9b2cbcac98e..789a4f226f7 100644
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -134,7 +134,16 @@
#define GPIO_IRQ_BASE IRQ_PF0
-#define NR_MACH_IRQS (IRQ_PH15 + 1)
+#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
+#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
+#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
+#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
+#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
+#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
+#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
+#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
+
+#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
#define IVG7 7