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authorMike Frysinger <michael.frysinger@analog.com>2007-06-11 15:31:30 +0800
committerBryan Wu <bryan.wu@analog.com>2007-06-11 15:31:30 +0800
commit83a5c3e3218f138b1a99f787c76e380d6a6ecec9 (patch)
treed71fb83fb0406af38d4e3266cb2d54dabb1bb3eb /arch/blackfin/mach-bf533/head.S
parent16983de0cec7b93cc2568f96909d4ea7c118bd8a (diff)
downloadlinux-2.6.34-ux500-83a5c3e3218f138b1a99f787c76e380d6a6ecec9.tar.gz
Blackfin arch: unify differences between our diff head.S files -- no functional changes
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-bf533/head.S')
-rw-r--r--arch/blackfin/mach-bf533/head.S17
1 files changed, 9 insertions, 8 deletions
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 4db9e624090..33d1f623fe4 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -51,13 +51,14 @@ ENTRY(__start)
ENTRY(__stext)
/* R0: argument of command line string, passed from uboot, save it */
R7 = R0;
- /* Set the SYSCFG register */
+ /* Set the SYSCFG register:
+ * Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
+ */
R0 = 0x36;
- /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
SYSCFG = R0;
R0 = 0;
- /*Clear Out All the data and pointer Registers*/
+ /* Clear Out All the data and pointer Registers */
R1 = R0;
R2 = R0;
R3 = R0;
@@ -79,7 +80,7 @@ ENTRY(__stext)
L2 = r0;
L3 = r0;
- /* Clear Out All the DAG Registers*/
+ /* Clear Out All the DAG Registers */
B0 = r0;
B1 = r0;
B2 = r0;
@@ -303,7 +304,7 @@ ENTRY(_real_start)
.L_clear_zero:
W[p1++] = r0;
-/* pass the uboot arguments to the global value command line */
+ /* pass the uboot arguments to the global value command line */
R0 = R7;
call _cmdline_init;
@@ -322,7 +323,7 @@ ENTRY(_real_start)
[p1] = r1;
/*
- * load the current thread pointer and stack
+ * load the current thread pointer and stack
*/
r1.l = _init_thread_union;
r1.h = _init_thread_union;
@@ -439,8 +440,8 @@ ENTRY(_start_dma_code)
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
- r0.l = lo(IWR_ENABLE_ALL)
- r0.h = hi(IWR_ENABLE_ALL)
+ r0.l = lo(IWR_ENABLE_ALL);
+ r0.h = hi(IWR_ENABLE_ALL);
[p0] = r0;
SSYNC;