diff options
| author | Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com> | 2010-07-07 12:55:45 +0200 |
|---|---|---|
| committer | John Rigby <john.rigby@linaro.org> | 2010-09-02 22:45:44 -0600 |
| commit | 2f4aed910f7ddec3c27b8a48f52ac4b437cf4b07 (patch) | |
| tree | 73e2943ae5c3070043c023c4dc64aa2bfd9f3204 /arch/arm | |
| parent | e3db021e2cacd8054092ce83259fb9e1b4458d3e (diff) | |
l2x0: take l2x0 updates from linux-next
Signed-off-by: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
Change-Id: I7c4a53e27ac2a43e244c17e812619529ce9fbc1e
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/2546
Reviewed-by: Jonas ABERG <jonas.aberg@stericsson.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/hardware/cache-l2x0.h | 3 | ||||
| -rw-r--r-- | arch/arm/mm/cache-l2x0.c | 47 |
2 files changed, 37 insertions, 13 deletions
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index cdb9022716f..6bcba48800f 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -21,6 +21,9 @@ #define __ASM_ARM_HARDWARE_L2X0_H #define L2X0_CACHE_ID 0x000 +#define L2X0_CACHE_ID_PART_MASK (0xf << 6) +#define L2X0_CACHE_ID_PART_L210 (1 << 6) +#define L2X0_CACHE_ID_PART_L310 (3 << 6) #define L2X0_CACHE_TYPE 0x004 #define L2X0_CTRL 0x100 #define L2X0_AUX_CTRL 0x104 diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 8740624a779..9819869d2bc 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -27,6 +27,7 @@ static void __iomem *l2x0_base; static DEFINE_SPINLOCK(l2x0_lock); +static uint32_t l2x0_way_mask; /* Bitmask of active ways */ static inline void cache_wait(void __iomem *reg, unsigned long mask) { @@ -108,8 +109,8 @@ static inline void l2x0_inv_all(void) /* invalidate all ways */ spin_lock_irqsave(&l2x0_lock, flags); - writel(0xff, l2x0_base + L2X0_INV_WAY); - cache_wait(l2x0_base + L2X0_INV_WAY, 0xff); + writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); + cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); cache_sync(); spin_unlock_irqrestore(&l2x0_lock, flags); } @@ -208,9 +209,37 @@ static void l2x0_flush_range(unsigned long start, unsigned long end) void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) { __u32 aux; + __u32 cache_id; + int ways; + const char *type; l2x0_base = base; + cache_id = readl(l2x0_base + L2X0_CACHE_ID); + aux = readl(l2x0_base + L2X0_AUX_CTRL); + + /* Determine the number of ways */ + switch (cache_id & L2X0_CACHE_ID_PART_MASK) { + case L2X0_CACHE_ID_PART_L310: + if (aux & (1 << 16)) + ways = 16; + else + ways = 8; + type = "L310"; + break; + case L2X0_CACHE_ID_PART_L210: + ways = (aux >> 13) & 0xf; + type = "L210"; + break; + default: + /* Assume unknown chips have 8 ways */ + ways = 8; + type = "L2x0 series"; + break; + } + + l2x0_way_mask = (1 << ways) - 1; + /* * Check if l2x0 controller is already enabled. * If you are booting from non-secure mode @@ -219,8 +248,6 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) if (!(readl(l2x0_base + L2X0_CTRL) & 1)) { /* l2x0 controller is disabled */ - - aux = readl(l2x0_base + L2X0_AUX_CTRL); aux &= aux_mask; aux |= aux_val; writel(aux, l2x0_base + L2X0_AUX_CTRL); @@ -229,14 +256,6 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) /* enable L2X0 */ writel(1, l2x0_base + L2X0_CTRL); - } else { - /* Unlock Data and Instruction Lock if locked */ - if (readl(l2x0_base + L2X0_LOCKDOWN_WAY_D) & 0xFF) { - writel(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D); - } - if (readl(l2x0_base + L2X0_LOCKDOWN_WAY_I) & 0xFF) { - writel(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I); - } } outer_cache.inv_range = l2x0_inv_range; @@ -244,5 +263,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) outer_cache.flush_range = l2x0_flush_range; outer_cache.sync = l2x0_cache_sync; - printk(KERN_INFO "L2X0 cache controller enabled\n"); + printk(KERN_INFO "%s cache controller enabled\n", type); + printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", + ways, cache_id, aux); } |