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authorAlexey Dobriyan <adobriyan@gmail.com>2006-02-01 03:06:19 -0800
committerLinus Torvalds <torvalds@g5.osdl.org>2006-02-01 08:53:21 -0800
commit896f361bd291f34e0ef439c249b79d7c51ed3f9a (patch)
tree14914fbe38c35188227aa7e8640158e7e2aa0af6 /arch/arm26
parenta16ef86c87f4b029f55fa41979134d73d1375398 (diff)
downloadlinux-2.6.34-ux500-896f361bd291f34e0ef439c249b79d7c51ed3f9a.tar.gz
[PATCH] arm26: fixup asm statement in kernel/fiq.c
Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Acked-by: Ian Molton <spyro@f2s.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/arm26')
-rw-r--r--arch/arm26/kernel/fiq.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm26/kernel/fiq.c b/arch/arm26/kernel/fiq.c
index 08a97c9498f..a24272b61f3 100644
--- a/arch/arm26/kernel/fiq.c
+++ b/arch/arm26/kernel/fiq.c
@@ -104,14 +104,14 @@ void set_fiq_regs(struct pt_regs *regs)
{
register unsigned long tmp, tmp2;
__asm__ volatile (
- "mov %0, pc
- bic %1, %0, #0x3
- orr %1, %1, %3
- teqp %1, #0 @ select FIQ mode
- mov r0, r0
- ldmia %2, {r8 - r14}
- teqp %0, #0 @ return to SVC mode
- mov r0, r0"
+ "mov %0, pc \n"
+ "bic %1, %0, #0x3 \n"
+ "orr %1, %1, %3 \n"
+ "teqp %1, #0 @ select FIQ mode \n"
+ "mov r0, r0 \n"
+ "ldmia %2, {r8 - r14} \n"
+ "teqp %0, #0 @ return to SVC mode \n"
+ "mov r0, r0 "
: "=&r" (tmp), "=&r" (tmp2)
: "r" (&regs->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | MODE_FIQ26)
/* These registers aren't modified by the above code in a way
@@ -125,14 +125,14 @@ void get_fiq_regs(struct pt_regs *regs)
{
register unsigned long tmp, tmp2;
__asm__ volatile (
- "mov %0, pc
- bic %1, %0, #0x3
- orr %1, %1, %3
- teqp %1, #0 @ select FIQ mode
- mov r0, r0
- stmia %2, {r8 - r14}
- teqp %0, #0 @ return to SVC mode
- mov r0, r0"
+ "mov %0, pc \n"
+ "bic %1, %0, #0x3 \n"
+ "orr %1, %1, %3 \n"
+ "teqp %1, #0 @ select FIQ mode \n"
+ "mov r0, r0 \n"
+ "stmia %2, {r8 - r14} \n"
+ "teqp %0, #0 @ return to SVC mode \n"
+ "mov r0, r0 "
: "=&r" (tmp), "=&r" (tmp2)
: "r" (&regs->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | MODE_FIQ26)
/* These registers aren't modified by the above code in a way