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authorMian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>2010-05-10 18:08:53 +0200
committerJohn Rigby <john.rigby@linaro.org>2010-09-02 22:44:36 -0600
commit3ea2f3a7cd8e2d470bdaba599efb57968d7114a6 (patch)
treec84adc3431887fb0b515ec5265e86905c3cef0f5 /arch/arm/mach-ux500
parent747e3fcf01bb45034fe21512fe244d175559b493 (diff)
downloadlinux-2.6.34-ux500-3ea2f3a7cd8e2d470bdaba599efb57968d7114a6.tar.gz
ux500: move mach-u8500 to mach-ux500
Diffstat (limited to 'arch/arm/mach-ux500')
-rwxr-xr-xarch/arm/mach-ux500/Kconfig70
-rwxr-xr-xarch/arm/mach-ux500/Kconfig-arch690
-rwxr-xr-xarch/arm/mach-ux500/Makefile26
-rwxr-xr-xarch/arm/mach-ux500/Makefile.boot4
-rw-r--r--arch/arm/mach-ux500/board-u5500.c115
-rwxr-xr-xarch/arm/mach-ux500/clock.c724
-rwxr-xr-xarch/arm/mach-ux500/clock.h76
-rw-r--r--arch/arm/mach-ux500/cpu-db5500.c47
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c79
-rwxr-xr-xarch/arm/mach-ux500/cpufreq.c163
-rwxr-xr-xarch/arm/mach-ux500/cpuidle.c246
-rwxr-xr-xarch/arm/mach-ux500/cpuidle.h34
-rw-r--r--arch/arm/mach-ux500/db5500-devices.c240
-rw-r--r--arch/arm/mach-ux500/db8500-devices.c327
-rw-r--r--arch/arm/mach-ux500/devices.c1094
-rwxr-xr-xarch/arm/mach-ux500/dma_40.c3903
-rwxr-xr-xarch/arm/mach-ux500/headsmp.S38
-rwxr-xr-xarch/arm/mach-ux500/hotplug.c141
-rw-r--r--arch/arm/mach-ux500/hsi.c336
-rwxr-xr-xarch/arm/mach-ux500/include/mach/ab8500-dev.h30
-rwxr-xr-xarch/arm/mach-ux500/include/mach/ab8500.h586
-rwxr-xr-xarch/arm/mach-ux500/include/mach/ab8500_codec.h435
-rwxr-xr-xarch/arm/mach-ux500/include/mach/ab8500_codec_p.h3371
-rw-r--r--arch/arm/mach-ux500/include/mach/ab8500_gpadc.h28
-rwxr-xr-xarch/arm/mach-ux500/include/mach/av8100.h531
-rwxr-xr-xarch/arm/mach-ux500/include/mach/av8100_fw.h1050
-rwxr-xr-xarch/arm/mach-ux500/include/mach/av8100_p.h188
-rwxr-xr-xarch/arm/mach-ux500/include/mach/bit_mask.h110
-rwxr-xr-xarch/arm/mach-ux500/include/mach/bits.h64
-rwxr-xr-xarch/arm/mach-ux500/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-ux500/include/mach/db5500-regs.h96
-rw-r--r--arch/arm/mach-ux500/include/mach/db8500-regs.h117
-rwxr-xr-xarch/arm/mach-ux500/include/mach/debug-macro.S20
-rwxr-xr-xarch/arm/mach-ux500/include/mach/debug.h52
-rw-r--r--arch/arm/mach-ux500/include/mach/devices.h72
-rwxr-xr-xarch/arm/mach-ux500/include/mach/dma.h106
-rwxr-xr-xarch/arm/mach-ux500/include/mach/dma_40-8500.h788
-rwxr-xr-xarch/arm/mach-ux500/include/mach/dsi.h777
-rwxr-xr-xarch/arm/mach-ux500/include/mach/dsi_reg.h495
-rwxr-xr-xarch/arm/mach-ux500/include/mach/entry-macro.S84
-rwxr-xr-xarch/arm/mach-ux500/include/mach/gpio.h190
-rwxr-xr-xarch/arm/mach-ux500/include/mach/hardware.h219
-rwxr-xr-xarch/arm/mach-ux500/include/mach/hcl_defs.h252
-rwxr-xr-xarch/arm/mach-ux500/include/mach/hsi-stm.h186
-rwxr-xr-xarch/arm/mach-ux500/include/mach/i2c-stm.h404
-rwxr-xr-xarch/arm/mach-ux500/include/mach/io.h22
-rwxr-xr-xarch/arm/mach-ux500/include/mach/irqs.h109
-rwxr-xr-xarch/arm/mach-ux500/include/mach/isa_ioctl.h51
-rwxr-xr-xarch/arm/mach-ux500/include/mach/kpd.h117
-rw-r--r--arch/arm/mach-ux500/include/mach/mcde-base.h83
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde.h1381
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde_a0.h866
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde_common.h173
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde_ioctls.h737
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde_reg.h794
-rwxr-xr-xarch/arm/mach-ux500/include/mach/memory.h20
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mmc.h341
-rwxr-xr-xarch/arm/mach-ux500/include/mach/msp.h963
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mtu.h59
-rwxr-xr-xarch/arm/mach-ux500/include/mach/prcmu-fw-api.h68
-rwxr-xr-xarch/arm/mach-ux500/include/mach/prcmu-fw-defs_ed.h415
-rwxr-xr-xarch/arm/mach-ux500/include/mach/prcmu-fw-defs_v1.h549
-rwxr-xr-xarch/arm/mach-ux500/include/mach/prcmu-regs.h110
-rwxr-xr-xarch/arm/mach-ux500/include/mach/scu.h25
-rw-r--r--arch/arm/mach-ux500/include/mach/setup.h42
-rwxr-xr-xarch/arm/mach-ux500/include/mach/shrm.h33
-rwxr-xr-xarch/arm/mach-ux500/include/mach/smp.h38
-rwxr-xr-xarch/arm/mach-ux500/include/mach/ste_conn_devices.h227
-rwxr-xr-xarch/arm/mach-ux500/include/mach/stmpe1601.h290
-rwxr-xr-xarch/arm/mach-ux500/include/mach/stmpe2401.h99
-rwxr-xr-xarch/arm/mach-ux500/include/mach/system.h29
-rwxr-xr-xarch/arm/mach-ux500/include/mach/tc35892.h183
-rwxr-xr-xarch/arm/mach-ux500/include/mach/timex.h13
-rwxr-xr-xarch/arm/mach-ux500/include/mach/u8500_acodec_ab8500.h227
-rwxr-xr-xarch/arm/mach-ux500/include/mach/u8500_tsc.h216
-rwxr-xr-xarch/arm/mach-ux500/include/mach/uart.h17
-rwxr-xr-xarch/arm/mach-ux500/include/mach/uncompress.h58
-rwxr-xr-xarch/arm/mach-ux500/include/mach/vmalloc.h18
-rwxr-xr-xarch/arm/mach-ux500/localtimer.c207
-rw-r--r--arch/arm/mach-ux500/mcde.c763
-rw-r--r--arch/arm/mach-ux500/mop500-sdi.c274
-rwxr-xr-xarch/arm/mach-ux500/mop500_devices.c965
-rwxr-xr-xarch/arm/mach-ux500/platsmp.c224
-rwxr-xr-xarch/arm/mach-ux500/pm.c78
-rwxr-xr-xarch/arm/mach-ux500/prcmu-fw.c1992
-rwxr-xr-xarch/arm/mach-ux500/prcmu-fw_ed.h86
-rwxr-xr-xarch/arm/mach-ux500/prcmu-fw_v1.h174
-rw-r--r--arch/arm/mach-ux500/regulator.c305
-rwxr-xr-xarch/arm/mach-ux500/ste_conn_devices.c388
-rw-r--r--arch/arm/mach-ux500/timer-rtt.c171
-rwxr-xr-xarch/arm/mach-ux500/timer.c205
91 files changed, 32816 insertions, 0 deletions
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
new file mode 100755
index 00000000000..a84e5b6463a
--- /dev/null
+++ b/arch/arm/mach-ux500/Kconfig
@@ -0,0 +1,70 @@
+if ARCH_U8500
+
+config UX500_SOC_DB8500
+ bool
+ depends on (MACH_U8500_MOP || MACH_U8500_SIMULATOR)
+ default y
+
+config UX500_SOC_DB5500
+ bool
+ default y
+ depends on MACH_U5500_SIMULATOR
+
+choice
+ prompt "Ux500 target platform"
+ default MACH_U8500_MOP
+
+config MACH_U8500_SIMULATOR
+ bool "U8500 Simulator (SVP8500)"
+ select CPU_V7
+ select ARM_GIC
+ select SMP
+ help
+ Supports Simulation for u8500 platform
+
+config MACH_U5500_SIMULATOR
+ bool "U5500 Simulator (SVP5500)"
+ select CPU_V7
+ select ARM_GIC
+ select SMP
+ help
+ Supports Simulation for u5500(FairBanks) platform
+
+config MACH_U8500_MOP
+ bool "U8500 MOP500/HREF"
+ select CPU_V7
+ select ARM_GIC
+ select SMP
+ help
+ Supports MOP500 target board
+
+endchoice
+
+config U8500_CPUIDLE
+ tristate "CPUIdle support"
+ depends on UX500_SOC_DB8500 && CPU_IDLE
+ select GENERIC_CLOCKEVENTS_BROADCAST
+ help
+ Add support for CPUIdle for U8500
+
+config U8500_CPUFREQ
+ tristate "CPUFreq support"
+ depends on UX500_SOC_DB8500 && CPU_FREQ
+ default y
+ help
+ Add support for CPU Frequency scaling for U8500
+
+config U8500_PM
+ bool
+ depends on UX500_SOC_DB8500 && PM
+
+config ARCH_HAS_CPU_IDLE_WAIT
+ def_bool y
+
+source "arch/arm/mach-ux500/Kconfig-arch"
+
+config FORCE_MAX_ZONEORDER
+ int "Maximum zone order"
+ default "12"
+
+endif
diff --git a/arch/arm/mach-ux500/Kconfig-arch b/arch/arm/mach-ux500/Kconfig-arch
new file mode 100755
index 00000000000..82aeebabd57
--- /dev/null
+++ b/arch/arm/mach-ux500/Kconfig-arch
@@ -0,0 +1,690 @@
+config MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
+ bool "MCDE HW V1 support"
+ default n
+ help
+ Say yes here if V1 HW
+
+config GPIO_STM
+ bool "STM GPIO driver support"
+ default y
+ help
+ Say yes here to support the STM GPIO device
+
+config STM_DMA
+ tristate "STM DMA SUPPORT"
+ default y
+ help
+ STM DMA low level driver for standrd DMA interface
+
+config U8500_SECURE
+ bool "Support for running in Secure mode"
+ default n
+ help
+ Build the kernel to run in Secure mode.
+
+menu "Debug level for STM drivers"
+config STM_ACODEC_DEBUG
+ int "STM ACODEC Debug Level"
+ depends on U8500_ACODEC
+ default 0
+ help
+ Sets the ACODEC debug ON/OFF for U8500 SoC
+ * 0 OFF
+ * 1 ON
+
+config STM_ALSA_DEBUG
+ int "STM ALSA Debug Level"
+ depends on SND_U8500_ALSA || SND_U8500_ALSA_AB8500
+ default 0
+ help
+ Sets the ALSA debug ON/OFF for U8500 SoC
+ * 0 OFF
+ * 1 ON
+endmenu
+#Configuration for MCDE setup
+
+menu "Display Channel Selection"
+
+menuconfig FB_U8500_MCDE_CHANNELA
+ depends on FB
+ bool "MCDE Channel A configuration"
+ default y
+ help
+ If you want to connect your panel to MCDE channel A then configure this option
+
+choice
+ prompt "Display Panel Type"
+ depends on FB && FB_U8500_MCDE_CHANNELA
+ default FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI
+
+config FB_U8500_MCDE_CHANNELA_DISPLAY_WVGA
+ bool "CLCD WVGA"
+
+config FB_U8500_MCDE_CHANNELA_DISPLAY_VGA
+ bool "CLCD VGA"
+
+config FB_U8500_MCDE_CHANNELA_DISPLAY_CRT
+ bool "CRT VGA"
+
+config FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
+ bool "SDTV"
+
+config FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI
+ depends on MCDE_ENABLE_FEATURE_HW_V1_SUPPORT && FB_HDMI
+ bool "HDMI A"
+
+config FB_U8500_MCDE_CHANNELA_DISPLAY_QVGA_PORTRAIT
+ bool "CLCD QVGA Portrait"
+
+config FB_U8500_MCDE_CHANNELA_DISPLAY_QVGA_LANDSCAPE
+ bool "CLCD QVGA Landscape"
+
+endchoice
+
+
+choice
+ prompt "HDMI resolution"
+ depends on FB && FB_U8500_MCDE_CHANNELA && FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI
+ default FB_U8500_MCDE_HDMI_1280x720P60
+
+config FB_U8500_MCDE_HDMI_1920x1080P30
+ bool "1920x1080P@30Hz"
+
+config FB_U8500_MCDE_HDMI_1280x720P60
+ bool "1280x720P@60Hz"
+
+#config FB_U8500_MCDE_HDMI_720x480P60
+# bool "720x480P@60Hz"
+
+#config FB_U8500_MCDE_HDMI_640x480P60
+# bool "640x480P@60Hz"
+
+endchoice
+
+
+choice
+ prompt "InputSource BPP"
+ depends on FB && FB_U8500_MCDE_CHANNELA
+ default FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB
+
+
+config FB_U8500_MCDE_CHANNELA_INPUT_16BPP_IRGB
+ bool "16 BPP IRGB"
+
+config FB_U8500_MCDE_CHANNELA_INPUT_8BPP
+ bool "8 BPP"
+
+config FB_U8500_MCDE_CHANNELA_INPUT_12BPP
+ bool "12 BPP"
+
+config FB_U8500_MCDE_CHANNELA_INPUT_16BPP_ARGB
+ bool "16 BPP ARGB"
+
+config FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB
+ bool "16 BPP RGB"
+
+config FB_U8500_MCDE_CHANNELA_INPUT_24BPP
+ bool "24 BPP"
+
+config FB_U8500_MCDE_CHANNELA_INPUT_24BPP_PACKED
+ bool "24 BPP Packed"
+
+config FB_U8500_MCDE_CHANNELA_INPUT_32BPP
+ bool "32 BPP"
+
+config FB_U8500_MCDE_CHANNELA_INPUT_YCBCR
+ bool "YCbCr422"
+
+
+endchoice
+
+
+choice
+ prompt "OutputPanel BPP"
+ depends on FB && FB_U8500_MCDE_CHANNELA
+ default FB_U8500_MCDE_CHANNELA_OUTPUT_16BPP
+
+config FB_U8500_MCDE_CHANNELA_OUTPUT_12BPP
+ bool "12 BPP"
+
+config FB_U8500_MCDE_CHANNELA_OUTPUT_16BPP
+ bool "16 BPP"
+
+config FB_U8500_MCDE_CHANNELA_OUTPUT_18BPP
+ bool "18 BPP"
+
+config FB_U8500_MCDE_CHANNELA_OUTPUT_24BPP
+ bool "24 BPP"
+
+
+endchoice
+
+config FB_U8500_MCDE_CHANNELA_INPUT_BGRDATA
+ bool "BGR Input data"
+ depends on FB && FB_U8500_MCDE_CHANNELA
+ default no
+ help
+ Select this option if your input data is in BGR format
+
+
+config FB_U8500_MCDE_CHANNELA_INPUT_BPP
+ int
+ default 16 if !FB
+ default 8 if FB_U8500_MCDE_CHANNELA_INPUT_8BPP
+ default 16 if FB_U8500_MCDE_CHANNELA_INPUT_12BPP
+ default 16 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_ARGB
+ default 16 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_IRGB
+ default 16 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB
+ default 25 if FB_U8500_MCDE_CHANNELA_INPUT_24BPP
+ default 24 if FB_U8500_MCDE_CHANNELA_INPUT_24BPP_PACKED
+ default 32 if FB_U8500_MCDE_CHANNELA_INPUT_32BPP
+ default 11 if FB_U8500_MCDE_CHANNELA_INPUT_YCBCR
+
+
+config FB_U8500_MCDE_CHANNELA_INPUT_16BPP_TYPE
+ int
+ default 0 if ((!FB_U8500_MCDE_CHANNELA_INPUT_12BPP) && (!FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB) && (!FB_U8500_MCDE_CHANNELA_INPUT_16BPP_IRGB) && (!FB_U8500_MCDE_CHANNELA_INPUT_16BPP_ARGB))
+ default 35 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB
+ default 36 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_IRGB
+ default 37 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_ARGB
+ default 38 if FB_U8500_MCDE_CHANNELA_INPUT_12BPP
+
+
+config FB_U8500_MCDE_CHANNELA_DISPLAY_TYPE
+ string
+ default "VGA" if !FB
+ default "WVGA" if FB_U8500_MCDE_CHANNELA_DISPLAY_WVGA
+ default "VGA" if FB_U8500_MCDE_CHANNELA_DISPLAY_VGA
+ default "CRT" if FB_U8500_MCDE_CHANNELA_DISPLAY_CRT
+ default "SDTV" if FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
+ default "HDMI A" if FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI
+ default "QVGA_Portrait" if FB_U8500_MCDE_CHANNELA_DISPLAY_QVGA_PORTRAIT
+ default "QVGA_Landscape" if FB_U8500_MCDE_CHANNELA_DISPLAY_QVGA_LANDSCAPE
+
+config FB_U8500_MCDE_CHANNELA_OUTPUT_BPP
+ hex
+ default 0x2 if !FB
+ default 0x1 if FB_U8500_MCDE_CHANNELA_OUTPUT_12BPP
+ default 0x2 if FB_U8500_MCDE_CHANNELA_OUTPUT_16BPP
+ default 0x3 if FB_U8500_MCDE_CHANNELA_OUTPUT_18BPP
+ default 0x4 if FB_U8500_MCDE_CHANNELA_OUTPUT_24BPP
+
+config FB_U8500_MCDE_CHANNELA_INPUT_BGR
+ hex
+ default 0x0 if !FB || !FB_U8500_MCDE_CHANNELA_INPUT_BGRDATA
+ default 0x1 if FB_U8500_MCDE_CHANNELA_INPUT_BGRDATA
+
+
+menuconfig FB_U8500_MCDE_CHANNELB
+ depends on FB
+ bool "MCDE Channel B configuration"
+ default n
+ help
+ If you want to connect your panel to MCDE channel B then configure this option
+
+choice
+ prompt "Display Panel Type"
+ depends on FB && FB_U8500_MCDE_CHANNELB
+ default FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV
+
+config FB_U8500_MCDE_CHANNELB_DISPLAY_WVGA
+ bool "CLCD WVGA"
+
+config FB_U8500_MCDE_CHANNELB_DISPLAY_VGA
+ bool "CLCD VGA"
+
+config FB_U8500_MCDE_CHANNELB_DISPLAY_CRT
+ bool "CRT VGA"
+
+config FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV
+ depends on !FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI
+ bool "SDTV"
+
+config FB_U8500_MCDE_CHANNELB_DISPLAY_QVGA_PORTRAIT
+ bool "CLCD QVGA Portrait"
+
+config FB_U8500_MCDE_CHANNELB_DISPLAY_QVGA_LANDSCAPE
+ bool "CLCD QVGA Landscape"
+
+config FB_U8500_MCDE_CHANNELB_DISPLAY_VUIB_WVGA
+ bool "VUIB WVGA"
+
+endchoice
+
+
+choice
+ prompt "InputDataFormat BPP"
+ depends on FB && FB_U8500_MCDE_CHANNELB
+ default FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB
+
+
+config FB_U8500_MCDE_CHANNELB_INPUT_16BPP_IRGB
+ bool "16 BPP IRGB"
+
+config FB_U8500_MCDE_CHANNELB_INPUT_8BPP
+ bool "8 BPP"
+
+config FB_U8500_MCDE_CHANNELB_INPUT_12BPP
+ bool "12 BPP"
+
+config FB_U8500_MCDE_CHANNELB_INPUT_16BPP_ARGB
+ bool "16 BPP ARGB"
+
+config FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB
+ bool "16 BPP RGB"
+
+config FB_U8500_MCDE_CHANNELB_INPUT_24BPP
+ bool "24 BPP"
+
+config FB_U8500_MCDE_CHANNELB_INPUT_24BPP_PACKED
+ bool "24 BPP Packed"
+
+config FB_U8500_MCDE_CHANNELB_INPUT_32BPP
+ bool "32 BPP"
+
+config FB_U8500_MCDE_CHANNELB_INPUT_YCBCR
+ bool "YCbCr422"
+
+endchoice
+
+
+choice
+ prompt "OutputPanel BPP"
+ depends on FB && FB_U8500_MCDE_CHANNELB
+ default FB_U8500_MCDE_CHANNELB_OUTPUT_24BPP if FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV
+ default FB_U8500_MCDE_CHANNELB_OUTPUT_16BPP
+
+config FB_U8500_MCDE_CHANNELB_OUTPUT_12BPP
+ bool "12 BPP"
+
+config FB_U8500_MCDE_CHANNELB_OUTPUT_16BPP
+ bool "16 BPP"
+
+config FB_U8500_MCDE_CHANNELB_OUTPUT_18BPP
+ bool "18 BPP"
+
+config FB_U8500_MCDE_CHANNELB_OUTPUT_24BPP
+ bool "24 BPP"
+
+
+endchoice
+
+
+
+config FB_U8500_MCDE_CHANNELB_INPUT_BGRDATA
+ bool "BGR Input data"
+ depends on FB && FB_U8500_MCDE_CHANNELB
+ default no
+ help
+ Select this option if your input data is in BGR format
+
+
+config FB_U8500_MCDE_CHANNELB_INPUT_BPP
+ int
+ default 16 if !FB
+ default 8 if FB_U8500_MCDE_CHANNELB_INPUT_8BPP
+ default 16 if FB_U8500_MCDE_CHANNELB_INPUT_12BPP
+ default 16 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_ARGB
+ default 16 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_IRGB
+ default 16 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB
+ default 25 if FB_U8500_MCDE_CHANNELB_INPUT_24BPP
+ default 24 if FB_U8500_MCDE_CHANNELB_INPUT_24BPP_PACKED
+ default 32 if FB_U8500_MCDE_CHANNELB_INPUT_32BPP
+ default 11 if FB_U8500_MCDE_CHANNELB_INPUT_YCBCR
+
+
+config FB_U8500_MCDE_CHANNELB_INPUT_16BPP_TYPE
+ int
+ default 0 if ((!FB_U8500_MCDE_CHANNELB_INPUT_12BPP) && (!FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB) && (!FB_U8500_MCDE_CHANNELB_INPUT_16BPP_IRGB) && (!FB_U8500_MCDE_CHANNELB_INPUT_16BPP_ARGB))
+ default 1 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB
+ default 2 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_IRGB
+ default 3 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_ARGB
+ default 4 if FB_U8500_MCDE_CHANNELB_INPUT_12BPP
+
+
+config FB_U8500_MCDE_CHANNELB_DISPLAY_TYPE
+ string
+ default "VGA" if !FB
+ default "WVGA" if FB_U8500_MCDE_CHANNELB_DISPLAY_WVGA
+ default "VGA" if FB_U8500_MCDE_CHANNELB_DISPLAY_VGA
+ default "CRT" if FB_U8500_MCDE_CHANNELB_DISPLAY_CRT
+ default "PAL" if FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV
+ default "QVGA_Portrait" if FB_U8500_MCDE_CHANNELB_DISPLAY_QVGA_PORTRAIT
+ default "QVGA_Landscape" if FB_U8500_MCDE_CHANNELB_DISPLAY_QVGA_LANDSCAPE
+ default "VUIB WVGA" if FB_U8500_MCDE_CHANNELB_DISPLAY_VUIB_WVGA
+
+config FB_U8500_MCDE_CHANNELB_OUTPUT_BPP
+ hex
+ default 0x2 if !FB
+ default 0x1 if FB_U8500_MCDE_CHANNELB_OUTPUT_12BPP
+ default 0x2 if FB_U8500_MCDE_CHANNELB_OUTPUT_16BPP
+ default 0x3 if FB_U8500_MCDE_CHANNELB_OUTPUT_18BPP
+ default 0x4 if FB_U8500_MCDE_CHANNELB_OUTPUT_24BPP
+
+config FB_U8500_MCDE_CHANNELB_INPUT_BGR
+ hex
+ default 0x0 if !FB || !FB_U8500_MCDE_CHANNELB_INPUT_BGRDATA
+ default 0x1 if FB_U8500_MCDE_CHANNELB_INPUT_BGRDATA
+
+config U8500_MCDE_DHO_LBW_SWAPPED
+ bool "SDTV-MCDE: Swap LBW and DHO fields"
+ depends on FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV || FB_U8500_MCDE_CHANNEL
+ default y
+ help
+ In early development the MCDE register fields DHO and LBW are sw
+
+config U8500_TVOUT_DDR_MODE
+ bool "SDTV: use Dual Data Rate"
+ depends on FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV || FB_U8500_MCDE_CHANNEL
+ default y
+ help
+ Set to use dual data rate (using 4 data lines instead of 8)
+
+config TVOUT_TEST_PATTERN
+ bool "SDTV: Generate Test Pattern"
+ depends on FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV || FB_U8500_MCDE_CHANNEL
+ default n
+ help
+ Only generate a test pattern (MCDE is not used)
+
+menuconfig FB_U8500_MCDE_CHANNELC0
+ depends on FB
+ bool "MCDE Channel C0 configuration"
+ default n
+ help
+ If you want to connect your panel to MCDE channel C then configure this option
+
+choice
+ prompt "Display Panel Type"
+ depends on FB && FB_U8500_MCDE_CHANNELC0
+ default FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA
+
+config FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT
+# depends on MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
+ bool "CLCD WVGA Portrait"
+
+config FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA
+ bool "CLCD WVGA"
+
+config FB_U8500_MCDE_CHANNELC0_DISPLAY_VGA
+ bool "CLCD VGA"
+
+config FB_U8500_MCDE_CHANNELC0_DISPLAY_CRT
+ bool "CRT VGA"
+
+config FB_U8500_MCDE_CHANNELC0_DISPLAY_SDTV
+ bool "SDTV"
+
+config FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_PORTRAIT
+ bool "CLCD QVGA Portrait"
+
+config FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_LANDSCAPE
+ bool "CLCD QVGA Landscape"
+
+endchoice
+
+
+choice
+ prompt "InputDataFormat BPP"
+ depends on FB && FB_U8500_MCDE_CHANNELC0
+ default FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB
+
+
+config FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB
+ bool "16 BPP IRGB"
+
+config FB_U8500_MCDE_CHANNELC0_INPUT_8BPP
+ bool "8 BPP"
+
+config FB_U8500_MCDE_CHANNELC0_INPUT_12BPP
+ bool "12 BPP"
+
+config FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB
+ bool "16 BPP ARGB"
+
+config FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB
+ bool "16 BPP RGB"
+
+config FB_U8500_MCDE_CHANNELC0_INPUT_24BPP
+ bool "24 BPP"
+
+config FB_U8500_MCDE_CHANNELC0_INPUT_24BPP_PACKED
+ bool "24 BPP Packed"
+
+config FB_U8500_MCDE_CHANNELC0_INPUT_32BPP
+ bool "32 BPP"
+
+config FB_U8500_MCDE_CHANNELC0_INPUT_YCBCR
+ bool "YCbCr422"
+
+endchoice
+
+
+choice
+ prompt "OutputPanel BPP"
+ depends on FB && FB_U8500_MCDE_CHANNELC0
+ default FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP
+
+config FB_U8500_MCDE_CHANNELC0_OUTPUT_12BPP
+ bool "12 BPP"
+
+config FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP
+ bool "16 BPP"
+
+config FB_U8500_MCDE_CHANNELC0_OUTPUT_18BPP
+ bool "18 BPP"
+
+config FB_U8500_MCDE_CHANNELC0_OUTPUT_24BPP
+ bool "24 BPP"
+
+
+endchoice
+
+
+
+config FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA
+ bool "BGR Input data"
+ depends on FB && FB_U8500_MCDE_CHANNELC0
+ default no
+ help
+ Select this option if your input data is in BGR format
+
+
+config FB_U8500_MCDE_CHANNELC0_INPUT_BPP
+ int
+ default 16 if !FB
+ default 8 if FB_U8500_MCDE_CHANNELC0_INPUT_8BPP
+ default 16 if FB_U8500_MCDE_CHANNELC0_INPUT_12BPP
+ default 16 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB
+ default 16 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB
+ default 16 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB
+ default 25 if FB_U8500_MCDE_CHANNELC0_INPUT_24BPP
+ default 24 if FB_U8500_MCDE_CHANNELC0_INPUT_24BPP_PACKED
+ default 32 if FB_U8500_MCDE_CHANNELC0_INPUT_32BPP
+ default 11 if FB_U8500_MCDE_CHANNELC0_INPUT_YCBCR
+
+
+config FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_TYPE
+ int
+ default 0 if ((!FB_U8500_MCDE_CHANNELC0_INPUT_12BPP) && (!FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB) && (!FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB) && (!FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB))
+ default 1 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB
+ default 2 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB
+ default 3 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB
+ default 4 if FB_U8500_MCDE_CHANNELC0_INPUT_12BPP
+
+
+config FB_U8500_MCDE_CHANNELC0_DISPLAY_TYPE
+ string
+ default "VGA" if !FB
+ default "WVGA_Portrait" if FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT
+ default "WVGA" if FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA
+ default "VGA" if FB_U8500_MCDE_CHANNELC0_DISPLAY_VGA
+ default "CRT" if FB_U8500_MCDE_CHANNELC0_DISPLAY_CRT
+ default "SDTV" if FB_U8500_MCDE_CHANNELC0_DISPLAY_SDTV
+ default "QVGA_Portrait" if FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_PORTRAIT
+ default "QVGA_Landscape" if FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_LANDSCAPE
+
+config FB_U8500_MCDE_CHANNELC0_OUTPUT_BPP
+ hex
+ default 0x2 if !FB
+ default 0x1 if FB_U8500_MCDE_CHANNELC0_OUTPUT_12BPP
+ default 0x2 if FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP
+ default 0x3 if FB_U8500_MCDE_CHANNELC0_OUTPUT_18BPP
+ default 0x4 if FB_U8500_MCDE_CHANNELC0_OUTPUT_24BPP
+
+config FB_U8500_MCDE_CHANNELC0_INPUT_BGR
+ hex
+ default 0x0 if !FB || !FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA
+ default 0x1 if FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA
+
+menuconfig FB_U8500_MCDE_CHANNELC1
+ depends on FB
+ bool "MCDE Channel C1 configuration"
+ default n
+ help
+ If you want to connect your panel to MCDE channel C then configure this option
+
+choice
+ prompt "Display Panel Type"
+ depends on FB && FB_U8500_MCDE_CHANNELC1
+ default FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA_PORTRAIT
+
+config FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA_PORTRAIT
+ bool "CLCD WVGA Portrait"
+
+config FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA
+ bool "CLCD WVGA"
+
+config FB_U8500_MCDE_CHANNELC1_DISPLAY_VGA
+ bool "CLCD VGA"
+
+config FB_U8500_MCDE_CHANNELC1_DISPLAY_CRT
+ bool "CRT VGA"
+
+config FB_U8500_MCDE_CHANNELC1_DISPLAY_SDTV
+ bool "SDTV"
+
+config FB_U8500_MCDE_CHANNELC1_DISPLAY_QVGA_PORTRAIT
+ bool "CLCD QVGA Portrait"
+
+config FB_U8500_MCDE_CHANNELC1_DISPLAY_QVGA_LANDSCAPE
+ bool "CLCD QVGA Landscape"
+
+endchoice
+
+
+choice
+ prompt "InputDataFormat BPP"
+ depends on FB && FB_U8500_MCDE_CHANNELC1
+ default FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB
+
+
+config FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_IRGB
+ bool "16 BPP IRGB"
+
+config FB_U8500_MCDE_CHANNELC1_INPUT_8BPP
+ bool "8 BPP"
+
+config FB_U8500_MCDE_CHANNELC1_INPUT_12BPP
+ bool "12 BPP"
+
+config FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_ARGB
+ bool "16 BPP ARGB"
+
+config FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB
+ bool "16 BPP RGB"
+
+config FB_U8500_MCDE_CHANNELC1_INPUT_24BPP
+ bool "24 BPP"
+
+config FB_U8500_MCDE_CHANNELC1_INPUT_24BPP_PACKED
+ bool "24 BPP Packed"
+
+config FB_U8500_MCDE_CHANNELC1_INPUT_32BPP
+ bool "32 BPP"
+
+config FB_U8500_MCDE_CHANNELC1_INPUT_YCBCR
+ bool "YCbCr422"
+
+endchoice
+
+
+choice
+ prompt "OutputPanel BPP"
+ depends on FB && FB_U8500_MCDE_CHANNELC1
+ default FB_U8500_MCDE_CHANNELC1_OUTPUT_16BPP
+
+config FB_U8500_MCDE_CHANNELC1_OUTPUT_12BPP
+ bool "12 BPP"
+
+config FB_U8500_MCDE_CHANNELC1_OUTPUT_16BPP
+ bool "16 BPP"
+
+config FB_U8500_MCDE_CHANNELC1_OUTPUT_18BPP
+ bool "18 BPP"
+
+config FB_U8500_MCDE_CHANNELC1_OUTPUT_24BPP
+ bool "24 BPP"
+
+
+endchoice
+
+
+
+config FB_U8500_MCDE_CHANNELC1_INPUT_BGRDATA
+ bool "BGR Input data"
+ depends on FB && FB_U8500_MCDE_CHANNELC1
+ default no
+ help
+ Select this option if your input data is in BGR format
+
+
+config FB_U8500_MCDE_CHANNELC1_INPUT_BPP
+ int
+ default 16 if !FB
+ default 8 if FB_U8500_MCDE_CHANNELC1_INPUT_8BPP
+ default 16 if FB_U8500_MCDE_CHANNELC1_INPUT_12BPP
+ default 16 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_ARGB
+ default 16 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_IRGB
+ default 16 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB
+ default 25 if FB_U8500_MCDE_CHANNELC1_INPUT_24BPP
+ default 24 if FB_U8500_MCDE_CHANNELC1_INPUT_24BPP_PACKED
+ default 32 if FB_U8500_MCDE_CHANNELC1_INPUT_32BPP
+ default 11 if FB_U8500_MCDE_CHANNELC1_INPUT_YCBCR
+
+
+config FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_TYPE
+ int
+ default 0 if ((!FB_U8500_MCDE_CHANNELC1_INPUT_12BPP) && (!FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB) && (!FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_IRGB) && (!FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_ARGB))
+ default 1 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB
+ default 2 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_IRGB
+ default 3 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_ARGB
+ default 4 if FB_U8500_MCDE_CHANNELC1_INPUT_12BPP
+
+
+config FB_U8500_MCDE_CHANNELC1_DISPLAY_TYPE
+ string
+ default "VGA" if !FB
+ default "WVGA_Portrait" if FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA_PORTRAIT
+ default "WVGA" if FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA
+ default "VGA" if FB_U8500_MCDE_CHANNELC1_DISPLAY_VGA
+ default "CRT" if FB_U8500_MCDE_CHANNELC1_DISPLAY_CRT
+ default "SDTV" if FB_U8500_MCDE_CHANNELC1_DISPLAY_SDTV
+ default "QVGA_Portrait" if FB_U8500_MCDE_CHANNELC1_DISPLAY_QVGA_PORTRAIT
+ default "QVGA_Landscape" if FB_U8500_MCDE_CHANNELC1_DISPLAY_QVGA_LANDSCAPE
+
+config FB_U8500_MCDE_CHANNELC1_OUTPUT_BPP
+ hex
+ default 0x2 if !FB
+ default 0x1 if FB_U8500_MCDE_CHANNELC1_OUTPUT_12BPP
+ default 0x2 if FB_U8500_MCDE_CHANNELC1_OUTPUT_16BPP
+ default 0x3 if FB_U8500_MCDE_CHANNELC1_OUTPUT_18BPP
+ default 0x4 if FB_U8500_MCDE_CHANNELC1_OUTPUT_24BPP
+
+config FB_U8500_MCDE_CHANNELC1_INPUT_BGR
+ hex
+ default 0x0 if !FB || !FB_U8500_MCDE_CHANNELC1_INPUT_BGRDATA
+ default 0x1 if FB_U8500_MCDE_CHANNELC1_INPUT_BGRDATA
+endmenu
+
+
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
new file mode 100755
index 00000000000..adb63af8991
--- /dev/null
+++ b/arch/arm/mach-ux500/Makefile
@@ -0,0 +1,26 @@
+#
+# Makefile for the linux kernel, U8500 machine.
+#
+#
+
+obj-y := clock.o timer.o timer-rtt.o
+obj-$(CONFIG_REGULATOR) += regulator.o
+obj-$(CONFIG_ARCH_U8500) += devices.o
+obj-$(CONFIG_STM_DMA) += dma_40.o #part1 no. of dma is 0x40
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+obj-$(CONFIG_MACH_U8500_MOP) += mop500_devices.o mop500-sdi.o
+obj-$(CONFIG_UX500_SOC_DB5500) += db5500-devices.o cpu-db5500.o
+obj-$(CONFIG_UX500_SOC_DB8500) += db8500-devices.o hsi.o mcde.o \
+ cpu-db8500.o prcmu-fw.o
+obj-$(CONFIG_MACH_U8500_SIMULATOR) += mop500_devices.o mop500-sdi.o
+obj-$(CONFIG_MACH_U5500_SIMULATOR) += board-u5500.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o
+obj-$(CONFIG_U8500_CPUIDLE) += cpuidle.o
+obj-$(CONFIG_U8500_CPUFREQ) += cpufreq.o
+obj-$(CONFIG_U8500_PM) += pm.o
+
+ifeq ($(CONFIG_MFD_STE_CONN), m)
+obj-y += ste_conn_devices.o
+else
+obj-$(CONFIG_MFD_STE_CONN) += ste_conn_devices.o
+endif
diff --git a/arch/arm/mach-ux500/Makefile.boot b/arch/arm/mach-ux500/Makefile.boot
new file mode 100755
index 00000000000..c7e75acfe6c
--- /dev/null
+++ b/arch/arm/mach-ux500/Makefile.boot
@@ -0,0 +1,4 @@
+ zreladdr-y := 0x00008000
+params_phys-y := 0x00000100
+initrd_phys-y := 0x00800000
+
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
new file mode 100644
index 00000000000..3dcbde07aba
--- /dev/null
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/amba/bus.h>
+#include <linux/gpio.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <mach/i2c-stm.h>
+#include <mach/devices.h>
+#include <mach/setup.h>
+
+#ifdef CONFIG_FB_MCDE
+/*
+ * This is only for MCDE to build. Remove this once MCDE is fixed to not
+ * depend on this variable.
+ */
+int platform_id;
+#endif
+
+/*
+ * I2C
+ */
+
+static struct i2c_platform_data u8500_i2c1_data = {
+ .gpio_alt_func = GPIO_ALT_I2C_1,
+ .name = "i2c1",
+ .own_addr = I2C1_LP_OWNADDR,
+ .mode = I2C_FREQ_MODE_STANDARD,
+ .clk_freq = 100000,
+ .slave_addressing_mode = I2C_7_BIT_ADDRESS,
+ .digital_filter_control = I2C_DIGITAL_FILTERS_OFF,
+ .dma_sync_logic_control = I2C_DISABLED,
+ .start_byte_procedure = I2C_DISABLED,
+ .slave_data_setup_time = 0xE,
+ .bus_control_mode = I2C_BUS_MASTER_MODE,
+ .i2c_loopback_mode = I2C_DISABLED,
+ .xfer_mode = I2C_TRANSFER_MODE_INTERRUPT,
+ .high_speed_master_code = 0,
+ .i2c_tx_int_threshold = 1,
+ .i2c_rx_int_threshold = 1
+};
+
+static struct i2c_platform_data u8500_i2c2_data = {
+ .gpio_alt_func = GPIO_ALT_I2C_2,
+ .name = "i2c2",
+ .own_addr = I2C2_LP_OWNADDR,
+ .mode = I2C_FREQ_MODE_STANDARD,
+ .clk_freq = 100000,
+ .slave_addressing_mode = I2C_7_BIT_ADDRESS,
+ .digital_filter_control = I2C_DIGITAL_FILTERS_OFF,
+ .dma_sync_logic_control = I2C_DISABLED,
+ .start_byte_procedure = I2C_DISABLED,
+ .slave_data_setup_time = 0xE,
+ .bus_control_mode = I2C_BUS_MASTER_MODE,
+ .i2c_loopback_mode = I2C_DISABLED,
+ .xfer_mode = I2C_TRANSFER_MODE_INTERRUPT,
+ .high_speed_master_code = 0,
+ .i2c_tx_int_threshold = 1,
+ .i2c_rx_int_threshold = 1
+};
+
+static struct i2c_platform_data u8500_i2c3_data = {
+ .gpio_alt_func = GPIO_ALT_I2C_3,
+ .name = "i2c3",
+ .own_addr = I2C3_LP_OWNADDR,
+ .mode = I2C_FREQ_MODE_STANDARD,
+ .clk_freq = 100000,
+ .slave_addressing_mode = I2C_7_BIT_ADDRESS,
+ .digital_filter_control = I2C_DIGITAL_FILTERS_OFF,
+ .dma_sync_logic_control = I2C_DISABLED,
+ .start_byte_procedure = I2C_DISABLED,
+ .slave_data_setup_time = 0xE,
+ .bus_control_mode = I2C_BUS_MASTER_MODE,
+ .i2c_loopback_mode = I2C_DISABLED,
+ .xfer_mode = I2C_TRANSFER_MODE_INTERRUPT,
+ .high_speed_master_code = 0,
+ .i2c_tx_int_threshold = 1,
+ .i2c_rx_int_threshold = 1
+};
+
+static struct amba_device *amba_board_devs[] __initdata = {
+ &ux500_uart0_device,
+ &ux500_uart1_device,
+ &ux500_uart2_device,
+};
+
+static void __init u5500_init_machine(void)
+{
+ u5500_init_devices();
+
+ amba_add_devices(amba_board_devs, ARRAY_SIZE(amba_board_devs));
+
+ u8500_register_device(&ux500_i2c1_device, &u8500_i2c1_data);
+ u8500_register_device(&ux500_i2c2_device, &u8500_i2c2_data);
+ u8500_register_device(&ux500_i2c3_device, &u8500_i2c3_data);
+}
+
+MACHINE_START(NOMADIK, "ST-Ericsson U5500 Platform")
+ .phys_io = UX500_UART0_BASE,
+ .io_pg_offst = (IO_ADDRESS(UX500_UART0_BASE) >> 18) & 0xfffc,
+ .boot_params = 0x00000100,
+ .map_io = u5500_map_io,
+ .init_irq = u8500_init_irq,
+ .timer = &u8500_timer,
+ .init_machine = u5500_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
new file mode 100755
index 00000000000..5f84994e3ab
--- /dev/null
+++ b/arch/arm/mach-ux500/clock.c
@@ -0,0 +1,724 @@
+/*
+ * linux/arch/arm/mach-u8500/clock.c
+ *
+ * Copyright (C) ST Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+
+#include <asm/clkdev.h>
+#include <asm/io.h>
+
+#include <mach/hardware.h>
+#include <mach/prcmu-regs.h>
+#include "clock.h"
+
+static DEFINE_SPINLOCK(clocks_lock);
+
+static void __clk_enable(struct clk *clk)
+{
+ if (clk->enabled++ == 0) {
+ if (clk->parent_cluster)
+ __clk_enable(clk->parent_cluster);
+
+ if (clk->parent_periph)
+ __clk_enable(clk->parent_periph);
+
+ if (clk->ops && clk->ops->enable)
+ clk->ops->enable(clk);
+ }
+}
+
+int clk_enable(struct clk *clk)
+{
+ unsigned long flags;
+
+ if (!clk || IS_ERR(clk))
+ return -EINVAL;
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ __clk_enable(clk);
+ spin_unlock_irqrestore(&clocks_lock, flags);
+
+ return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+static void __clk_disable(struct clk *clk)
+{
+ if (--clk->enabled == 0) {
+ if (clk->ops && clk->ops->disable)
+ clk->ops->disable(clk);
+
+ if (clk->parent_periph)
+ __clk_disable(clk->parent_periph);
+
+ if (clk->parent_cluster)
+ __clk_disable(clk->parent_cluster);
+ }
+}
+
+void clk_disable(struct clk *clk)
+{
+ unsigned long flags;
+
+ if (!clk || IS_ERR(clk))
+ return;
+
+ WARN_ON(!clk->enabled);
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ __clk_disable(clk);
+ spin_unlock_irqrestore(&clocks_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ unsigned long rate;
+
+ if (clk->ops && clk->ops->get_rate)
+ return clk->ops->get_rate(clk);
+
+ rate = clk->rate;
+ if (!rate) {
+ if (clk->parent_periph)
+ rate = clk_get_rate(clk->parent_periph);
+ else if (clk->parent_cluster)
+ rate = clk_get_rate(clk->parent_cluster);
+ }
+
+ return rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+static void clk_prcmu_enable(struct clk *clk)
+{
+ void __iomem *cg_set_reg = (void __iomem *)PRCM_YYCLKEN0_MGT_SET
+ + clk->prcmu_cg_off;
+
+ writel(1 << clk->prcmu_cg_bit, cg_set_reg);
+}
+
+static void clk_prcmu_disable(struct clk *clk)
+{
+ void __iomem *cg_clr_reg = (void __iomem *)PRCM_YYCLKEN0_MGT_CLR
+ + clk->prcmu_cg_off;
+
+ writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
+}
+
+/* ED doesn't have the combined set/clr registers */
+
+static void clk_prcmu_ed_enable(struct clk *clk)
+{
+ unsigned int val = readl(clk->prcmu_cg_mgt);
+
+ val |= 1 << 8;
+ writel(val, clk->prcmu_cg_mgt);
+}
+
+static void clk_prcmu_ed_disable(struct clk *clk)
+{
+ unsigned int val = readl(clk->prcmu_cg_mgt);
+
+ val &= ~(1 << 8);
+ writel(val, clk->prcmu_cg_mgt);
+}
+
+static struct clkops clk_prcmu_ops = {
+ .enable = clk_prcmu_enable,
+ .disable = clk_prcmu_disable,
+};
+
+static void clk_prcc_enable(struct clk *clk)
+{
+ if (clk->prcc_kernel != -1)
+ writel(1 << (clk->prcc_kernel), clk->prcc_base + 0x8);
+
+ if (clk->prcc_bus != -1)
+ writel(1 << (clk->prcc_bus), clk->prcc_base + 0x0);
+}
+
+static void clk_prcc_disable(struct clk *clk)
+{
+ if (clk->prcc_bus != -1)
+ writel(1 << (clk->prcc_bus), clk->prcc_base + 0x4);
+
+ if (clk->prcc_kernel != -1)
+ writel(1 << (clk->prcc_kernel), clk->prcc_base + 0xc);
+}
+
+static struct clkops clk_prcc_ops = {
+ .enable = clk_prcc_enable,
+ .disable = clk_prcc_disable,
+};
+
+static struct clk clk_32khz = {
+ .rate = 32000,
+};
+
+/*
+ * PRCMU level clock gating
+ */
+
+/* Bank 0 */
+static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK);
+static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK);
+static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK);
+static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000);
+static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK);
+static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */
+static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000);
+static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 50000000);
+static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK);
+static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK);
+static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK);
+static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK);
+static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK);
+static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000);
+static DEFINE_PRCMU_CLK_RATE(per7clk, 0x0, 16, PER7CLK, 100000000);
+static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK);
+static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK);
+static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK);
+static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK);
+static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK);
+static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK);
+static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK);
+static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK);
+static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK);
+static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */
+static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK);
+static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK);
+static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK);
+static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */
+static DEFINE_PRCMU_CLK(sspclk, 0x0, 31, SSPCLK); /* v1 */
+
+/* Bank 1 */
+static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */
+static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */
+
+/*
+ * PRCC level clock gating
+ * Format: per#, clk, PCKEN bit, KCKEN bit, parent
+ */
+
+/* Peripheral Cluster #1 */
+static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk);
+static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL);
+static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk);
+static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL);
+static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL);
+static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk);
+static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk);
+static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk);
+static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk);
+static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk);
+static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk);
+static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk);
+
+/* Peripheral Cluster #2 */
+
+static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL);
+static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL);
+static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL);
+static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL);
+static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk);
+static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL);
+static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL);
+static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL);
+static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk);
+
+static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL);
+static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL);
+static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL);
+static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL);
+static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk);
+static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL);
+static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL);
+static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL);
+static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk);
+
+/* Peripheral Cluster #3 */
+static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL);
+static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk);
+static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz);
+static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk);
+static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk);
+static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk);
+static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk);
+static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk);
+static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL);
+
+/* Peripheral Cluster #4 is in the always on domain */
+
+/* Peripheral Cluster #5 */
+static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL);
+static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk);
+static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL);
+
+/* Peripheral Cluster #6 */
+
+static DEFINE_PRCC_CLK(6, mtu1_v1, 8, -1, NULL);
+static DEFINE_PRCC_CLK(6, mtu0_v1, 7, -1, NULL);
+static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL);
+static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL);
+static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL);
+static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk);
+static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL);
+static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL);
+static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL);
+static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL);
+static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk);
+static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk);
+
+/* Peripheral Cluster #7 */
+
+static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL);
+static DEFINE_PRCC_CLK(7, mtu1_ed, 3, -1, NULL);
+static DEFINE_PRCC_CLK(7, mtu0_ed, 2, -1, NULL);
+static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL);
+static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL);
+
+/*
+ * TODO: Ensure names match with devices and then remove unnecessary entries
+ * when all drivers use the clk API.
+ */
+
+static struct clk_lookup u8500_common_clkregs[] = {
+ /* Peripheral Cluster #1 */
+ CLK(gpio0, "gpioblock0", NULL),
+ CLK(slimbus0, "slimbus0", NULL),
+ CLK(i2c2, "STM-I2C.2", NULL),
+ CLK(sdi0, NULL, "MMC"), /* remove */
+ CLK(sdi0, "sdi0", NULL),
+ CLK(msp0, "msp0", NULL),
+ CLK(msp0, "MSP_I2S.0", NULL),
+ CLK(i2c1, "STM-I2C.1", NULL),
+ CLK(uart1, "uart1", NULL),
+ CLK(uart0, "uart0", NULL),
+
+ /* Peripheral Cluster #3 */
+ CLK(gpio2, "gpioblock2", NULL),
+ CLK(sdi5, "sdi5", NULL),
+ CLK(uart2, "uart2", NULL),
+ CLK(ske, "ske", NULL),
+ CLK(sdi2, "sdi2", NULL),
+ CLK(i2c0, "STM-I2C.0", NULL),
+ CLK(fsmc, "fsmc", NULL),
+
+ /* Peripheral Cluster #5 */
+ CLK(gpio3, "gpioblock3", NULL),
+
+ /* Peripheral Cluster #6 */
+ CLK(hash1, "hash1", NULL),
+ CLK(pka, "pka", NULL),
+ CLK(hash0, "hash0", NULL),
+ CLK(cryp0, "cryp0", NULL),
+
+ /*
+ * PRCMU level clock gating
+ */
+
+ /* Bank 0 */
+ CLK(svaclk, "sva", NULL),
+ CLK(siaclk, "sia", NULL),
+ CLK(sgaclk, "sga", NULL),
+ CLK(uartclk, "UART", NULL),
+ CLK(msp02clk, "MSP02", NULL),
+ CLK(i2cclk, "I2C", NULL),
+ CLK(sdmmcclk, "sdmmc", NULL),
+ CLK(slimclk, "SLIM", NULL),
+ CLK(per1clk, "PERIPH1", NULL),
+ CLK(per2clk, "PERIPH2", NULL),
+ CLK(per3clk, "PERIPH3", NULL),
+ CLK(per5clk, "PERIPH5", NULL),
+ CLK(per6clk, "PERIPH6", NULL),
+ CLK(per7clk, "PERIPH7", NULL),
+ CLK(lcdclk, "lcd", NULL),
+ CLK(bmlclk, "bml", NULL),
+ CLK(hsitxclk, "stm-hsi.0", NULL),
+ CLK(hsirxclk, "stm-hsi.1", NULL),
+ CLK(hdmiclk, "hdmi", NULL),
+ CLK(apeatclk, "apeat", NULL),
+ CLK(apetraceclk, "apetrace", NULL),
+ CLK(mcdeclk, "mcde", NULL),
+ CLK(ipi2clk, "ipi2", NULL),
+ CLK(dmaclk, "STM-DMA.0", NULL),
+ CLK(b2r2clk, "b2r2", NULL),
+ CLK(tvclk, "tv", NULL),
+
+ /* With device names */
+
+ CLK(mcdeclk, "U8500-MCDE.0", "mcde"),
+ CLK(hdmiclk, "U8500-MCDE.0", "hdmi"),
+ CLK(tvclk, "U8500-MCDE.0", "tv"),
+ CLK(lcdclk, "U8500-MCDE.0", "lcd"),
+ CLK(mcdeclk, "U8500-MCDE.1", "mcde"),
+ CLK(hdmiclk, "U8500-MCDE.1", "hdmi"),
+ CLK(tvclk, "U8500-MCDE.1", "tv"),
+ CLK(lcdclk, "U8500-MCDE.1", "lcd"),
+ CLK(mcdeclk, "U8500-MCDE.2", "mcde"),
+ CLK(hdmiclk, "U8500-MCDE.2", "hdmi"),
+ CLK(tvclk, "U8500-MCDE.2", "tv"),
+ CLK(lcdclk, "U8500-MCDE.2", "lcd"),
+ CLK(mcdeclk, "U8500-MCDE.3", "mcde"),
+ CLK(hdmiclk, "U8500-MCDE.3", "hdmi"),
+ CLK(tvclk, "U8500-MCDE.3", "tv"),
+ CLK(lcdclk, "U8500-MCDE.3", "lcd"),
+ CLK(b2r2clk, "U8500-B2R2.0", NULL),
+};
+
+static struct clk_lookup u8500_ed_clkregs[] = {
+ /* Peripheral Cluster #1 */
+ CLK(spi3_ed, "spi3", NULL),
+ CLK(msp1_ed, "msp1", NULL),
+ CLK(msp1_ed, "MSP_I2S.1", NULL),
+
+ /* Peripheral Cluster #2 */
+ CLK(gpio1_ed, "gpioblock1", NULL),
+ CLK(ssitx_ed, "ssitx", NULL),
+ CLK(ssirx_ed, "ssirx", NULL),
+ CLK(spi0_ed, "spi0", NULL),
+ CLK(sdi3_ed, "sdi3", NULL),
+ CLK(sdi1_ed, "sdi1", NULL),
+ CLK(msp2_ed, "msp2", NULL),
+ CLK(msp2_ed, "MSP_I2S.2", NULL),
+ CLK(sdi4_ed, NULL, "EMMC"), /* remove */
+ CLK(sdi4_ed, "sdi4", NULL),
+ CLK(pwl_ed, "pwl", NULL),
+ CLK(spi1_ed, "spi1", NULL),
+ CLK(spi2_ed, "spi2", NULL),
+ CLK(i2c3_ed, "STM-I2C.3", NULL),
+
+ /* Peripheral Cluster #3 */
+ CLK(ssp1_ed, "ssp1", NULL),
+ CLK(ssp0_ed, "ssp0", NULL),
+
+ /* Peripheral Cluster #5 */
+ CLK(usb_ed, "musb_hdrc.0", "usb"),
+
+ /* Peripheral Cluster #6 */
+ CLK(dmc_ed, "dmc", NULL),
+ CLK(cryp1_ed, "cryp1", NULL),
+ CLK(rng_ed, "rng", NULL),
+
+ /* Peripheral Cluster #7 */
+ CLK(tzpc0_ed, "tzpc0", NULL),
+ CLK(mtu1_ed, "mtu1", NULL),
+ CLK(mtu0_ed, "mtu0", NULL),
+ CLK(wdg_ed, "wdg", NULL),
+ CLK(cfgreg_ed, "cfgreg", NULL),
+};
+
+static struct clk_lookup u8500_v1_clkregs[] = {
+ /* Peripheral Cluster #1 */
+ CLK(i2c4, "STM-I2C.4", NULL),
+ CLK(spi3_v1, "spi3", NULL),
+ CLK(msp1_v1, "msp1", NULL),
+ CLK(msp1_v1, "MSP_I2S.1", NULL),
+
+ /* Peripheral Cluster #2 */
+ CLK(gpio1_v1, "gpioblock1", NULL),
+ CLK(ssitx_v1, "ssitx", NULL),
+ CLK(ssirx_v1, "ssirx", NULL),
+ CLK(spi0_v1, "spi0", NULL),
+ CLK(sdi3_v1, "sdi3", NULL),
+ CLK(sdi1_v1, "sdi1", NULL),
+ CLK(msp2_v1, "msp2", NULL),
+ CLK(msp2_v1, "MSP_I2S.2", NULL),
+ CLK(sdi4_v1, NULL, "EMMC"), /* remove */
+ CLK(sdi4_v1, "sdi4", NULL),
+ CLK(pwl_v1, "pwl", NULL),
+ CLK(spi1_v1, "spi1", NULL),
+ CLK(spi2_v1, "spi2", NULL),
+ CLK(i2c3_v1, "STM-I2C.3", NULL),
+
+ /* Peripheral Cluster #3 */
+ CLK(ssp1_v1, "ssp1", NULL),
+ CLK(ssp0_v1, "ssp0", NULL),
+
+ /* Peripheral Cluster #5 */
+ CLK(usb_v1, "musb_hdrc.0", "usb"),
+
+ /* Peripheral Cluster #6 */
+ CLK(mtu1_v1, "mtu1", NULL),
+ CLK(mtu0_v1, "mtu0", NULL),
+ CLK(cfgreg_v1, "cfgreg", NULL),
+ CLK(hash1, "hash1", NULL),
+ CLK(unipro_v1, "unipro", NULL),
+ CLK(rng_v1, "rng", NULL),
+
+ /*
+ * PRCMU level clock gating
+ */
+
+ /* Bank 0 */
+ CLK(msp1clk, "MSP1", NULL),
+ CLK(uniproclk, "uniproclk", NULL),
+ CLK(sspclk, "SSP", NULL),
+ CLK(dsialtclk, "dsialt", NULL),
+
+ /* Bank 1 */
+ CLK(rngclk, "rng", NULL),
+ CLK(uiccclk, "uicc", NULL),
+};
+
+static void clk_register(struct clk *clk);
+
+static void clks_register(struct clk_lookup *clks, size_t num)
+{
+ int i;
+
+ for (i = 0; i < num; i++) {
+ clkdev_add(&clks[i]);
+ clk_register(clks[i].clk);
+ }
+}
+
+/* these are the clocks which are default from the bootloader */
+static const char *u8500_boot_clk[] = {
+ "uart0",
+ "uart1",
+ "uart2",
+ "gpio0",
+ "gpio1",
+ "gpio2",
+ "gpio3",
+ "mtu0",
+ "mtu1",
+ "ssp0",
+ "ssp1",
+ "spi0",
+ "spi1",
+ "spi2",
+ "spi3",
+ "msp0",
+ "msp1",
+ "msp2",
+ "msp3",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "i2c3",
+ "i2c4"
+};
+
+struct clk *boot_clks[ARRAY_SIZE(u8500_boot_clk)];
+
+/* we disable a majority of peripherals enabled by default
+ * but without drivers
+ */
+static void __init u8500_boot_clk_disable(void)
+{
+ int i = 0;
+ for (i = 0; i < ARRAY_SIZE(u8500_boot_clk); i++) {
+ clk_disable(boot_clks[i]);
+ clk_put(boot_clks[i]);
+ }
+}
+late_initcall_sync(u8500_boot_clk_disable);
+
+static void u8500_amba_clk_enable(void)
+{
+ int i = 0;
+
+ writel(~0x0 & ~(1 << 9), IO_ADDRESS(U8500_PER1_BASE + 0xF000 + 0x04));
+ writel(~0x0, IO_ADDRESS(U8500_PER1_BASE + 0xF000 + 0x0C));
+
+ writel(~0x0 & ~(1 << 11), IO_ADDRESS(U8500_PER2_BASE + 0xF000 + 0x04));
+ writel(~0x0, IO_ADDRESS(U8500_PER2_BASE + 0xF000 + 0x0C));
+
+ /*GPIO,UART2 are enabled for booting*/
+ writel(0xBF, IO_ADDRESS(U8500_PER3_BASE + 0xF000 + 0x04));
+ writel(~0x0 & ~(1 << 6), IO_ADDRESS(U8500_PER3_BASE + 0xF000 + 0x0C));
+
+ /* enable AMBA configuration clock ONLY */
+ writel(~0x0, IO_ADDRESS(U8500_PER6_BASE + 0xF000 + 0x04));
+ writel(~0x0, IO_ADDRESS(U8500_PER6_BASE + 0xF000 + 0x0C));
+
+ for (i = 0; i < ARRAY_SIZE(u8500_boot_clk); i++) {
+ boot_clks[i] = clk_get_sys(u8500_boot_clk[i], NULL);
+ clk_enable(boot_clks[i]);
+ }
+}
+
+int __init clk_init(void)
+{
+ if (cpu_is_u8500ed()) {
+ clk_prcmu_ops.enable = clk_prcmu_ed_enable;
+ clk_prcmu_ops.disable = clk_prcmu_ed_disable;
+ } else if (cpu_is_u8500v1()) {
+ void __iomem *sdmmclkmgt = (void __iomem *) PRCM_SDMMCCLK_MGT;
+ unsigned int val;
+
+ /* Switch SDMMCCLK to 52Mhz instead of 104Mhz */
+ val = readl(sdmmclkmgt);
+ val = (val & ~0x1f) | 16;
+ writel(val, sdmmclkmgt);
+ } else if (cpu_is_u5500()) {
+ clk_prcmu_ops.enable = NULL;
+ clk_prcmu_ops.disable = NULL;
+ clk_prcc_ops.enable = NULL;
+ clk_prcc_ops.disable = NULL;
+ }
+
+ clks_register(u8500_common_clkregs, ARRAY_SIZE(u8500_common_clkregs));
+
+ if (cpu_is_u8500ed())
+ clks_register(u8500_ed_clkregs, ARRAY_SIZE(u8500_ed_clkregs));
+ else
+ clks_register(u8500_v1_clkregs, ARRAY_SIZE(u8500_v1_clkregs));
+
+ if (cpu_is_u8500() && !cpu_is_u8500ed())
+ u8500_amba_clk_enable();
+
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+static LIST_HEAD(clocks);
+static DEFINE_MUTEX(clocks_mutex);
+
+static void clk_register(struct clk *clk)
+{
+ mutex_lock(&clocks_mutex);
+
+ /* Ignore duplicate clocks */
+ if (clk->list.prev != NULL || clk->list.next != NULL) {
+ mutex_unlock(&clocks_mutex);
+ return;
+ }
+
+ list_add(&clk->list, &clocks);
+ mutex_unlock(&clocks_mutex);
+}
+
+/*
+ * The following makes it possible to view the status (especially reference
+ * count and reset status) for the clocks in the platform by looking into the
+ * special file <debugfs>/u8500_clocks
+ */
+static void *u8500_clocks_start(struct seq_file *m, loff_t *pos)
+{
+ return *pos < 1 ? (void *)1 : NULL;
+}
+
+static void *u8500_clocks_next(struct seq_file *m, void *v, loff_t *pos)
+{
+ ++*pos;
+ return NULL;
+}
+
+static void u8500_clocks_stop(struct seq_file *m, void *v)
+{
+}
+
+static int u8500_clocks_show(struct seq_file *m, void *v)
+{
+ struct clk *clk;
+
+ list_for_each_entry(clk, &clocks, list) {
+ struct clk *child;
+ bool first = true;
+
+ seq_printf(m, "%-11s %d", clk->name, clk->enabled);
+
+ list_for_each_entry(child, &clocks, list) {
+ if (!child->enabled)
+ continue;
+
+ if (child->parent_cluster == clk ||
+ child->parent_periph == clk) {
+ if (first) {
+ first = false;
+ seq_printf(m, "\t[active children:");
+ }
+
+ seq_printf(m, " %s", child->name);
+ }
+ }
+
+ seq_printf(m, "%s\n", first ? "" : "]");
+ }
+
+ printk(KERN_INFO "Periph1 PCKEN : 0x%x\n",
+ readl(IO_ADDRESS(U8500_PER1_BASE + 0xF000 + 0x10)));
+ printk(KERN_INFO "Periph1 KCKEN : 0x%x\n",
+ readl(IO_ADDRESS(U8500_PER1_BASE + 0xF000 + 0x14)));
+ printk(KERN_INFO "Periph2 PCKEN : 0x%x\n",
+ readl(IO_ADDRESS(U8500_PER2_BASE + 0xF000 + 0x10)));
+ printk(KERN_INFO "Periph2 KCKEN : 0x%x\n",
+ readl(IO_ADDRESS(U8500_PER2_BASE + 0xF000 + 0x14)));
+ printk(KERN_INFO "Periph3 PCKEN : 0x%x\n",
+ readl(IO_ADDRESS(U8500_PER3_BASE + 0xF000 + 0x10)));
+ printk(KERN_INFO "Periph3 KCKEN : 0x%x\n",
+ readl(IO_ADDRESS(U8500_PER3_BASE + 0xF000 + 0x14)));
+ printk(KERN_INFO "Periph5 PCKEN : 0x%x\n",
+ readl(IO_ADDRESS(U8500_PER5_BASE + 0x1F000 + 0x10)));
+ printk(KERN_INFO "Periph5 KCKEN : 0x%x\n",
+ readl(IO_ADDRESS(U8500_PER5_BASE + 0x1F000 + 0x14)));
+ printk(KERN_INFO "Periph6 PCKEN : 0x%x\n",
+ readl(IO_ADDRESS(U8500_PER6_BASE + 0xF000 + 0x10)));
+ printk(KERN_INFO "Periph6 KCKEN : 0x%x\n",
+ readl(IO_ADDRESS(U8500_PER6_BASE + 0xF000 + 0x14)));
+
+ return 0;
+}
+
+static const struct seq_operations u8500_clocks_op = {
+ .start = u8500_clocks_start,
+ .next = u8500_clocks_next,
+ .stop = u8500_clocks_stop,
+ .show = u8500_clocks_show
+};
+
+static int u8500_clocks_open(struct inode *inode, struct file *file)
+{
+ return seq_open(file, &u8500_clocks_op);
+}
+
+static const struct file_operations u8500_clocks_operations = {
+ .open = u8500_clocks_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = seq_release,
+};
+
+static int __init init_clk_read_debugfs(void)
+{
+ /* Expose a simple debugfs interface to view all clocks */
+ (void) debugfs_create_file("u8500_clocks", S_IFREG | S_IRUGO,
+ NULL, NULL, &u8500_clocks_operations);
+ return 0;
+}
+/*
+ * This needs to come in after the arch_initcall() for the
+ * overall clocks, because debugfs is not available until
+ * the subsystems come up.
+ */
+module_init(init_clk_read_debugfs);
+#else
+static void clk_register(struct clk *clk) { }
+#endif
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
new file mode 100755
index 00000000000..bcf246dcfa4
--- /dev/null
+++ b/arch/arm/mach-ux500/clock.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) ST Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+extern int __init clk_init(void);
+
+struct clkops {
+ void (*enable) (struct clk *);
+ void (*disable) (struct clk *);
+ unsigned long (*get_rate) (struct clk *);
+};
+
+struct clk {
+ const struct clkops *ops;
+ const char *name;
+ unsigned int enabled;
+
+ unsigned long rate;
+ struct list_head list;
+
+ /* These three are only for PRCMU clks */
+
+ unsigned int prcmu_cg_off;
+ unsigned int prcmu_cg_bit;
+ void __iomem *prcmu_cg_mgt;
+
+ /* The rest are only for PRCC clks */
+
+ void __iomem *prcc_base;
+ unsigned int prcc_bus;
+ unsigned int prcc_kernel;
+
+ struct clk *parent_cluster;
+ struct clk *parent_periph;
+};
+
+#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \
+struct clk clk_##_name = { \
+ .name = #_name, \
+ .ops = &clk_prcmu_ops, \
+ .prcmu_cg_off = _cg_off, \
+ .prcmu_cg_bit = _cg_bit, \
+ .prcmu_cg_mgt = (void __iomem *)PRCM_##_reg##_MGT \
+ }
+
+#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate) \
+struct clk clk_##_name = { \
+ .name = #_name, \
+ .ops = &clk_prcmu_ops, \
+ .prcmu_cg_off = _cg_off, \
+ .prcmu_cg_bit = _cg_bit, \
+ .rate = _rate, \
+ .prcmu_cg_mgt = (void __iomem *)PRCM_##_reg##_MGT \
+ }
+
+#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk) \
+struct clk clk_##_name = { \
+ .name = #_name, \
+ .ops = &clk_prcc_ops, \
+ .prcc_base = (void __iomem *)IO_ADDRESS(U8500_CLKRST##_pclust##_BASE), \
+ .prcc_bus = _bus_en, \
+ .prcc_kernel = _kernel_en, \
+ .parent_cluster = &clk_per##_pclust##clk, \
+ .parent_periph = _kernclk \
+ }
+
+#define CLK(_clk, _devname, _conname) \
+ { \
+ .clk = &clk_##_clk, \
+ .dev_id = _devname, \
+ .con_id = _conname, \
+ }
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
new file mode 100644
index 00000000000..3c4adac835b
--- /dev/null
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/amba/bus.h>
+#include <linux/io.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/devices.h>
+#include <mach/setup.h>
+
+static struct map_desc u5500_io_desc[] __initdata = {
+ __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K),
+ __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K),
+ __IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K),
+ __IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K),
+ __IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K),
+};
+
+static struct amba_device *u5500_amba_devs[] __initdata = {
+ &u5500_gpio0_device,
+ &u5500_gpio1_device,
+ &u5500_gpio2_device,
+ &u5500_gpio3_device,
+ &u5500_gpio4_device,
+};
+
+void __init u5500_map_io(void)
+{
+ ux500_map_io();
+
+ iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc));
+}
+
+void __init u5500_init_devices(void)
+{
+ ux500_init_devices();
+
+ amba_add_devices(u5500_amba_devs, ARRAY_SIZE(u5500_amba_devs));
+}
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
new file mode 100644
index 00000000000..fb7def59b22
--- /dev/null
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/amba/bus.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/devices.h>
+#include <mach/setup.h>
+
+static struct map_desc u8500_io_desc[] __initdata = {
+ __IO_DEV_DESC(U8500_MSP0_BASE, SZ_4K),
+ __IO_DEV_DESC(U8500_MSP1_BASE, SZ_4K),
+ __IO_DEV_DESC(U8500_MSP2_BASE, SZ_4K),
+ __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
+ __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
+ __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
+ __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
+ __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
+ __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
+};
+
+static struct map_desc u8500_ed_io_desc[] __initdata = {
+ __IO_DEV_DESC(U8500_CLKRST7_BASE, SZ_4K),
+ __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K),
+ __IO_DEV_DESC(U8500_MTU1_BASE_ED, SZ_4K),
+};
+
+static struct amba_device *u8500_amba_devs[] __initdata = {
+ &u8500_gpio0_device,
+ &u8500_gpio1_device,
+ &u8500_gpio2_device,
+ &u8500_gpio3_device,
+};
+
+void __init u8500_map_io(void)
+{
+ ux500_map_io();
+
+ iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
+ if (cpu_is_u8500ed())
+ iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc));
+}
+
+static void __init u8500_earlydrop_fixup(void)
+{
+ ux500_dma_device.resource[0].start = U8500_DMA_BASE_ED;
+ ux500_dma_device.resource[0].end = U8500_DMA_BASE_ED + SZ_4K - 1;
+ u8500_shrm_device.resource[1].start = IRQ_CA_WAKE_REQ_ED;
+ u8500_shrm_device.resource[1].end = IRQ_CA_WAKE_REQ_ED;
+ u8500_shrm_device.resource[2].start = IRQ_AC_READ_NOTIFICATION_0_ED;
+ u8500_shrm_device.resource[2].end = IRQ_AC_READ_NOTIFICATION_0_ED;
+ u8500_shrm_device.resource[3].start = IRQ_AC_READ_NOTIFICATION_1_ED;
+ u8500_shrm_device.resource[3].end = IRQ_AC_READ_NOTIFICATION_1_ED;
+ u8500_shrm_device.resource[4].start = IRQ_CA_MSG_PEND_NOTIFICATION_0_ED;
+ u8500_shrm_device.resource[4].end = IRQ_CA_MSG_PEND_NOTIFICATION_0_ED;
+ u8500_shrm_device.resource[5].start = IRQ_CA_MSG_PEND_NOTIFICATION_1_ED;
+ u8500_shrm_device.resource[5].end = IRQ_CA_MSG_PEND_NOTIFICATION_1_ED;
+}
+
+void __init u8500_init_devices(void)
+{
+ if (u8500_is_earlydrop())
+ u8500_earlydrop_fixup();
+
+ ux500_init_devices();
+
+ amba_add_devices(u8500_amba_devs, ARRAY_SIZE(u8500_amba_devs));
+}
diff --git a/arch/arm/mach-ux500/cpufreq.c b/arch/arm/mach-ux500/cpufreq.c
new file mode 100755
index 00000000000..54f37e30c4c
--- /dev/null
+++ b/arch/arm/mach-ux500/cpufreq.c
@@ -0,0 +1,163 @@
+/*
+ * CPU frequency module for U8500
+ *
+ * Copyright 2009 STMicroelectronics.
+ * Copyright 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+#include <linux/cpufreq.h>
+#include <linux/delay.h>
+
+#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu-regs.h>
+
+static struct cpufreq_frequency_table freq_table[] = {
+ {
+ .index = 0,
+ .frequency = 200000,
+ },
+ {
+ .index = 1,
+ .frequency = 300000,
+ },
+ {
+ .index = 2,
+ .frequency = 600000,
+ },
+ {
+ .index = 3,
+ .frequency = CPUFREQ_TABLE_END
+ }
+};
+
+static struct freq_attr *u8500_cpufreq_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ NULL,
+};
+
+int u8500_verify_speed(struct cpufreq_policy *policy)
+{
+ return cpufreq_frequency_table_verify(policy, freq_table);
+}
+
+static int u8500_target(struct cpufreq_policy *policy, unsigned int target_freq,
+ unsigned int relation)
+{
+ struct cpufreq_freqs freqs;
+ unsigned int idx;
+ enum arm_opp_t op;
+
+
+ /* scale the target frequency to one of the extremes supported */
+ if (target_freq < policy->cpuinfo.min_freq)
+ target_freq = policy->cpuinfo.min_freq;
+ if (target_freq > policy->cpuinfo.max_freq)
+ target_freq = policy->cpuinfo.max_freq;
+
+ /* Lookup the next frequency */
+ if (cpufreq_frequency_table_target
+ (policy, freq_table, target_freq, relation, &idx)) {
+ return -EINVAL;
+ }
+
+ freqs.old = policy->cur;
+ freqs.new = freq_table[idx].frequency;
+ freqs.cpu = policy->cpu;
+
+ /* pre-change notification */
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+ switch (idx) {
+ case 0:
+ op = ARM_EXTCLK; break;
+ case 1:
+ op = ARM_50_OPP; break;
+ case 2:
+ op = ARM_100_OPP; break;
+ default:
+ printk(KERN_INFO "u8500-cpufreq : Error in OPP\n");
+ return -EINVAL;
+ }
+
+ /* request the PRCM unit for opp change */
+ if (prcmu_set_arm_opp(op))
+ return -EINVAL;
+
+ /* post change notification */
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+ return 0;
+}
+
+unsigned int u8500_getspeed(unsigned int cpu)
+{
+ /* request the prcm to get the current ARM opp */
+ enum arm_opp_t opp = prcmu_get_arm_opp();
+
+ switch (opp) {
+ case ARM_EXTCLK: return freq_table[0].frequency;
+ case ARM_50_OPP: return freq_table[1].frequency;
+ case ARM_100_OPP: return freq_table[2].frequency;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int __cpuinit u8500_cpu_init(struct cpufreq_policy *policy)
+{
+ int res;
+
+ /* get policy fields based on the table */
+ res = cpufreq_frequency_table_cpuinfo(policy, freq_table);
+ if (!res)
+ cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
+ else {
+ printk(KERN_INFO "u8500-cpufreq : Null CPUFreq Tables!!!\n");
+ return -EINVAL;
+ }
+
+ policy->min = policy->cpuinfo.min_freq;
+ policy->max = policy->cpuinfo.max_freq;
+ policy->cur = u8500_getspeed(policy->cpu);
+
+ policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+
+ /* FIXME : Need to take time measurement across the target()
+ * function with no/some/all drivers in the notification
+ * list.
+ */
+ policy->cpuinfo.transition_latency = 200 * 1000; /* in ns */
+
+ /* policy->cpus = cpu_possible_map; TODO will cpufreq.c do this? */
+
+ policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
+
+ return res;
+}
+
+static int u8500_cpu_exit(struct cpufreq_policy *policy)
+{
+ return 0;
+}
+
+static struct cpufreq_driver u8500_driver = {
+ .flags = CPUFREQ_STICKY,
+ .verify = u8500_verify_speed,
+ .target = u8500_target,
+ .get = u8500_getspeed,
+ .init = u8500_cpu_init,
+ .exit = u8500_cpu_exit,
+ .name = "U8500",
+ .attr = u8500_cpufreq_attr,
+};
+
+static int __init u8500_cpufreq_init(void)
+{
+ return cpufreq_register_driver(&u8500_driver);
+}
+
+device_initcall(u8500_cpufreq_init);
diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c
new file mode 100755
index 00000000000..98409ea1c43
--- /dev/null
+++ b/arch/arm/mach-ux500/cpuidle.c
@@ -0,0 +1,246 @@
+/*
+ * CPU idle module for U8500
+ *
+ * Copyright 2009 STMicroelectronics.
+ * Copyright 2009 ST-Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+/* CPUIdle driver for U8500 */
+
+#include <linux/module.h>
+#include <linux/hrtimer.h>
+#include <linux/sched.h>
+#include <linux/clockchips.h>
+#include <mach/prcmu-fw-api.h>
+#include "cpuidle.h"
+
+struct u8500_cstate u8500_cstates[U8500_NUM_CSTATES] = {
+ {
+ .type = U8500_CSTATE_C0,
+ .sleep_latency = 0,
+ .wakeup_latency = 0,
+ .threshold = 0,
+ .power_usage = -1,
+ .flags = CPUIDLE_FLAG_SHALLOW | CPUIDLE_FLAG_TIME_VALID,
+ .desc = "C0 - running",
+ },
+ {
+ .type = U8500_CSTATE_C1,
+ .sleep_latency = 10,
+ .wakeup_latency = 10,
+ .threshold = 10,
+ .power_usage = 10,
+ .flags = CPUIDLE_FLAG_SHALLOW | CPUIDLE_FLAG_TIME_VALID,
+ .desc = "C1 - wait for interrupt",
+ },
+ {
+ .type = U8500_CSTATE_C2,
+ .sleep_latency = 50,
+ .wakeup_latency = 50,
+ .threshold = 20000,
+ .power_usage = 5,
+ .flags = CPUIDLE_FLAG_SHALLOW | CPUIDLE_FLAG_TIME_VALID,
+ .desc = "C2 - WFI-Retention",
+ },
+};
+
+DEFINE_PER_CPU(struct cpuidle_device, u8500_cpuidle_dev);
+DEFINE_PER_CPU(int, u8500_cpu_in_wfi) = {0};
+
+struct cpuidle_driver u8500_cpuidle_drv = {
+ .name = "U8500_CPUIdle",
+ .owner = THIS_MODULE,
+};
+
+static void do_nothing(void *unused)
+{
+}
+
+/*
+ * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
+ * pm_idle and update to new pm_idle value. Required while changing pm_idle
+ * handler on SMP systems.
+ *
+ * Caller must have changed pm_idle to the new value before the call. Old
+ * pm_idle value will not be used by any CPU after the return of this function.
+ */
+void cpu_idle_wait(void)
+{
+ smp_mb();
+ /* kick all the CPUs so that they exit out of pm_idle */
+ smp_call_function(do_nothing, NULL, 1);
+}
+EXPORT_SYMBOL_GPL(cpu_idle_wait);
+
+static int poll_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
+{
+ ktime_t t1, t2;
+ s64 diff;
+ int ret;
+ t1 = ktime_get();
+ local_irq_enable();
+ while (!need_resched())
+ cpu_relax();
+
+ t2 = ktime_get();
+ diff = ktime_to_us(ktime_sub(t2, t1));
+ if (diff > INT_MAX)
+ diff = INT_MAX;
+
+ ret = (int)diff;
+ return ret;
+}
+
+static int wfi_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
+{
+ ktime_t t1, t2;
+ s64 diff;
+ int ret;
+
+ t1 = ktime_get();
+
+ __asm__ __volatile__("dsb\n\t" "wfi\n\t" : : : "memory");
+
+ t2 = ktime_get();
+ diff = ktime_to_us(ktime_sub(t2, t1));
+ if (diff > INT_MAX)
+ diff = INT_MAX;
+
+ ret = (int)diff;
+ return ret;
+}
+
+static int wfi_retention_idle(struct cpuidle_device *dev,
+ struct cpuidle_state *state)
+{
+ ktime_t t1, t2;
+ s64 diff;
+ int ret, cpu, i = 0;
+
+ t1 = ktime_get();
+
+ per_cpu(u8500_cpu_in_wfi, smp_processor_id()) = 1;
+ smp_wmb();
+
+ cpu = smp_processor_id();
+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
+
+ for_each_online_cpu(cpu)
+ if (per_cpu(u8500_cpu_in_wfi, cpu) == 1)
+ i++;
+
+ if (i == num_online_cpus())
+ prcmu_apply_ap_state_transition(APEXECUTE_TO_APIDLE,
+ DDR_PWR_STATE_UNCHANGED, 0);
+ else {
+ __asm__ __volatile__("dsb\n\t" "wfi\n\t" : : : "memory");
+ }
+
+ local_irq_disable();
+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
+ local_irq_enable();
+
+ per_cpu(u8500_cpu_in_wfi, smp_processor_id()) = 0;
+ smp_wmb();
+
+ t2 = ktime_get();
+ diff = ktime_to_us(ktime_sub(t2, t1));
+ if (diff > INT_MAX)
+ diff = INT_MAX;
+
+ ret = (int)diff;
+ return ret;
+
+}
+
+static int u8500_enter_idle(struct cpuidle_device *dev,
+ struct cpuidle_state *state)
+{
+ struct u8500_cstate *cstate;
+ int ret = 0;
+ cstate = cpuidle_get_statedata(state);
+
+ if (cstate->type == U8500_CSTATE_C1)
+ ret = wfi_idle(dev, state);
+
+ if (cstate->type == U8500_CSTATE_C2)
+ ret = wfi_retention_idle(dev, state);
+
+ if (cstate->type == U8500_CSTATE_C0)
+ ret = poll_idle(dev, state);
+
+ return ret;
+}
+
+static void u8500_cpu_cstate_init(unsigned int cpu)
+{
+ struct cpuidle_device *dev;
+ struct u8500_cstate *cstate;
+ struct cpuidle_state *state;
+ int i;
+
+ printk("Initializing CPUIdle for CPU%d...\n", cpu);
+ dev = &per_cpu(u8500_cpuidle_dev, cpu);
+ dev->cpu = cpu;
+ for (i = 0; i < U8500_NUM_CSTATES; i++) {
+ cstate = &u8500_cstates[i];
+ state = &dev->states[i];
+
+ cpuidle_set_statedata(state, cstate);
+
+ state->exit_latency =
+ cstate->sleep_latency + cstate->wakeup_latency;
+ state->target_residency = cstate->threshold;
+ state->flags = cstate->flags;
+ state->enter = u8500_enter_idle;
+ state->power_usage = cstate->power_usage;
+ snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i);
+ strncpy(state->desc, cstate->desc, CPUIDLE_DESC_LEN);
+ }
+
+ dev->state_count = U8500_NUM_CSTATES;
+
+ if (dev->state_count >= 2)
+ dev->safe_state = &dev->states[1];
+ else
+ dev->safe_state = &dev->states[0];
+
+ if (cpuidle_register_device(dev)) {
+ printk(KERN_ERR "%s: CPUidle register device failed\n",
+ __func__);
+ }
+
+}
+
+static int __init u8500_cpuidle_init(void)
+{
+ int result = 0;
+ unsigned int cpu;
+
+ result = cpuidle_register_driver(&u8500_cpuidle_drv);
+ if (result < 0)
+ goto out;
+
+ /* TODO: pass a per-cpu var to get the return value of
+ cpuidle_register_device */
+ /* on_each_cpu(u8500_cpu_cstate_init, NULL, 0); */
+ for_each_online_cpu(cpu)
+ u8500_cpu_cstate_init(cpu);
+ out:
+ return result;
+}
+static void __exit u8500_cpuidle_exit(void)
+{
+ /* TODO: disable cpuidle devices & unregister driver */
+}
+
+module_init(u8500_cpuidle_init);
+module_exit(u8500_cpuidle_exit);
+
+MODULE_DESCRIPTION("U8500 CPUIdle driver");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("STMicroelectronics");
diff --git a/arch/arm/mach-ux500/cpuidle.h b/arch/arm/mach-ux500/cpuidle.h
new file mode 100755
index 00000000000..bfa5221a718
--- /dev/null
+++ b/arch/arm/mach-ux500/cpuidle.h
@@ -0,0 +1,34 @@
+/*
+ * CPU frequency module for U8500
+ *
+ * Copyright 2009 STMicroelectronics.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+#ifndef __U8500_CPUIDLE_H
+#define __U8500_CPUIDLE_H
+
+#include <linux/cpuidle.h>
+
+#define U8500_NUM_CSTATES 3
+
+#define U8500_CSTATE_C0 0 /* running */
+#define U8500_CSTATE_C1 1 /* wfi */
+#define U8500_CSTATE_C2 2 /* wfi or wfi retention */
+
+/* this is the c-state template structure used to populate the cpuidle
+ * c-states for all cpu's */
+
+struct u8500_cstate {
+ u8 type;
+ u32 sleep_latency;
+ u32 wakeup_latency;
+ u32 threshold;
+ u32 power_usage;
+ u32 flags;
+ char desc[CPUIDLE_DESC_LEN];
+};
+
+#endif
diff --git a/arch/arm/mach-ux500/db5500-devices.c b/arch/arm/mach-ux500/db5500-devices.c
new file mode 100644
index 00000000000..8ba9fb86cb4
--- /dev/null
+++ b/arch/arm/mach-ux500/db5500-devices.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/amba/bus.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+
+/* gpio alternate funtions on this platform */
+#define __GPIO_ALT(_fun, _start, _end, _cont, _type, _name) { \
+ .altfun = _fun, \
+ .start = _start, \
+ .end = _end, \
+ .cont = _cont, \
+ .type = _type, \
+ .dev_name = _name }
+
+static struct gpio_altfun_data gpio_altfun_table[] = {
+ __GPIO_ALT(GPIO_ALT_I2C_4, 4, 5, 0, GPIO_ALTF_B, "i2c4"),
+ __GPIO_ALT(GPIO_ALT_I2C_1, 16, 17, 0, GPIO_ALTF_B, "i2c1"),
+ __GPIO_ALT(GPIO_ALT_I2C_2, 8, 9, 0, GPIO_ALTF_B, "i2c2"),
+ __GPIO_ALT(GPIO_ALT_I2C_0, 147, 148, 0, GPIO_ALTF_A, "i2c0"),
+ __GPIO_ALT(GPIO_ALT_I2C_3, 229, 230, 0, GPIO_ALTF_C, "i2c3"),
+ __GPIO_ALT(GPIO_ALT_UART_2, 177, 180, 0, GPIO_ALTF_A, "uart2"),
+ __GPIO_ALT(GPIO_ALT_SSP_0, 143, 146, 0, GPIO_ALTF_A, "ssp0"),
+ __GPIO_ALT(GPIO_ALT_SSP_1, 139, 142, 0, GPIO_ALTF_A, "ssp1"),
+ __GPIO_ALT(GPIO_ALT_USB_OTG, 256, 267, 0, GPIO_ALTF_A, "usb"),
+ __GPIO_ALT(GPIO_ALT_UART_1, 200, 203, 0, GPIO_ALTF_A, "uart1"),
+ __GPIO_ALT(GPIO_ALT_UART_0_NO_MODEM, 28, 29, 0, GPIO_ALTF_A, "uart0"),
+ __GPIO_ALT(GPIO_ALT_MSP_0, 12, 15, 0, GPIO_ALTF_A, "msp0"),
+ __GPIO_ALT(GPIO_ALT_MSP_1, 33, 36, 0, GPIO_ALTF_A, "msp1"),
+ __GPIO_ALT(GPIO_ALT_MSP_2, 192, 196, 0, GPIO_ALTF_A, "msp2"),
+ __GPIO_ALT(GPIO_ALT_HSIR, 219, 221, 0, GPIO_ALTF_A, "hsir"),
+ __GPIO_ALT(GPIO_ALT_HSIT, 222, 224, 0, GPIO_ALTF_A, "hsit"),
+ __GPIO_ALT(GPIO_ALT_EMMC, 197, 207, 0, GPIO_ALTF_A, "emmc"),
+ __GPIO_ALT(GPIO_ALT_SDMMC, 18, 28, 0, GPIO_ALTF_A, "sdmmc"),
+ __GPIO_ALT(GPIO_ALT_SDIO, 208, 214, 0, GPIO_ALTF_A, "sdio"),
+ __GPIO_ALT(GPIO_ALT_TRACE, 70, 74, 0, GPIO_ALTF_C, "stm"),
+ __GPIO_ALT(GPIO_ALT_SDMMC2, 128, 138, 0, GPIO_ALTF_A, "mmc2"),
+#ifndef CONFIG_FB_NOMADIK_MCDE_CHANNELB_DISPLAY_VUIB_WVGA
+ __GPIO_ALT(GPIO_ALT_LCD_PANELB_ED, 78, 85, 1, GPIO_ALTF_A, "mcde tvout"),
+ __GPIO_ALT(GPIO_ALT_LCD_PANELB_ED, 150, 150, 0, GPIO_ALTF_B, "mcde tvout"),
+ __GPIO_ALT(GPIO_ALT_LCD_PANELB, 78, 81, 1, GPIO_ALTF_A, "mcde tvout"),
+ __GPIO_ALT(GPIO_ALT_LCD_PANELB, 150, 150, 0, GPIO_ALTF_B, "mcde tvout"),
+#else
+ __GPIO_ALT(GPIO_ALT_LCD_PANELB, 153, 171, 1, GPIO_ALTF_B, "mcde tvout"),
+ __GPIO_ALT(GPIO_ALT_LCD_PANELB, 64, 77, 0, GPIO_ALTF_A, "mcde tvout"),
+#endif
+ __GPIO_ALT(GPIO_ALT_LCD_PANELA, 68, 68, 0, GPIO_ALTF_A, "mcde tvout"),
+ __GPIO_ALT(GPIO_ALT_MMIO_INIT_BOARD, 141, 142, 0, GPIO_ALTF_B, "mmio"),
+ __GPIO_ALT(GPIO_ALT_MMIO_CAM_SET_I2C, 8, 9, 0, GPIO_ALTF_A, "mmio"),
+ __GPIO_ALT(GPIO_ALT_MMIO_CAM_SET_EXT_CLK, 227, 228, 0, GPIO_ALTF_A, "mmio"),
+#ifdef CONFIG_TOUCHP_EXT_CLK
+ __GPIO_ALT(GPIO_ALT_TP_SET_EXT_CLK, 228, 228, 0, GPIO_ALTF_A, "u8500_tp1"),
+#endif
+};
+
+static struct gpio_block_data gpio0_block_data[] = {
+ {
+ .irq = IRQ_GPIO0,
+ .base_offset = 0x0,
+ .blocks_per_irq = 1,
+ .block_base = 0,
+ .block_size = 32,
+ },
+ {
+ .irq = IRQ_GPIO1,
+ .base_offset = 0x080,
+ .blocks_per_irq = 1,
+ .block_base = 32,
+ .block_size = 4,
+ },
+};
+
+static struct gpio_platform_data gpio0_platform_data = {
+ .gpio_data = gpio0_block_data,
+ .gpio_block_size = ARRAY_SIZE(gpio0_block_data),
+ .altfun_table = gpio_altfun_table,
+ .altfun_table_size = ARRAY_SIZE(gpio_altfun_table)
+};
+
+struct amba_device u5500_gpio0_device = {
+ .dev = {
+ .bus_id = "gpioblock0",
+ .platform_data = &gpio0_platform_data,
+ },
+ .res = {
+ .start = U5500_GPIO0_BASE,
+ .end = U5500_GPIO0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .periphid = GPIO_PER_ID,
+ .irq = {IRQ_GPIO0, NO_IRQ},
+};
+
+static struct gpio_block_data gpio1_block_data[] = {
+ {
+ .irq = IRQ_GPIO2,
+ .base_offset = 0x0,
+ .blocks_per_irq = 1,
+ .block_base = 64,
+ .block_size = 19,
+ }
+};
+
+static struct gpio_platform_data gpio1_platform_data = {
+ .gpio_data = gpio1_block_data,
+ .gpio_block_size = ARRAY_SIZE(gpio1_block_data),
+ .altfun_table = gpio_altfun_table,
+ .altfun_table_size = ARRAY_SIZE(gpio_altfun_table)
+
+};
+
+struct amba_device u5500_gpio1_device = {
+ .dev = {
+ .bus_id = "gpioblock1",
+ .platform_data = &gpio1_platform_data,
+ },
+ .res = {
+ .start = U5500_GPIO1_BASE,
+ .end = U5500_GPIO1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .periphid = GPIO_PER_ID,
+ .irq = {IRQ_GPIO2, NO_IRQ},
+};
+
+static struct gpio_block_data gpio2_block_data[] = {
+ {
+ .irq = IRQ_GPIO3,
+ .base_offset = 0x0,
+ .blocks_per_irq = 1,
+ .block_base = 96,
+ .block_size = 6,
+ }
+};
+
+static struct gpio_platform_data gpio2_platform_data = {
+ .gpio_data = gpio2_block_data,
+ .gpio_block_size = ARRAY_SIZE(gpio2_block_data),
+ .altfun_table = gpio_altfun_table,
+ .altfun_table_size = ARRAY_SIZE(gpio_altfun_table)
+};
+
+struct amba_device u5500_gpio2_device = {
+ .dev = {
+ .bus_id = "gpioblock2",
+ .platform_data = &gpio2_platform_data,
+ },
+ .res = {
+ .start = U5500_GPIO2_BASE,
+ .end = U5500_GPIO2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .periphid = GPIO_PER_ID,
+ .irq = {IRQ_GPIO3, NO_IRQ},
+};
+
+static struct gpio_block_data gpio3_block_data[] = {
+ {
+ .irq = IRQ_GPIO4,
+ .base_offset = 0x0,
+ .blocks_per_irq = 1,
+ .block_base = 128,
+ .block_size = 21,
+ }
+};
+
+static struct gpio_platform_data gpio3_platform_data = {
+ .gpio_data = gpio3_block_data,
+ .gpio_block_size = ARRAY_SIZE(gpio3_block_data),
+ .altfun_table = gpio_altfun_table,
+ .altfun_table_size = ARRAY_SIZE(gpio_altfun_table)
+
+};
+
+struct amba_device u5500_gpio3_device = {
+ .dev = {
+ .bus_id = "gpioblock3",
+ .platform_data = &gpio3_platform_data,
+ },
+ .res = {
+ .start = U5500_GPIO3_BASE,
+ .end = U5500_GPIO3_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .periphid = GPIO_PER_ID,
+ .irq = {IRQ_GPIO4, NO_IRQ},
+};
+
+static struct gpio_block_data gpio4_block_data[] = {
+ {
+ .irq = IRQ_GPIO5,
+ .base_offset = 0x0,
+ .blocks_per_irq = 1,
+ .block_base = 160,
+ .block_size = 32,
+ },
+ {
+ .irq = IRQ_GPIO6,
+ .base_offset = 0x80,
+ .blocks_per_irq = 1,
+ .block_base = 192,
+ .block_size = 32,
+ },
+ {
+ .irq = IRQ_GPIO7,
+ .base_offset = 0x100,
+ .blocks_per_irq = 1,
+ .block_base = 224,
+ .block_size = 4,
+ }
+};
+static struct gpio_platform_data gpio4_platform_data = {
+ .gpio_data = gpio4_block_data,
+ .gpio_block_size = ARRAY_SIZE(gpio4_block_data),
+ .altfun_table = gpio_altfun_table,
+ .altfun_table_size = ARRAY_SIZE(gpio_altfun_table)
+
+};
+struct amba_device u5500_gpio4_device = {
+ .dev = {
+ .bus_id = "gpioblock4",
+ .platform_data = &gpio4_platform_data,
+ },
+ .res = {
+ .start = U5500_GPIO4_BASE,
+ .end = U5500_GPIO4_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .periphid = GPIO_PER_ID,
+ .irq = {IRQ_GPIO5, NO_IRQ},
+};
diff --git a/arch/arm/mach-ux500/db8500-devices.c b/arch/arm/mach-ux500/db8500-devices.c
new file mode 100644
index 00000000000..4bba6684bbb
--- /dev/null
+++ b/arch/arm/mach-ux500/db8500-devices.c
@@ -0,0 +1,327 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/amba/bus.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/spi/spi.h>
+
+#include <mach/dma.h>
+#include <linux/spi/spi-stm.h>
+
+/* gpio alternate funtions on this platform */
+#define __GPIO_ALT(_fun, _start, _end, _cont, _type, _name) { \
+ .altfun = _fun, \
+ .start = _start, \
+ .end = _end, \
+ .cont = _cont, \
+ .type = _type, \
+ .dev_name = _name }
+
+static struct gpio_altfun_data gpio_altfun_table[] = {
+ __GPIO_ALT(GPIO_ALT_I2C_4, 4, 5, 0, GPIO_ALTF_B, "i2c4"),
+ __GPIO_ALT(GPIO_ALT_I2C_1, 16, 17, 0, GPIO_ALTF_B, "i2c1"),
+ __GPIO_ALT(GPIO_ALT_I2C_2, 8, 9, 0, GPIO_ALTF_B, "i2c2"),
+ __GPIO_ALT(GPIO_ALT_I2C_0, 147, 148, 0, GPIO_ALTF_A, "i2c0"),
+ __GPIO_ALT(GPIO_ALT_I2C_3, 229, 230, 0, GPIO_ALTF_C, "i2c3"),
+ __GPIO_ALT(GPIO_ALT_UART_2, 29, 32, 0, GPIO_ALTF_C, "uart2"),
+ __GPIO_ALT(GPIO_ALT_SSP_0, 143, 146, 0, GPIO_ALTF_A, "ssp0"),
+ __GPIO_ALT(GPIO_ALT_SSP_1, 139, 142, 0, GPIO_ALTF_A, "ssp1"),
+ __GPIO_ALT(GPIO_ALT_USB_OTG, 256, 267, 0, GPIO_ALTF_A, "usb"),
+ __GPIO_ALT(GPIO_ALT_UART_1, 4, 7, 0, GPIO_ALTF_A, "uart1"),
+ __GPIO_ALT(GPIO_ALT_UART_0_NO_MODEM, 0, 3, 0, GPIO_ALTF_A, "uart0"),
+ __GPIO_ALT(GPIO_ALT_UART_0_MODEM, 0, 3, 1, GPIO_ALTF_A, "uart0"),
+ __GPIO_ALT(GPIO_ALT_UART_0_MODEM, 33, 36, 0, GPIO_ALTF_C, "uart0"),
+ __GPIO_ALT(GPIO_ALT_MSP_0, 12, 15, 0, GPIO_ALTF_A, "msp0"),
+ __GPIO_ALT(GPIO_ALT_MSP_1, 33, 36, 0, GPIO_ALTF_A, "msp1"),
+ __GPIO_ALT(GPIO_ALT_MSP_2, 192, 196, 0, GPIO_ALTF_A, "msp2"),
+ __GPIO_ALT(GPIO_ALT_HSIR, 219, 221, 0, GPIO_ALTF_A, "hsir"),
+ __GPIO_ALT(GPIO_ALT_HSIT, 222, 224, 0, GPIO_ALTF_A, "hsit"),
+ __GPIO_ALT(GPIO_ALT_EMMC, 197, 207, 0, GPIO_ALTF_A, "emmc"),
+ __GPIO_ALT(GPIO_ALT_SDMMC, 18, 28, 0, GPIO_ALTF_A, "sdmmc"),
+ __GPIO_ALT(GPIO_ALT_SDIO, 208, 214, 0, GPIO_ALTF_A, "sdio"),
+ __GPIO_ALT(GPIO_ALT_TRACE, 70, 74, 0, GPIO_ALTF_C, "stm"),
+ __GPIO_ALT(GPIO_ALT_SDMMC2, 128, 138, 0, GPIO_ALTF_A, "mmc2"),
+#ifndef CONFIG_FB_NOMADIK_MCDE_CHANNELB_DISPLAY_VUIB_WVGA
+ __GPIO_ALT(GPIO_ALT_LCD_PANELB_ED, 78, 85, 1, GPIO_ALTF_A, "mcde tvout"),
+ __GPIO_ALT(GPIO_ALT_LCD_PANELB_ED, 150, 150, 0, GPIO_ALTF_B, "mcde tvout"),
+ __GPIO_ALT(GPIO_ALT_LCD_PANELB, 78, 81, 1, GPIO_ALTF_A, "mcde tvout"),
+ __GPIO_ALT(GPIO_ALT_LCD_PANELB, 150, 150, 0, GPIO_ALTF_B, "mcde tvout"),
+#else
+ __GPIO_ALT(GPIO_ALT_LCD_PANELB, 153, 171, 1, GPIO_ALTF_B, "mcde tvout"),
+ __GPIO_ALT(GPIO_ALT_LCD_PANELB, 64, 77, 0, GPIO_ALTF_A, "mcde tvout"),
+#endif
+ __GPIO_ALT(GPIO_ALT_LCD_PANELA, 68, 68, 0, GPIO_ALTF_A, "mcde tvout"),
+ __GPIO_ALT(GPIO_ALT_MMIO_INIT_BOARD, 141, 142, 0, GPIO_ALTF_B, "mmio"),
+ __GPIO_ALT(GPIO_ALT_MMIO_CAM_SET_I2C, 8, 9, 0, GPIO_ALTF_A, "mmio"),
+ __GPIO_ALT(GPIO_ALT_MMIO_CAM_SET_EXT_CLK, 227, 228, 0, GPIO_ALTF_A, "mmio"),
+#ifdef CONFIG_TOUCHP_EXT_CLK
+ __GPIO_ALT(GPIO_ALT_TP_SET_EXT_CLK, 228, 228, 0, GPIO_ALTF_A, "u8500_tp1"),
+#endif
+};
+
+static struct gpio_block_data gpio0_block_data[] = {
+ {
+ .irq = IRQ_GPIO0,
+ .base_offset = 0x0,
+ .blocks_per_irq = 1,
+ .block_base = 0,
+ .block_size = 32,
+ },
+ {
+ .irq = IRQ_GPIO1,
+ .base_offset = 0x080,
+ .blocks_per_irq = 1,
+ .block_base = 32,
+ .block_size = 5,
+ }
+};
+
+static struct gpio_platform_data gpio0_platform_data = {
+ .gpio_data = gpio0_block_data,
+ .gpio_block_size = ARRAY_SIZE(gpio0_block_data),
+ .altfun_table = gpio_altfun_table,
+ .altfun_table_size = ARRAY_SIZE(gpio_altfun_table),
+};
+
+struct amba_device u8500_gpio0_device = {
+ .dev = {
+ .bus_id = "gpioblock0",
+ .platform_data = &gpio0_platform_data,
+ },
+ .res = {
+ .start = U8500_GPIO0_BASE,
+ .end = U8500_GPIO0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .periphid = GPIO_PER_ID,
+ .irq = {IRQ_GPIO0, NO_IRQ},
+};
+
+static struct gpio_block_data gpio1_block_data[] = {
+ {
+ .irq = IRQ_GPIO2,
+ .base_offset = 0x0,
+ .blocks_per_irq = 1,
+ .block_base = 64,
+ .block_size = 32,
+ },
+ {
+ .irq = IRQ_GPIO3,
+ .base_offset = 0x080,
+ .blocks_per_irq = 1,
+ .block_base = 96,
+ .block_size = 2,
+ },
+ {
+ .irq = IRQ_GPIO4,
+ .base_offset = 0x100,
+ .blocks_per_irq = 1,
+ .block_base = 128,
+ .block_size = 32,
+ },
+ {
+ .irq = IRQ_GPIO5,
+ .base_offset = 0x180,
+ .blocks_per_irq = 1,
+ .block_base = 160,
+ .block_size = 12,
+ }
+};
+static struct gpio_platform_data gpio1_platform_data = {
+ .gpio_data = gpio1_block_data,
+ .gpio_block_size = ARRAY_SIZE(gpio1_block_data),
+ .altfun_table = gpio_altfun_table,
+ .altfun_table_size = ARRAY_SIZE(gpio_altfun_table)
+};
+
+struct amba_device u8500_gpio1_device = {
+ .dev = {
+ .bus_id = "gpioblock1",
+ .platform_data = &gpio1_platform_data,
+ },
+ .res = {
+ .start = U8500_GPIO1_BASE,
+ .end = U8500_GPIO1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .periphid = GPIO_PER_ID,
+ .irq = {IRQ_GPIO2, NO_IRQ},
+};
+
+static struct gpio_block_data gpio2_block_data[] = {
+ {
+ .irq = IRQ_GPIO6,
+ .base_offset = 0x0,
+ .blocks_per_irq = 1,
+ .block_base = 192,
+ .block_size = 32,
+ },
+ {
+ .irq = IRQ_GPIO7,
+ .base_offset = 0x080,
+ .blocks_per_irq = 1,
+ .block_base = 224,
+ .block_size = 7,
+ }
+};
+
+static struct gpio_platform_data gpio2_platform_data = {
+ .gpio_data = gpio2_block_data,
+ .gpio_block_size = ARRAY_SIZE(gpio2_block_data),
+ .altfun_table = gpio_altfun_table,
+ .altfun_table_size = ARRAY_SIZE(gpio_altfun_table)
+};
+
+struct amba_device u8500_gpio2_device = {
+ .dev = {
+ .bus_id = "gpioblock2",
+ .platform_data = &gpio2_platform_data,
+ },
+ .res = {
+ .start = U8500_GPIO2_BASE,
+ .end = U8500_GPIO2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .periphid = GPIO_PER_ID,
+ .irq = {IRQ_GPIO6, NO_IRQ},
+};
+
+static struct gpio_block_data gpio3_block_data[] = {
+ {
+ .irq = IRQ_GPIO8,
+ .base_offset = 0x0,
+ .blocks_per_irq = 1,
+ .block_base = 256,
+ .block_size = 12,
+ }
+};
+
+static struct gpio_platform_data gpio3_platform_data = {
+ .gpio_data = gpio3_block_data,
+ .gpio_block_size = ARRAY_SIZE(gpio3_block_data),
+ .altfun_table = gpio_altfun_table,
+ .altfun_table_size = ARRAY_SIZE(gpio_altfun_table)
+
+};
+
+struct amba_device u8500_gpio3_device = {
+ .dev = {
+ .bus_id = "gpioblock3",
+ .platform_data = &gpio3_platform_data,
+ },
+ .res = {
+ .start = U8500_GPIO3_BASE,
+ .end = U8500_GPIO3_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .periphid = GPIO_PER_ID,
+ .irq = {IRQ_GPIO8, NO_IRQ},
+};
+
+static struct resource u8500_i2c0_resources[] = {
+ [0] = {
+ .start = U8500_I2C0_BASE,
+ .end = U8500_I2C0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_I2C0,
+ .end = IRQ_I2C0,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device u8500_i2c0_device = {
+ .name = "STM-I2C",
+ .id = 0,
+ .resource = u8500_i2c0_resources,
+ .num_resources = ARRAY_SIZE(u8500_i2c0_resources),
+};
+
+static struct resource u8500_i2c4_resources[] = {
+ [0] = {
+ .start = U8500_I2C4_BASE,
+ .end = U8500_I2C4_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_I2C4,
+ .end = IRQ_I2C4,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device u8500_i2c4_device = {
+ .name = "STM-I2C",
+ .id = 4,
+ .resource = u8500_i2c4_resources,
+ .num_resources = ARRAY_SIZE(u8500_i2c4_resources),
+};
+
+#define NUM_SSP_CLIENTS 10
+
+static struct nmdk_spi_master_cntlr ssp0_platform_data = {
+ .enable_dma = 1,
+ .id = SSP_0_CONTROLLER,
+ .num_chipselect = NUM_SSP_CLIENTS,
+ .base_addr = U8500_SSP0_BASE,
+ .rx_fifo_addr = U8500_SSP0_BASE + SSP_TX_RX_REG_OFFSET,
+ .rx_fifo_dev_type = DMA_DEV_SSP0_RX,
+ .tx_fifo_addr = U8500_SSP0_BASE + SSP_TX_RX_REG_OFFSET,
+ .tx_fifo_dev_type = DMA_DEV_SSP0_TX,
+ .gpio_alt_func = GPIO_ALT_SSP_0,
+ .device_name = "ssp0",
+};
+
+struct amba_device u8500_ssp0_device = {
+ .dev = {
+ .bus_id = "ssp0",
+ .platform_data = &ssp0_platform_data,
+ },
+ .res = {
+ .start = U8500_SSP0_BASE,
+ .end = U8500_SSP0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .dma_mask = DMA_BIT_MASK(32),
+ .irq = {IRQ_SSP0, NO_IRQ},
+ .periphid = SSP_PER_ID,
+};
+
+static struct nmdk_spi_master_cntlr ssp1_platform_data = {
+ .enable_dma = 1,
+ .id = SSP_1_CONTROLLER,
+ .num_chipselect = NUM_SSP_CLIENTS,
+ .base_addr = U8500_SSP1_BASE,
+ .rx_fifo_addr = U8500_SSP1_BASE + SSP_TX_RX_REG_OFFSET,
+ .rx_fifo_dev_type = DMA_DEV_SSP1_RX,
+ .tx_fifo_addr = U8500_SSP1_BASE + SSP_TX_RX_REG_OFFSET,
+ .tx_fifo_dev_type = DMA_DEV_SSP1_TX,
+ .gpio_alt_func = GPIO_ALT_SSP_1,
+ .device_name = "ssp1",
+};
+
+struct amba_device u8500_ssp1_device = {
+ .dev = {
+ .bus_id = "ssp1",
+ .platform_data = &ssp1_platform_data,
+ },
+ .res = {
+ .start = U8500_SSP1_BASE,
+ .end = U8500_SSP1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .dma_mask = DMA_BIT_MASK(32),
+ .irq = {IRQ_SSP1, NO_IRQ},
+ .periphid = SSP_PER_ID,
+};
diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c
new file mode 100644
index 00000000000..98c906ecd7f
--- /dev/null
+++ b/arch/arm/mach-ux500/devices.c
@@ -0,0 +1,1094 @@
+/*
+ * Copyright (C) 2009 ST Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/serial.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/i2s/i2s.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/usb/musb.h>
+#include <linux/regulator/machine.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/devices.h>
+#include <asm/dma.h>
+#include <mach/dma.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-stm.h>
+#include <linux/mmc/host.h>
+#include <asm/setup.h>
+#include <linux/android_pmem.h>
+#include <mach/msp.h>
+#include <mach/i2c-stm.h>
+#include <mach/shrm.h>
+#include <mach/mmc.h>
+#include <mach/ab8500.h>
+#include <mach/stmpe2401.h>
+#include <mach/tc35892.h>
+#include <mach/uart.h>
+#include <mach/setup.h>
+
+void __init u8500_register_device(struct platform_device *dev, void *data)
+{
+ int ret;
+
+ dev->dev.platform_data = data;
+
+ ret = platform_device_register(dev);
+ if (ret)
+ dev_err(&dev->dev, "unable to register device: %d\n", ret);
+}
+
+void __init u8500_register_amba_device(struct amba_device *dev, void *data)
+{
+ int ret;
+
+ dev->dev.platform_data = data;
+
+ ret = amba_device_register(dev, &iomem_resource);
+ if (ret)
+ dev_err(&dev->dev, "unable to register device: %d\n", ret);
+}
+
+#ifdef CONFIG_UX500_SOC_DB8500
+/* MSP is being used as a platform device because the perif id of all MSPs
+ * is same & hence probe would be called for
+ * 2 drivers namely: msp-spi & msp-i2s.
+ * Inorder to avoid this & bind a set of MSPs to each driver a platform
+ * bus is being used- binding based on name.
+ */
+static int msp_i2s_init(gpio_alt_function gpio)
+{
+ return stm_gpio_altfuncenable(gpio);
+}
+
+static int msp_i2s_exit(gpio_alt_function gpio)
+{
+ return stm_gpio_altfuncdisable(gpio);
+}
+
+static struct msp_i2s_platform_data msp0_platform_data = {
+ .id = MSP_0_I2S_CONTROLLER,
+ .gpio_alt_func = GPIO_ALT_MSP_0,
+ .msp_tx_dma_addr = DMA_DEV_MSP0_TX,
+ .msp_rx_dma_addr = DMA_DEV_MSP0_RX,
+ .msp_base_addr = U8500_MSP0_BASE,
+ .msp_i2s_init = msp_i2s_init,
+ .msp_i2s_exit = msp_i2s_exit,
+};
+static struct resource u8500_msp_0_resources[] = {
+ [0] = {
+ .start = U8500_MSP0_BASE,
+ .end = U8500_MSP0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_MSP0,
+ .end = IRQ_MSP0,
+ .flags = IORESOURCE_IRQ}
+};
+struct platform_device u8500_msp0_device = {
+ .name = "MSP_I2S",
+ .id = 0,
+ .num_resources = 2,
+ .resource = u8500_msp_0_resources,
+ .dev = {
+ .bus_id = "msp0",
+ .platform_data = &msp0_platform_data,
+ },
+
+};
+static struct msp_i2s_platform_data msp1_platform_data = {
+ .id = MSP_1_I2S_CONTROLLER,
+ .gpio_alt_func = GPIO_ALT_MSP_1,
+ .msp_tx_dma_addr = DMA_DEV_MSP1_TX,
+ .msp_rx_dma_addr = DMA_DEV_MSP1_RX,
+ .msp_base_addr = U8500_MSP1_BASE,
+ .msp_i2s_init = msp_i2s_init,
+ .msp_i2s_exit = msp_i2s_exit,
+};
+static struct resource u8500_msp_1_resources[] = {
+ [0] = {
+ .start = U8500_MSP1_BASE,
+ .end = U8500_MSP1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_MSP1,
+ .end = IRQ_MSP1,
+ .flags = IORESOURCE_IRQ}
+};
+struct platform_device u8500_msp1_device = {
+ .name = "MSP_I2S",
+ .id = 1,
+ .num_resources = 2,
+ .resource = u8500_msp_1_resources,
+ .dev = {
+ .bus_id = "msp1",
+ .platform_data = &msp1_platform_data,
+ },
+
+};
+static struct msp_i2s_platform_data msp2_platform_data = {
+ .id = MSP_2_I2S_CONTROLLER,
+ .gpio_alt_func = GPIO_ALT_MSP_2,
+ .msp_tx_dma_addr = DMA_DEV_MSP2_TX,
+ .msp_rx_dma_addr = DMA_DEV_MSP2_RX,
+ .msp_base_addr = U8500_MSP2_BASE,
+ .msp_i2s_init = msp_i2s_init,
+ .msp_i2s_exit = msp_i2s_exit,
+};
+
+static struct resource u8500_msp_2_resources[] = {
+ [0] = {
+ .start = U8500_MSP2_BASE,
+ .end = U8500_MSP2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_MSP2,
+ .end = IRQ_MSP2,
+ .flags = IORESOURCE_IRQ
+ }
+};
+
+struct platform_device u8500_msp2_device = {
+ .name = "MSP_I2S",
+ .id = 2,
+ .num_resources = 2,
+ .resource = u8500_msp_2_resources,
+ .dev = {
+ .bus_id = "msp2",
+ .platform_data = &msp2_platform_data,
+ },
+};
+#endif
+
+#define NUM_MSP_CLIENTS 10
+
+static struct nmdk_spi_master_cntlr msp2_spi_platform_data = {
+ .enable_dma = 1,
+ .id = MSP_2_CONTROLLER,
+ .num_chipselect = NUM_MSP_CLIENTS,
+ .base_addr = U8500_MSP2_BASE,
+ .rx_fifo_addr = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
+ .rx_fifo_dev_type = DMA_DEV_MSP2_RX,
+ .tx_fifo_addr = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
+ .tx_fifo_dev_type = DMA_DEV_MSP2_TX,
+ .gpio_alt_func = GPIO_ALT_MSP_2,
+ .device_name = "msp2",
+};
+
+struct amba_device u8500_msp2_spi_device = {
+ .dev = {
+ .bus_id = "msp2",
+ .platform_data = &msp2_spi_platform_data,
+ },
+ .res = {
+ .start = U8500_MSP2_BASE,
+ .end = U8500_MSP2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .dma_mask = ~0,
+ .irq = {IRQ_MSP2, NO_IRQ},
+ .periphid = MSP_PER_ID,
+};
+
+static struct resource ux500_i2c1_resources[] = {
+ [0] = {
+ .start = UX500_I2C1_BASE,
+ .end = UX500_I2C1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_I2C1,
+ .end = IRQ_I2C1,
+ .flags = IORESOURCE_IRQ
+ }
+};
+
+struct platform_device ux500_i2c1_device = {
+ .name = "STM-I2C",
+ .id = 1,
+ .resource = ux500_i2c1_resources,
+ .num_resources = ARRAY_SIZE(ux500_i2c1_resources),
+};
+
+static struct resource ux500_i2c2_resources[] = {
+ [0] = {
+ .start = UX500_I2C2_BASE,
+ .end = UX500_I2C2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_I2C2,
+ .end = IRQ_I2C2,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device ux500_i2c2_device = {
+ .name = "STM-I2C",
+ .id = 2,
+ .resource = ux500_i2c2_resources,
+ .num_resources = ARRAY_SIZE(ux500_i2c2_resources),
+};
+
+static struct resource ux500_i2c3_resources[] = {
+ [0] = {
+ .start = UX500_I2C3_BASE,
+ .end = UX500_I2C3_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_I2C3,
+ .end = IRQ_I2C3,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device ux500_i2c3_device = {
+ .name = "STM-I2C",
+ .id = 3,
+ .resource = ux500_i2c3_resources,
+ .num_resources = ARRAY_SIZE(ux500_i2c3_resources),
+};
+
+static struct shrm_plat_data shrm_platform_data = {
+
+ .pshm_dev_data = 0
+};
+
+static struct resource u8500_shrm_resources[] = {
+ [0] = {
+ .start = U8500_SHRM_GOP_INTERRUPT_BASE,
+ .end = U8500_SHRM_GOP_INTERRUPT_BASE + ((4*4)-1),
+ .name = "shrm_gop_register_base",
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_CA_WAKE_REQ_V1,
+ .end = IRQ_CA_WAKE_REQ_V1,
+ .name = "ca_irq_wake_req",
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = IRQ_AC_READ_NOTIFICATION_0_V1,
+ .end = IRQ_AC_READ_NOTIFICATION_0_V1,
+ .name = "ac_read_notification_0_irq",
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = IRQ_AC_READ_NOTIFICATION_1_V1,
+ .end = IRQ_AC_READ_NOTIFICATION_1_V1,
+ .name = "ac_read_notification_1_irq",
+ .flags = IORESOURCE_IRQ,
+ },
+ [4] = {
+ .start = IRQ_CA_MSG_PEND_NOTIFICATION_0_V1,
+ .end = IRQ_CA_MSG_PEND_NOTIFICATION_0_V1,
+ .name = "ca_msg_pending_notification_0_irq",
+ .flags = IORESOURCE_IRQ,
+ },
+ [5] = {
+ .start = IRQ_CA_MSG_PEND_NOTIFICATION_1_V1,
+ .end = IRQ_CA_MSG_PEND_NOTIFICATION_1_V1,
+ .name = "ca_msg_pending_notification_1_irq",
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device u8500_shrm_device = {
+ .name = "u8500_shrm",
+ .id = 0,
+ .dev = {
+ .bus_id = "shrm_bus",
+ .coherent_dma_mask = ~0,
+ .platform_data = &shrm_platform_data,
+ },
+
+ .num_resources = ARRAY_SIZE(u8500_shrm_resources),
+ .resource = u8500_shrm_resources
+};
+
+static struct resource b2r2_resources[] = {
+ [0] = {
+ .start = UX500_B2R2_BASE,
+ .end = UX500_B2R2_BASE + ((4*1024)-1),
+ .name = "b2r2_base",
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = PRCM_B2R2CLK_MGT_REG,
+ .end = PRCM_B2R2CLK_MGT_REG + (sizeof(u32) - 1),
+ .name = "prcm_b2r2_clk",
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device ux500_b2r2_device = {
+ .name = "U8500-B2R2",
+ .id = 0,
+ .dev = {
+ .bus_id = "b2r2_bus",
+ .coherent_dma_mask = ~0,
+ },
+ .num_resources = ARRAY_SIZE(b2r2_resources),
+ .resource = b2r2_resources,
+};
+
+static void __init early_pmem_generic_parse(char **p, struct android_pmem_platform_data * data)
+{
+ data->size = memparse(*p, p);
+ if (**p == '@')
+ data->start = memparse(*p + 1, p);
+}
+
+/********************************************************************************
+ * Pmem device used by surface flinger
+ ********************************************************************************/
+
+static struct android_pmem_platform_data pmem_pdata = {
+ .name = "pmem",
+ .no_allocator = 1, /* MemoryHeapBase is having an allocator */
+ .cached = 1,
+ .start = 0,
+ .size = 0,
+};
+
+static void __init early_pmem(char **p)
+{
+ early_pmem_generic_parse(p, &pmem_pdata);
+}
+__early_param("pmem=", early_pmem);
+
+struct platform_device u8500_pmem_device = {
+ .name = "android_pmem",
+ .id = 0,
+ .dev = {
+ .platform_data = &pmem_pdata,
+ },
+};
+
+/********************************************************************************
+ * Pmem device used by PV video output node
+ ********************************************************************************/
+
+static struct android_pmem_platform_data pmem_mio_pdata = {
+ .name = "pmem_mio",
+ .no_allocator = 1, /* We'll manage allocation */
+ .cached = 1,
+ .start = 0,
+ .size = 0,
+};
+
+static void __init early_pmem_mio(char **p)
+{
+ early_pmem_generic_parse(p, &pmem_mio_pdata);
+}
+__early_param("pmem_mio=", early_pmem_mio);
+
+struct platform_device u8500_pmem_mio_device = {
+ .name = "android_pmem",
+ .id = 1,
+ .dev = {
+ .platform_data = &pmem_mio_pdata,
+ },
+};
+
+/********************************************************************************
+ * Pmem device used by OMX components allocating buffers
+ ********************************************************************************/
+
+static struct android_pmem_platform_data pmem_hwb_pdata = {
+ .name = "pmem_hwb",
+ .no_allocator = 1, /* We'll manage allocation */
+ .cached = 1,
+ .start = 0,
+ .size = 0,
+};
+
+static void __init early_pmem_hwb(char **p)
+{
+ early_pmem_generic_parse(p, &pmem_hwb_pdata);
+}
+__early_param("pmem_hwb=", early_pmem_hwb);
+
+struct platform_device u8500_pmem_hwb_device = {
+ .name = "android_pmem",
+ .id = 2,
+ .dev = {
+ .platform_data = &pmem_hwb_pdata,
+ },
+};
+
+struct amba_device ux500_rtc_device = {
+ .dev = {
+ .bus_id = "mb:15",
+ },
+ .res = {
+ .start = UX500_RTC_BASE,
+ .end = UX500_RTC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_RTC_RTT, NO_IRQ},
+ .periphid = RTC_PER_ID,
+};
+
+#include "clock.h"
+
+static struct map_desc ux500_io_desc[] __initdata = {
+ __IO_DEV_DESC(U8500_RTC_BASE, SZ_4K),
+
+ __IO_DEV_DESC(U8500_MSP0_BASE, SZ_4K),
+ __IO_DEV_DESC(U8500_MSP1_BASE, SZ_4K),
+ __IO_DEV_DESC(U8500_MSP2_BASE, SZ_4K),
+
+ __IO_DEV_DESC(UX500_UART0_BASE, SZ_4K),
+ __IO_DEV_DESC(UX500_UART1_BASE, SZ_4K),
+ __IO_DEV_DESC(UX500_UART2_BASE, SZ_4K),
+
+ __IO_DEV_DESC(UX500_GIC_CPU_BASE, SZ_4K),
+ __IO_DEV_DESC(UX500_GIC_DIST_BASE, SZ_4K),
+ __IO_DEV_DESC(UX500_L2CC_BASE, SZ_4K),
+
+ __IO_DEV_DESC(UX500_CLKRST1_BASE, SZ_4K),
+ __IO_DEV_DESC(UX500_CLKRST2_BASE, SZ_4K),
+ __IO_DEV_DESC(UX500_CLKRST3_BASE, SZ_4K),
+ __IO_DEV_DESC(UX500_CLKRST5_BASE, SZ_4K),
+ __IO_DEV_DESC(UX500_CLKRST6_BASE, SZ_4K),
+
+ __IO_DEV_DESC(UX500_MTU0_BASE, SZ_4K),
+ __IO_DEV_DESC(UX500_MTU1_BASE, SZ_4K),
+
+ __IO_DEV_DESC(UX500_BACKUPRAM0_BASE, SZ_8K),
+};
+
+static struct platform_device *ux500_platform_devs[] __initdata = {
+ &ux500_dma_device,
+};
+
+static struct amba_device *ux500_amba_devs[] __initdata = {
+ &ux500_rtc_device,
+};
+
+void __init ux500_init_devices(void)
+{
+ platform_add_devices(ux500_platform_devs,
+ ARRAY_SIZE(ux500_platform_devs));
+ amba_add_devices(ux500_amba_devs, ARRAY_SIZE(ux500_amba_devs));
+}
+
+static struct resource ux500_dma_resources[] = {
+ [0] = {
+ .start = UX500_DMA_BASE,
+ .end = UX500_DMA_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_DMA,
+ .end = IRQ_DMA,
+ .flags = IORESOURCE_IRQ
+ },
+};
+
+struct platform_device ux500_dma_device = {
+ .name = "STM-DMA",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(ux500_dma_resources),
+ .resource = ux500_dma_resources
+};
+
+#define NUM_SPI023_CLIENTS 10
+static struct nmdk_spi_master_cntlr spi0_platform_data = {
+ .enable_dma = 1,
+ .id = SPI023_0_CONTROLLER,
+ .num_chipselect = NUM_SPI023_CLIENTS,
+ .base_addr = UX500_SPI0_BASE,
+ .rx_fifo_addr = UX500_SPI0_BASE + SPI_TX_RX_REG_OFFSET,
+ .rx_fifo_dev_type = DMA_DEV_SPI0_RX,
+ .tx_fifo_addr = UX500_SPI0_BASE + SPI_TX_RX_REG_OFFSET,
+ .tx_fifo_dev_type = DMA_DEV_SPI0_TX,
+ .gpio_alt_func = GPIO_ALT_SSP_0,
+ .device_name = "spi0",
+};
+
+struct amba_device ux500_spi0_device = {
+ .dev = {
+ .bus_id = "spi0",
+ .platform_data = &spi0_platform_data,
+ },
+ .res = {
+ .start = UX500_SPI0_BASE,
+ .end = UX500_SPI0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .dma_mask = DMA_BIT_MASK(32),
+ .irq = {IRQ_SPI0, NO_IRQ},
+ .periphid = SPI_PER_ID,
+};
+
+struct amba_device ux500_sdi0_device = {
+ .dev = {
+ .init_name = "sdi0",
+ },
+ .res = {
+ .start = UX500_SDI0_BASE,
+ .end = UX500_SDI0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_SDMMC0, NO_IRQ},
+ .periphid = SDI_PER_ID,
+};
+
+struct amba_device ux500_sdi1_device = {
+ .dev = {
+ .init_name = "sdi1",
+ },
+ .res = {
+ .start = UX500_SDI1_BASE,
+ .end = UX500_SDI1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_SDMMC1, NO_IRQ},
+ .periphid = SDI_PER_ID,
+};
+
+struct amba_device ux500_sdi2_device = {
+ .dev = {
+ .init_name = "sdi2",
+ },
+ .res = {
+ .start = UX500_SDI2_BASE,
+ .end = UX500_SDI2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_SDMMC2, NO_IRQ},
+ .periphid = SDI_PER_ID,
+};
+
+struct amba_device ux500_sdi4_device = {
+ .dev = {
+ .init_name = "sdi4",
+ },
+ .res = {
+ .start = UX500_SDI4_BASE,
+ .end = UX500_SDI4_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_SDMMC4, NO_IRQ},
+ .periphid = SDI_PER_ID,
+};
+
+static struct resource ab8500_resources[] = {
+ [0] = {
+ .start = STW4500_IRQ,
+ .end = STW4500_IRQ,
+ .flags = IORESOURCE_IRQ
+ }
+};
+
+/**
+ * ab8500_spi_cs_enable - disables the chip select for STw4500
+ */
+void ab8500_spi_cs_enable(void)
+{
+
+}
+
+/**
+ * ab8500_spi_cs_disable - enables the chip select for STw4500
+ */
+void ab8500_spi_cs_disable(void)
+{
+
+}
+
+static struct ab8500_device ab8500_board = {
+ .cs_en = ab8500_spi_cs_enable,
+ .cs_dis = ab8500_spi_cs_disable,
+ .ssp_controller = SSP_0_CONTROLLER,
+};
+
+struct platform_device u8500_ab8500_device = {
+ .name = "ab8500",
+ .id = 0,
+ .dev = {
+ .platform_data = &ab8500_board,
+ },
+ .num_resources = 1,
+ .resource = ab8500_resources,
+};
+
+#if defined(CONFIG_USB_MUSB_HOST)
+#define MUSB_MODE MUSB_HOST
+#elif defined(CONFIG_USB_MUSB_PERIPHERAL)
+#define MUSB_MODE MUSB_PERIPHERAL
+#elif defined(CONFIG_USB_MUSB_OTG)
+#define MUSB_MODE MUSB_OTG
+#else
+#define MUSB_MODE MUSB_UNDEFINED
+#endif
+static struct musb_hdrc_config musb_hdrc_hs_otg_config = {
+ .multipoint = true, /* multipoint device */
+ .dyn_fifo = true, /* supports dynamic fifo sizing */
+ .num_eps = 16, /* number of endpoints _with_ ep0 */
+ .ram_bits = 16, /* ram address size */
+};
+
+static struct musb_hdrc_platform_data musb_hdrc_hs_otg_platform_data = {
+ .mode = MUSB_MODE,
+ .clock = "usb", /* for clk_get() */
+ .config = &musb_hdrc_hs_otg_config,
+};
+
+static struct resource usb_resources[] = {
+ [0] = {
+ .name = "usb-mem",
+ .start = UX500_USBOTG_BASE,
+ .end = (UX500_USBOTG_BASE + SZ_64K - 1),
+ .flags = IORESOURCE_MEM,
+ },
+
+ [1] = {
+ .name = "usb-irq",
+ .start = IRQ_USBOTG,
+ .end = IRQ_USBOTG,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device ux500_musb_device = {
+ .name = "musb_hdrc",
+ .id = 0,
+ .dev = {
+ .bus_id = "musb_hdrc.0", /* for clk_get() */
+ .platform_data = &musb_hdrc_hs_otg_platform_data,
+ .dma_mask = (u64 *)0xFFFFFFFF,
+ .coherent_dma_mask = (u64)0xFFFFFFFF
+ },
+ .num_resources = ARRAY_SIZE(usb_resources),
+ .resource = usb_resources,
+};
+
+void __init ux500_map_io(void)
+{
+ iotable_init(ux500_io_desc, ARRAY_SIZE(ux500_io_desc));
+}
+
+void __init u8500_init_irq(void)
+{
+ gic_dist_init(0, (void __iomem *)IO_ADDRESS(UX500_GIC_DIST_BASE), 29);
+ gic_cpu_init(0, (void __iomem *)IO_ADDRESS(UX500_GIC_CPU_BASE));
+
+ /*
+ * Init clocks here so that they are available for system timer
+ * initialization.
+ */
+ clk_init();
+}
+
+static void uart0_init(void)
+{
+ stm_gpio_altfuncenable(GPIO_ALT_UART_0_NO_MODEM);
+}
+
+static void uart0_exit(void)
+{
+ stm_gpio_altfuncdisable(GPIO_ALT_UART_0_NO_MODEM);
+}
+
+struct uart_amba_plat_data uart0_plat = {
+ .init = uart0_init,
+ .exit = uart0_exit,
+};
+
+static void uart1_init(void)
+{
+ stm_gpio_altfuncenable(GPIO_ALT_UART_1);
+}
+
+static void uart1_exit(void)
+{
+ stm_gpio_altfuncdisable(GPIO_ALT_UART_1);
+}
+
+struct uart_amba_plat_data uart1_plat = {
+ .init = uart1_init,
+ .exit = uart1_exit,
+};
+
+static void uart2_init(void)
+{
+ stm_gpio_altfuncenable(GPIO_ALT_UART_2);
+}
+
+static void uart2_exit(void)
+{
+ stm_gpio_altfuncdisable(GPIO_ALT_UART_2);
+}
+
+struct uart_amba_plat_data uart2_plat = {
+ .init = uart2_init,
+ .exit = uart2_exit,
+};
+
+#define __MEM_4K_RESOURCE(x) \
+ .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
+
+/* These are active devices on this board, FIXME
+ * move this to board file
+ */
+#if defined(CONFIG_MACH_U5500_SIMULATOR)
+/* Remap of uart0 and uart2 when using SVP5500
+ * remove this when uart2 problem solved in SVP5500
+ */
+struct amba_device ux500_uart2_device = {
+ .dev = {.bus_id = "uart2", .platform_data = &uart0_plat, },
+ __MEM_4K_RESOURCE(UX500_UART0_BASE),
+ .irq = {IRQ_UART0, NO_IRQ},
+};
+
+struct amba_device ux500_uart1_device = {
+ .dev = {.bus_id = "uart1", .platform_data = &uart1_plat, },
+ __MEM_4K_RESOURCE(UX500_UART1_BASE),
+ .irq = {IRQ_UART1, NO_IRQ},
+};
+
+struct amba_device ux500_uart0_device = {
+ .dev = {.bus_id = "uart0", .platform_data = &uart2_plat, },
+ __MEM_4K_RESOURCE(UX500_UART2_BASE),
+ .irq = {IRQ_UART2, NO_IRQ},
+};
+#else
+struct amba_device ux500_uart0_device = {
+ .dev = {.bus_id = "uart0", .platform_data = &uart0_plat, },
+ __MEM_4K_RESOURCE(UX500_UART0_BASE),
+ .irq = {IRQ_UART0, NO_IRQ},
+};
+
+struct amba_device ux500_uart1_device = {
+ .dev = {.bus_id = "uart1", .platform_data = &uart1_plat, },
+ __MEM_4K_RESOURCE(UX500_UART1_BASE),
+ .irq = {IRQ_UART1, NO_IRQ},
+};
+
+struct amba_device ux500_uart2_device = {
+ .dev = {.bus_id = "uart2", .platform_data = &uart2_plat, },
+ __MEM_4K_RESOURCE(UX500_UART2_BASE),
+ .irq = {IRQ_UART2, NO_IRQ},
+};
+
+#endif
+
+#ifdef CONFIG_CACHE_L2X0
+static int __init u8500_l2x0_init(void)
+{
+ l2x0_init((void *)IO_ADDRESS(UX500_L2CC_BASE), 0x3e060000, 0x3e060000);
+ return 0;
+}
+early_initcall(u8500_l2x0_init);
+#endif
+
+void __init amba_add_devices(struct amba_device *devs[], int num)
+{
+ int i;
+
+ for (i = 0; i < num; i++) {
+ struct amba_device *d = devs[i];
+ amba_device_register(d, &iomem_resource);
+ }
+}
+
+/* U8500 Power section */
+#ifdef CONFIG_REGULATOR
+
+#define U8500_VAPE_REGULATOR_MIN_VOLTAGE (1800000)
+#define U8500_VAPE_REGULATOR_MAX_VOLTAGE (2000000)
+
+static int db8500_vape_regulator_init(void)
+{ return 0; }
+
+/* tying VAPE regulator to symbolic consumer devices */
+static struct regulator_consumer_supply db8500_vape_consumers[] = {
+ {
+ .supply = "v-ape",
+ },
+};
+
+/* VAPE supply, for interconnect */
+static struct regulator_init_data db8500_vape_init = {
+ .supply_regulator_dev = NULL,
+ .constraints = {
+ .name = "DB8500-VAPE",
+ .min_uV = U8500_VAPE_REGULATOR_MIN_VOLTAGE,
+ .max_uV = U8500_VAPE_REGULATOR_MAX_VOLTAGE,
+ .input_uV = 1, /* notional, for set_mode* */
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+ REGULATOR_CHANGE_MODE|REGULATOR_CHANGE_DRMS,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL|REGULATOR_MODE_IDLE,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
+ .regulator_init = db8500_vape_regulator_init,
+ .consumer_supplies = db8500_vape_consumers,
+};
+
+static struct platform_device db8500_vape_regulator_dev = {
+ .name = "db8500-regulator",
+ .id = 0,
+ .dev = {
+ .platform_data = &db8500_vape_init,
+ },
+};
+
+/* VANA Supply, for analogue part of displays */
+#define U8500_VANA_REGULATOR_MIN_VOLTAGE (0)
+#define U8500_VANA_REGULATOR_MAX_VOLTAGE (1200000)
+
+static int db8500_vana_regulator_init(void) { return 0; }
+
+static struct regulator_consumer_supply db8500_vana_consumers[] = {
+#ifdef CONFIG_FB_U8500_MCDE_CHANNELA
+ {
+ .dev = &u8500_mcde0_device.dev,
+ .supply = "v-ana",
+ },
+#endif
+#ifdef CONFIG_FB_U8500_MCDE_CHANNELB
+ {
+ .dev = &u8500_mcde1_device.dev,
+ .supply = "v-ana",
+ },
+#endif
+#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0
+ {
+ .dev = &u8500_mcde2_device.dev,
+ .supply = "v-ana",
+ },
+#endif
+#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1
+ {
+ .dev = &u8500_mcde3_device.dev,
+ .supply = "v-ana",
+ },
+#endif
+};
+
+static struct regulator_init_data db8500_vana_init = {
+ .supply_regulator_dev = NULL,
+ .constraints = {
+ .name = "VANA",
+ .min_uV = U8500_VANA_REGULATOR_MIN_VOLTAGE,
+ .max_uV = U8500_VANA_REGULATOR_MAX_VOLTAGE,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL |
+ REGULATOR_MODE_IDLE,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(db8500_vana_consumers),
+ .regulator_init = db8500_vana_regulator_init,
+ .consumer_supplies = db8500_vana_consumers,
+};
+
+static struct platform_device db8500_vana_regulator_dev = {
+ .name = "db8500-regulator",
+ .id = 1,
+ .dev = {
+ .platform_data = &db8500_vana_init,
+ },
+};
+
+/* VAUX1 supply */
+#define AB8500_VAUXN_LDO_MIN_VOLTAGE (1100000)
+#define AB8500_VAUXN_LDO_MAX_VOLTAGE (3300000)
+
+static int ab8500_vaux1_regulator_init(void) { return 0; }
+
+static struct regulator_consumer_supply ab8500_vaux1_consumers[] = {
+#ifdef CONFIG_FB_U8500_MCDE_CHANNELA
+ {
+ .dev = &u8500_mcde0_device.dev,
+ .supply = "v-mcde",
+ },
+#endif
+#ifdef CONFIG_FB_U8500_MCDE_CHANNELB
+ {
+ .dev = &u8500_mcde1_device.dev,
+ .supply = "v-mcde",
+ },
+#endif
+#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0
+ {
+ .dev = &u8500_mcde2_device.dev,
+ .supply = "v-mcde",
+ },
+#endif
+#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1
+ {
+ .dev = &u8500_mcde3_device.dev,
+ .supply = "v-mcde",
+ },
+#endif
+};
+
+static struct regulator_init_data ab8500_vaux1_init = {
+ .supply_regulator_dev = NULL,
+ .constraints = {
+ .name = "AB8500-VAUX1",
+ .min_uV = AB8500_VAUXN_LDO_MIN_VOLTAGE,
+ .max_uV = AB8500_VAUXN_LDO_MIN_VOLTAGE,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+ REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL|REGULATOR_MODE_IDLE,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers),
+ .regulator_init = ab8500_vaux1_regulator_init,
+ .consumer_supplies = ab8500_vaux1_consumers,
+};
+
+/* as the vaux2 is not a u8500 specific regulator, it is named
+ * as the ab8500 series */
+static struct platform_device ab8500_vaux1_regulator_dev = {
+ .name = "ab8500-regulator",
+ .id = 0,
+ .dev = {
+ .platform_data = &ab8500_vaux1_init,
+ },
+};
+
+/* VAUX2 supply */
+static int ab8500_vaux2_regulator_init(void) { return 0; }
+
+/* supply for on-board eMMC */
+static struct regulator_consumer_supply ab8500_vaux2_consumers[] = {
+ {
+ .dev = &u8500_sdi4_device.dev,
+ .supply = "v-eMMC",
+ }
+};
+
+static struct regulator_init_data ab8500_vaux2_init = {
+ .supply_regulator_dev = NULL,
+ .constraints = {
+ .name = "AB8500-VAUX2",
+ .min_uV = AB8500_VAUXN_LDO_MIN_VOLTAGE,
+ .max_uV = AB8500_VAUXN_LDO_MAX_VOLTAGE,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+ REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL|REGULATOR_MODE_IDLE,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux2_consumers),
+ .regulator_init = ab8500_vaux2_regulator_init,
+ .consumer_supplies = ab8500_vaux2_consumers,
+};
+
+static struct platform_device ab8500_vaux2_regulator_dev = {
+ .name = "ab8500-regulator",
+ .id = 1,
+ .dev = {
+ .platform_data = &ab8500_vaux2_init,
+ },
+};
+
+/* supply for tvout, gpadc, TVOUT LDO */
+#define AB8500_VTVOUT_LDO_MIN_VOLTAGE (0)
+#define AB8500_VTVOUT_LDO_MAX_VOLTAGE (2000000)
+
+static int ab8500_vtvout_regulator_init(void) { return 0; }
+
+static struct regulator_consumer_supply ab8500_vtvout_consumers[] = {
+};
+
+static struct regulator_init_data ab8500_vtvout_init = {
+ .supply_regulator_dev = NULL,
+ .constraints = {
+ .name = "AB8500-VTVOUT",
+ .min_uV = AB8500_VTVOUT_LDO_MIN_VOLTAGE,
+ .max_uV = AB8500_VTVOUT_LDO_MAX_VOLTAGE,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+ REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL|REGULATOR_MODE_IDLE,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(ab8500_vtvout_consumers),
+ .regulator_init = ab8500_vtvout_regulator_init,
+ .consumer_supplies = ab8500_vtvout_consumers,
+};
+
+static struct platform_device ab8500_vtvout_regulator_dev = {
+ .name = "ab8500-regulator",
+ .id = 2,
+ .dev = {
+ .platform_data = &ab8500_vtvout_init,
+ },
+};
+
+/* supply for usb, VBUS LDO */
+#define AB8500_VBUS_REGULATOR_MIN_VOLTAGE (0)
+#define AB8500_VBUS_REGULATOR_MAX_VOLTAGE (5000000)
+
+static int ab8500_vbus_regulator_init(void) { return 0; }
+
+static struct regulator_consumer_supply ab8500_vbus_consumers[] = {
+ {
+ .supply = "v-bus",
+ }
+};
+
+static struct regulator_init_data ab8500_vbus_init = {
+ .supply_regulator_dev = NULL,
+ .constraints = {
+ .name = "AB8500-VBUS",
+ .min_uV = AB8500_VBUS_REGULATOR_MIN_VOLTAGE,
+ .max_uV = AB8500_VBUS_REGULATOR_MAX_VOLTAGE,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+ REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL|REGULATOR_MODE_IDLE,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(ab8500_vbus_consumers),
+ .regulator_init = ab8500_vbus_regulator_init,
+ .consumer_supplies = ab8500_vbus_consumers,
+};
+
+static struct platform_device ab8500_vbus_regulator_dev = {
+ .name = "ab8500-regulator",
+ .id = 3,
+ .dev = {
+ .platform_data = &ab8500_vbus_init,
+ },
+};
+
+static struct platform_device *u8500_regulators[] = {
+ &db8500_vape_regulator_dev,
+ &db8500_vana_regulator_dev,
+ &ab8500_vaux1_regulator_dev,
+ &ab8500_vaux2_regulator_dev,
+ &ab8500_vtvout_regulator_dev,
+ &ab8500_vbus_regulator_dev,
+};
+
+#endif
+
+/* FIXME: move this to the appropriate file */
+void __init u8500_init_regulators(void)
+{
+#ifdef CONFIG_REGULATOR
+ /* we want the on-chip regulator before any device registration */
+ platform_add_devices(u8500_regulators, ARRAY_SIZE(u8500_regulators));
+#endif
+}
diff --git a/arch/arm/mach-ux500/dma_40.c b/arch/arm/mach-ux500/dma_40.c
new file mode 100755
index 00000000000..b1b84a9e25c
--- /dev/null
+++ b/arch/arm/mach-ux500/dma_40.c
@@ -0,0 +1,3903 @@
+/*----------------------------------------------------------------------------*/
+/* Copyright STMicroelectronics, 2008. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it */
+/* under the terms of the GNU General Public License as published by the Free */
+/* Software Foundation; either version 2.1 of the License, or (at your option)*/
+/* any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY */
+/* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*----------------------------------------------------------------------------*/
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/platform_device.h>
+#include <linux/cpufreq.h>
+#include <linux/dma-mapping.h>
+#include <linux/spinlock.h>
+#include <linux/scatterlist.h>
+#include <linux/uaccess.h>
+#include <linux/clk.h>
+#include <asm/page.h>
+#include <asm/fiq.h>
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <mach/memory.h>
+#include <mach/debug.h>
+
+#include <mach/dma.h>
+
+#ifndef CONFIG_U8500_SECURE
+/* Define this macro if in non-secure mode */
+#define CONFIG_STM_SECURITY
+#endif
+
+#define DRIVER_NAME "DRIVER DMA"
+
+/* enables/disables debug msgs */
+#define DRIVER_DEBUG 0
+#define DRIVER_DEBUG_PFX DRIVER_NAME
+#define DRIVER_DBG KERN_ERR
+
+#define MAX_BACKUP_REGS 24
+
+struct dma_addr {
+ dma_addr_t phys_addr;
+ void *log_addr;
+};
+
+/**
+ * struct elem_pool - Structure of element pool
+ * @name: Name of the Element pool
+ * @allocation_map: Whether a pool element is allocated or not
+ * @lchan_allocation_map: Pool allocation map for Logical channels,
+ * (for each phy res)
+ * @num_blocks: Number of elements in the pool
+ * @block_size: Size of each element in the pool
+ * @allocation_size: Total memory allocated for the pool
+ * @unalign_base: Unaligned Base address of pool
+ * @base_addr: Aligned base address of pool
+ *
+ *
+ **/
+struct elem_pool {
+ char name[20];
+ spinlock_t pool_lock;
+ u32 allocation_map;
+ u32 lchan_allocation_map[MAX_PHYSICAL_CHANNELS];
+ int num_blocks;
+ int block_size;
+ int allocation_size;
+ struct dma_addr unalign_base;
+ struct dma_addr base_addr;
+};
+
+/**
+ * struct dma_driver_data - DMA driver private data structure
+ * @reg_base: pointer to DMA controller Register area
+ * @dma_chan_info: Array of pointer to channel info structure.
+ * It is used by DMA driver internally to access information
+ * of each channel (Physical or Logical). It is accessed in
+ * the interrupt handler also.
+ * @pipe_info: Array of pointers to channel info structure, used
+ * access channel info structure when client makes a request.
+ * pipe_id used by client in all requests is an entry
+ * in this array.
+ * @pipe_id_map: Map from where we allocate ID's to client drivers.
+ * If a particular bit is set in this map, it means that
+ * particular id can be given to a client.
+ * @pipe_id_lock: Mutex to provide access to pipe_id_map
+ * @pr_info: stores current status of all physical resources
+ * whether physical channel or Logical channel.
+ * If Logical then count of how many channels are there
+ * @pr_info_lock: Lock to synchronise access to pr_info
+ * @cfg_lock: Lock to synchronize access to write on DMA registers
+ * @lchan_params_base: Base address where logical channel params are
+ * stored.
+ * @pchan_lli_pool: Pool from where LLI's are allocated for phy channels
+ * @sg_pool: Pool from where SG blocks are allocated to keep SG info
+ * @lchan_lli_pool: Pool from where LLI's are allocated for Log channels
+ * @backup_regs: Used to store and restore DMA regs during suspend resume.
+ *
+ **/
+
+struct dma_driver_data {
+ void __iomem *reg_base;
+ struct clk *clk;
+ struct dma_channel_info *dma_chan_info[NUM_CHANNELS];
+ struct dma_channel_info *pipe_info[NUM_CHANNELS];
+ DECLARE_BITMAP(pipe_id_map, NUM_CHANNELS);
+ spinlock_t pipe_id_lock;
+ struct phy_res_info pr_info[MAX_AVAIL_PHY_CHANNELS];
+ spinlock_t pr_info_lock;
+ struct dma_addr lchan_params_base;
+ struct elem_pool *pchan_lli_pool;
+ struct elem_pool *sg_pool;
+ struct elem_pool *lchan_lli_pool;
+ spinlock_t cfg_ch_lock[MAX_AVAIL_PHY_CHANNELS];
+ u32 backup_regs[MAX_BACKUP_REGS];
+};
+static struct dma_driver_data *dma_drv_data;
+
+static inline void __iomem *io_addr(unsigned int offset)
+{
+ return dma_drv_data->reg_base + offset;
+}
+
+static inline void __iomem *cio_addr(unsigned int phys_chan_id,
+ unsigned int offset)
+{
+ return dma_drv_data->reg_base + 0x400 + (phys_chan_id * (8 * 4)) +
+ offset;
+}
+
+/**
+ * print_sg_info() - To Print info of the scatter gather list items
+ * @sg: Pointer to sg List which you want to print
+ * @nents: Number of elements in the list
+ *
+ **/
+static void print_sg_info(struct scatterlist *sg, int nents)
+{
+ int i = 0;
+ stm_dbg(DBG_ST.dma, "Scatter Gather info........\n");
+ for (i = 0; i < nents; i++) {
+ stm_dbg(DBG_ST.dma, "SG[%d] , dma_addr = %x\n", i,
+ sg[i].dma_address);
+ stm_dbg(DBG_ST.dma, "SG[%d] , length = %d\n", i, sg[i].length);
+ stm_dbg(DBG_ST.dma, "SG[%d] , offset = %d\n", i, sg[i].offset);
+ }
+}
+
+/**
+ * print_dma_lli() - To Print the Information that we stored in LLI Struct
+ * @idx: LLI number whose info we are printing
+ * @lli: LLI structure whose value would be printed
+ *
+ **/
+static void print_dma_lli(int idx, struct dma_lli_info *lli)
+{
+ stm_dbg(DBG_ST.dma, "---------------------------------\n");
+ stm_dbg(DBG_ST.dma, "##### %x\n", (u32) lli);
+ stm_dbg(DBG_ST.dma, "LLI[%d]:: Link Register\t %x\n", idx,
+ lli->reg_lnk);
+ stm_dbg(DBG_ST.dma, "LLI[%d]:: Pointer Register\t %x\n", idx,
+ lli->reg_ptr);
+ stm_dbg(DBG_ST.dma, "LLI[%d]:: Element Register\t %x\n", idx,
+ lli->reg_elt);
+ stm_dbg(DBG_ST.dma, "LLI[%d]:: Config Register\t %x\n", idx,
+ lli->reg_cfg);
+ stm_dbg(DBG_ST.dma, "---------------------------------\n");
+}
+
+/**
+ * print_allocation_map() - To print Allocation map of Pipe Ids given to client
+ *
+ */
+static void print_allocation_map(void)
+{
+ stm_dbg(DBG_ST.dma,
+ "==================================================\n");
+ stm_dbg(DBG_ST.dma, "=====pipe_id_map(0) = %x\n",
+ (u32) dma_drv_data->pipe_id_map[0]);
+ stm_dbg(DBG_ST.dma, "=====pipe_id_map(1) = %x\n",
+ (u32) dma_drv_data->pipe_id_map[1]);
+ stm_dbg(DBG_ST.dma, "=====pipe_id_map(2) = %x\n",
+ (u32) dma_drv_data->pipe_id_map[2]);
+ stm_dbg(DBG_ST.dma, "=====pipe_id_map(3) = %x\n",
+ (u32) dma_drv_data->pipe_id_map[3]);
+ stm_dbg(DBG_ST.dma, "=====pipe_id_map(4) = %x\n",
+ (u32) dma_drv_data->pipe_id_map[4]);
+ stm_dbg(DBG_ST.dma,
+ "==================================================\n");
+}
+
+/**
+ * initialize_dma_regs() - To Initialize the DMA global registers
+ *
+ */
+static inline void initialize_dma_regs(void)
+{
+ /*
+ * Some registers can only be touched in secure mode. Normally, we
+ * will not modify these registers, as xloader would initialize these
+ * registers for us.
+ *
+ * It appears that we are allowed a write if we don't change the value
+ * of the register.
+ */
+
+#ifndef CONFIG_STM_SECURITY
+ REG_WR_BITS(io_addr(DREG_GCC), 0xff01, FULL32_MASK, NO_SHIFT);
+#else
+ REG_WR_BITS(io_addr(DREG_GCC), 0x0, FULL32_MASK, NO_SHIFT);
+#endif
+
+ /*All resources are standard */
+ REG_WR_BITS(io_addr(DREG_PRTYP), 0x55555555, FULL32_MASK, NO_SHIFT);
+ /*All in non secure mode */
+ REG_WR_BITS(io_addr(DREG_PRSME), 0xaaaaaaaa, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(io_addr(DREG_PRSMO), 0xaaaaaaaa, FULL32_MASK, NO_SHIFT);
+ /*Basic mode */
+ REG_WR_BITS(io_addr(DREG_PRMSE), 0x55555555, FULL32_MASK, NO_SHIFT);
+ /*Basic mode */
+ REG_WR_BITS(io_addr(DREG_PRMSO), 0x55555555, FULL32_MASK, NO_SHIFT);
+ /*Basic mode */
+ REG_WR_BITS(io_addr(DREG_PRMOE), 0x55555555, FULL32_MASK, NO_SHIFT);
+ /*Basic mode */
+ REG_WR_BITS(io_addr(DREG_PRMOO), 0x55555555, FULL32_MASK, NO_SHIFT);
+ /***************************************************************/
+ /*Currently dont modify as we are only using basic mode and not logical */
+ REG_WR_BITS(io_addr(DREG_LCPA), 0x0, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(io_addr(DREG_LCLA), 0x0, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(io_addr(DREG_SLCPA), 0x0, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(io_addr(DREG_SLCLA), 0x0, FULL32_MASK, NO_SHIFT);
+ /***************************************************************/
+ /*Registers to activate channels */
+ REG_WR_BITS(io_addr(DREG_ACTIVE), 0x0, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(io_addr(DREG_ACTIVO), 0x0, FULL32_MASK, NO_SHIFT);
+ /***************************************************************/
+ REG_WR_BITS(io_addr(DREG_FSEB1), 0x0, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(io_addr(DREG_FSEB2), 0x0, FULL32_MASK, NO_SHIFT);
+ /***************************************************************/
+ /*Allow all interrupts */
+ REG_WR_BITS(io_addr(DREG_PCMIS), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT);
+ /*Clear all interrupts */
+ REG_WR_BITS(io_addr(DREG_PCICR), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT);
+
+ REG_WR_BITS(io_addr(DREG_SPCMIS), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(io_addr(DREG_SPCICR), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT);
+
+ REG_WR_BITS(io_addr(DREG_LCMIS(0)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(io_addr(DREG_LCMIS(1)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(io_addr(DREG_LCMIS(2)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(io_addr(DREG_LCMIS(3)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT);
+
+ REG_WR_BITS(io_addr(DREG_LCICR(0)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(io_addr(DREG_LCICR(1)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(io_addr(DREG_LCICR(2)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(io_addr(DREG_LCICR(3)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT);
+
+ REG_WR_BITS(io_addr(DREG_LCTIS(0)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(io_addr(DREG_LCTIS(1)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(io_addr(DREG_LCTIS(2)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(io_addr(DREG_LCTIS(3)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT);
+}
+
+/**
+ * print_channel_reg_params() - To print Channel registers of the physical
+ * channel for debug
+ * @channel: Physical channel whose register values to be printed
+ *
+ */
+static inline void print_channel_reg_params(int channel)
+{
+ if ((channel < 0) || (channel > MAX_AVAIL_PHY_CHANNELS)) {
+ stm_dbg(DBG_ST.dma, "Invalid channel number....");
+ return;
+ }
+ stm_dbg(DBG_ST.dma,
+ "\n===================================================\n");
+ stm_dbg(DBG_ST.dma, "\t\tChannel params %d\n", channel);
+ stm_dbg(DBG_ST.dma,
+ "\n===================================================\n");
+ stm_dbg(DBG_ST.dma, "CHANNEL_params_regs (CHAN_REG_sscfg_excfg)=%x\n",
+ ioread32(cio_addr(channel, CHAN_REG_SSCFG)));
+ stm_dbg(DBG_ST.dma, "CHANNEL_params_regs (CHAN_REG_sselt_exelt)=%x\n",
+ ioread32(cio_addr(channel, CHAN_REG_SSELT)));
+ stm_dbg(DBG_ST.dma, "CHANNEL_params_regs (CHAN_REG_ssptr_exptr)=%x\n",
+ ioread32(cio_addr(channel, CHAN_REG_SSPTR)));
+ stm_dbg(DBG_ST.dma, "CHANNEL_params_regs (CHAN_REG_sslnk_exlnk)=%x\n",
+ ioread32(cio_addr(channel, CHAN_REG_SSLNK)));
+ stm_dbg(DBG_ST.dma, "CHANNEL_params_regs (CHAN_REG_sdcfg_exexc)=%x\n",
+ ioread32(cio_addr(channel, CHAN_REG_SDCFG)));
+ stm_dbg(DBG_ST.dma, "CHANNEL_params_regs (CHAN_REG_sdelt_exfrm)=%x\n",
+ ioread32(cio_addr(channel, CHAN_REG_SDELT)));
+ stm_dbg(DBG_ST.dma, "CHANNEL_params_regs (CHAN_REG_sdptr_exrld)=%x\n",
+ ioread32(cio_addr(channel, CHAN_REG_SDPTR)));
+ stm_dbg(DBG_ST.dma, "CHANNEL_params_regs (CHAN_REG_sdlnk_exblk)=%x\n",
+ ioread32(cio_addr(channel, CHAN_REG_SDLNK)));
+ stm_dbg(DBG_ST.dma,
+ "\n=================================================\n");
+}
+
+/**
+ * print_dma_regs() - To print DMA global registers
+ *
+ */
+static void print_dma_regs(void)
+{
+ stm_dbg(DBG_ST.dma,
+ "\n=====================================================\n");
+ stm_dbg(DBG_ST.dma, "\t\tGLOBAL DMA REGISTERS");
+ stm_dbg(DBG_ST.dma,
+ "\n=====================================================\n");
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_gcc)=%x\n",
+ ioread32(io_addr(DREG_GCC)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_prtyp)=%x\n",
+ ioread32(io_addr(DREG_PRTYP)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_prsme)=%x\n",
+ ioread32(io_addr(DREG_PRSME)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_prsmo)=%x\n",
+ ioread32(io_addr(DREG_PRSMO)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_prmse)=%x\n",
+ ioread32(io_addr(DREG_PRMSE)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_prmso)=%x\n",
+ ioread32(io_addr(DREG_PRMSO)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_prmoe)=%x\n",
+ ioread32(io_addr(DREG_PRMOE)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_prmoo)=%x\n",
+ ioread32(io_addr(DREG_PRMOO)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcpa)=%x\n",
+ ioread32(io_addr(DREG_LCPA)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcla)=%x\n",
+ ioread32(io_addr(DREG_LCLA)));
+#ifndef CONFIG_STM_SECURITY
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcpa)=%x\n",
+ ioread32(io_addr(DREG_SLCPA)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcla) =%x\n",
+ ioread32(io_addr(DREG_SLCLA)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_sseg[0])=%x\n",
+ ioread32(io_addr(DREG_SSEG(0))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_sseg[1])=%x\n",
+ ioread32(io_addr(DREG_SSEG(1))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_sseg[2])=%x\n",
+ ioread32(io_addr(DREG_SSEG(2))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_sseg[3])=%x\n",
+ ioread32(io_addr(DREG_SSEG(3))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_sceg[0])=%x\n",
+ ioread32(io_addr(DREG_SCEG(0))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_sceg[1])=%x\n",
+ ioread32(io_addr(DREG_SCEG(1))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_sceg[2])=%x\n",
+ ioread32(io_addr(DREG_SCEG(2))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_sceg[3])=%x\n",
+ ioread32(io_addr(DREG_SCEG(3))));
+#endif
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_active)=%x\n",
+ ioread32(io_addr(DREG_ACTIVE)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_activo)=%x\n",
+ ioread32(io_addr(DREG_ACTIVO)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_fsebs1)=%x\n",
+ ioread32(io_addr(DREG_FSEB1)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_fsebs2)=%x\n",
+ ioread32(io_addr(DREG_FSEB2)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_pcmis)=%x\n",
+ ioread32(io_addr(DREG_PCMIS)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_pcicr)=%x\n",
+ ioread32(io_addr(DREG_PCICR)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_pctis)=%x\n",
+ ioread32(io_addr(DREG_PCTIS)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_pceis)=%x\n",
+ ioread32(io_addr(DREG_PCEIS)));
+#ifndef CONFIG_STM_SECURITY
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_spcmis)=%x\n",
+ ioread32(io_addr(DREG_SPCMIS)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_spcicr)=%x\n",
+ ioread32(io_addr(DREG_SPCICR)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_spctis)=%x\n",
+ ioread32(io_addr(DREG_SPCTIS)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_spceis)=%x\n",
+ ioread32(io_addr(DREG_SPCEIS)));
+#endif
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcmis[0])=%x\n",
+ ioread32(io_addr(DREG_LCMIS(0))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcmis[1])=%x\n",
+ ioread32(io_addr(DREG_LCMIS(1))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcmis[2])=%x\n",
+ ioread32(io_addr(DREG_LCMIS(2))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcmis[3])=%x\n",
+ ioread32(io_addr(DREG_LCMIS(3))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcicr[0])=%x\n",
+ ioread32(io_addr(DREG_LCICR(0))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcicr[1])=%x\n",
+ ioread32(io_addr(DREG_LCICR(1))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcicr[2])=%x\n",
+ ioread32(io_addr(DREG_LCICR(2))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcicr[3])=%x\n",
+ ioread32(io_addr(DREG_LCICR(3))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lctis[0])=%x\n",
+ ioread32(io_addr(DREG_LCTIS(0))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lctis[1])=%x\n",
+ ioread32(io_addr(DREG_LCTIS(1))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lctis[2])=%x\n",
+ ioread32(io_addr(DREG_LCTIS(2))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lctis[3])=%x\n",
+ ioread32(io_addr(DREG_LCTIS(3))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lceis[0])=%x\n",
+ ioread32(io_addr(DREG_LCEIS(0))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lceis[1])=%x\n",
+ ioread32(io_addr(DREG_LCEIS(1))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lceis[2])=%x\n",
+ ioread32(io_addr(DREG_LCEIS(2))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lceis[3])=%x\n",
+ ioread32(io_addr(DREG_LCEIS(3))));
+#ifndef CONFIG_STM_SECURITY
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcmis[0])=%x\n",
+ ioread32(io_addr(DREG_SLCMIS(0))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcmis[1])=%x\n",
+ ioread32(io_addr(DREG_SLCMIS(1))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcmis[2])=%x\n",
+ ioread32(io_addr(DREG_SLCMIS(2))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcmis[3])=%x\n",
+ ioread32(io_addr(DREG_SLCMIS(3))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcicr[0])=%x\n",
+ ioread32(io_addr(DREG_SLCICR(0))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcicr[1])=%x\n",
+ ioread32(io_addr(DREG_SLCICR(1))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcicr[2])=%x\n",
+ ioread32(io_addr(DREG_SLCICR(2))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcicr[3])=%x\n",
+ ioread32(io_addr(DREG_SLCICR(3))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slctis[0])=%x\n",
+ ioread32(io_addr(DREG_SLCTIS(0))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slctis[1])=%x\n",
+ ioread32(io_addr(DREG_SLCTIS(1))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slctis[2])=%x\n",
+ ioread32(io_addr(DREG_SLCTIS(2))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slctis[3])=%x\n",
+ ioread32(io_addr(DREG_SLCTIS(3))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slceis[0])=%x\n",
+ ioread32(io_addr(DREG_SLCEIS(0))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slceis[1])=%x\n",
+ ioread32(io_addr(DREG_SLCEIS(1))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slceis[2])=%x\n",
+ ioread32(io_addr(DREG_SLCEIS(2))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slceis[3])=%x\n",
+ ioread32(io_addr(DREG_SLCEIS(3))));
+#endif
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_stfu)=%x\n",
+ ioread32(io_addr(DREG_STFU)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_icfg)=%x\n",
+ ioread32(io_addr(DREG_ICFG)));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_mplug[0])=%x\n",
+ ioread32(io_addr(DREG_MPLUG(0))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_mplug[1])=%x\n",
+ ioread32(io_addr(DREG_MPLUG(1))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_mplug[2])=%x\n",
+ ioread32(io_addr(DREG_MPLUG(2))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_mplug[3])=%x\n",
+ ioread32(io_addr(DREG_MPLUG(3))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dma_periphid0)=%x\n",
+ ioread32(io_addr(DREG_PERIPHID(0))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dma_periphid1)=%x\n",
+ ioread32(io_addr(DREG_PERIPHID(1))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dma_periphid2)=%x\n",
+ ioread32(io_addr(DREG_PERIPHID(2))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dma_periphid3)=%x\n",
+ ioread32(io_addr(DREG_PERIPHID(2))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dma_cellid0)=%x\n",
+ ioread32(io_addr(DREG_CELLID(0))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dma_cellid1)=%x\n",
+ ioread32(io_addr(DREG_CELLID(1))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dma_cellid2)=%x\n",
+ ioread32(io_addr(DREG_CELLID(2))));
+ stm_dbg(DBG_ST.dma, "DMA_REGS (dma_cellid3)=%x\n",
+ ioread32(io_addr(DREG_CELLID(3))));
+ stm_dbg(DBG_ST.dma,
+ "\n===================================================\n");
+}
+
+/**
+ * print_dma_channel_info() - To print DMA channel info that is maintained by
+ * DMA driver internally
+ * @info: Info structure where information is maintained
+ *
+ */
+static void print_dma_channel_info(struct dma_channel_info *info)
+{
+ stm_dbg(DBG_ST.dma, " info->phys_chan_id = %d \n", info->phys_chan_id);
+ stm_dbg(DBG_ST.dma, " info->dir = %d \n", info->dir);
+ stm_dbg(DBG_ST.dma, " info->security = %d \n", info->security);
+ stm_dbg(DBG_ST.dma, " info->ch_status = %d \n", info->ch_status);
+ stm_dbg(DBG_ST.dma, " info->src_info.endianess = %d \n",
+ info->src_info.endianess);
+ stm_dbg(DBG_ST.dma, " info->src_info.data_width = %d \n",
+ info->src_info.data_width);
+ stm_dbg(DBG_ST.dma, " info->src_info.burst_size = %d \n",
+ info->src_info.burst_size);
+ stm_dbg(DBG_ST.dma, " info->src_info.buffer_type = %d \n",
+ info->src_info.buffer_type);
+ if (info->src_addr)
+ stm_dbg(DBG_ST.dma, " info->src_addr = %x \n",
+ (u32) info->src_addr);
+ stm_dbg(DBG_ST.dma, " info->dst_info.endianess = %d \n",
+ info->dst_info.endianess);
+ stm_dbg(DBG_ST.dma, " info->dst_info.data_width = %d \n",
+ info->dst_info.data_width);
+ stm_dbg(DBG_ST.dma, " info->dst_info.burst_size = %d \n",
+ info->dst_info.burst_size);
+ stm_dbg(DBG_ST.dma, " info->dst_info.buffer_type = %d \n",
+ info->dst_info.buffer_type);
+ if (info->dst_addr)
+ stm_dbg(DBG_ST.dma, " info->dst_addr = %x \n",
+ (u32) info->dst_addr);
+}
+
+/**
+ * is_pipeid_invalid() - To check validity of client pipe_id
+ * @pipe_id: pipe_id whose validity needs to be checked
+ *
+ * It will return -1 if pipe_id is invalid and 0 if valid
+ **/
+static inline int is_pipeid_invalid(int pipe_id)
+{
+ if ((pipe_id < 0)
+ || (pipe_id > (MAX_LOGICAL_CHANNELS + MAX_PHYSICAL_CHANNELS)))
+ return -1;
+ else {
+ if (test_bit(pipe_id, dma_drv_data->pipe_id_map))
+ return 0;
+ else
+ return -1;
+ }
+}
+
+/**
+ * get_xfer_len() - To get the length of the transfer
+ * @info: Information struct of the channel parameters.
+ *
+ */
+static inline int get_xfer_len(struct dma_channel_info *info)
+{
+ return info->xfer_len;
+}
+
+/**
+ * allocate_pipe_id() - To mark allocation of free pipe id.
+ *
+ * This function searches the pipe_id_map to find first free zero.
+ * Presence of zero means we can use this position number as a pipe id.
+ * After finding a position we mark it as unavailable, by writting a 1
+ * at that position in the map. This function returns -1 if it
+ * cannot find a free pipe_id, or it returns pipe_id (>=0)
+ *
+ */
+static int allocate_pipe_id(void)
+{
+ int id = 0;
+ unsigned long flags;
+ spin_lock_irqsave(&dma_drv_data->pipe_id_lock, flags);
+ id = find_first_zero_bit((const unsigned long
+ *)(dma_drv_data->pipe_id_map), NUM_CHANNELS);
+ if (id >= 0 && id < NUM_CHANNELS) {
+ test_and_set_bit((id % BITS_PER_LONG),
+ &(dma_drv_data->pipe_id_map[BIT_WORD(id)]));
+ stm_dbg(DBG_ST.dma,
+ "allocate_pipe_id():: Client Id allocated = %d\n", id);
+ } else {
+ stm_error("Unable to allocate free channel....\n");
+ id = -1;
+ }
+ spin_unlock_irqrestore(&dma_drv_data->pipe_id_lock, flags);
+ return id;
+}
+
+/**
+ * deallocate_pipe_id() - Function to deallocate already allocated pipe_id
+ * @pipe_id: Pipe id which needs to be deallocated.
+ *
+ * This function deallocates the pipe_id by clearing the corresponding
+ * bit position in the pipe_id_map which is the allocation map for
+ * DMA pipes.
+ *
+ */
+static void deallocate_pipe_id(int pipe_id)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&dma_drv_data->pipe_id_lock, flags);
+ test_and_clear_bit((pipe_id % BITS_PER_LONG),
+ &(dma_drv_data->pipe_id_map[BIT_WORD(pipe_id)]));
+ spin_unlock_irqrestore(&dma_drv_data->pipe_id_lock, flags);
+ print_allocation_map();
+}
+
+/**
+ * get_phys_res_security() - Returns security type of the Physical resource.
+ * @pr: Physical resource whose security has to be returned
+ *
+ */
+enum dma_chan_security get_phys_res_security(int pr)
+{
+#ifndef CONFIG_STM_SECURITY
+ if (pr % 2)
+ return REG_RD_BITS(io_addr(DREG_PRSMO),
+ PHYSICAL_RESOURCE_SECURE_MODE_MASK(pr),
+ PHYSICAL_RESOURCE_SECURE_MODE_POS(pr));
+ else
+ return REG_RD_BITS(io_addr(DREG_PRSME),
+ PHYSICAL_RESOURCE_SECURE_MODE_MASK(pr),
+ PHYSICAL_RESOURCE_SECURE_MODE_POS(pr));
+#else
+ return DMA_NONSECURE_CHAN;
+#endif
+
+}
+
+/**
+ * dma_channel_get_status() - To check the activation status of a physical channel
+ * @channel: Channel whose activation status is to be checked
+ *
+ */
+static inline int dma_channel_get_status(int channel)
+{
+
+ if (channel % 2 == 0)
+ return REG_RD_BITS(io_addr(DREG_ACTIVE),
+ ACT_PHY_RES_MASK
+ (channel), ACT_PHY_RES_POS(channel));
+ else
+ return REG_RD_BITS(io_addr(DREG_ACTIVO),
+ ACT_PHY_RES_MASK
+ (channel), ACT_PHY_RES_POS(channel));
+}
+
+/**
+ * dma_channel_execute_command() - To execute cmds like run, stop,
+ * suspend on phy channels
+ * @command: Command to be executed(run, stop, suspend, etc...)
+ * @channel: Channel on which these commands have to be executed
+ *
+ */
+static int dma_channel_execute_command(int command, int channel)
+{
+ int status = 0;
+ int iter = 0;
+
+ if (get_phys_res_security(channel) == DMA_NONSECURE_CHAN) {
+ switch (command) {
+ case DMA_RUN:
+ {
+ if (channel % 2 == 0)
+ REG_WR_BITS_1(io_addr
+ (DREG_ACTIVE),
+ DMA_RUN,
+ ACT_PHY_RES_MASK
+ (channel),
+ ACT_PHY_RES_POS(channel));
+ else
+ REG_WR_BITS_1(io_addr
+ (DREG_ACTIVO),
+ DMA_RUN,
+ ACT_PHY_RES_MASK
+ (channel),
+ ACT_PHY_RES_POS(channel));
+ return 0;
+ }
+ case DMA_STOP:
+ {
+ if (channel % 2 == 0)
+ REG_WR_BITS_1(io_addr
+ (DREG_ACTIVE),
+ DMA_STOP,
+ ACT_PHY_RES_MASK
+ (channel),
+ ACT_PHY_RES_POS(channel));
+ else
+ REG_WR_BITS_1(io_addr
+ (DREG_ACTIVO),
+ DMA_STOP,
+ ACT_PHY_RES_MASK
+ (channel),
+ ACT_PHY_RES_POS(channel));
+ return 0;
+ }
+ case DMA_SUSPEND_REQ:
+ {
+ status = dma_channel_get_status(channel);
+ if ((status == DMA_SUSPENDED)
+ || (status == DMA_STOP))
+ return 0;
+ if (channel % 2 == 0)
+ REG_WR_BITS_1(io_addr
+ (DREG_ACTIVE),
+ DMA_SUSPEND_REQ,
+ ACT_PHY_RES_MASK
+ (channel),
+ ACT_PHY_RES_POS(channel));
+ else
+ REG_WR_BITS_1(io_addr
+ (DREG_ACTIVO),
+ DMA_SUSPEND_REQ,
+ ACT_PHY_RES_MASK
+ (channel),
+ ACT_PHY_RES_POS(channel));
+ status = dma_channel_get_status(channel);
+ while ((status != DMA_STOP)
+ && (status != DMA_SUSPENDED)) {
+ if (iter == MAX_ITERATIONS) {
+ stm_error("Unable to suspend \
+ the Channel \
+ %d\n", channel);
+ return -1;
+ }
+ udelay(2);
+ status =
+ dma_channel_get_status(channel);
+ iter++;
+ }
+ return 0;
+ }
+ default:
+ {
+ stm_error("dma_channel_execute_command(): \
+ Unknown command \n");
+ return -1;
+ }
+ }
+ } else {
+ stm_error("Secure mode not activated yet!!\n");
+
+ }
+ return 0;
+}
+
+/**
+ * get_phy_res_usage_count() - To find how many clients are sharing
+ * this phy res.
+ * @pchan: id of Physical resource whose usage count has to be returned
+ * This function returns the number of clients sharing a physical resource.
+ * Count > 1 means, this is a logical resource.
+ *
+ */
+static inline int get_phy_res_usage_count(int pchan)
+{
+ int count;
+ count = dma_drv_data->pr_info[pchan].count;
+ return count;
+}
+
+/**
+ * release_phys_resource() - Function to deallocate a physical resource.
+ * @info: dma info staructure
+ * This function deallocates a physical resource
+ *
+ */
+
+static int release_phys_resource(struct dma_channel_info *info)
+{
+ int phy_channel = info->phys_chan_id;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dma_drv_data->pr_info_lock, flags);
+ if (dma_drv_data->pr_info[phy_channel].status == RESOURCE_LOGICAL) {
+ if (--dma_drv_data->pr_info[phy_channel].count == 0) {
+ if (dma_channel_execute_command
+ (DMA_SUSPEND_REQ, phy_channel) == -1) {
+ stm_error("Unable to suspend the Channel %d\n",
+ phy_channel);
+ goto error_release;
+ }
+ if (dma_channel_execute_command(DMA_STOP, phy_channel)
+ == -1) {
+ stm_error("Unable to stop the Channel %d\n",
+ phy_channel);
+ goto error_release;
+ }
+ dma_drv_data->pr_info[phy_channel].status =
+ RESOURCE_FREE;
+ /*Resource is clean now */
+ dma_drv_data->pr_info[phy_channel].dirty = 0;
+ }
+ } else if (dma_drv_data->pr_info[phy_channel].status ==
+ RESOURCE_PHYSICAL) {
+ dma_drv_data->pr_info[phy_channel].status = RESOURCE_FREE;
+ /*Resource is clean now */
+ dma_drv_data->pr_info[phy_channel].dirty = 0;
+ } else {
+ stm_error("\n Already freed");
+ goto error_release;
+ }
+ spin_unlock_irqrestore(&dma_drv_data->pr_info_lock, flags);
+ return 0;
+error_release:
+ spin_unlock_irqrestore(&dma_drv_data->pr_info_lock, flags);
+ return -1;
+}
+
+/**
+ * allocate_free_dma_channel() - To allocate free Physical channel for a
+ * dma xfer.
+ * @info: client id for which channel allocation has to be done
+ * This function allocates free Physical channel for a dma xfer.
+ * Allocation is done based on requirement of client and
+ * availability of channels.
+ * Logical channels would be used only for mem-periph, periph-mem.
+ * mem-mem, periph-periph would used Physical mode only.
+ * If a physical channel wants to reserve, a flag would mark
+ * the physical resource.
+ * If a logical channel has been requested, but corresponding
+ * Physical resource(based on event line of Logical channel)is
+ * reserved, request would be rejected straightaway.
+ *
+ */
+static int allocate_free_dma_channel(struct dma_channel_info *info)
+{
+ int i, j, tmp;
+ int event_group;
+ unsigned long flags;
+ if (info->dir == PERIPH_TO_PERIPH &&
+ (info->src_info.event_group != info->dst_info.event_group))
+ return -EINVAL;
+ if (info->dir == MEM_TO_PERIPH)
+ event_group = info->dst_info.event_group;
+ else
+ event_group = info->src_info.event_group;
+
+ spin_lock_irqsave(&dma_drv_data->pr_info_lock, flags);
+ if (info->chan_mode == DMA_CHAN_IN_PHYS_MODE) {
+ if (info->dir == MEM_TO_MEM) {
+ for (i = 0; i < MAX_AVAIL_PHY_CHANNELS; i++) {
+ if (dma_drv_data->pr_info[i].status ==
+ RESOURCE_FREE) {
+ info->phys_chan_id = i;
+ dma_drv_data->pr_info[i].status =
+ RESOURCE_PHYSICAL;
+ info->channel_id =
+ (MAX_LOGICAL_CHANNELS +
+ info->phys_chan_id);
+ goto done;
+ }
+ }
+ } else {
+ for (i = 0; i < MAX_AVAIL_PHY_CHANNELS; i += 8) {
+ tmp = i * 8 + event_group * 2;
+ for (j = tmp; j < tmp + 2; j++) {
+ if (dma_drv_data->pr_info[j].status ==
+ RESOURCE_FREE) {
+ info->phys_chan_id = j;
+ info->channel_id =
+ (MAX_LOGICAL_CHANNELS +
+ info->phys_chan_id);
+ dma_drv_data->
+ pr_info[j].status =
+ RESOURCE_PHYSICAL;
+ goto done;
+ }
+ }
+ }
+ }
+ } else { /* Logical mode */
+ if (info->dir == MEM_TO_PERIPH)
+ info->channel_id = 2 * (info->dst_dev_type) + 1;
+ else
+ info->channel_id = 2 * (info->src_dev_type);
+ if (info->dir == MEM_TO_MEM) {
+ spin_unlock_irqrestore(&dma_drv_data->pr_info_lock,
+ flags);
+ return -EINVAL;
+ } else {
+ for (i = 0; i < MAX_AVAIL_PHY_CHANNELS; i += 8) {
+ tmp = i * 8 + event_group * 2;
+ for (j = tmp; j < tmp + 2; j++) {
+ if (dma_drv_data->pr_info[j].status ==
+ RESOURCE_FREE
+ || dma_drv_data->
+ pr_info[j].status ==
+ RESOURCE_LOGICAL) {
+ if (dma_drv_data->
+ pr_info[j].count >= 16)
+ continue;
+ else {
+ dma_drv_data->pr_info
+ [j].count++;
+ info->phys_chan_id = j;
+ dma_drv_data->pr_info
+ [j].status =
+ RESOURCE_LOGICAL;
+ goto done;
+ }
+ }
+ }
+
+ }
+ }
+ }
+ spin_unlock_irqrestore(&dma_drv_data->pr_info_lock, flags);
+ return -EBUSY;
+done:
+ spin_unlock_irqrestore(&dma_drv_data->pr_info_lock, flags);
+ return 0;
+
+}
+
+/**
+ * get_phys_res_type() - returns Type of a Physical resource
+ * (standard or extended)
+ * @pr: Physical resource whose type will be returned
+ *
+ */
+static inline enum dma_phys_res_type get_phys_res_type(int pr)
+{
+ return REG_RD_BITS(io_addr(DREG_PRTYP),
+ PHYSICAL_RESOURCE_TYPE_MASK(pr),
+ PHYSICAL_RESOURCE_TYPE_POS(pr));
+}
+
+/**
+ * set_phys_res_type() - To set Type of a Phys resource(standard or extended)
+ * @pr: Physical resource whose type is to be set
+ * @type: standard or extended
+ *
+ */
+static inline void set_phys_res_type(int pr, enum dma_phys_res_type type)
+{
+ REG_WR_BITS(io_addr(DREG_PRTYP), type,
+ PHYSICAL_RESOURCE_TYPE_MASK(pr),
+ PHYSICAL_RESOURCE_TYPE_POS(pr));
+}
+
+/**
+ * set_phys_res_security() - To set security type of the Physical resource.
+ * @pr: Physical resource whose security has to be set
+ * @type: type (secure, non secure)
+ *
+ */
+static inline void set_phys_res_security(int pr,
+ enum dma_chan_security type)
+{
+ if (pr % 2)
+ REG_WR_BITS(io_addr(DREG_PRSMO), type,
+ PHYSICAL_RESOURCE_SECURE_MODE_MASK(pr),
+ PHYSICAL_RESOURCE_SECURE_MODE_POS(pr));
+ else
+ REG_WR_BITS(io_addr(DREG_PRSME), type,
+ PHYSICAL_RESOURCE_SECURE_MODE_MASK(pr),
+ PHYSICAL_RESOURCE_SECURE_MODE_POS(pr));
+}
+
+/**
+ * get_phys_res_mode() - To read the mode of the physical resource.
+ * @pr: Physical resource whose mode is to be retrieved.
+ * This function returns the current mode of the physical resources
+ * by reading the DMA control registers. It returns enum
+ * dma_channel_mode which is either DMA_CHAN_IN_PHYS_MODE,
+ * DMA_CHAN_IN_LOG_MODE ,DMA_CHAN_IN_OPERATION_MODE.
+ *
+ */
+static inline enum dma_channel_mode get_phys_res_mode(int pr)
+{
+ if (pr % 2)
+ return REG_RD_BITS(io_addr(DREG_PRMSO),
+ PHYSICAL_RESOURCE_CHANNEL_MODE_MASK
+ (pr),
+ PHYSICAL_RESOURCE_CHANNEL_MODE_POS(pr));
+ else
+ return REG_RD_BITS(io_addr(DREG_PRMSE),
+ PHYSICAL_RESOURCE_CHANNEL_MODE_MASK
+ (pr),
+ PHYSICAL_RESOURCE_CHANNEL_MODE_POS(pr));
+}
+
+/**
+ * set_phys_res_mode() - To set the mode of the Physical resource
+ * @pr: Physical resource whose mode has to be set
+ * @mode: The mode in which the physical resource is to be set.
+ *
+ */
+static inline void set_phys_res_mode(int pr, enum dma_channel_mode mode)
+{
+#if 0
+ if (pr % 2)
+ REG_WR_BITS(io_addr(DREG_PRMSO), mode,
+ PHYSICAL_RESOURCE_CHANNEL_MODE_MASK(pr),
+ PHYSICAL_RESOURCE_CHANNEL_MODE_POS(pr));
+ else
+ REG_WR_BITS(io_addr(DREG_PRMSE), mode,
+ PHYSICAL_RESOURCE_CHANNEL_MODE_MASK(pr),
+ PHYSICAL_RESOURCE_CHANNEL_MODE_POS(pr));
+#endif
+
+ if (get_phys_res_security(pr) == DMA_NONSECURE_CHAN) {
+ if (pr % 2)
+ REG_WR_BITS(io_addr(DREG_PRMSO), mode,
+ PHYSICAL_RESOURCE_CHANNEL_MODE_MASK
+ (pr),
+ PHYSICAL_RESOURCE_CHANNEL_MODE_POS(pr));
+ else
+ REG_WR_BITS(io_addr(DREG_PRMSE), mode,
+ PHYSICAL_RESOURCE_CHANNEL_MODE_MASK
+ (pr),
+ PHYSICAL_RESOURCE_CHANNEL_MODE_POS(pr));
+
+ } else {
+ stm_error("DMA Driver: Secure register not touched\n");
+ }
+}
+
+/**
+ * set_phys_res_mode_option() - To set the mode option of physical resource.
+ * @pr: Physical resource whose mode option needs to be set.
+ * @option: enum dma_channel_mode_option
+ *
+ */
+static inline void set_phys_res_mode_option(int pr,
+ enum dma_channel_mode_option
+ option)
+{
+#if 0
+ if (pr % 2)
+ REG_WR_BITS(io_addr(DREG_PRMOO), option,
+ PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_MASK
+ (pr),
+ PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS(pr));
+ else
+ REG_WR_BITS(io_addr(DREG_PRMOE), option,
+ PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_MASK
+ (pr),
+ PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS(pr));
+#endif
+ if (get_phys_res_security(pr) == DMA_NONSECURE_CHAN) {
+ if (pr % 2)
+ REG_WR_BITS(io_addr(DREG_PRMOO), option,
+ PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_MASK
+ (pr),
+ PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS
+ (pr));
+ else
+ REG_WR_BITS(io_addr(DREG_PRMOE), option,
+ PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_MASK
+ (pr),
+ PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS
+ (pr));
+ } else {
+ stm_error
+ ("DMA Driver:Secure reg not touched for mode option\n");
+ }
+
+}
+
+enum dma_channel_mode_option get_phys_res_mode_option(int pr)
+{
+ if (pr % 2)
+ return REG_RD_BITS(io_addr(DREG_PRMOO),
+ PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_MASK
+ (pr),
+ PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS
+ (pr));
+ else
+ return REG_RD_BITS(io_addr(DREG_PRMOE),
+ PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_MASK
+ (pr),
+ PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS
+ (pr));
+}
+
+/**
+ * set_event_line_security() - To set event line security
+ * @line: Event line whose security has to be set
+ * @event_group: Event group of the event line
+ * @security: Type of security(enum dma_chan_security) to set
+ *
+ */
+static inline void set_event_line_security(int line,
+ enum dma_event_group
+ event_group,
+ enum dma_chan_security security)
+{
+ u32 tmp;
+ if (security == DMA_SECURE_CHAN) {
+ tmp =
+ REG_RD_BITS(io_addr(DREG_SSEG(event_group)),
+ FULL32_MASK, NO_SHIFT);
+ tmp |= (0x1 << line);
+ REG_WR_BITS(io_addr(DREG_SSEG(event_group)), tmp,
+ FULL32_MASK, NO_SHIFT);
+ } else {
+ tmp =
+ REG_RD_BITS(io_addr(DREG_SCEG(event_group)),
+ FULL32_MASK, NO_SHIFT);
+ tmp |= (0x1 << line);
+ REG_WR_BITS(io_addr(DREG_SCEG(event_group)), tmp,
+ FULL32_MASK, NO_SHIFT);
+ }
+}
+
+/**
+ * create_elem_pool() - To create pool of elements
+ * @name: Name of the Element pool created
+ * @block_size: Number of bytes in one element
+ * @num_block: Number of elements.
+ * @allignment_bits: Allignment of memory allocated in terms of bit position
+ * This function creates a pool of "num_block" blocks with fixed
+ * block size of "block_size" It returns a logical address or null if
+ * allocation fails. It uses dma_alloc_coherent() for allocation of pool memory.
+ * The memory allocated would be alligned as given by allignment_bits argument.
+ * For e.g if allignment_bits = 16, then last 16 bits of alligned
+ * memory would be 0.
+ * This function returns pointer to the element pool created , or NULL on error
+ *
+ */
+static struct elem_pool *create_elem_pool(char *name, int block_size,
+ int num_block, int allignment_bits)
+{
+ int allignment_size;
+ int alloc_size;
+ struct elem_pool *pool = kzalloc(sizeof(struct elem_pool), GFP_KERNEL);
+ if (!pool) {
+ stm_error("Could not allocate memory for pool");
+ return NULL;
+ }
+
+ pool->num_blocks = num_block;
+ pool->block_size = block_size;
+ pool->allocation_map = 0;
+ spin_lock_init(&pool->pool_lock);
+ strcpy(pool->name, name);
+
+ if (allignment_bits <= PAGE_SHIFT) {
+ /*Because dma_alloc_coherent is already page_aligned */
+ void *ptr = dma_alloc_coherent(NULL,
+ num_block * block_size,
+ &pool->unalign_base.phys_addr,
+ GFP_KERNEL | GFP_DMA);
+ pool->unalign_base.log_addr = ptr;
+ pool->base_addr = pool->unalign_base;
+ pool->allocation_size = num_block * block_size;
+ } else {
+ void *ptr;
+
+ allignment_size = (0x1 << allignment_bits);
+ alloc_size =
+ num_block * block_size + allignment_size + sizeof(void *);
+
+ pool->allocation_size = alloc_size;
+ ptr = dma_alloc_coherent(NULL,
+ alloc_size,
+ &pool->unalign_base.phys_addr,
+ GFP_KERNEL | GFP_DMA);
+ pool->unalign_base.log_addr = ptr;
+ if ((pool->unalign_base.phys_addr % allignment_size +
+ pool->unalign_base.phys_addr) ==
+ pool->unalign_base.phys_addr) {
+ pool->base_addr.log_addr = pool->unalign_base.log_addr;
+ pool->base_addr.phys_addr =
+ pool->unalign_base.phys_addr;
+ stm_dbg(DBG_ST.dma, "No need to Allign.............\n");
+ goto complete_pool;
+ }
+
+ pool->base_addr.log_addr =
+ (char *)pool->unalign_base.log_addr +
+ sizeof(void *) + allignment_size;
+ pool->base_addr.log_addr =
+ (char *)pool->base_addr.log_addr -
+ ((unsigned long)pool->base_addr.log_addr) % allignment_size;
+
+ pool->base_addr.phys_addr = pool->unalign_base.phys_addr
+ + sizeof(void *) + allignment_size;
+ pool->base_addr.phys_addr = pool->base_addr.phys_addr
+ -
+ ((unsigned long)pool->base_addr.phys_addr) %
+ allignment_size;
+
+ pool->base_addr.log_addr = pool->unalign_base.log_addr
+ + ((unsigned long)pool->base_addr.phys_addr
+ - (unsigned long)pool->unalign_base.phys_addr);
+ }
+complete_pool:
+ stm_dbg(DBG_ST.dma,
+ "UNALLIGNED BASE ADDRESS :: LOGICAL = %x, PHYSICAL = %x\n",
+ (u32) pool->unalign_base.log_addr,
+ (u32) pool->unalign_base.phys_addr);
+ stm_dbg(DBG_ST.dma,
+ "ALLIGNED BASE ADDRESS :: LOGICAL = %x, PHYSICAL = %x\n",
+ (u32) pool->base_addr.log_addr,
+ (u32) pool->base_addr.phys_addr);
+ return pool;
+}
+
+static struct elem_pool *create_elem_pool_fixed_mem(char *name, int block_size,
+ int num_block, u32 mem_base,
+ int max_avail_mem)
+{
+ struct elem_pool *pool = kzalloc(sizeof(struct elem_pool), GFP_KERNEL);
+ if (!pool) {
+ stm_error("Could not allocate memory for pool");
+ return NULL;
+ }
+
+ pool->num_blocks = num_block;
+ pool->block_size = block_size;
+ pool->allocation_map = 0;
+ spin_lock_init(&pool->pool_lock);
+ strcpy(pool->name, name);
+
+ if ((block_size * num_block) > max_avail_mem) {
+ stm_error("Too much memory requested\n");
+ kfree(pool);
+ return NULL;
+ }
+ pool->unalign_base.log_addr = ioremap(mem_base, max_avail_mem);
+ if (!(pool->unalign_base.log_addr)) {
+ stm_error("Could not ioremap the LCLA memory\n");
+ kfree(pool);
+ return NULL;
+ }
+
+ pool->unalign_base.phys_addr = mem_base;
+ pool->base_addr = pool->unalign_base;
+ pool->allocation_size = num_block * block_size;
+
+ stm_dbg(DBG_ST.dma,
+ "UNALLIGNED BASE ADDRESS :: LOGICAL = %x, PHYSICAL = %x\n",
+ (u32) pool->unalign_base.log_addr,
+ (u32) pool->unalign_base.phys_addr);
+ stm_dbg(DBG_ST.dma,
+ "ALLIGNED BASE ADDRESS :: LOGICAL = %x, PHYSICAL = %x\n",
+ (u32) pool->base_addr.log_addr,
+ (u32) pool->base_addr.phys_addr);
+ return pool;
+}
+
+/**
+ * destroy_elem_pool() - To destroy the Element pool created
+ * @pool: Pointer to pool which needs to be destroyed
+ *
+ */
+static void destroy_elem_pool(struct elem_pool *pool)
+{
+ if (pool) {
+ dma_free_coherent(NULL, pool->allocation_size,
+ pool->unalign_base.log_addr,
+ pool->unalign_base.phys_addr);
+ kfree(pool);
+ }
+}
+
+/**
+ * get_free_block() - To allocate a Free block from an element pool
+ * @pool: Pointer to pool from which free block is required
+ * This function checks in the allocation bitmap of the pool
+ * and returns a free block after setting corresponding bit in the
+ * allocation map of the pool.
+ * It will return block id(>=0) on success and -1 on failure.
+ */
+static int get_free_block(struct elem_pool *pool)
+{
+ int i;
+ stm_dbg(DBG_ST.dma, "%s :: Allocation Map: %d\n", pool->name,
+ pool->allocation_map);
+ spin_lock(&pool->pool_lock);
+ for (i = 0; i < pool->num_blocks; i++) {
+ if (!(pool->allocation_map & (0x1 << i))) {
+ pool->allocation_map |= (0x1 << i);
+ spin_unlock(&pool->pool_lock);
+ return i;
+ }
+ }
+ spin_unlock(&pool->pool_lock);
+ return -1;
+}
+
+/**
+ * get_free_log_lli_block() - To allocate a Free block for a Logical channel
+ * @pool: Element pool from where allocation has to be done
+ * @pchan: Physical resource corresponding to the Logical channel
+ * There are a fixed number of blocks for Logical LLI per physical channel.
+ * Hence allocation is done by searching free blocks for a particular
+ * physical channel. It will return block id(>=0) on success and -1 on failure.
+ *
+ */
+static int get_free_log_lli_block(struct elem_pool *pool, int pchan)
+{
+ int i = 0;
+ int num_log_lli_blocks;
+ num_log_lli_blocks = 126 / NUM_LLI_PER_LOG_CHANNEL;
+
+ stm_dbg(DBG_ST.dma, "NAME:%s :: Phys_chan:: %d :: Allocation Map: %d\n",
+ pool->name, pchan, pool->lchan_allocation_map[pchan]);
+ spin_lock(&pool->pool_lock);
+ for (i = 0; i < num_log_lli_blocks; i++) {
+ if (!(pool->lchan_allocation_map[pchan] & (0x1 << i))) {
+ pool->lchan_allocation_map[pchan] |= (0x1 << i);
+ spin_unlock(&pool->pool_lock);
+ return i;
+ }
+ }
+ spin_unlock(&pool->pool_lock);
+ return -1;
+}
+
+/**
+ * rel_free_log_lli_block() - To release a Free block for a Logical channel
+ * @pool: Element pool from where relese has to be done
+ * @pchan: Physical resource corresponding to this Logical channel
+ * @idx: index of the block to be released
+ *
+ */
+static void rel_free_log_lli_block(struct elem_pool *pool, int pchan, int idx)
+{
+ int num_log_lli_blocks;
+ num_log_lli_blocks = 126 / NUM_LLI_PER_LOG_CHANNEL;
+
+ stm_dbg(DBG_ST.dma, "NAME:%s :: Phys_chan:: %d :: Allocation Map: %d\n",
+ pool->name, pchan, pool->lchan_allocation_map[pchan]);
+ spin_lock(&pool->pool_lock);
+ pool->lchan_allocation_map[pchan] &= (~(0x1 << idx));
+ spin_unlock(&pool->pool_lock);
+}
+
+/**
+ * release_block() - To release a Free block
+ * @idx: index of the block to be released
+ * @pool: Pool from which block is to be released
+ *
+ */
+static void release_block(int idx, struct elem_pool *pool)
+{
+ if (idx < pool->num_blocks) {
+ spin_lock(&pool->pool_lock);
+ pool->allocation_map &= (~(0x1 << idx));
+ spin_unlock(&pool->pool_lock);
+ }
+}
+
+int calculate_lli_required(struct dma_channel_info *info,
+ int *lli_size_req)
+{
+ int lli_count = 0;
+ int lli_size = 0;
+ int xfer_len = get_xfer_len(info);
+
+ u32 src_data_width = (0x1 << info->src_info.data_width);
+ u32 dst_data_width = (0x1 << info->dst_info.data_width);
+
+ lli_size = ((SIXTY_FOUR_KB - 4) *
+ ((dst_data_width >
+ src_data_width) ? src_data_width : dst_data_width));
+
+ lli_count = xfer_len / lli_size;
+ if (xfer_len % lli_size)
+ lli_count++;
+ *lli_size_req = lli_size;
+ stm_dbg(DBG_ST.dma, "LLI_size = %d LLI Count = %d\n", lli_size,
+ lli_count);
+ return lli_count;
+}
+
+/**
+ * generate_sg_list() - To Generate a sg list if DMA xfer len > 64K elems
+ * @info: Information of the channel parameters.
+ * @type: Whether Source or Destination half channel.
+ * @lli_size: Max size of each LLI to be generated.
+ * @lli_count: Number of LLI's to be generated.
+ * This function generates a sg list by breaking current length into
+ * length of size lli_size. It will generate lli_count lli's. It will
+ * finally return the sg list.
+ *
+ */
+struct scatterlist *generate_sg_list(struct dma_channel_info *info,
+ enum dma_half_chan type, int lli_size,
+ int lli_count)
+{
+ struct scatterlist *sg = NULL;
+ struct scatterlist *temp_sg = NULL;
+ int i = 0;
+ void *temp_addr;
+
+ if (type == DMA_SRC_HALF_CHANNEL) {
+ if (info->sg_block_id_src < 0)
+ info->sg_block_id_src =
+ get_free_block(dma_drv_data->sg_pool);
+ sg = ((struct scatterlist *)((u32) dma_drv_data->sg_pool->
+ base_addr.log_addr +
+ info->sg_block_id_src *
+ dma_drv_data->sg_pool->
+ block_size));
+ info->sgcount_src = lli_count;
+ info->sg_src = sg;
+ temp_addr = info->src_addr;
+ } else {
+ if (info->sg_block_id_dest < 0)
+ info->sg_block_id_dest =
+ get_free_block(dma_drv_data->sg_pool);
+ sg = ((struct scatterlist *)((u32) dma_drv_data->sg_pool->
+ base_addr.log_addr +
+ info->sg_block_id_dest *
+ dma_drv_data->sg_pool->
+ block_size));
+ info->sgcount_dest = lli_count;
+ info->sg_dest = sg;
+ temp_addr = info->dst_addr;
+ }
+
+ sg_init_table(sg, lli_count);
+ for_each_sg(sg, temp_sg, lli_count, i) {
+ if ((type == DMA_SRC_HALF_CHANNEL)
+ && ((info->dir == PERIPH_TO_MEM)
+ || (info->dir == PERIPH_TO_PERIPH)))
+ temp_sg->dma_address = (dma_addr_t) temp_addr;
+ else if ((type == DMA_DEST_HALF_CHANNEL)
+ && ((info->dir == MEM_TO_PERIPH)
+ || (info->dir == PERIPH_TO_PERIPH)))
+ temp_sg->dma_address = (dma_addr_t) temp_addr;
+ else
+ temp_sg->dma_address =
+ (dma_addr_t) (temp_addr + i * (lli_size));
+
+ temp_sg->length = lli_size;
+ temp_sg->offset = 0;
+ if (i == (lli_count - 1)) {
+ int len = get_xfer_len(info) % lli_size;
+ if (len)
+ temp_sg->length = len;
+ }
+ }
+ return sg;
+}
+
+/**
+ * map_lli_info_log_chan() - To Map the SG info into LLI's for Log channels.
+ * @info: Information of the channel parameters.
+ * @type: Whether source or destination half channel.
+ * @params: Memory location pointer where standard Logical channel register
+ * parameters are Loaded.
+ * This function maps the SG info into LLI's for the Logical channels.
+ * A free block of LLI's is allocated for a particular physical
+ * channel and SG info is mapped in that memory block. For a particular
+ * physical channel 1Kb of memory is there for LLI's which has to be
+ * shared by all Logical channels running on it.
+ * It returns 0 on success, -1 on failure.
+ *
+ */
+static int map_lli_info_log_chan(struct dma_channel_info *info, int type,
+ struct std_log_memory_param *params)
+{
+ int idx = 0;
+ struct scatterlist *sg;
+ u32 step_size = 0;
+ u32 lli_count = 0;
+ void *base =
+ dma_drv_data->lchan_lli_pool->base_addr.log_addr +
+ info->phys_chan_id * 1024;
+
+ stm_dbg(DBG_ST.dma, "Setting LLI for %s\n",
+ (type ==
+ DMA_SRC_HALF_CHANNEL) ? "DMA_SRC_HALF_CHANNEL" :
+ "DMA_DEST_HALF_CHANNEL");
+
+ if (type == DMA_SRC_HALF_CHANNEL) {
+ struct dma_logical_src_lli_info *lli_ptr = NULL;
+ u32 slos;
+ step_size = (0x1 << info->src_info.data_width);
+ sg = info->sg_src;
+ lli_count = info->sgcount_src;
+ if (info->lli_block_id_src < 0)
+ info->lli_block_id_src =
+ get_free_log_lli_block(dma_drv_data->lchan_lli_pool,
+ info->phys_chan_id);
+ if (info->lli_block_id_src < 0) {
+ stm_error("Free LLI's not available\n");
+ return -1;
+ }
+
+ slos = info->lli_block_id_src * NUM_LLI_PER_LOG_CHANNEL + 1;
+ /*********************************************************/
+ /*Use first SG item to fill params register */
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSELT),
+ info->phys_chan_id, SREG_ELEM_LOG_LIDX_MASK,
+ SREG_ELEM_LOG_LIDX_POS);
+ MEM_WRITE_BITS(params->dmac_lcsp0,
+ (sg_dma_len(sg) >> info->src_info.data_width),
+ MEM_LCSP0_ECNT_MASK, MEM_LCSP0_ECNT_POS);
+ MEM_WRITE_BITS(params->dmac_lcsp1, slos, MEM_LCSP1_SLOS_MASK,
+ MEM_LCSP1_SLOS_POS);
+ MEM_WRITE_BITS(params->dmac_lcsp0,
+ (0x0000FFFFUL & (u32) (sg_dma_address(sg))),
+ MEM_LCSP0_SPTR_MASK, MEM_LCSP0_SPTR_POS);
+ MEM_WRITE_BITS(params->dmac_lcsp1,
+ (0xFFFF0000 & (u32) (sg_dma_address(sg))) >> 16,
+ MEM_LCSP1_SPTR_MASK, MEM_LCSP1_SPTR_POS);
+ if ((info->lli_interrupt == 1) && (info->dir == PERIPH_TO_MEM))
+ MEM_WRITE_BITS(params->dmac_lcsp1, DMA_TRUE,
+ MEM_LCSP1_SCFG_TIM_MASK,
+ MEM_LCSP1_SCFG_TIM_POS);
+ else
+ MEM_WRITE_BITS(params->dmac_lcsp1, DMA_FALSE,
+ MEM_LCSP1_SCFG_TIM_MASK,
+ MEM_LCSP1_SCFG_TIM_POS);
+ sg++;
+ lli_count--;
+ /***********************************************************/
+ lli_ptr = (struct dma_logical_src_lli_info *)base + slos;
+
+ for (idx = 0; idx < lli_count; idx++) {
+ lli_ptr[idx].dmac_lcsp1 = params->dmac_lcsp1;
+ MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp0,
+ (sg_dma_len(sg) >> info->
+ src_info.data_width),
+ MEM_LCSP0_ECNT_MASK, MEM_LCSP0_ECNT_POS);
+ MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp0,
+ (0x0000FFFFUL &
+ (u32) (sg_dma_address(sg))),
+ MEM_LCSP0_SPTR_MASK, MEM_LCSP0_SPTR_POS);
+ MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp1,
+ (0xFFFF0000UL &
+ (u32) (sg_dma_address(sg))) >> 16,
+ MEM_LCSP1_SPTR_MASK, MEM_LCSP1_SPTR_POS);
+ MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp1,
+ (slos + idx + 1), MEM_LCSP1_SLOS_MASK,
+ MEM_LCSP1_SLOS_POS);
+ if ((info->lli_interrupt == 1)
+ && (info->dir == PERIPH_TO_MEM))
+ MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp1,
+ DMA_TRUE,
+ MEM_LCSP1_SCFG_TIM_MASK,
+ MEM_LCSP1_SCFG_TIM_POS);
+ else
+ MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp1,
+ DMA_FALSE,
+ MEM_LCSP1_SCFG_TIM_MASK,
+ MEM_LCSP1_SCFG_TIM_POS);
+ sg++;
+ }
+ MEM_WRITE_BITS(lli_ptr[idx - 1].dmac_lcsp1, 0x0,
+ MEM_LCSP1_SLOS_MASK, MEM_LCSP1_SLOS_POS);
+ MEM_WRITE_BITS(lli_ptr[idx - 1].dmac_lcsp1, DMA_TRUE,
+ MEM_LCSP1_SCFG_TIM_MASK, MEM_LCSP1_SCFG_TIM_POS);
+ } else {
+ struct dma_logical_dest_lli_info *lli_ptr = NULL;
+ u32 dlos;
+ step_size = (0x1 << info->dst_info.data_width);
+ lli_count = info->sgcount_dest;
+ sg = info->sg_dest;
+ info->current_sg = sg;
+ if (info->lli_block_id_dest < 0)
+ info->lli_block_id_dest =
+ get_free_log_lli_block(dma_drv_data->lchan_lli_pool,
+ info->phys_chan_id);
+ if (info->lli_block_id_dest < 0) {
+ stm_error("Free LLI's not available\n");
+ return -1;
+ }
+ dlos = info->lli_block_id_dest * NUM_LLI_PER_LOG_CHANNEL + 1;
+ /**********************************************************/
+ /*Use first SG item to fill params register */
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDELT),
+ info->phys_chan_id, SREG_ELEM_LOG_LIDX_MASK,
+ SREG_ELEM_LOG_LIDX_POS);
+ MEM_WRITE_BITS(params->dmac_lcsp2,
+ (sg_dma_len(sg) >> info->dst_info.data_width),
+ MEM_LCSP2_ECNT_MASK, MEM_LCSP2_ECNT_POS);
+ MEM_WRITE_BITS(params->dmac_lcsp3, dlos, MEM_LCSP3_DLOS_MASK,
+ MEM_LCSP3_DLOS_POS);
+ MEM_WRITE_BITS(params->dmac_lcsp2,
+ (0x0000FFFFUL & (u32) (sg_dma_address(sg))),
+ MEM_LCSP2_DPTR_MASK, MEM_LCSP2_DPTR_POS);
+ MEM_WRITE_BITS(params->dmac_lcsp3,
+ (0xFFFF0000UL & (u32) (sg_dma_address(sg))) >>
+ 16, MEM_LCSP3_DPTR_MASK, MEM_LCSP3_DPTR_POS);
+ if (info->lli_interrupt == 1)
+ MEM_WRITE_BITS(params->dmac_lcsp3, DMA_TRUE,
+ MEM_LCSP3_DCFG_TIM_MASK,
+ MEM_LCSP3_DCFG_TIM_POS);
+ else
+ MEM_WRITE_BITS(params->dmac_lcsp3, DMA_FALSE,
+ MEM_LCSP3_DCFG_TIM_MASK,
+ MEM_LCSP3_DCFG_TIM_POS);
+ sg++;
+ lli_count--;
+ /************************************************************/
+ lli_ptr = (struct dma_logical_dest_lli_info *)base + dlos;
+
+ for (idx = 0; idx < lli_count; idx++) {
+ lli_ptr[idx].dmac_lcsp3 = params->dmac_lcsp3;
+ MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp2,
+ (sg_dma_len(sg) >> info->
+ dst_info.data_width),
+ MEM_LCSP2_ECNT_MASK, MEM_LCSP2_ECNT_POS);
+ MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp2,
+ (0x0000FFFFUL &
+ (u32) (sg_dma_address(sg))),
+ MEM_LCSP2_DPTR_MASK, MEM_LCSP2_DPTR_POS);
+ MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp3,
+ (0xFFFF0000UL &
+ (u32) (sg_dma_address(sg))) >> 16,
+ MEM_LCSP3_DPTR_MASK, MEM_LCSP3_DPTR_POS);
+ MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp3,
+ (dlos + idx + 1), MEM_LCSP3_DLOS_MASK,
+ MEM_LCSP3_DLOS_POS);
+ if (info->lli_interrupt == 1)
+ MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp3,
+ DMA_TRUE,
+ MEM_LCSP3_DCFG_TIM_MASK,
+ MEM_LCSP3_DCFG_TIM_POS);
+ else
+ MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp3,
+ DMA_FALSE,
+ MEM_LCSP3_DCFG_TIM_MASK,
+ MEM_LCSP3_DCFG_TIM_POS);
+ sg++;
+ }
+ MEM_WRITE_BITS(lli_ptr[idx - 1].dmac_lcsp3, 0x0,
+ MEM_LCSP3_DLOS_MASK, MEM_LCSP3_DLOS_POS);
+ MEM_WRITE_BITS(lli_ptr[idx - 1].dmac_lcsp3, DMA_TRUE,
+ MEM_LCSP3_DCFG_TIM_MASK, MEM_LCSP3_DCFG_TIM_POS);
+ }
+ return 0;
+}
+
+/**
+ * map_lli_info_phys_chan() - To Map the SG info into LLI's for Phys channels.
+ * @info: Information of the channel parameters.
+ * @type: Whether source or destination half channel.
+ * This function maps the SG info into LLI's for the Physical channels.
+ * A free block of LLI's is allocated for a particular physical
+ * channel and SG info is mapped in that memory block.
+ * This function returns 0 on success and -1 on failure
+ *
+ */
+static int map_lli_info_phys_chan(struct dma_channel_info *info, int type)
+{
+ int idx = 0;
+ struct dma_lli_info *lli_ptr = NULL;
+ u32 temp;
+ dma_addr_t phys_lli_addr = 0;
+ struct scatterlist *sg;
+ u32 lli_count = 0;
+ u32 fifo_ptr_incr = 0;
+ stm_dbg(DBG_ST.dma, "map_lli_info_phys_chan():: Setting LLI for %s\n",
+ (type ==
+ DMA_SRC_HALF_CHANNEL) ? "DMA_SRC_HALF_CHANNEL" :
+ "DMA_DEST_HALF_CHANNEL");
+
+ if (type == DMA_SRC_HALF_CHANNEL) {
+ sg = info->sg_src;
+ lli_count = info->sgcount_src;
+ if (info->src_info.addr_inc)
+ fifo_ptr_incr = (0x1 << info->src_info.data_width);
+ if (info->lli_block_id_src < 0)
+ info->lli_block_id_src =
+ get_free_block(dma_drv_data->pchan_lli_pool);
+ if (info->lli_block_id_src < 0) {
+ stm_error("Free LLI's not available\n");
+ return -1;
+ }
+ temp = ((u32) dma_drv_data->pchan_lli_pool->base_addr.log_addr +
+ info->lli_block_id_src *
+ dma_drv_data->pchan_lli_pool->block_size);
+ lli_ptr = (struct dma_lli_info *)temp;
+ temp = (u32) (dma_drv_data->pchan_lli_pool->base_addr.phys_addr
+ +
+ info->lli_block_id_src
+ * dma_drv_data->pchan_lli_pool->block_size);
+ phys_lli_addr = (dma_addr_t) temp;
+ if (info->link_type == POSTLINK) {
+ REG_WR_BITS(cio_addr
+ (info->phys_chan_id, CHAN_REG_SSELT),
+ (sg_dma_len(sg) >> info->
+ src_info.data_width),
+ SREG_ELEM_PHY_ECNT_MASK,
+ SREG_ELEM_PHY_ECNT_POS);
+ REG_WR_BITS(cio_addr
+ (info->phys_chan_id, CHAN_REG_SSELT),
+ fifo_ptr_incr, SREG_ELEM_PHY_EIDX_MASK,
+ SREG_ELEM_PHY_EIDX_POS);
+ REG_WR_BITS(cio_addr
+ (info->phys_chan_id, CHAN_REG_SSPTR),
+ sg_dma_address(sg), FULL32_MASK, NO_SHIFT);
+ sg++;
+ lli_count--;
+ }
+
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSLNK),
+ (u32) (phys_lli_addr), FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSLNK),
+ info->link_type, SREG_LNK_PHYS_PRE_MASK,
+ SREG_LNK_PHY_PRE_POS);
+
+ for (idx = 0; idx < lli_count; idx++) {
+ lli_ptr[idx].reg_cfg =
+ REG_RD_BITS(cio_addr
+ (info->phys_chan_id,
+ CHAN_REG_SSCFG), FULL32_MASK,
+ NO_SHIFT);
+ lli_ptr[idx].reg_elt =
+ REG_RD_BITS(cio_addr
+ (info->phys_chan_id,
+ CHAN_REG_SSELT), FULL32_MASK,
+ NO_SHIFT);
+ MEM_WRITE_BITS(lli_ptr[idx].reg_elt,
+ (sg_dma_len(sg) >> info->
+ src_info.data_width),
+ SREG_ELEM_PHY_ECNT_MASK,
+ SREG_ELEM_PHY_ECNT_POS);
+ MEM_WRITE_BITS(lli_ptr[idx].reg_elt, fifo_ptr_incr,
+ SREG_ELEM_PHY_EIDX_MASK,
+ SREG_ELEM_PHY_EIDX_POS);
+ lli_ptr[idx].reg_ptr = sg_dma_address(sg);
+ lli_ptr[idx].reg_lnk =
+ (u32) (phys_lli_addr +
+ (idx + 1) * sizeof(struct dma_lli_info));
+ MEM_WRITE_BITS(lli_ptr[idx].reg_lnk, info->link_type,
+ SREG_LNK_PHYS_PRE_MASK,
+ SREG_LNK_PHY_PRE_POS);
+
+ sg++;
+ print_dma_lli(idx, &lli_ptr[idx]);
+ }
+ lli_ptr[idx - 1].reg_lnk = 0x0;
+ MEM_WRITE_BITS(lli_ptr[idx - 1].reg_lnk, info->link_type,
+ SREG_LNK_PHYS_PRE_MASK, SREG_LNK_PHY_PRE_POS);
+ MEM_WRITE_BITS(lli_ptr[idx - 1].reg_lnk, DMA_TRUE,
+ SREG_LNK_PHYS_TCP_MASK, SREG_LNK_PHY_TCP_POS);
+ MEM_WRITE_BITS(lli_ptr[idx - 1].reg_cfg, DMA_TRUE,
+ SREG_CFG_PHY_TIM_MASK, SREG_CFG_PHY_TIM_POS);
+
+ } else {
+ sg = info->sg_dest;
+ info->current_sg = sg;
+ lli_count = info->sgcount_dest;
+ if ((info->dst_info.addr_inc))
+ fifo_ptr_incr = (0x1 << info->dst_info.data_width);
+ info->lli_block_id_dest =
+ get_free_block(dma_drv_data->pchan_lli_pool);
+ if (info->lli_block_id_dest < 0) {
+ stm_error("Free LLI's not available\n");
+ return -1;
+ }
+
+ lli_ptr = (struct dma_lli_info *)
+ (dma_drv_data->pchan_lli_pool->base_addr.log_addr +
+ info->lli_block_id_dest *
+ dma_drv_data->pchan_lli_pool->block_size);
+ phys_lli_addr = (dma_addr_t) (((u32)
+ dma_drv_data->pchan_lli_pool->
+ base_addr.phys_addr +
+ info->lli_block_id_dest *
+ dma_drv_data->pchan_lli_pool->
+ block_size));
+
+ if (info->link_type == POSTLINK) {
+ if ((info->dir != MEM_TO_MEM)
+ && (info->lli_interrupt == 1))
+ REG_WR_BITS(cio_addr
+ (info->phys_chan_id,
+ CHAN_REG_SDCFG),
+ DMA_TRUE,
+ SREG_CFG_PHY_TIM_MASK,
+ SREG_CFG_PHY_TIM_POS);
+ else
+ REG_WR_BITS(cio_addr
+ (info->phys_chan_id,
+ CHAN_REG_SDCFG),
+ DMA_FALSE,
+ SREG_CFG_PHY_TIM_MASK,
+ SREG_CFG_PHY_TIM_POS);
+ REG_WR_BITS(cio_addr
+ (info->phys_chan_id, CHAN_REG_SDELT),
+ (sg_dma_len(sg)) >> info->
+ dst_info.data_width,
+ SREG_ELEM_PHY_ECNT_MASK,
+ SREG_ELEM_PHY_ECNT_POS);
+ REG_WR_BITS(cio_addr
+ (info->phys_chan_id, CHAN_REG_SDELT),
+ fifo_ptr_incr, SREG_ELEM_PHY_EIDX_MASK,
+ SREG_ELEM_PHY_EIDX_POS);
+ REG_WR_BITS(cio_addr
+ (info->phys_chan_id, CHAN_REG_SDPTR),
+ sg_dma_address(sg), FULL32_MASK, NO_SHIFT);
+ sg++;
+ lli_count--;
+ }
+
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDLNK),
+ (u32) (phys_lli_addr), FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDLNK),
+ info->link_type, SREG_LNK_PHYS_PRE_MASK,
+ SREG_LNK_PHY_PRE_POS);
+
+ for (idx = 0; idx < lli_count; idx++) {
+ lli_ptr[idx].reg_cfg =
+ REG_RD_BITS(cio_addr
+ (info->phys_chan_id,
+ CHAN_REG_SDCFG), FULL32_MASK,
+ NO_SHIFT);
+ lli_ptr[idx].reg_lnk =
+ (u32) (phys_lli_addr +
+ (idx + 1) * sizeof(struct dma_lli_info));
+ MEM_WRITE_BITS(lli_ptr[idx].reg_lnk, info->link_type,
+ SREG_LNK_PHYS_PRE_MASK,
+ SREG_LNK_PHY_PRE_POS);
+ lli_ptr[idx].reg_elt =
+ REG_RD_BITS(cio_addr
+ (info->phys_chan_id,
+ CHAN_REG_SDELT), FULL32_MASK,
+ NO_SHIFT);
+ MEM_WRITE_BITS(lli_ptr[idx].reg_elt,
+ (sg_dma_len(sg) >> info->
+ dst_info.data_width),
+ SREG_ELEM_PHY_ECNT_MASK,
+ SREG_ELEM_PHY_ECNT_POS);
+ MEM_WRITE_BITS(lli_ptr[idx].reg_elt, fifo_ptr_incr,
+ SREG_ELEM_PHY_EIDX_MASK,
+ SREG_ELEM_PHY_EIDX_POS);
+ lli_ptr[idx].reg_ptr = sg_dma_address(sg);
+ if ((info->dir != MEM_TO_MEM)
+ && (info->lli_interrupt == 1))
+ MEM_WRITE_BITS(lli_ptr[idx].reg_cfg,
+ DMA_TRUE,
+ SREG_CFG_PHY_TIM_MASK,
+ SREG_CFG_PHY_TIM_POS);
+ else
+ MEM_WRITE_BITS(lli_ptr[idx].reg_cfg,
+ DMA_FALSE,
+ SREG_CFG_PHY_TIM_MASK,
+ SREG_CFG_PHY_TIM_POS);
+ print_dma_lli(idx, &lli_ptr[idx]);
+ sg++;
+ }
+ MEM_WRITE_BITS(lli_ptr[idx - 1].reg_cfg, DMA_TRUE,
+ SREG_CFG_PHY_TIM_MASK, SREG_CFG_PHY_TIM_POS);
+ lli_ptr[idx - 1].reg_lnk = 0x0;
+ MEM_WRITE_BITS(lli_ptr[idx - 1].reg_lnk, info->link_type,
+ SREG_LNK_PHYS_PRE_MASK, SREG_LNK_PHY_PRE_POS);
+ MEM_WRITE_BITS(lli_ptr[idx - 1].reg_lnk, DMA_TRUE,
+ SREG_LNK_PHYS_TCP_MASK, SREG_LNK_PHY_TCP_POS);
+ }
+ return 0;
+}
+
+/**
+ * set_std_phy_src_half_channel_params() - set params for src phy half channel
+ * @info: Information of the channel parameters.
+ * This function sets the channel Parameters for standard source half channel.
+ * Channel is configured as Physical channel. It maps sg info by calling
+ * map_lli_info_phys_chan() for src channel. If transfer length is more than
+ * 64K elements, it calls calculate_lli_required() and generate_sg_list()
+ * API's to create LLI's.
+ * It returns 0 on success and -1 on failure
+ *
+ */
+static int set_std_phy_src_half_channel_params(struct dma_channel_info
+ *info)
+{
+ u32 num_elems;
+ u32 step_size = 0;
+ if (info->src_info.addr_inc)
+ step_size = (0x1 << info->src_info.data_width);
+
+ num_elems = info->src_xfer_elem;
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSCFG),
+ info->src_cfg, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSPTR), 0x0,
+ FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSELT), 0x0,
+ FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSLNK), 0x0,
+ FULL32_MASK, NO_SHIFT);
+
+ if ((num_elems >= MAX_NUM_OF_ELEM_IN_A_XFER) || (info->sg_src)) {
+ u32 lli_size;
+ u32 lli_count;
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSCFG),
+ DMA_FALSE, SREG_CFG_PHY_TIM_MASK,
+ SREG_CFG_PHY_TIM_POS);
+ if (!info->sg_src) {
+ lli_count = calculate_lli_required(info, &lli_size);
+ if (lli_count > NUM_SG_PER_REQUEST) {
+ stm_error("Insufficient LLI's, \
+ lli count very high = %d\n", lli_count);
+ return -1;
+ }
+ if (!generate_sg_list
+ (info, DMA_SRC_HALF_CHANNEL, lli_size, lli_count)) {
+ stm_error("cannot generate sg list\n");
+ return -1;
+ }
+ }
+ print_sg_info(info->sg_src, info->sgcount_src);
+ if (map_lli_info_phys_chan(info, DMA_SRC_HALF_CHANNEL)) {
+ stm_error("Unable to map SG info to LLI....");
+ return -1;
+ }
+ } else {
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSELT),
+ num_elems, SREG_ELEM_PHY_ECNT_MASK,
+ SREG_ELEM_PHY_ECNT_POS);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSELT),
+ step_size, SREG_ELEM_PHY_EIDX_MASK,
+ SREG_ELEM_PHY_EIDX_POS);
+
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSPTR),
+ (u32) info->src_addr, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSLNK),
+ 0x1, FULL32_MASK, NO_SHIFT);
+ }
+ return 0;
+}
+
+static int set_std_phy_src_half_channel_params_mem(struct dma_channel_info
+ *info)
+{
+
+ enum dma_master_id master_id;
+ enum dma_half_chan_sync sync_type;
+
+ info->src_cfg = 0;
+
+ if ((info->dir == PERIPH_TO_MEM) || (info->dir == PERIPH_TO_PERIPH)) {
+ master_id = DMA_MASTER_1;
+ sync_type = DMA_PACKET_SYNC;
+ info->src_info.addr_inc = DMA_ADR_NOINC;
+ } else {
+ master_id = DMA_MASTER_0;
+ sync_type = DMA_NO_SYNC;
+ }
+
+ MEM_WRITE_BITS(info->src_cfg, master_id,
+ SREG_CFG_PHY_MST_MASK, SREG_CFG_PHY_MST_POS);
+ MEM_WRITE_BITS(info->src_cfg, DMA_FALSE,
+ SREG_CFG_PHY_TIM_MASK, SREG_CFG_PHY_TIM_POS);
+ MEM_WRITE_BITS(info->src_cfg, DMA_TRUE,
+ SREG_CFG_PHY_EIM_MASK, SREG_CFG_PHY_EIM_POS);
+ MEM_WRITE_BITS(info->src_cfg, DMA_TRUE,
+ SREG_CFG_PHY_PEN_MASK, SREG_CFG_PHY_PEN_POS);
+ MEM_WRITE_BITS(info->src_cfg, info->src_info.burst_size,
+ SREG_CFG_PHY_PSIZE_MASK, SREG_CFG_PHY_PSIZE_POS);
+ MEM_WRITE_BITS(info->src_cfg, info->src_info.data_width,
+ SREG_CFG_PHY_ESIZE_MASK, SREG_CFG_PHY_ESIZE_POS);
+ MEM_WRITE_BITS(info->src_cfg, info->priority,
+ SREG_CFG_PHY_PRI_MASK, SREG_CFG_PHY_PRI_POS);
+ MEM_WRITE_BITS(info->src_cfg, info->src_info.endianess,
+ SREG_CFG_PHY_LBE_MASK, SREG_CFG_PHY_LBE_POS);
+ MEM_WRITE_BITS(info->src_cfg, sync_type,
+ SREG_CFG_PHY_TM_MASK, SREG_CFG_PHY_TM_POS);
+ MEM_WRITE_BITS(info->src_cfg, info->src_info.event_line,
+ SREG_CFG_PHY_EVTL_MASK, SREG_CFG_PHY_EVTL_POS);
+ return 0;
+
+}
+
+/**
+ * set_std_phy_dst_half_channel_params() - set params for dst phy half channel
+ * @info: Information of the channel parameters.
+ * This function sets the channel Parameters for standard dest half channel.
+ * Channel is configured as Physical channel. It maps sg info by calling
+ * map_lli_info_phys_chan() for dst channel. If transfer length is more than
+ * 64K elements, it calls calculate_lli_required() and generate_sg_list()
+ * API's to create LLI's.
+ * It returns 0 on success and -1 on failure
+ *
+ */
+static int set_std_phy_dst_half_channel_params(struct dma_channel_info
+ *info)
+{
+ u32 step_size = 0;
+ u32 num_elems;
+ num_elems = info->dst_xfer_elem;
+ if (info->dst_info.addr_inc)
+ step_size = (0x1 << info->dst_info.data_width);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDCFG),
+ info->dst_cfg, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDELT), 0x0,
+ FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDPTR), 0x0,
+ FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDLNK), 0x0,
+ FULL32_MASK, NO_SHIFT);
+
+ if ((num_elems >= MAX_NUM_OF_ELEM_IN_A_XFER) || (info->sg_dest)) {
+ u32 lli_size;
+ u32 lli_count;
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDCFG),
+ DMA_FALSE, SREG_CFG_PHY_TIM_MASK,
+ SREG_CFG_PHY_TIM_POS);
+ if (!info->sg_dest) {
+ lli_count = calculate_lli_required(info, &lli_size);
+ if (lli_count > NUM_SG_PER_REQUEST) {
+ stm_error("Insufficient LLI's, \
+ lli count very high = %d\n", lli_count);
+ return -1;
+ }
+ if (!generate_sg_list
+ (info, DMA_DEST_HALF_CHANNEL, lli_size,
+ lli_count)) {
+ stm_error("cannot generate sg list\n");
+ return -1;
+ }
+ }
+ print_sg_info(info->sg_dest, info->sgcount_dest);
+ if (map_lli_info_phys_chan(info, DMA_DEST_HALF_CHANNEL))
+ return -1;
+ } else {
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDELT),
+ num_elems, SREG_ELEM_PHY_ECNT_MASK,
+ SREG_ELEM_PHY_ECNT_POS);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDELT),
+ step_size, SREG_ELEM_PHY_EIDX_MASK,
+ SREG_ELEM_PHY_EIDX_POS);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDPTR),
+ (u32) info->dst_addr, FULL32_MASK, NO_SHIFT);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDLNK),
+ 0x1, FULL32_MASK, NO_SHIFT);
+ }
+ return 0;
+}
+
+static int set_std_phy_dst_half_channel_params_mem(struct dma_channel_info
+ *info)
+{
+ enum dma_master_id master_id;
+ enum dma_half_chan_sync sync_type;
+
+ info->dst_cfg = 0;
+
+ if ((info->dir == MEM_TO_PERIPH) || (info->dir == PERIPH_TO_PERIPH)) {
+ master_id = DMA_MASTER_1;
+ sync_type = DMA_PACKET_SYNC;
+ info->dst_info.addr_inc = DMA_ADR_NOINC;
+ } else {
+ master_id = DMA_MASTER_0;
+ sync_type = DMA_NO_SYNC;
+ }
+
+ MEM_WRITE_BITS(info->dst_cfg, master_id,
+ SREG_CFG_PHY_MST_MASK, SREG_CFG_PHY_MST_POS);
+ MEM_WRITE_BITS(info->dst_cfg, DMA_TRUE,
+ SREG_CFG_PHY_TIM_MASK, SREG_CFG_PHY_TIM_POS);
+ MEM_WRITE_BITS(info->dst_cfg, DMA_TRUE,
+ SREG_CFG_PHY_EIM_MASK, SREG_CFG_PHY_EIM_POS);
+ MEM_WRITE_BITS(info->dst_cfg, DMA_TRUE,
+ SREG_CFG_PHY_PEN_MASK, SREG_CFG_PHY_PEN_POS);
+ MEM_WRITE_BITS(info->dst_cfg, info->dst_info.burst_size,
+ SREG_CFG_PHY_PSIZE_MASK, SREG_CFG_PHY_PSIZE_POS);
+ MEM_WRITE_BITS(info->dst_cfg, info->dst_info.data_width,
+ SREG_CFG_PHY_ESIZE_MASK, SREG_CFG_PHY_ESIZE_POS);
+ MEM_WRITE_BITS(info->dst_cfg, info->priority,
+ SREG_CFG_PHY_PRI_MASK, SREG_CFG_PHY_PRI_POS);
+ MEM_WRITE_BITS(info->dst_cfg, info->dst_info.endianess,
+ SREG_CFG_PHY_LBE_MASK, SREG_CFG_PHY_LBE_POS);
+ MEM_WRITE_BITS(info->dst_cfg, sync_type,
+ SREG_CFG_PHY_TM_MASK, SREG_CFG_PHY_TM_POS);
+ MEM_WRITE_BITS(info->dst_cfg, info->dst_info.event_line,
+ SREG_CFG_PHY_EVTL_MASK, SREG_CFG_PHY_EVTL_POS);
+
+ return 0;
+
+}
+
+/**
+ * set_std_phy_channel_params() - maps the cfg params for std phy channel
+ * @info: Information of the channel parameters.
+ * This function maps the configuration parameters of source and dest
+ * half channels on to the registers by calling function
+ * set_std_phy_src_half_channel_params() for source half channel and
+ * set_std_phy_dst_half_channel_params() for dest half channel.
+ * This function returns 0 on success and -1 on failure.
+ *
+ */
+static int set_std_phy_channel_params(struct dma_channel_info *info)
+{
+ if (set_std_phy_src_half_channel_params(info)) {
+ stm_error("Unable to map source half channel params");
+ return -1;
+ }
+ if (set_std_phy_dst_half_channel_params(info)) {
+ stm_error("Unable to map destination half channel params");
+ return -1;
+ }
+ return 0;
+}
+
+static int set_std_phy_channel_params_mem(struct dma_channel_info *info)
+{
+ if (set_std_phy_src_half_channel_params_mem(info)) {
+ stm_error("Unable to map source half channel params");
+ return -1;
+ }
+ if (set_std_phy_dst_half_channel_params_mem(info)) {
+ stm_error("Unable to map destination half channel params");
+ return -1;
+ }
+ return 0;
+}
+
+/**
+ * set_std_log_dst_half_channel_params() - map channel params for dest
+ * logical half channel
+ * @info: Information of the channel parameters.
+ * This function sets the channel Parameters for standard Destination
+ * half channel.
+ * Channel is configured as Logical channel. It maps sg info by calling
+ * map_lli_info_log_chan() for destination half channel. If transfer
+ * length is more than 64K elements, it calls calculate_lli_required()
+ * and generate_sg_list() API's to create LLI's. Activate Event Line
+ * if destination is a peripheral.
+ * This function returns 0 on success and -1 on failure.
+ *
+ */
+static int set_std_log_dst_half_channel_params(struct dma_channel_info
+ *info)
+{
+ u32 num_elems;
+ struct std_log_memory_param *params;
+
+ num_elems = info->dst_xfer_elem;
+
+ if (info->dir == MEM_TO_PERIPH) {
+ params =
+ (struct std_log_memory_param
+ *)((void *)(dma_drv_data->lchan_params_base.log_addr)
+ + (info->dst_dev_type * 32) + 16);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDLNK),
+ ACTIVATE_EVENTLINE,
+ EVENTLINE_MASK(info->dst_info.event_line),
+ EVENTLINE_POS(info->dst_info.event_line));
+ } else {
+ params =
+ (struct std_log_memory_param
+ *)((void *)(dma_drv_data->lchan_params_base.log_addr)
+ + (info->src_dev_type * 32));
+ }
+ params->dmac_lcsp3 = info->dmac_lcsp3;
+ if (info->invalid) {
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDCFG),
+ info->priority, SREG_CFG_LOG_PRI_MASK,
+ SREG_CFG_LOG_PRI_POS);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDCFG),
+ info->dst_info.endianess,
+ SREG_CFG_LOG_LBE_MASK, SREG_CFG_LOG_LBE_POS);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDCFG),
+ 0x1, SREG_CFG_LOG_GIM_MASK, SREG_CFG_LOG_GIM_POS);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDCFG),
+ DMA_MASTER_0, SREG_CFG_LOG_MFU_MASK,
+ SREG_CFG_LOG_MFU_POS);
+ }
+
+ if ((num_elems >= MAX_NUM_OF_ELEM_IN_A_XFER) || (info->sg_dest)) {
+ u32 lli_size;
+ u32 lli_count;
+ MEM_WRITE_BITS(params->dmac_lcsp3, DMA_FALSE,
+ MEM_LCSP3_DCFG_TIM_MASK, MEM_LCSP3_DCFG_TIM_POS);
+ if (!info->sg_dest) {
+ lli_count = calculate_lli_required(info, &lli_size);
+ if (lli_count > NUM_LLI_PER_LOG_CHANNEL + 1) {
+ stm_error("Insufficient LLI's, \
+ lli count very high = %d\n", lli_count);
+ return -1;
+ }
+ if (!generate_sg_list
+ (info, DMA_DEST_HALF_CHANNEL, lli_size,
+ lli_count)) {
+ stm_error("cannot generate sg list\n");
+ return -1;
+ }
+ }
+ print_sg_info(info->sg_dest, info->sgcount_dest);
+ if (map_lli_info_log_chan(info, DMA_DEST_HALF_CHANNEL, params))
+ return -1;
+ } else {
+ MEM_WRITE_BITS(params->dmac_lcsp2, num_elems,
+ MEM_LCSP2_ECNT_MASK, MEM_LCSP2_ECNT_POS);
+ MEM_WRITE_BITS(params->dmac_lcsp2,
+ (0x0000FFFFUL & (u32) (info->dst_addr)),
+ MEM_LCSP2_DPTR_MASK, MEM_LCSP2_DPTR_POS);
+ MEM_WRITE_BITS(params->dmac_lcsp3,
+ (0xFFFF0000UL & (u32) (info->dst_addr)) >> 16,
+ MEM_LCSP3_DPTR_MASK, MEM_LCSP3_DPTR_POS);
+ MEM_WRITE_BITS(params->dmac_lcsp3, 0x1, MEM_LCSP3_DTCP_MASK,
+ MEM_LCSP3_DTCP_POS);
+ }
+ return 0;
+}
+
+static int set_std_log_dst_half_channel_params_mem(struct dma_channel_info
+ *info)
+{
+
+ enum dma_master_id master_id;
+ int tim;
+ int increment_addr;
+ if (info->dir == MEM_TO_PERIPH) {
+ master_id = DMA_MASTER_1;
+ tim = DMA_TRUE;
+ increment_addr = DMA_FALSE;
+ } else {
+ master_id = DMA_MASTER_0;
+ tim = DMA_TRUE;
+ increment_addr = DMA_TRUE;
+ }
+ MEM_WRITE_BITS(info->dmac_lcsp3, master_id, MEM_LCSP3_DCFG_MST_MASK,
+ MEM_LCSP3_DCFG_MST_POS);
+ MEM_WRITE_BITS(info->dmac_lcsp3, tim, MEM_LCSP3_DCFG_TIM_MASK,
+ MEM_LCSP3_DCFG_TIM_POS);
+ MEM_WRITE_BITS(info->dmac_lcsp3, DMA_TRUE,
+ MEM_LCSP3_DCFG_EIM_MASK, MEM_LCSP3_DCFG_EIM_POS);
+ MEM_WRITE_BITS(info->dmac_lcsp3, increment_addr,
+ MEM_LCSP3_DCFG_INCR_MASK, MEM_LCSP3_DCFG_INCR_POS);
+ MEM_WRITE_BITS(info->dmac_lcsp3, info->dst_info.burst_size,
+ MEM_LCSP3_DCFG_PSIZE_MASK, MEM_LCSP3_DCFG_PSIZE_POS);
+ MEM_WRITE_BITS(info->dmac_lcsp3, info->dst_info.data_width,
+ MEM_LCSP3_DCFG_ESIZE_MASK, MEM_LCSP3_DCFG_ESIZE_POS);
+ MEM_WRITE_BITS(info->dmac_lcsp3, 0x0, MEM_LCSP3_DLOS_MASK,
+ MEM_LCSP3_DLOS_POS);
+ MEM_WRITE_BITS(info->dmac_lcsp3, 0x1, MEM_LCSP3_DTCP_MASK,
+ MEM_LCSP3_DTCP_POS);
+
+ return 0;
+
+}
+
+/**
+ * set_std_log_src_half_channel_params() - map channel params for src
+ * logical half channel
+ * @info: Information of the channel parameters.
+ * This function sets the channel Parameters for standard src half channel.
+ * Channel is configured as Logical channel. It maps sg info by calling
+ * map_lli_info_log_chan() for source half channel. If transfer
+ * length is more than 64K elements, it calls calculate_lli_required()
+ * and generate_sg_list() API's to create LLI's. Activate Event Line
+ * if source is a peripheral.
+ * This function returns 0 on success and -1 on failure.
+ *
+ */
+static int set_std_log_src_half_channel_params(struct dma_channel_info
+ *info)
+{
+ u32 num_elems;
+ struct std_log_memory_param *params = NULL;
+
+ num_elems = info->src_xfer_elem;
+
+ if (info->dir == PERIPH_TO_MEM) {
+ params =
+ (struct std_log_memory_param
+ *)((void *)(dma_drv_data->lchan_params_base.log_addr)
+ + (info->src_dev_type * 32));
+ stm_dbg(DBG_ST.dma, "Params address : %x dev_indx = %d \n",
+ (u32) params, info->src_dev_type);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSLNK),
+ ACTIVATE_EVENTLINE,
+ EVENTLINE_MASK(info->src_info.event_line),
+ EVENTLINE_POS(info->src_info.event_line));
+ } else {
+ params =
+ (struct std_log_memory_param
+ *)((void *)(dma_drv_data->lchan_params_base.log_addr)
+ + (info->dst_dev_type * 32) + 16);
+ }
+ params->dmac_lcsp1 = info->dmac_lcsp1;
+ if (info->invalid) {
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSCFG),
+ info->priority, SREG_CFG_LOG_PRI_MASK,
+ SREG_CFG_LOG_PRI_POS);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSCFG),
+ info->src_info.endianess,
+ SREG_CFG_LOG_LBE_MASK, SREG_CFG_LOG_LBE_POS);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSCFG),
+ 0x1, SREG_CFG_LOG_GIM_MASK, SREG_CFG_LOG_GIM_POS);
+ REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSCFG),
+ DMA_MASTER_0, SREG_CFG_LOG_MFU_MASK,
+ SREG_CFG_LOG_MFU_POS);
+ }
+ if ((num_elems >= MAX_NUM_OF_ELEM_IN_A_XFER) || (info->sg_src)) {
+ u32 lli_size;
+ u32 lli_count;
+ MEM_WRITE_BITS(params->dmac_lcsp1, DMA_FALSE,
+ MEM_LCSP1_SCFG_TIM_MASK, MEM_LCSP1_SCFG_TIM_POS);
+ if (!info->sg_src) {
+ lli_count = calculate_lli_required(info, &lli_size);
+ if (lli_count > NUM_LLI_PER_LOG_CHANNEL + 1) {
+ stm_error("Insufficient LLI's, \
+ lli count very high = %d\n", lli_count);
+ return -1;
+ }
+ if (!generate_sg_list
+ (info, DMA_SRC_HALF_CHANNEL, lli_size, lli_count)) {
+ stm_error("cannot generate sg list\n");
+ return -1;
+ }
+ }
+ print_sg_info(info->sg_src, info->sgcount_src);
+ if (map_lli_info_log_chan(info, DMA_SRC_HALF_CHANNEL, params)) {
+ stm_error("Unable to map SG info on \
+ LLI for src half channel");
+ return -1;
+ }
+ } else {
+ MEM_WRITE_BITS(params->dmac_lcsp0, num_elems,
+ MEM_LCSP0_ECNT_MASK, MEM_LCSP0_ECNT_POS);
+ MEM_WRITE_BITS(params->dmac_lcsp0,
+ (0x0000FFFFUL & (u32) (info->src_addr)),
+ MEM_LCSP0_SPTR_MASK, MEM_LCSP0_SPTR_POS);
+ MEM_WRITE_BITS(params->dmac_lcsp1,
+ (0xFFFF0000 & (u32) (info->src_addr)) >> 16,
+ MEM_LCSP1_SPTR_MASK, MEM_LCSP1_SPTR_POS);
+ }
+ return 0;
+}
+
+static int set_std_log_src_half_channel_params_mem(struct dma_channel_info
+ *info)
+{
+
+ enum dma_master_id master_id;
+ int tim;
+ int increment_addr;
+ if (info->dir == PERIPH_TO_MEM) {
+ master_id = DMA_MASTER_1;
+ tim = DMA_FALSE;
+ increment_addr = DMA_FALSE;
+ } else {
+ master_id = DMA_MASTER_0;
+ tim = DMA_FALSE;
+ increment_addr = DMA_TRUE;
+ }
+ MEM_WRITE_BITS(info->dmac_lcsp1, master_id, MEM_LCSP1_SCFG_MST_MASK,
+ MEM_LCSP1_SCFG_MST_POS);
+ MEM_WRITE_BITS(info->dmac_lcsp1, tim, MEM_LCSP1_SCFG_TIM_MASK,
+ MEM_LCSP1_SCFG_TIM_POS);
+ MEM_WRITE_BITS(info->dmac_lcsp1, DMA_TRUE,
+ MEM_LCSP1_SCFG_EIM_MASK, MEM_LCSP1_SCFG_EIM_POS);
+ MEM_WRITE_BITS(info->dmac_lcsp1, increment_addr,
+ MEM_LCSP1_SCFG_INCR_MASK, MEM_LCSP1_SCFG_INCR_POS);
+ MEM_WRITE_BITS(info->dmac_lcsp1, info->src_info.burst_size,
+ MEM_LCSP1_SCFG_PSIZE_MASK, MEM_LCSP1_SCFG_PSIZE_POS);
+ MEM_WRITE_BITS(info->dmac_lcsp1, info->src_info.data_width,
+ MEM_LCSP1_SCFG_ESIZE_MASK, MEM_LCSP1_SCFG_ESIZE_POS);
+ MEM_WRITE_BITS(info->dmac_lcsp1, 0x0, MEM_LCSP1_SLOS_MASK,
+ MEM_LCSP1_SLOS_POS);
+ MEM_WRITE_BITS(info->dmac_lcsp1, 0x1, MEM_LCSP1_STCP_MASK,
+ MEM_LCSP1_STCP_POS);
+
+ return 0;
+
+}
+
+/**
+ * set_std_log_channel_params() - maps cfg params for std logical channel
+ * @info: Information of the channel parameters.
+ *
+ */
+static int set_std_log_channel_params(struct dma_channel_info *info)
+{
+ if (set_std_log_src_half_channel_params(info))
+ return -1;
+ if (set_std_log_dst_half_channel_params(info))
+ return -1;
+ return 0;
+}
+
+static int set_std_log_channel_params_mem(struct dma_channel_info *info)
+{
+ if (set_std_log_src_half_channel_params_mem(info))
+ return -1;
+ if (set_std_log_dst_half_channel_params_mem(info))
+ return -1;
+ return 0;
+}
+
+/**
+ * process_dma_pipe_info() - process the DMA channel info sent by user
+ * @pipe_id: Channel Id for which this information is to be set
+ * @pipe_info: Information struct of the given channel given by user
+ * This function processes info supplied by the client driver. It stores
+ * the required info in to it;s internal data structure.
+ * It returns 0 on success and -1 on failure
+ *
+ */
+static int process_dma_pipe_info(struct dma_channel_info *info,
+ struct stm_dma_pipe_info *pipe_info)
+{
+ unsigned long flags;
+
+ if (info && pipe_info) {
+ info->invalid = 1;
+ spin_lock_irqsave(&info->cfg_lock, flags);
+ if (info->active)
+ stm_dbg(DBG_ST.dma,
+ "Modifying the info while channel active..\n");
+ info->pr_type =
+ MEM_READ_BITS(pipe_info->channel_type, 0x3,
+ INFO_CH_TYPE_POS);
+ info->priority =
+ MEM_READ_BITS(pipe_info->channel_type,
+ (0x3 << INFO_PRIO_TYPE_POS),
+ INFO_PRIO_TYPE_POS);
+ info->security =
+ MEM_READ_BITS(pipe_info->channel_type,
+ (0x3 << INFO_SEC_TYPE_POS),
+ INFO_SEC_TYPE_POS);
+ info->chan_mode =
+ MEM_READ_BITS(pipe_info->channel_type,
+ (0x3 << INFO_CH_MODE_TYPE_POS),
+ INFO_CH_MODE_TYPE_POS);
+ info->mode_option =
+ MEM_READ_BITS(pipe_info->channel_type,
+ (0x3 << INFO_CH_MODE_OPTION_POS),
+ INFO_CH_MODE_OPTION_POS);
+ info->link_type =
+ MEM_READ_BITS(pipe_info->channel_type,
+ (0x1 << INFO_LINK_TYPE_POS),
+ INFO_LINK_TYPE_POS);
+ info->lli_interrupt =
+ MEM_READ_BITS(pipe_info->channel_type,
+ (0x1 << INFO_TIM_POS), INFO_TIM_POS);
+ info->dir = pipe_info->dir;
+ info->src_dev_type = pipe_info->src_dev_type;
+ info->dst_dev_type = pipe_info->dst_dev_type;
+ info->src_info.endianess = pipe_info->src_info.endianess;
+ info->src_info.data_width = pipe_info->src_info.data_width;
+ info->src_info.burst_size = pipe_info->src_info.burst_size;
+ info->src_info.buffer_type = pipe_info->src_info.buffer_type;
+ if (info->src_dev_type != DMA_DEV_SRC_MEMORY) {
+ info->src_info.event_group = info->src_dev_type / 16;
+ info->src_info.event_line = info->src_dev_type % 16;
+ } else {
+ info->src_info.event_group = 0;
+ info->src_info.event_line = 0;
+ }
+ info->dst_info.endianess = pipe_info->dst_info.endianess;
+ info->dst_info.data_width = pipe_info->dst_info.data_width;
+ info->dst_info.burst_size = pipe_info->dst_info.burst_size;
+ info->dst_info.buffer_type = pipe_info->dst_info.buffer_type;
+ if (info->dst_dev_type != DMA_DEV_DEST_MEMORY) {
+ info->dst_info.event_group = info->dst_dev_type / 16;
+ info->dst_info.event_line = info->dst_dev_type % 16;
+ } else {
+ info->dst_info.event_group = 0;
+ info->dst_info.event_line = 0;
+ }
+
+ if (info->dir == MEM_TO_MEM) {
+ info->src_info.addr_inc = pipe_info->src_info.addr_inc;
+ info->dst_info.addr_inc = pipe_info->dst_info.addr_inc;
+ }
+
+ print_dma_channel_info(info);
+ if (info->pr_type == DMA_STANDARD) {
+ if (info->chan_mode == DMA_CHAN_IN_PHYS_MODE) {
+ if (set_std_phy_channel_params_mem(info)) {
+ stm_error("Could not set parameters \
+ for channel in phy mode\n");
+ }
+ } else if (info->chan_mode == DMA_CHAN_IN_LOG_MODE) {
+ if (set_std_log_channel_params_mem(info)) {
+ stm_error
+ ("Could not set parameters for \
+ channel in Log mode\n");
+ }
+ } else {
+ stm_error("Operation Mode not yet supported");
+ }
+ } else { /*DMA_EXTENDED */
+ stm_error("Extended Channels not supported");
+ }
+ spin_unlock_irqrestore(&info->cfg_lock, flags);
+ return 0;
+ } else {
+ stm_error("NULL info structure\n");
+ return -1;
+ }
+}
+
+static inline int validate_pipe_info(struct stm_dma_pipe_info *info)
+{
+ if (!info) {
+ stm_error("Info is Null");
+ return -1;
+ }
+ if (0x0 == MEM_READ_BITS(info->channel_type, 0x3, INFO_CH_TYPE_POS)) {
+ stm_error("Configuration wrong:: \
+ Physical resource type incorrect\n");
+ return -1;
+ }
+ if (0x0 == MEM_READ_BITS(info->channel_type,
+ (0x3 << INFO_PRIO_TYPE_POS),
+ INFO_PRIO_TYPE_POS)) {
+ stm_error("Configuration wrong:: incorrect Priority...\n");
+ return -1;
+ }
+ if (0x0 == MEM_READ_BITS(info->channel_type,
+ (0x3 << INFO_SEC_TYPE_POS),
+ INFO_SEC_TYPE_POS)) {
+ stm_error("Configuration wrong: incorrect security type\n");
+ return -1;
+ }
+ if (0x0 == MEM_READ_BITS(info->channel_type,
+ (0x3 << INFO_CH_MODE_TYPE_POS),
+ INFO_CH_MODE_TYPE_POS)) {
+ stm_error("Configuration wrong:: Wrong channel mode\n");
+ return -1;
+ }
+ if (0x0 == MEM_READ_BITS(info->channel_type,
+ (0x3 << INFO_CH_MODE_OPTION_POS),
+ INFO_CH_MODE_OPTION_POS)) {
+ stm_error("Configuration wrong:: incorrect mode option\n");
+
+ return -1;
+ }
+ return 0;
+}
+
+/**
+ * get_inititalized_info_structure() - Allocate a new channel info structure
+ * Returns pointer inititalized info structure(struct dma_channel_info *),
+ * or NULL in case of error
+ */
+static struct dma_channel_info *get_inititalized_info_structure(void)
+{
+ struct dma_channel_info *info = NULL;
+ info = (struct dma_channel_info *)
+ kzalloc(sizeof(struct dma_channel_info), GFP_KERNEL);
+ if (!info) {
+ stm_error("Could not allocate memory for \
+ info structure for new channel\n");
+ return NULL;
+ }
+ info->phys_chan_id = DMA_CHAN_NOT_ALLOCATED;
+ info->channel_id = -1;
+ info->lli_block_id_src = -1;
+ info->lli_block_id_dest = -1;
+ info->sg_block_id_src = -1;
+ info->sg_block_id_dest = -1;
+ info->sg_dest = NULL;
+ info->sg_src = NULL;
+ info->current_sg = NULL;
+ info->active = 0;
+ info->invalid = 1;
+ info->dmac_lcsp3 = 0;
+ info->dmac_lcsp1 = 0;
+ info->src_info.addr_inc = DMA_ADR_INC;
+ info->dst_info.addr_inc = DMA_ADR_INC;
+ spin_lock_init(&info->cfg_lock);
+ return info;
+}
+
+/**
+ * stm_request_dma() - API for requesting a DMA channel used by
+ * client driver
+ * @channel: Channel Id which is returned to client on succefull allocation
+ * @pipe_info: Information struct of the given channel given by user
+ * This API is called by the client driver to request for a channel. On
+ * successful allocation of channel 0 is returned. This API first allocates
+ * a new info structure for the channel(used by Driver to maintain internal
+ * state for this pipe). A new pipe_id is allocated for this request.The channel
+ * information as requested by client in pipe_info structure are then verified
+ * and copied in the info structure we allocated using process_dma_pipe_info().
+ * If client requests to reserve channel, it is done at this point by calling
+ * acquire_physical_resource(). Reference for this info structure are then
+ * stored in pipe_info array. If channel has been reserved then entry is also
+ * stored in dma_chan_info array.
+ *
+ */
+int stm_request_dma(int *channel, struct stm_dma_pipe_info *pipe_info)
+{
+ struct dma_channel_info *new_info;
+ int pipe_id = -1;
+ int retval = 0;
+
+ if (validate_pipe_info(pipe_info)) {
+ *channel = -1;
+ return -EINVAL;
+ }
+
+ new_info = get_inititalized_info_structure();
+
+ if (!new_info) {
+ *channel = -1;
+ return -ENOMEM;
+ }
+
+ pipe_id = allocate_pipe_id();
+
+ if (pipe_id >= 0) {
+ *channel = pipe_id;
+ new_info->pipe_id = pipe_id;
+
+ if (process_dma_pipe_info(new_info, pipe_info)) {
+ retval = -EINVAL;
+ goto error_request;
+ }
+ if (pipe_info->reserve_channel) {
+ allocate_free_dma_channel(new_info);
+ if (new_info->phys_chan_id == -1) {
+ retval = -EINVAL;
+ goto error_request;
+ }
+ }
+ dma_drv_data->pipe_info[pipe_id] = new_info;
+ if (new_info->channel_id >= 0) {
+ /*i.e. for reserved channels only */
+ dma_drv_data->dma_chan_info[new_info->channel_id] =
+ new_info;
+ }
+
+ } else {
+ retval = -EAGAIN;
+ goto error_pipeid;
+ }
+ return retval;
+
+error_request:
+ deallocate_pipe_id(pipe_id);
+error_pipeid:
+ *channel = -1;
+ kfree(new_info);
+ return retval;
+}
+EXPORT_SYMBOL(stm_request_dma);
+
+/**
+ * stm_set_callback_handler() - To set a callback handler for the
+ * given channel
+ * @pipe_id: pipe id allocated to client driver from the call
+ * stm_request_dma()
+ * @callback_handler: Callback function to be invoked in case of
+ * completion or error on xfer
+ * @data: Data pointer with which this callback function must be invoked.
+ * This function returns 0 on success, -1 on error.
+ * This callback handler you set here would be invoked when Xfer is complete.
+ * Calling this function is optional.
+ * If you do not call this function then you need to poll using
+ * stm_dma_residue() API to check whether you DMA xfer has completed or not
+ *
+ */
+int stm_set_callback_handler(int pipe_id, void *callback_handler,
+ void *data)
+{
+ struct dma_channel_info *info;
+ unsigned long flags;
+
+ if (is_pipeid_invalid(pipe_id)) {
+ stm_error("Invalid pipe id");
+ return -1;
+ }
+ info = dma_drv_data->pipe_info[pipe_id];
+ if (info) {
+ if (info->active)
+ stm_dbg(DBG_ST.dma,
+ "Modifying the info while channel active..\n");
+ spin_lock_irqsave(&info->cfg_lock, flags);
+ info->callback = callback_handler;
+ info->data = data;
+ spin_unlock_irqrestore(&info->cfg_lock, flags);
+ return 0;
+ } else {
+ stm_error("Info structure for this pipe is unavailable\n");
+ return -EINVAL;
+ }
+}
+EXPORT_SYMBOL(stm_set_callback_handler);
+
+/**
+ * stm_configure_dma_channel() - To configure a DMA pipe after it
+ * has been requested
+ * @pipe_id: pipe id allocated to client driver from the call
+ * stm_request_dma()
+ * @pipe_info: Updated pipe information structure.
+ * This function returns 0 on success, negative value on error.
+ * Calling this function is optional if you have already configured
+ * your pipe during call to API stm_request_dma().
+ * It is required only if you need to update params.
+ *
+ */
+int stm_configure_dma_channel(int pipe_id,
+ struct stm_dma_pipe_info *pipe_info)
+{
+ int retval = 0;
+ struct dma_channel_info *info;
+
+ if (is_pipeid_invalid(pipe_id)) {
+ stm_error("Invalid pipe id");
+ return -1;
+ }
+ info = dma_drv_data->pipe_info[pipe_id];
+ if (!info) {
+ stm_error("Null Info structure....");
+ return -1;
+ }
+
+ retval = process_dma_pipe_info(info, pipe_info);
+ if (retval)
+ return -EINVAL;
+ else
+ return 0;
+}
+EXPORT_SYMBOL(stm_configure_dma_channel);
+
+/**
+ * stm_set_dma_addr() - To set source and destination address for
+ * the given DMA channel
+ * @pipe_id: pipe_id for which dma addresses have to be set
+ * @src_addr: Source address from where DMA will start
+ * @dst_addr: Dest address at which DMA controller will copy data
+ *
+ */
+void stm_set_dma_addr(int pipe_id, void *src_addr, void *dst_addr)
+{
+ struct dma_channel_info *info;
+ unsigned long flags = 0;
+
+ if (is_pipeid_invalid(pipe_id)) {
+ stm_error("Invalid pipe id");
+ return;
+ }
+ info = dma_drv_data->pipe_info[pipe_id];
+ if (!info) {
+ stm_error("Null Info structure....");
+ return;
+ }
+ if (info->active)
+ stm_dbg(DBG_ST.dma,
+ "Modifying the info while channel active..\n");
+
+ spin_lock_irqsave(&info->cfg_lock, flags);
+ info->src_addr = src_addr;
+ info->dst_addr = dst_addr;
+ spin_unlock_irqrestore(&info->cfg_lock, flags);
+}
+EXPORT_SYMBOL(stm_set_dma_addr);
+
+/**
+ * stm_set_dma_count() - To set dma count(number of bytes to transfer)
+ * @pipe_id: client Pipe id for which count to transfer has to be set
+ * @count: Number of bytes to xfer
+ *
+ */
+void stm_set_dma_count(int pipe_id, int count)
+{
+ struct dma_channel_info *info;
+ unsigned long flags = 0;
+
+ if (is_pipeid_invalid(pipe_id)) {
+ stm_error("Invalid pipe id");
+ return;
+ }
+ info = dma_drv_data->pipe_info[pipe_id];
+ if (!info) {
+ stm_error("Null Info structure....");
+ return;
+ }
+ if (info->active)
+ stm_dbg(DBG_ST.dma,
+ "Modifying the info while channel active..\n");
+ spin_lock_irqsave(&info->cfg_lock, flags);
+ info->xfer_len = count;
+ info->src_xfer_elem = count >> info->src_info.data_width;
+ info->dst_xfer_elem = count >> info->dst_info.data_width;
+ spin_unlock_irqrestore(&info->cfg_lock, flags);
+}
+EXPORT_SYMBOL(stm_set_dma_count);
+
+/**
+ * stm_set_dma_sg() - To set the SG list for a given pipe id.
+ * @pipe_id: client Pipe id for which sg list has to be set
+ * @sg: sg List to be set
+ * @nr_sg: Number of items in SG list
+ * @type: Whether sg list is for src or destination(0 - src, 1 - dst)
+ *
+ */
+void stm_set_dma_sg(int pipe_id, struct scatterlist *sg, int nr_sg,
+ int type)
+{
+ struct dma_channel_info *info;
+ unsigned long flags = 0;
+
+ if (is_pipeid_invalid(pipe_id)) {
+ stm_error("Invalid pipe id");
+ return;
+ }
+ info = dma_drv_data->pipe_info[pipe_id];
+ if (!info) {
+ stm_error("Null Info structure....");
+ return;
+ }
+ if (info->active)
+ stm_dbg(DBG_ST.dma,
+ "Modifying the info while channel active..\n");
+ spin_lock_irqsave(&info->cfg_lock, flags);
+ if (type == DMA_SRC_HALF_CHANNEL) {
+ info->sg_src = sg;
+ info->sgcount_src = nr_sg;
+ } else {
+ info->sg_dest = sg;
+ info->sgcount_dest = nr_sg;
+ }
+ spin_unlock_irqrestore(&info->cfg_lock, flags);
+}
+EXPORT_SYMBOL(stm_set_dma_sg);
+
+/**
+ * stm_enable_dma() - To enable a DMA channel
+ * @pipe_id: client Id whose DMA channel has to be enabled
+ * Unless DMA channel was reserved, at this point allocation for a
+ * physical resource is done on which this request would run.
+ * Once a physical resource is allocated, corresponding DMA channel
+ * parameters are loaded on to the DMA registers, and physical
+ * resource is put in a running state.
+ * It returns 0 on success, -1 on error
+ *
+ */
+int stm_enable_dma(int pipe_id)
+{
+ struct dma_channel_info *info = NULL;
+ unsigned long flags;
+
+ if (is_pipeid_invalid(pipe_id)) {
+ stm_error("Invalid pipe id");
+ return -1;
+ }
+ info = dma_drv_data->pipe_info[pipe_id];
+ if (!info) {
+ stm_error("Null Info structure....");
+ return -1;
+ }
+ if ((info->phys_chan_id) == DMA_CHAN_NOT_ALLOCATED) {
+ if (allocate_free_dma_channel(info)) {
+ stm_error("stm_enable_dma():: \
+ No free DMA channel available.....\n");
+ return -1;
+ }
+ dma_drv_data->dma_chan_info[info->channel_id] = info;
+ }
+ stm_dbg(DBG_ST.dma, "info->phys_chan_id Allocated = %d\n",
+ (info->phys_chan_id));
+
+ spin_lock_irqsave(&dma_drv_data->cfg_ch_lock[info->phys_chan_id],
+ flags);
+#if 0
+ if (dma_channel_execute_command
+ (DMA_SUSPEND_REQ, info->phys_chan_id) == -1) {
+ stm_error("Unable to suspend the Channel %d\n",
+ info->phys_chan_id);
+ goto error_enable_dma;
+ }
+ stm_error("--->suspending the Channel %d\n", info->phys_chan_id);
+
+#endif
+ if (info->invalid) {
+ if (info->chan_mode == DMA_CHAN_IN_LOG_MODE) {
+ if (!dma_drv_data->pr_info[info->phys_chan_id].dirty) {
+ set_phys_res_type(info->phys_chan_id,
+ info->pr_type);
+ set_phys_res_mode(info->phys_chan_id,
+ info->chan_mode);
+ set_phys_res_mode_option(info->phys_chan_id,
+ info->mode_option);
+ set_phys_res_security(info->phys_chan_id,
+ info->security);
+ /*Resource is Dirty now */
+ dma_drv_data->pr_info[info->
+ phys_chan_id].dirty = 1;
+ }
+ if ((info->dir == PERIPH_TO_PERIPH)
+ || (info->dir == PERIPH_TO_MEM)) {
+ set_event_line_security(info->src_info.
+ event_line,
+ info->src_info.
+ event_group,
+ info->security);
+ }
+ if ((info->dir == PERIPH_TO_PERIPH)
+ || (info->dir == MEM_TO_PERIPH))
+ set_event_line_security((info->dst_info.
+ event_line + 16),
+ info->dst_info.
+ event_group,
+ info->security);
+ } else { /*Channel in Physical mode */
+
+ set_phys_res_type(info->phys_chan_id, info->pr_type);
+ set_phys_res_mode(info->phys_chan_id, info->chan_mode);
+ set_phys_res_mode_option(info->phys_chan_id,
+ info->mode_option);
+ set_phys_res_security(info->phys_chan_id,
+ info->security);
+
+ if ((info->dir == PERIPH_TO_PERIPH)
+ || (info->dir == PERIPH_TO_MEM)) {
+ set_event_line_security(info->src_info.
+ event_line,
+ info->src_info.
+ event_group,
+ info->security);
+ }
+ if ((info->dir == PERIPH_TO_PERIPH)
+ || (info->dir == MEM_TO_PERIPH))
+ set_event_line_security((info->dst_info.
+ event_line + 16),
+ info->dst_info.
+ event_group,
+ info->security);
+
+ }
+ }
+ if (info->pr_type == DMA_STANDARD) {
+ if (info->chan_mode == DMA_CHAN_IN_PHYS_MODE) {
+ if (set_std_phy_channel_params(info)) {
+ stm_error("Could not set parameters \
+ for channel in phy mode\n");
+ goto error_enable_dma;
+ }
+ } else if (info->chan_mode == DMA_CHAN_IN_LOG_MODE) {
+ if (dma_channel_execute_command
+ (DMA_SUSPEND_REQ, info->phys_chan_id) == -1) {
+ stm_error("Unable to suspend the Channel %d\n",
+ info->phys_chan_id);
+ goto error_enable_dma;
+ }
+ if (set_std_log_channel_params(info)) {
+ stm_error("Could not set parameters \
+ for channel in Log mode\n");
+ goto error_enable_dma;
+ }
+ } else {
+ stm_error("Operation Mode not yet supported");
+ goto error_enable_dma;
+ }
+ } else { /*DMA_EXTENDED */
+ stm_error("Extended Channels not supported");
+ goto error_enable_dma;
+ }
+ /*Now after doing all necessary settings put the channel in RUN state */
+ info->active = 1;
+ info->invalid = 0;
+ dma_channel_execute_command(DMA_RUN, info->phys_chan_id);
+ spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock[info->phys_chan_id],
+ flags);
+
+ return 0;
+
+error_enable_dma:
+ spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock[info->phys_chan_id],
+ flags);
+ return -1;
+}
+EXPORT_SYMBOL(stm_enable_dma);
+
+/**
+ * halt_dma_channel() - To halt a Running DMA channel.
+ * @pipe_id: client Id whose DMA channel has to be halted
+ * We suspend the channel first. For Physical channel we just
+ * stop it and return. For Logical channels, we check if some other
+ * Logical channel is still running(Other than one we halted),
+ * then we again put that physical resource in run state.
+ *
+ */
+static int halt_dma_channel(int pipe_id)
+{
+ struct dma_channel_info *info = NULL;
+
+ info = dma_drv_data->pipe_info[pipe_id];
+ if (dma_channel_execute_command(DMA_SUSPEND_REQ, info->phys_chan_id) ==
+ -1) {
+ stm_error("Unable to suspend the Channel %d\n",
+ info->phys_chan_id);
+ return -1;
+ }
+ if (info->chan_mode == DMA_CHAN_IN_PHYS_MODE) {
+ if (dma_channel_execute_command(DMA_STOP, info->phys_chan_id) ==
+ -1) {
+ stm_error("Unable to stop the Channel %d\n",
+ info->phys_chan_id);
+ return -1;
+ }
+ } else if (info->chan_mode == DMA_CHAN_IN_LOG_MODE) {
+ /*Deactivate the event line during
+ * the time physical res is suspended */
+ print_channel_reg_params(info->phys_chan_id);
+
+ if (info->dir == MEM_TO_PERIPH) {
+ REG_WR_BITS(cio_addr
+ (info->phys_chan_id, CHAN_REG_SDLNK),
+ DEACTIVATE_EVENTLINE,
+ EVENTLINE_MASK(info->dst_info.event_line),
+ EVENTLINE_POS(info->dst_info.event_line));
+ } else if (info->dir == PERIPH_TO_MEM) {
+ REG_WR_BITS(cio_addr
+ (info->phys_chan_id, CHAN_REG_SSLNK),
+ DEACTIVATE_EVENTLINE,
+ EVENTLINE_MASK(info->src_info.event_line),
+ EVENTLINE_POS(info->src_info.event_line));
+ } else {
+ stm_dbg(DBG_ST.dma, "Unknown request\n");
+ }
+ print_channel_reg_params(info->phys_chan_id);
+
+ if (get_phy_res_usage_count(info->phys_chan_id) <= 1) {
+ stm_dbg(DBG_ST.dma,
+ "Stopping the Logical channel..............\n");
+ if (dma_channel_execute_command
+ (DMA_STOP, info->phys_chan_id) == -1) {
+ stm_error("Unable to stop the Channel %d\n",
+ info->phys_chan_id);
+ return -1;
+ }
+ /*info->chan_mode = DMA_CHAN_IN_PHYS_MODE; */
+ } else {
+ stm_dbg(DBG_ST.dma,
+ "since some other Logical channel might "
+ "be using it" "putting "
+ "it to running state again..\n");
+ dma_channel_execute_command(DMA_RUN,
+ info->phys_chan_id);
+ }
+ } else {
+ stm_error
+ ("stm_disable_dma()::Operation mode not supported\n");
+ }
+ info->active = 0;
+ return 0;
+}
+
+/**
+ * stm_disable_dma() - API to disable a DMA channel
+ * @pipe_id: client id whose channel has to be disabled
+ * This function halts the concerned DMA channel and returns.
+ *
+ */
+void stm_disable_dma(int pipe_id)
+{
+ struct dma_channel_info *info = NULL;
+ unsigned long flags;
+
+ if (is_pipeid_invalid(pipe_id)) {
+ stm_error("Invalid pipe id");
+ return;
+ }
+
+ info = dma_drv_data->pipe_info[pipe_id];
+ if (info->phys_chan_id != DMA_CHAN_NOT_ALLOCATED) {
+ spin_lock_irqsave(&dma_drv_data->cfg_ch_lock
+ [info->phys_chan_id], flags);
+ if (halt_dma_channel(pipe_id))
+ stm_error("Unable to Halt DMA pipe_id :: %d\n",
+ pipe_id);
+ spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock
+ [info->phys_chan_id], flags);
+ }
+}
+EXPORT_SYMBOL(stm_disable_dma);
+
+/**
+ * stm_free_dma() - API to release a DMA channel
+ * @pipe_id: id whose channel has to be freed
+ * This function first halts the channel, then the resources
+ * held by the channel are released and pipe deallocated.
+ *
+ */
+void stm_free_dma(int pipe_id)
+{
+ struct dma_channel_info *info = NULL;
+ unsigned long flags;
+
+ if (is_pipeid_invalid(pipe_id)) {
+ stm_error("Invalid pipe id %d", pipe_id);
+ return;
+ }
+
+ info = dma_drv_data->pipe_info[pipe_id];
+ if (!info) {
+ stm_error("Null Info structure....");
+ return;
+ }
+ stm_dbg(DBG_ST.dma, "Trying to free DMA pipe_id %d\n", pipe_id);
+
+ if (info->phys_chan_id != DMA_CHAN_NOT_ALLOCATED) {
+ spin_lock_irqsave(&dma_drv_data->cfg_ch_lock
+ [info->phys_chan_id], flags);
+ if (info->chan_mode == DMA_CHAN_IN_PHYS_MODE) {
+ if (halt_dma_channel(pipe_id)) {
+ stm_error("Unable to Halt DMA pipe_id :: %d\n",
+ pipe_id);
+ spin_unlock_irqrestore
+ (&dma_drv_data->cfg_ch_lock
+ [info->phys_chan_id], flags);
+ return;
+ }
+ if (info->lli_block_id_src >= 0) {
+ release_block(info->lli_block_id_src,
+ dma_drv_data->pchan_lli_pool);
+ info->lli_block_id_src = -1;
+ }
+ if (info->lli_block_id_dest >= 0) {
+ release_block(info->lli_block_id_dest,
+ dma_drv_data->pchan_lli_pool);
+ info->lli_block_id_dest = -1;
+ }
+ if (info->sg_block_id_src >= 0) {
+ release_block(info->sg_block_id_src,
+ dma_drv_data->sg_pool);
+ info->sg_block_id_src = -1;
+ }
+ if (info->sg_block_id_dest >= 0) {
+ release_block(info->sg_block_id_dest,
+ dma_drv_data->sg_pool);
+ info->sg_block_id_dest = -1;
+ }
+ if (release_phys_resource(info) == -1) {
+ stm_error
+ ("Unable to free Physical resource %d\n",
+ info->phys_chan_id);
+ BUG();
+ }
+ } else { /*Logical */
+
+ halt_dma_channel(pipe_id);
+ if (release_phys_resource(info) == -1) {
+ stm_error
+ ("Unable to free Physical resource %d\n",
+ info->phys_chan_id);
+ BUG();
+ }
+ if (info->lli_block_id_src >= 0) {
+ rel_free_log_lli_block
+ (dma_drv_data->lchan_lli_pool,
+ info->phys_chan_id,
+ info->lli_block_id_src);
+ info->lli_block_id_src = -1;
+ }
+ if (info->lli_block_id_dest >= 0) {
+ rel_free_log_lli_block
+ (dma_drv_data->lchan_lli_pool,
+ info->phys_chan_id,
+ info->lli_block_id_dest);
+ info->lli_block_id_dest = -1;
+ }
+ if (info->sg_block_id_src >= 0) {
+ release_block(info->sg_block_id_src,
+ dma_drv_data->sg_pool);
+ info->sg_block_id_src = -1;
+ }
+ if (info->sg_block_id_dest >= 0) {
+ release_block(info->sg_block_id_dest,
+ dma_drv_data->sg_pool);
+ info->sg_block_id_dest = -1;
+ }
+ }
+ spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock
+ [info->phys_chan_id], flags);
+ }
+ dma_drv_data->pipe_info[pipe_id] = NULL;
+ if (info->channel_id >= 0)
+ dma_drv_data->dma_chan_info[info->channel_id] = NULL;
+ kfree(info);
+ deallocate_pipe_id(pipe_id);
+ stm_dbg(DBG_ST.dma, "Succesfully freed DMA pipe_id %d\n", pipe_id);
+}
+EXPORT_SYMBOL(stm_free_dma);
+
+/**
+ * stm_dma_residue() - To Return remaining bytes of transfer
+ * @pipe_id: client id whose residue is to be returned
+ *
+ */
+int stm_dma_residue(int pipe_id)
+{
+ struct dma_channel_info *info = NULL;
+ unsigned long flags;
+ int remaining = 0;
+ if (is_pipeid_invalid(pipe_id)) {
+ stm_error("Invalid pipe id");
+ return -1;
+ }
+ info = dma_drv_data->pipe_info[pipe_id];
+ if (!info) {
+ stm_error("Null Info structure....");
+ return -1;
+ }
+
+ if (info->active == 0) {
+ stm_error("Channel callback done... no residue\n");
+ return 0;
+ }
+ spin_lock_irqsave(&dma_drv_data->cfg_ch_lock[info->phys_chan_id],
+ flags);
+ if (dma_channel_execute_command(DMA_SUSPEND_REQ, info->phys_chan_id) ==
+ -1) {
+ stm_error("Unable to suspend the Channel %d\n",
+ info->phys_chan_id);
+ spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock
+ [info->phys_chan_id], flags);
+ return -1;
+ }
+
+ if (info->chan_mode == DMA_CHAN_IN_PHYS_MODE) {
+ remaining =
+ REG_RD_BITS(cio_addr
+ (info->phys_chan_id, CHAN_REG_SDELT),
+ SREG_ELEM_PHY_ECNT_MASK,
+ SREG_ELEM_PHY_ECNT_POS);
+ } else {
+ struct std_log_memory_param *params = NULL;
+
+ if (info->dir == MEM_TO_PERIPH)
+ params = ((void *)
+ (dma_drv_data->lchan_params_base.log_addr)
+ + (info->dst_dev_type * 32) + 16);
+ else if (info->dir == PERIPH_TO_MEM)
+ params = ((void *)
+ (dma_drv_data->lchan_params_base.log_addr)
+ + (info->src_dev_type * 32));
+ remaining =
+ MEM_READ_BITS(params->dmac_lcsp2, MEM_LCSP2_ECNT_MASK,
+ MEM_LCSP2_ECNT_POS);
+ }
+ if (remaining)
+ dma_channel_execute_command(DMA_RUN, info->phys_chan_id);
+ spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock[info->phys_chan_id],
+ flags);
+ return remaining * (0x1 << info->src_info.data_width);
+}
+EXPORT_SYMBOL(stm_dma_residue);
+
+/**
+ * stm_pause_dma() - To pause an ongoing transfer on a pipe
+ * @pipe_id: client id whose transfer has to be paused
+ * This function pauses the transfer on a pipe.
+ *
+ *
+ *
+ */
+int stm_pause_dma(int pipe_id)
+{
+ struct dma_channel_info *info = NULL;
+ unsigned long flags;
+
+ if (is_pipeid_invalid(pipe_id)) {
+ stm_error("Invalid pipe id");
+ return -1;
+ }
+ info = dma_drv_data->pipe_info[pipe_id];
+ if (!info) {
+ stm_error("Null Info structure....");
+ return -1;
+ }
+ if (info->active == 0) {
+ stm_dbg(DBG_ST.dma, "Channel is not active\n");
+ return 0;
+ }
+ spin_lock_irqsave(&dma_drv_data->cfg_ch_lock[info->phys_chan_id],
+ flags);
+ if (dma_channel_execute_command(DMA_SUSPEND_REQ, info->phys_chan_id) ==
+ -1) {
+ stm_error("Unable to suspend the Channel %d\n",
+ info->phys_chan_id);
+ if (dma_channel_execute_command
+ (DMA_SUSPEND_REQ, info->phys_chan_id) == -1)
+ goto error_pause;
+ }
+
+ if (info->chan_mode == DMA_CHAN_IN_PHYS_MODE) {
+ if ((info->dir == PERIPH_TO_MEM)
+ || (info->dir == PERIPH_TO_PERIPH)) {
+ u32 tmp;
+ if (info->src_dev_type < 32) {
+ tmp =
+ REG_RD_BITS(io_addr(DREG_FSEB1),
+ FULL32_MASK, NO_SHIFT);
+ tmp |= (0x1 << info->src_dev_type);
+ REG_WR_BITS(io_addr(DREG_FSEB1), tmp,
+ FULL32_MASK, NO_SHIFT);
+ } else {
+ tmp =
+ REG_RD_BITS(io_addr(DREG_FSEB2),
+ FULL32_MASK, NO_SHIFT);
+ tmp |= (0x1 << info->src_dev_type) + 32;
+ REG_WR_BITS(io_addr(DREG_FSEB2), tmp,
+ FULL32_MASK, NO_SHIFT);
+ }
+ }
+ } else if (info->chan_mode == DMA_CHAN_IN_LOG_MODE) {
+ /*Deactivate the event line during the
+ *time physical res is suspended */
+ if (info->dir == MEM_TO_PERIPH) {
+ REG_WR_BITS(cio_addr
+ (info->phys_chan_id, CHAN_REG_SDLNK),
+ DEACTIVATE_EVENTLINE,
+ EVENTLINE_MASK(info->dst_info.event_line),
+ EVENTLINE_POS(info->dst_info.event_line));
+ } else if (info->dir == PERIPH_TO_MEM) {
+ REG_WR_BITS(cio_addr
+ (info->phys_chan_id, CHAN_REG_SSLNK),
+ DEACTIVATE_EVENTLINE,
+ EVENTLINE_MASK(info->src_info.event_line),
+ EVENTLINE_POS(info->src_info.event_line));
+ } else {
+ stm_dbg(DBG_ST.dma, "Unknown request\n");
+ goto error_pause;
+ }
+ if ((info->dir == PERIPH_TO_MEM)
+ || (info->dir == PERIPH_TO_PERIPH)) {
+ u32 tmp;
+ if (info->src_dev_type < 32) {
+ tmp =
+ REG_RD_BITS(io_addr(DREG_FSEB1),
+ FULL32_MASK, NO_SHIFT);
+ tmp |= (0x1 << info->src_dev_type);
+ REG_WR_BITS(io_addr(DREG_FSEB1), tmp,
+ FULL32_MASK, NO_SHIFT);
+ } else {
+ tmp =
+ REG_RD_BITS(io_addr(DREG_FSEB2),
+ FULL32_MASK, NO_SHIFT);
+ tmp |= (0x1 << info->src_dev_type) + 32;
+ REG_WR_BITS(io_addr(DREG_FSEB2), tmp,
+ FULL32_MASK, NO_SHIFT);
+ }
+ }
+ /*Restart the Physical resource */
+ dma_channel_execute_command(DMA_RUN, info->phys_chan_id);
+ } else {
+ stm_error("Operation mode not supported\n");
+ goto error_pause;
+ }
+
+ spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock[info->phys_chan_id],
+ flags);
+ return 0;
+error_pause:
+ spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock[info->phys_chan_id],
+ flags);
+ return -1;
+}
+EXPORT_SYMBOL(stm_pause_dma);
+
+void stm_unpause_dma(int pipe_id)
+{
+ struct dma_channel_info *info = NULL;
+ unsigned long flags;
+
+ if (is_pipeid_invalid(pipe_id)) {
+ stm_error("Invalid pipe id");
+ return;
+ }
+ info = dma_drv_data->pipe_info[pipe_id];
+ if (!info) {
+ stm_error("Null Info structure....");
+ return;
+ }
+ spin_lock_irqsave(&dma_drv_data->cfg_ch_lock[info->phys_chan_id],
+ flags);
+ if (dma_channel_execute_command(DMA_SUSPEND_REQ, info->phys_chan_id) ==
+ -1) {
+ stm_error("Unable to suspend the Channel %d\n",
+ info->phys_chan_id);
+ spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock
+ [info->phys_chan_id], flags);
+ return;
+ }
+ if (info->chan_mode == DMA_CHAN_IN_LOG_MODE) {
+ /*activate the event line */
+ int line_status = 0;
+ if (info->dir == MEM_TO_PERIPH) {
+ REG_WR_BITS(cio_addr
+ (info->phys_chan_id, CHAN_REG_SDLNK),
+ ACTIVATE_EVENTLINE,
+ EVENTLINE_MASK(info->dst_info.event_line),
+ EVENTLINE_POS(info->dst_info.event_line));
+ line_status =
+ REG_RD_BITS(cio_addr
+ (info->phys_chan_id,
+ CHAN_REG_SDLNK),
+ EVENTLINE_MASK(info->
+ dst_info.event_line),
+ EVENTLINE_POS(info->
+ dst_info.event_line));
+ print_channel_reg_params(info->phys_chan_id);
+ } else if (info->dir == PERIPH_TO_MEM) {
+ REG_WR_BITS(cio_addr
+ (info->phys_chan_id, CHAN_REG_SSLNK),
+ ACTIVATE_EVENTLINE,
+ EVENTLINE_MASK(info->src_info.event_line),
+ EVENTLINE_POS(info->src_info.event_line));
+ line_status =
+ REG_RD_BITS(cio_addr
+ (info->phys_chan_id,
+ CHAN_REG_SSLNK),
+ EVENTLINE_MASK(info->
+ src_info.event_line),
+ EVENTLINE_POS(info->
+ src_info.event_line));
+ } else {
+ stm_dbg(DBG_ST.dma, "Unknown request\n");
+ }
+ }
+ dma_channel_execute_command(DMA_RUN, info->phys_chan_id);
+ spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock[info->phys_chan_id],
+ flags);
+}
+EXPORT_SYMBOL(stm_unpause_dma);
+
+#if 0
+static irqreturn_t stm_dma_secure_interrupt_handler(int irq, void *dev_id)
+{
+ u32 mask = 0x1;
+ int i = 0;
+ int k = 0;
+ unsigned long flags;
+ struct dma_channel_info *info = NULL;
+ dbg2("stm_dma_interrupt_handler22222 called...\n");
+
+ if (dma_drv_data->dma_regs->dmac_spcmis) {
+ for (mask = 1; mask != 0x80000000; mask = mask << 1, k++) {
+ if (dma_drv_data->dma_regs->dmac_spcmis & mask) {
+ dma_drv_data->dma_regs->dmac_spcicr |= mask;
+ spin_lock_irqsave(&dma_info_lock, flags);
+ info =
+ dma_drv_data->dma_chan_info
+ [MAX_LOGICAL_CHANNELS + k];
+ info->callback(info->data, 0);
+ print_channel_reg_params(info->phys_chan_id);
+ spin_unlock_irqrestore(&dma_info_lock, flags);
+ }
+ i++;
+ }
+ }
+ return IRQ_HANDLED;
+}
+#endif
+
+void process_phy_channel_inerrupt(void)
+{
+ int k = 0;
+ struct dma_channel_info *info = NULL;
+ u32 tmp;
+ if (ioread32(io_addr(DREG_PCMIS))) {
+ // Search Physical Interrupt source(s)
+ for (k = 0; k < MAX_AVAIL_PHY_CHANNELS; k++) {
+ // Is it due to an Error ?
+ if (ioread32(io_addr(DREG_PCEIS)) & (0x1 << k)) {
+ info =
+ dma_drv_data->dma_chan_info
+ [MAX_LOGICAL_CHANNELS + k];
+ stm_dbg(DBG_ST.dma, "Error interrupt\n");
+ if ((info->active) && (info->callback))
+ info->callback(info->data, XFER_ERROR);
+ }
+
+ // Is it due to a Terminal Count ?
+ if (ioread32(io_addr(DREG_PCTIS)) & (0x1 << k)) {
+ info =
+ dma_drv_data->dma_chan_info
+ [MAX_LOGICAL_CHANNELS + k];
+ stm_dbg(DBG_ST.dma, "TIS interrupt\n");
+ if ((info->lli_interrupt == 1)
+ && (info->sg_dest)
+ && ((info->dir == PERIPH_TO_MEM)
+ || (info->dir == MEM_TO_PERIPH))) {
+ info->bytes_xfred +=
+ sg_dma_len(info->current_sg);
+ stm_dbg(DBG_ST.dma,
+ "Channel(%d) :: Transfer "
+ "completed for %d bytes\n",
+ info->phys_chan_id,
+ info->bytes_xfred);
+ info->current_sg++;
+ if ((info->bytes_xfred ==
+ get_xfer_len(info))
+ && (info->active)
+ && (info->callback))
+ info->callback(info->data,
+ XFER_COMPLETE);
+ } else {
+ if ((info->active) && (info->callback))
+ info->callback(info->data,
+ XFER_COMPLETE);
+ }
+ }
+ // Acknoledge Interrupt
+ tmp =
+ REG_RD_BITS(io_addr(DREG_PCICR),
+ FULL32_MASK, NO_SHIFT);
+ tmp |= (0x1 << k);
+ REG_WR_BITS(io_addr(DREG_PCICR), tmp,
+ FULL32_MASK, NO_SHIFT);
+ }
+ }
+}
+
+void process_logical_channel_inerrupt(void)
+{
+ int j = 0;
+ int k = 0;
+ struct dma_channel_info *info = NULL;
+ u32 tmp;
+ for (j = 0; j < 4; j++) {
+ if (ioread32(io_addr(DREG_LCEIS(j)))) {
+ for (k = 0; k < 32; k++) {
+ if (ioread32(io_addr(DREG_LCEIS(j))) &
+ (0x1 << k)) {
+ tmp =
+ REG_RD_BITS(io_addr
+ (DREG_LCICR(j)),
+ FULL32_MASK, NO_SHIFT);
+ tmp |= (0x1 << k);
+ REG_WR_BITS(io_addr
+ (DREG_LCICR(j)), tmp,
+ FULL32_MASK, NO_SHIFT);
+ stm_dbg(DBG_ST.dma,
+ "Error Logical "
+ "Interrupt Line :: %d\n",
+ (j * 32 + k));
+ info =
+ dma_drv_data->dma_chan_info[j * 32 +
+ k];
+ if ((info->active) && (info->callback))
+ info->callback(info->data,
+ XFER_ERROR);
+ }
+ }
+ }
+ }
+
+ for (j = 0; j < 4; j++) {
+ if (ioread32(io_addr(DREG_LCTIS(j)))) {
+ for (k = 0; k < 32; k++) {
+ if (ioread32(io_addr(DREG_LCTIS(j))) &
+ (0x1 << k)) {
+ tmp =
+ REG_RD_BITS(io_addr
+ (DREG_LCICR(j)),
+ FULL32_MASK, NO_SHIFT);
+ tmp |= (0x1 << k);
+ REG_WR_BITS(io_addr
+ (DREG_LCICR(j)), tmp,
+ FULL32_MASK, NO_SHIFT);
+ stm_dbg(DBG_ST.dma,
+ "TIS interrupt:::: Logical "
+ "Interrupt Line :: %d\n",
+ (j * 32 + k));
+ info =
+ dma_drv_data->dma_chan_info[j * 32 +
+ k];
+ if (!info)
+ continue;
+
+ if ((info->lli_interrupt == 1)
+ && (info->sg_dest)
+ && ((info->dir == PERIPH_TO_MEM)
+ || (info->dir ==
+ MEM_TO_PERIPH))) {
+ info->bytes_xfred +=
+ sg_dma_len
+ (info->current_sg);
+ stm_dbg(DBG_ST.dma,
+ "Channel(%d) :: "
+ "Transfer completed "
+ "for %d bytes\n",
+ info->phys_chan_id,
+ info->bytes_xfred);
+ info->current_sg++;
+ if ((info->bytes_xfred ==
+ get_xfer_len(info))
+ && ((info->active)
+ && (info->callback)))
+ info->
+ callback(info->data,
+ XFER_COMPLETE);
+ } else {
+ if ((info->active)
+ && (info->callback))
+ info->
+ callback(info->data,
+ XFER_COMPLETE);
+ }
+ }
+ }
+ }
+ }
+}
+
+static irqreturn_t stm_dma_interrupt_handler(int irq, void *dev_id)
+{
+
+ process_phy_channel_inerrupt();
+ process_logical_channel_inerrupt();
+ return IRQ_HANDLED;
+}
+
+static int stm_dma_probe(struct platform_device *pdev)
+{
+ struct resource *res = NULL;
+ int status = 0, i;
+ stm_dbg(DBG_ST.dma, "stm_dma_probe called.....\n");
+ printk(KERN_INFO "In DMA PROBE \n");
+ dma_drv_data = kzalloc(sizeof(struct dma_driver_data), GFP_KERNEL);
+
+ if (!dma_drv_data) {
+ stm_error("DMA driver structure cannot be allocated...\n");
+ return -1;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ stm_error("IORESOURCE_MEM unavailable\n");
+ goto driver_cleanup;
+ }
+
+ dma_drv_data->reg_base =
+ (void __iomem *)ioremap(res->start, res->end - res->start + 1);
+
+ if (!dma_drv_data->reg_base) {
+ stm_error("ioremap of DMA register memory failed\n");
+ goto driver_cleanup;
+ }
+ stm_dbg(DBG_ST.dma, "DMA_REGS = %x\n", (u32) dma_drv_data->reg_base);
+
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (!res) {
+ stm_error("IORESOURCE_IRQ unavailable\n");
+ goto driver_ioremap_cleanup;
+ }
+
+ status =
+ request_irq(res->start, stm_dma_interrupt_handler, 0, "DMA",
+ NULL);
+ if (status) {
+ stm_error("Unable to request IRQ\n");
+ goto driver_ioremap_cleanup;
+ }
+
+ dma_drv_data->clk = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(dma_drv_data->clk)) {
+ stm_error("Unable to get clock\n");
+ goto driver_ioremap_cleanup;
+ }
+
+ clk_enable(dma_drv_data->clk);
+
+#ifndef CONFIG_STM_SECURITY
+ initialize_dma_regs();
+ dma_drv_data->lchan_params_base.log_addr =
+ dma_alloc_coherent(NULL, 128 * 4 * sizeof(u32),
+ &dma_drv_data->lchan_params_base.phys_addr,
+ GFP_KERNEL | GFP_DMA);
+ if (!dma_drv_data->lchan_params_base.log_addr) {
+ stm_error("Request for Memory allocation for \
+ Logical channel parameters failed\n");
+ goto driver_clk_cleanup;
+ }
+ REG_WR_BITS(io_addr(DREG_LCPA),
+ dma_drv_data->lchan_params_base.phys_addr,
+ FULL32_MASK, NO_SHIFT);
+#else
+ /* LCPA value cannot be programmed(we are in non-secure mode).
+ * We make use of ESRAM memory for this.
+ * (xloader programs this register with the value(ESRAM address)
+ * beforehand)
+ * */
+ dma_drv_data->lchan_params_base.log_addr =
+ ioremap(U8500_DMA_LCPA_BASE, 4096);
+ dma_drv_data->lchan_params_base.phys_addr = U8500_DMA_LCPA_BASE;
+
+ REG_WR_BITS(io_addr(DREG_LCPA),
+ U8500_DMA_LCPA_BASE,
+ FULL32_MASK, NO_SHIFT);
+#endif
+
+ dma_drv_data->pchan_lli_pool = create_elem_pool("PCHAN_LLI_POOL",
+ NUM_LLI_PER_REQUEST *
+ sizeof(struct
+ dma_lli_info),
+ NUM_PCHAN_LLI_BLOCKS,
+ 12);
+ if (!dma_drv_data->pchan_lli_pool) {
+ stm_error("Unable to allocate memory for Phys chan LLI pool");
+ goto driver_chan_mem_cleanup;
+ }
+ dma_drv_data->sg_pool = create_elem_pool("SG_POOL",
+ NUM_SG_PER_REQUEST *
+ sizeof(struct scatterlist),
+ NUM_SG_BLOCKS, 12);
+ if (!dma_drv_data->sg_pool) {
+ stm_error("Unable to allocate memory for SG pool");
+ goto pchan_lli_pool_cleanup;
+ }
+#ifndef CONFIG_STM_SECURITY
+ /*Allocate 1Kb block for each physical channels */
+ dma_drv_data->lchan_lli_pool = create_elem_pool("LCHAN_LLI_POOL",
+ 1024,
+ MAX_PHYSICAL_CHANNELS,
+ 18);
+ if (!dma_drv_data->lchan_lli_pool) {
+ stm_error("Unable to allocate memory for lchan_lli_pool");
+ goto sg_pool_cleanup;
+ }
+
+ REG_WR_BITS(io_addr(DREG_LCLA),
+ dma_drv_data->lchan_lli_pool->base_addr.phys_addr,
+ FULL32_MASK, NO_SHIFT);
+#else
+ /* LCLA value cannot be programmed(we are in non-secure mode).
+ * We make use of ESRAM memory for this.
+ * (xloader programs this register with the value(ESRAM address)
+ * beforehand)
+ * */
+ /*Allocate 1Kb block for each physical channels */
+ dma_drv_data->lchan_lli_pool =
+ create_elem_pool_fixed_mem("LCHAN_LLI_POOL", 1024,
+ MAX_AVAIL_PHY_CHANNELS,
+ U8500_DMA_LCLA_BASE, 16 * 1024);
+
+ if (!dma_drv_data->lchan_lli_pool) {
+ stm_error("Unable to allocate memory for lchan_lli_pool");
+ goto sg_pool_cleanup;
+ }
+ REG_WR_BITS(io_addr(DREG_LCLA),
+ dma_drv_data->lchan_lli_pool->base_addr.phys_addr,
+ FULL32_MASK, NO_SHIFT);
+#endif
+
+ spin_lock_init(&dma_drv_data->pipe_id_lock);
+ spin_lock_init(&dma_drv_data->pr_info_lock);
+ for (i = 0; i < MAX_AVAIL_PHY_CHANNELS; i++)
+ spin_lock_init(&dma_drv_data->cfg_ch_lock[i]);
+
+ /* Audio is using physical channels 2 and 3 from MMDSP */
+ dma_drv_data->pr_info[2].status = RESOURCE_PHYSICAL;
+ dma_drv_data->pr_info[3].status = RESOURCE_PHYSICAL;
+ /* End of Audio */
+
+ print_dma_regs();
+ return 0;
+sg_pool_cleanup:
+ destroy_elem_pool(dma_drv_data->sg_pool);
+pchan_lli_pool_cleanup:
+ destroy_elem_pool(dma_drv_data->pchan_lli_pool);
+driver_chan_mem_cleanup:
+#ifndef CONFIG_STM_SECURITY
+ dma_free_coherent(NULL, 128 * 4 * sizeof(u32),
+ dma_drv_data->lchan_params_base.log_addr,
+ dma_drv_data->lchan_params_base.phys_addr);
+driver_clk_cleanup:
+#endif
+ clk_disable(dma_drv_data->clk);
+ clk_put(dma_drv_data->clk);
+driver_ioremap_cleanup:
+ iounmap(dma_drv_data->reg_base);
+driver_cleanup:
+ kfree(dma_drv_data);
+ return -1;
+}
+
+/*
+ * Clean up routine
+ */
+static int stm_dma_remove(struct platform_device *pdev)
+{
+ struct resource *res = NULL;
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+#ifndef CONFIG_STM_SECURITY
+ /*Free Memory used for Storing Logical channel cfg params */
+ dma_free_coherent(NULL, 128 * 4 * sizeof(u32),
+ dma_drv_data->lchan_params_base.log_addr,
+ dma_drv_data->lchan_params_base.phys_addr);
+#endif
+ destroy_elem_pool(dma_drv_data->pchan_lli_pool);
+ destroy_elem_pool(dma_drv_data->sg_pool);
+#ifndef CONFIG_STM_SECURITY
+ destroy_elem_pool(dma_drv_data->lchan_lli_pool);
+#endif
+ free_irq(res->start, 0);
+ clk_disable(dma_drv_data->clk);
+ clk_put(dma_drv_data->clk);
+ iounmap(dma_drv_data->reg_base);
+ kfree(dma_drv_data);
+ return 0;
+}
+
+#ifdef CONFIG_PM
+
+/**
+ * stm_dma_suspend() - Function registered with Kernel Power Mgmt framework
+ * @pdev: Platform device structure for the DMA controller
+ * @state: pm_message_t state sent by PM framework
+ *
+ * This function will be called by the Linux Kernel Power Mgmt Framework, while
+ * going to sleep. It is assumed that no active tranfer is in progress
+ * at this time. Client driver should make sure of this.
+ */
+int stm_dma_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ /*
+ * writing back backed-up non-secure registers
+ * FIXME : DREG_GCC/FSEBn and few others are accesible
+ * only on a secure mode. this condition needs
+ * to be inserted before this operation
+ */
+ dma_drv_data->backup_regs[0] = ioread32(io_addr(DREG_GCC));
+ dma_drv_data->backup_regs[1] = ioread32(io_addr(DREG_PRTYP));
+ dma_drv_data->backup_regs[2] = ioread32(io_addr(DREG_PRMSE));
+ dma_drv_data->backup_regs[3] = ioread32(io_addr(DREG_PRMSO));
+ dma_drv_data->backup_regs[4] = ioread32(io_addr(DREG_PRMOE));
+ dma_drv_data->backup_regs[5] = ioread32(io_addr(DREG_PRMOO));
+ dma_drv_data->backup_regs[6] = ioread32(io_addr(DREG_LCPA));
+ dma_drv_data->backup_regs[7] = ioread32(io_addr(DREG_LCLA));
+ dma_drv_data->backup_regs[8] = ioread32(io_addr(DREG_ACTIVE));
+ dma_drv_data->backup_regs[9] = ioread32(io_addr(DREG_ACTIVO));
+ dma_drv_data->backup_regs[10] = ioread32(io_addr(DREG_FSEB1));
+ dma_drv_data->backup_regs[11] = ioread32(io_addr(DREG_FSEB2));
+ dma_drv_data->backup_regs[12] = ioread32(io_addr(DREG_PCICR));
+
+ stm_dbg(DBG_ST.dma, "stm_dma_suspend: called......\n");
+ return 0;
+}
+
+/**
+ * stm_dma_resume() - Function registered with Kernel Power Mgmt framework
+ * @pdev: Platform device structure for the DMA controller
+ *
+ * This function will be called by the Linux Kernel Power Mgmt Framework, when
+ * System comes out of sleep.
+ *
+ *
+ */
+int stm_dma_resume(struct platform_device *pdev)
+{
+ /*
+ * writing back backed-up non-secure registers
+ * FIXME : DREG_GCC/FSEBn and few others are accesible
+ * only on a secure mode. this condition needs
+ * to be inserted before this operation
+ */
+ iowrite32(dma_drv_data->backup_regs[0], (io_addr(DREG_GCC)));
+ iowrite32(dma_drv_data->backup_regs[1], (io_addr(DREG_PRTYP)));
+ iowrite32(dma_drv_data->backup_regs[2], (io_addr(DREG_PRMSE)));
+ iowrite32(dma_drv_data->backup_regs[3], (io_addr(DREG_PRMSO)));
+ iowrite32(dma_drv_data->backup_regs[4], (io_addr(DREG_PRMOE)));
+ iowrite32(dma_drv_data->backup_regs[5], (io_addr(DREG_PRMOO)));
+ iowrite32(dma_drv_data->backup_regs[6], (io_addr(DREG_LCPA)));
+ iowrite32(dma_drv_data->backup_regs[7], (io_addr(DREG_LCLA)));
+ iowrite32(dma_drv_data->backup_regs[8], (io_addr(DREG_ACTIVE)));
+ iowrite32(dma_drv_data->backup_regs[9], (io_addr(DREG_ACTIVO)));
+ iowrite32(dma_drv_data->backup_regs[10], (io_addr(DREG_FSEB1)));
+ iowrite32(dma_drv_data->backup_regs[11], (io_addr(DREG_FSEB2)));
+ iowrite32(dma_drv_data->backup_regs[12], (io_addr(DREG_PCICR)));
+
+
+ stm_dbg(DBG_ST.dma, "stm_dma_resume: called......\n");
+ return 0;
+}
+
+#else
+
+#define stm_dma_suspend NULL
+#define stm_dma_resume NULL
+
+#endif
+
+static struct platform_driver stm_dma_driver = {
+ .probe = stm_dma_probe,
+ .remove = stm_dma_remove,
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "STM-DMA",
+ },
+ .suspend = stm_dma_suspend,
+ .resume = stm_dma_resume,
+};
+
+static int __init stm_dma_init(void)
+{
+ return platform_driver_register(&stm_dma_driver);
+}
+
+module_init(stm_dma_init);
+static void __exit stm_dma_exit(void)
+{
+ platform_driver_unregister(&stm_dma_driver);
+ return;
+}
+
+module_exit(stm_dma_exit);
+
+/* Module parameters */
+
+MODULE_AUTHOR("ST Microelectronics");
+MODULE_DESCRIPTION("STM DMA Controller");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-ux500/headsmp.S b/arch/arm/mach-ux500/headsmp.S
new file mode 100755
index 00000000000..1f9aee4675d
--- /dev/null
+++ b/arch/arm/mach-ux500/headsmp.S
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) ST Ericsson
+ * based on ARM realview platform
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ __INIT
+
+/*
+ * u8500 specific entry point for secondary CPUs. This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(u8500_secondary_startup)
+ mrc p15, 0, r0, c0, c0, 5
+ and r0, r0, #15
+ adr r4, 1f
+ ldmia r4, {r5, r6}
+ sub r4, r4, r5
+ add r6, r6, r4
+ dsb
+pen: ldr r7, [r6]
+ cmp r7, r0
+ bne pen
+
+ /*
+ * we've been released from the holding pen: secondary_stack
+ * should now contain the SVC stack for this core
+ */
+ b secondary_startup
+
+1: .long .
+ .long pen_release
diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c
new file mode 100755
index 00000000000..f0c9471519c
--- /dev/null
+++ b/arch/arm/mach-ux500/hotplug.c
@@ -0,0 +1,141 @@
+/*
+ * linux/arch/arm/mach-realview/hotplug.c
+ *
+ * Copyright (C) 2002 ARM Ltd.
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <linux/completion.h>
+
+extern volatile int pen_release;
+
+static DECLARE_COMPLETION(cpu_killed);
+
+static inline void cpu_enter_lowpower(void)
+{
+ unsigned int v;
+ asm volatile("bl v7_flush_kern_cache_all\n"
+ " mcr p15, 0, %1, c7, c5, 0\n"
+ " dsb\n"
+ /*
+ * Turn off coherency
+ */
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " bic %0, %0, #0x40\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ " mrc p15, 0, %0, c1, c0, 0\n"
+ " bic %0, %0, #0x04\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ : "=&r" (v)
+ : "r" (0)
+ : "cc");
+
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+ unsigned int v;
+
+ asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
+ " orr %0, %0, #0x04\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " orr %0, %0, #0x40\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ : "=&r" (v)
+ :
+ : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu)
+{
+ /*
+ * there is no power-control hardware on this platform, so all
+ * we can do is put the core into WFI; this is safe as the calling
+ * code will have already disabled interrupts
+ */
+ for (;;) {
+
+ /*
+ * here's the WFI
+ */
+ asm(".word 0xe320f003\n"
+ :
+ :
+ : "memory", "cc");
+
+ if (pen_release == cpu) {
+ /*
+ * OK, proper wakeup, we're done
+ */
+ break;
+ }
+
+ /*
+ * getting here, means that we have come out of WFI without
+ * having been woken up - this shouldn't happen
+ *
+ * The trouble is, letting people know about this is not really
+ * possible, since we are currently running incoherently, and
+ * therefore cannot safely call printk() or anything else
+ */
+#ifdef DEBUG
+ printk("CPU%u: spurious wakeup call\n", cpu);
+#endif
+ }
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+ return wait_for_completion_timeout(&cpu_killed, 5000);
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+#ifdef DEBUG
+ unsigned int this_cpu = hard_smp_processor_id();
+
+ if (cpu != this_cpu) {
+ printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
+ this_cpu, cpu);
+ BUG();
+ }
+#endif
+
+ printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
+ complete(&cpu_killed);
+
+ /*
+ * we're ready for shutdown now, so do it
+ */
+ /* FIXME : skipping this for a temp hack */
+ /* cpu_enter_lowpower(); */
+ platform_do_lowpower(cpu);
+
+ /*
+ * bring this CPU back into the world of cache
+ * coherency, and then restore interrupts
+ */
+ /* FIXME : skipping this for a temp hack */
+ /* cpu_leave_lowpower(); */
+}
+
+int mach_cpu_disable(unsigned int cpu)
+{
+ /*
+ * we don't allow CPU 0 to be shutdown (it is still too special
+ * e.g. clock tick interrupts)
+ */
+ return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-ux500/hsi.c b/arch/arm/mach-ux500/hsi.c
new file mode 100644
index 00000000000..79d7f04f41a
--- /dev/null
+++ b/arch/arm/mach-ux500/hsi.c
@@ -0,0 +1,336 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <linux/hsi.h>
+#include <linux/hsi-legacy.h>
+
+#include <mach/hsi-stm.h>
+#include <mach/devices.h>
+#include <mach/hardware.h>
+
+static struct hsi_plat_data hsit_platform_data = {
+ .dev_type = 0x0 /** transmitter */ ,
+ .mode = 0x2 /** frame mode */ ,
+ .divisor = 0x12 /** half HSIT freq */ ,
+ .parity = 0x0 /** no parity */ ,
+ .channels = 0x4 /** 4 channels */ ,
+ .flushbits = 0x0 /** none */ ,
+ .priority = 0x3 /** ch0,ch1 high while ch2,ch3 low */ ,
+ .burstlen = 0x0 /** infinite b2b */ ,
+ .preamble = 0x0 /** none */ ,
+ .dataswap = 0x0 /** no swap */ ,
+ .framelen = 0x1f /** 32 bits all channels */ ,
+ .ch_base_span = {[0] = {.base = 0x0, .span = 0x3},
+ [1] = {.base = 0x4, .span = 0x3},
+ [2] = {.base = 0x8, .span = 0x7},
+ [3] = {.base = 0x10, .span = 0x7}
+ },
+#ifdef CONFIG_STN8500_HSI_LEGACY
+ .currmode = CONFIG_STN8500_HSI_TRANSFER_MODE,
+#else
+ .currmode = 1,
+#endif
+ .hsi_dma_info = {
+ [0] = {
+ .reserve_channel = 0,
+ .dir = MEM_TO_PERIPH,
+ .flow_cntlr = DMA_IS_FLOW_CNTLR,
+ .channel_type =
+ (STANDARD_CHANNEL | CHANNEL_IN_LOGICAL_MODE
+ | LCHAN_SRC_LOG_DEST_LOG | NO_TIM_FOR_LINK
+ | NON_SECURE_CHANNEL | HIGH_PRIORITY_CHANNEL),
+ .dst_dev_type = DMA_DEV_SLIM0_CH0_TX_HSI_TX_CH0,
+ .src_dev_type = DMA_DEV_DEST_MEMORY,
+ .src_info = {
+ .endianess = DMA_LITTLE_ENDIAN,
+ .data_width = DMA_WORD_WIDTH,
+ .burst_size = DMA_BURST_SIZE_4,
+ .buffer_type = SINGLE_BUFFERED,
+ },
+ .dst_info = {
+ .endianess = DMA_LITTLE_ENDIAN,
+ .data_width = DMA_WORD_WIDTH,
+ .burst_size = DMA_BURST_SIZE_4,
+ .buffer_type = SINGLE_BUFFERED,
+ }
+ },
+ [1] = {
+ .reserve_channel = 0,
+ .dir = MEM_TO_PERIPH,
+ .flow_cntlr = DMA_IS_FLOW_CNTLR,
+ .channel_type =
+ (STANDARD_CHANNEL | CHANNEL_IN_LOGICAL_MODE
+ | LCHAN_SRC_LOG_DEST_LOG | NO_TIM_FOR_LINK
+ | NON_SECURE_CHANNEL | HIGH_PRIORITY_CHANNEL),
+ .dst_dev_type = DMA_DEV_SLIM0_CH1_TX_HSI_TX_CH1,
+ .src_dev_type = DMA_DEV_DEST_MEMORY,
+ .src_info = {
+ .endianess = DMA_LITTLE_ENDIAN,
+ .data_width = DMA_WORD_WIDTH,
+ .burst_size = DMA_BURST_SIZE_4,
+ .buffer_type = SINGLE_BUFFERED,
+ },
+ .dst_info = {
+ .endianess = DMA_LITTLE_ENDIAN,
+ .data_width = DMA_WORD_WIDTH,
+ .burst_size = DMA_BURST_SIZE_4,
+ .buffer_type = SINGLE_BUFFERED,
+ }
+ },
+ [2] = {
+ .reserve_channel = 0,
+ .dir = MEM_TO_PERIPH,
+ .flow_cntlr = DMA_IS_FLOW_CNTLR,
+ .channel_type =
+ (STANDARD_CHANNEL | CHANNEL_IN_LOGICAL_MODE
+ | LCHAN_SRC_LOG_DEST_LOG | NO_TIM_FOR_LINK
+ | NON_SECURE_CHANNEL | HIGH_PRIORITY_CHANNEL),
+ .dst_dev_type = DMA_DEV_SLIM0_CH2_TX_HSI_TX_CH2,
+ .src_dev_type = DMA_DEV_DEST_MEMORY,
+ .src_info = {
+ .endianess = DMA_LITTLE_ENDIAN,
+ .data_width = DMA_WORD_WIDTH,
+ .burst_size = DMA_BURST_SIZE_4,
+ .buffer_type = SINGLE_BUFFERED,
+ },
+ .dst_info = {
+ .endianess = DMA_LITTLE_ENDIAN,
+ .data_width = DMA_WORD_WIDTH,
+ .burst_size = DMA_BURST_SIZE_4,
+ .buffer_type = SINGLE_BUFFERED,
+ }
+ },
+ [3] = {
+ .reserve_channel = 0,
+ .dir = MEM_TO_PERIPH,
+ .flow_cntlr = DMA_IS_FLOW_CNTLR,
+ .channel_type =
+ (STANDARD_CHANNEL | CHANNEL_IN_LOGICAL_MODE
+ | LCHAN_SRC_LOG_DEST_LOG | NO_TIM_FOR_LINK
+ | NON_SECURE_CHANNEL | HIGH_PRIORITY_CHANNEL),
+ .dst_dev_type = DMA_DEV_SLIM0_CH3_TX_HSI_TX_CH3,
+ .src_dev_type = DMA_DEV_DEST_MEMORY,
+ .src_info = {
+ .endianess = DMA_LITTLE_ENDIAN,
+ .data_width = DMA_WORD_WIDTH,
+ .burst_size = DMA_BURST_SIZE_4,
+ .buffer_type = SINGLE_BUFFERED,
+ },
+ .dst_info = {
+ .endianess = DMA_LITTLE_ENDIAN,
+ .data_width = DMA_WORD_WIDTH,
+ .burst_size = DMA_BURST_SIZE_4,
+ .buffer_type = SINGLE_BUFFERED,
+ }
+ },
+ },
+ .watermark = 0x2 /** 1 free entries for all channels */ ,
+ .gpio_alt_func = GPIO_ALT_HSIT,
+};
+
+static struct hsi_plat_data hsir_platform_data = {
+ .dev_type = 0x1 /** receiver */ ,
+ .mode = 0x3 /** pipelined */ ,
+ .threshold = 0x22 /** 35 zero bits for break */ ,
+ .parity = 0x0 /** no parity */ ,
+ .detector = 0x0 /** oversampling */ ,
+ .channels = 0x4 /** 4 channels */ ,
+ .realtime = 0x0 /** disabled,no overwrite,all channels */ ,
+ .framelen = 0x1f /** 32 bits all channels */ ,
+ .preamble = 0x0 /** max timeout cycles */ ,
+ .ch_base_span = {[0] = {.base = 0x0, .span = 0x3},
+ [1] = {.base = 0x4, .span = 0x3},
+ [2] = {.base = 0x8, .span = 0x7},
+ [3] = {.base = 0x10, .span = 0x7}
+ },
+#ifdef CONFIG_STN8500_HSI_LEGACY
+ .currmode = CONFIG_STN8500_HSI_TRANSFER_MODE,
+#else
+ .currmode = 1,
+#endif
+ .timeout = 0x0 /** immediate updation of channel buffer */ ,
+ .hsi_dma_info = {
+ [0] = {
+ .reserve_channel = 0,
+ .dir = PERIPH_TO_MEM,
+ .flow_cntlr = DMA_IS_FLOW_CNTLR,
+ .channel_type =
+ (STANDARD_CHANNEL | CHANNEL_IN_LOGICAL_MODE
+ | LCHAN_SRC_LOG_DEST_LOG | NO_TIM_FOR_LINK
+ | NON_SECURE_CHANNEL | HIGH_PRIORITY_CHANNEL),
+ .src_dev_type = DMA_DEV_SLIM0_CH0_RX_HSI_RX_CH0,
+ .dst_dev_type = DMA_DEV_DEST_MEMORY,
+ .src_info = {
+ .endianess = DMA_LITTLE_ENDIAN,
+ .data_width = DMA_WORD_WIDTH,
+ .burst_size = DMA_BURST_SIZE_4,
+ .buffer_type = SINGLE_BUFFERED,
+ },
+ .dst_info = {
+ .endianess = DMA_LITTLE_ENDIAN,
+ .data_width = DMA_WORD_WIDTH,
+ .burst_size = DMA_BURST_SIZE_4,
+ .buffer_type = SINGLE_BUFFERED,
+ }
+ },
+ [1] = {
+ .reserve_channel = 0,
+ .dir = PERIPH_TO_MEM,
+ .flow_cntlr = DMA_IS_FLOW_CNTLR,
+ .channel_type =
+ (STANDARD_CHANNEL | CHANNEL_IN_LOGICAL_MODE
+ | LCHAN_SRC_LOG_DEST_LOG | NO_TIM_FOR_LINK
+ | NON_SECURE_CHANNEL | HIGH_PRIORITY_CHANNEL),
+ .src_dev_type = DMA_DEV_SLIM0_CH1_RX_HSI_RX_CH1,
+ .dst_dev_type = DMA_DEV_DEST_MEMORY,
+ .src_info = {
+ .endianess = DMA_LITTLE_ENDIAN,
+ .data_width = DMA_WORD_WIDTH,
+ .burst_size = DMA_BURST_SIZE_4,
+ .buffer_type = SINGLE_BUFFERED,
+ },
+ .dst_info = {
+ .endianess = DMA_LITTLE_ENDIAN,
+ .data_width = DMA_WORD_WIDTH,
+ .burst_size = DMA_BURST_SIZE_4,
+ .buffer_type = SINGLE_BUFFERED,
+ }
+ },
+ [2] = {
+ .reserve_channel = 0,
+ .dir = PERIPH_TO_MEM,
+ .flow_cntlr = DMA_IS_FLOW_CNTLR,
+ .channel_type =
+ (STANDARD_CHANNEL | CHANNEL_IN_LOGICAL_MODE
+ | LCHAN_SRC_LOG_DEST_LOG | NO_TIM_FOR_LINK
+ | NON_SECURE_CHANNEL | HIGH_PRIORITY_CHANNEL),
+ .src_dev_type = DMA_DEV_SLIM0_CH2_RX_HSI_RX_CH2,
+ .dst_dev_type = DMA_DEV_DEST_MEMORY,
+ .src_info = {
+ .endianess = DMA_LITTLE_ENDIAN,
+ .data_width = DMA_WORD_WIDTH,
+ .burst_size = DMA_BURST_SIZE_4,
+ .buffer_type = SINGLE_BUFFERED,
+ },
+ .dst_info = {
+ .endianess = DMA_LITTLE_ENDIAN,
+ .data_width = DMA_WORD_WIDTH,
+ .burst_size = DMA_BURST_SIZE_4,
+ .buffer_type = SINGLE_BUFFERED,
+ }
+ },
+ [3] = {
+ .reserve_channel = 0,
+ .dir = PERIPH_TO_MEM,
+ .flow_cntlr = DMA_IS_FLOW_CNTLR,
+ .channel_type =
+ (STANDARD_CHANNEL | CHANNEL_IN_LOGICAL_MODE
+ | LCHAN_SRC_LOG_DEST_LOG | NO_TIM_FOR_LINK
+ | NON_SECURE_CHANNEL | HIGH_PRIORITY_CHANNEL),
+ .src_dev_type = DMA_DEV_SLIM0_CH3_RX_HSI_RX_CH3,
+ .dst_dev_type = DMA_DEV_DEST_MEMORY,
+ .src_info = {
+ .endianess = DMA_LITTLE_ENDIAN,
+ .data_width = DMA_WORD_WIDTH,
+ .burst_size = DMA_BURST_SIZE_4,
+ .buffer_type = SINGLE_BUFFERED,
+ },
+ .dst_info = {
+ .endianess = DMA_LITTLE_ENDIAN,
+ .data_width = DMA_WORD_WIDTH,
+ .burst_size = DMA_BURST_SIZE_4,
+ .buffer_type = SINGLE_BUFFERED,
+ }
+ },
+ },
+ .watermark = 0x2 /** 1 'occupated' entry for all channels */ ,
+ .gpio_alt_func = GPIO_ALT_HSIR,
+};
+
+static struct resource u8500_hsit_resource[] = {
+ [0] = {
+ .start = U8500_HSIT_BASE,
+ .end = U8500_HSIT_BASE + (SZ_4K - 1),
+ .name = "hsit_iomem_base",
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_HSITD0,
+ .end = IRQ_HSITD1,
+ .name = "hsit_irq",
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource u8500_hsir_resource[] = {
+ [0] = {
+ .start = U8500_HSIR_BASE,
+ .end = U8500_HSIR_BASE + (SZ_4K - 1),
+ .name = "hsir_iomem_base",
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_HSIRD0,
+ .end = IRQ_HSIRD1,
+ .name = "hsir_irq",
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = IRQ_HSIR_EXCEP,
+ .end = IRQ_HSIR_EXCEP,
+ .name = "hsir_irq_excep",
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = IRQ_HSIR_CH0_OVRRUN,
+ .end = IRQ_HSIR_CH0_OVRRUN,
+ .name = "hsir_irq_ch0_overrun",
+ .flags = IORESOURCE_IRQ,
+ },
+ [4] = {
+ .start = IRQ_HSIR_CH1_OVRRUN,
+ .end = IRQ_HSIR_CH1_OVRRUN,
+ .name = "hsir_irq_ch1_overrun",
+ .flags = IORESOURCE_IRQ,
+ },
+ [5] = {
+ .start = IRQ_HSIR_CH2_OVRRUN,
+ .end = IRQ_HSIR_CH2_OVRRUN,
+ .name = "hsir_irq_ch2_overrun",
+ .flags = IORESOURCE_IRQ,
+ },
+ [6] = {
+ .start = IRQ_HSIR_CH3_OVRRUN,
+ .end = IRQ_HSIR_CH3_OVRRUN,
+ .name = "hsir_irq_ch3_overrun",
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device u8500_hsit_device = {
+ .name = "stm-hsi",
+ .id = 0,
+ .dev = {
+ .platform_data = &hsit_platform_data,
+ },
+ .num_resources = ARRAY_SIZE(u8500_hsit_resource),
+ .resource = u8500_hsit_resource,
+};
+
+struct platform_device u8500_hsir_device = {
+ .name = "stm-hsi",
+ .id = 1,
+ .dev = {
+ .platform_data = &hsir_platform_data,
+ },
+ .num_resources = ARRAY_SIZE(u8500_hsir_resource),
+ .resource = u8500_hsir_resource,
+};
diff --git a/arch/arm/mach-ux500/include/mach/ab8500-dev.h b/arch/arm/mach-ux500/include/mach/ab8500-dev.h
new file mode 100755
index 00000000000..8b4d69f5d2e
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/ab8500-dev.h
@@ -0,0 +1,30 @@
+/*
+ * ab8500-dev.c - simple userspace interface to ab8500
+ *
+ * Copyright (C) 2009 STEricsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+/*
+ * struct ab8500dev_data - AB8500 /dev structure
+ * @block: bank address
+ * @addr: register address
+ * @data: data to be read/write to
+ *
+ * This supports access to AB8500 chip using normal userspace I/O calls.
+ */
+struct ab8500dev_data {
+ unsigned char block;
+ unsigned char addr;
+ unsigned char data;
+ unsigned char int_no;
+ unsigned char sig_no;
+};
+
+#define AB8500_IOC_MAGIC 'S'
+#define AB8500_GET_REGISTER _IOWR(AB8500_IOC_MAGIC, 1, struct ab8500dev_data)
+#define AB8500_SET_REGISTER _IOW(AB8500_IOC_MAGIC, 2, struct ab8500dev_data)
+#define SET_INT_SIGNAL _IOW(AB8500_IOC_MAGIC, 3, struct ab8500dev_data)
diff --git a/arch/arm/mach-ux500/include/mach/ab8500.h b/arch/arm/mach-ux500/include/mach/ab8500.h
new file mode 100755
index 00000000000..9dc62278731
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/ab8500.h
@@ -0,0 +1,586 @@
+/*
+ * Copyright ST-Ericsson 2009.
+ *
+ * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
+ * Licensed under GPLv2.
+ */
+#ifndef _AB8500_H
+#define _AB8500_H
+
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <mach/hardware.h>
+#include <asm/dma.h>
+#include <mach/dma.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-stm.h>
+#include <mach/prcmu-fw-api.h>
+/*
+ * AB8500 bank addresses
+ */
+#define AB8500_SYS_CTRL1_BLOCK 0x1
+#define AB8500_SYS_CTRL2_BLOCK 0x2
+#define AB8500_REGU_CTRL1 0x3
+#define AB8500_REGU_CTRL2 0x4
+#define AB8500_USB 0x5
+#define AB8500_TVOUT 0x6
+#define AB8500_DBI 0x7
+#define AB8500_ECI_AV_ACC 0x8
+#define AB8500_RESERVED 0x9
+#define STw4550_GPADC 0xA
+#define AB8500_GPADC 0xA
+#define AB8500_CHARGER 0xB
+#define AB8500_GAS_GAUGE 0xC
+#define AB8500_AUDIO 0xD
+#define AB8500_INTERRUPT 0xE
+#define AB8500_RTC 0xF
+#define AB8500_MISC 0x10
+#define AB8500_DEBUG 0x12
+#define AB8500_PROD_TEST 0x13
+#define AB8500_OTP_EMUL 0x15
+
+/*
+ * System control 1 register offsets.
+ * Bank = 0x01
+ */
+#define AB8500_TURNON_STAT_REG 0x0100
+#define AB8500_RESET_STAT_REG 0x0101
+#define AB8500_PONKEY1_PRESS_STAT_REG 0x0102
+
+#define AB8500_FSM_STAT1_REG 0x0140
+#define AB8500_FSM_STAT2_REG 0x0141
+#define AB8500_SYSCLK_REQ_STAT_REG 0x0142
+#define AB8500_USB_STAT1_REG 0x0143
+#define AB8500_USB_STAT2_REG 0x0144
+#define AB8500_STATUS_SPARE1_REG 0x0145
+#define AB8500_STATUS_SPARE2_REG 0x0146
+
+#define AB8500_CTRL1_REG 0x0180
+#define AB8500_CTRL2_REG 0x0181
+
+/*
+ * System control 2 register offsets.
+ * bank = 0x02
+ */
+#define AB8500_CTRL3_REG 0x0200
+#define AB8500_CTRL3_RST_DENC_MASK 0x4
+#define AB8500_CTRL3_RST_DENC_SHIFT 2
+#define AB8500_CTRL3_RST_AUD_MASK 0x2
+#define AB8500_CTRL3_RST_AUD_SHIFT 1
+#define AB8500_MAIN_WDOG_CTRL_REG 0x0201
+#define AB8500_MAIN_WDOG_TIMER_REG 0x0202
+#define AB8500_LOW_BAT_REG 0x0203
+#define AB8500_BATT_OK_REG 0x0204
+#define AB8500_SYSCLK_TIMER_REG 0x0205
+#define AB8500_SMPSCLK_CTRL_REG 0x0206
+#define AB8500_SMPSCLK_SEL1_REG 0x0207
+#define AB8500_SMPSCLK_SEL2_REG 0x0208
+#define AB8500_SMPSCLK_SEL3_REG 0x0209
+#define AB8500_SYSULPCLK_CONF_REG 0x020A
+#define AB8500_SYSULPCLK_CTRL1_REG 0x020B
+#define AB8500_SYSCLK_CTRL_REG 0x020C
+#define AB8500_SYSCLK_REQ1_VALID_REG 0x020D
+#define AB8500_SYSCLK_REQ_VALID_REG 0x020E
+#define AB8500_SYSCTRL_SPARE_REG 0x020F
+#define AB8500_PAD_CONF_REG 0x0210
+
+/*
+ * Regu control1 register offsets (SPI)
+ * Bank = 0x03
+ */
+#define AB8500_REGU_SERIAL_CTRL1_REG 0x0300
+#define AB8500_REGU_SERIAL_CTRL2_REG 0x0301
+#define AB8500_REGU_SERIAL_CTRL3_REG 0x0302
+#define AB8500_REGU_REQ_CTRL1_REG 0x0303
+#define AB8500_REGU_REQ_CTRL2_REG 0x0304
+#define AB8500_REGU_REQ_CTRL3_REG 0x0305
+#define AB8500_REGU_REQ_CTRL4_REG 0x0306
+#define AB8500_REGU_SYSCLK_REQ1HP_VALID1_REG 0x0307
+#define AB8500_REGU_SYSCLK_REQ1HP_VALID2_REG 0x0308
+#define AB8500_REGU_HWHPREQ1_VALID1_REG 0x0309
+#define AB8500_REGU_HWHPREQ1_VALID2_REG 0x030A
+#define AB8500_REGU_HWHPREQ2_VALID1_REG 0x030B
+#define AB8500_REGU_HWHPREQ2_VALID2_REG 0x030C
+#define AB8500_REGU_SWHPREQ_VALID1_REG 0x030D
+#define AB8500_REGU_SWHPREQ_VALID2_REG 0x030E
+
+#define AB8500_REGU_SYSCLK_REQ1_VALID_REG 0x030F /* only for ED*/
+#define AB8500_REGU_SYSCLK_REQ2_VALID_REG 0x0310 /*only for ED*/
+
+#define AB8500_REGU_MISC1_REG 0x0380
+#define AB8500_REGU_OTGSUPPLY_CTRL_REG 0x0381
+#define AB8500_REGU_VUSB_CTRL_REG 0x0382 /* see reg manaul*/
+#define AB8500_REGU_VAUDIO_SUPPLY_REG 0x0383
+#define AB8500_REGU_CTRL1_SPARE_REG 0x0384
+
+ /*
+ * Regu control2 register offsets (SPI/APE I2C)
+ * Bank = 0x04
+ */
+#define AB8500_REGU_ARM_REGU1_REG 0x0400
+#define AB8500_REGU_ARM_REGU2_REG 0x0401
+#define AB8500_REGU_VAPE_REGU_REG 0x0402
+#define AB8500_REGU_VSMPS1_REGU_REG 0x0403
+#define AB8500_REGU_VSMPS2_REGU_REG 0x0404
+#define AB8500_REGU_VSMPS3_REGU_REG 0x0405
+#define AB8500_REGU_VPLLVANA_REGU_REG 0x0406
+#define AB8500_REGU_VREF_DDR_REG 0x0407
+#define AB8500_REGU_EXTSUPPLY_REGU_REG 0x0408
+#define AB8500_REGU_VAUX12_REGU_REG 0x0409
+#define AB8500_REGU_VAUX12_REGU_VAUX1_MASK 0x3
+#define AB8500_REGU_VAUX12_REGU_VAUX1_SHIFT 0
+#define AB8500_REGU_VAUX12_REGU_VAUX1_FORCE_HP 0x1
+#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A
+#define AB8500_REGU_VARM_SEL1_REG 0x040B
+#define AB8500_REGU_VARM_SEL2_REG 0x040C
+#define AB8500_REGU_VARM_SEL3_REG 0x040D
+#define AB8500_REGU_VAPE_SEL1_REG 0x040E
+#define AB8500_REGU_VAPE_SEL2_REG 0x040F
+#define AB8500_REGU_VAPE_SEL3_REG 0x0410
+#define AB8500_REGU_VBB_SEL2_REG 0x0412
+#define AB8500_REGU_VSMPS1_SEL1_REG 0x0413
+#define AB8500_REGU_VSMPS1_SEL2_REG 0x0414
+#define AB8500_REGU_VSMPS1_SEL3_REG 0x0415
+#define AB8500_REGU_VSMPS2_SEL1_REG 0x0417
+#define AB8500_REGU_VSMPS2_SEL2_REG 0x0418
+#define AB8500_REGU_VSMPS2_SEL3_REG 0x0419
+#define AB8500_REGU_VSMPS3_SEL1_REG 0x041B
+#define AB8500_REGU_VSMPS3_SEL2_REG 0x041C
+#define AB8500_REGU_VSMPS3_SEL3_REG 0x041D
+#define AB8500_REGU_VAUX1_SEL_REG 0x041F
+#define AB8500_REGU_VAUX1_SEL_MASK 0xf
+#define AB8500_REGU_VAUX1_SEL_SHIFT 0
+#define AB8500_REGU_VAUX1_SEL_1_5V 0x4
+#define AB8500_REGU_VAUX1_SEL_2_5V 0x8
+#define AB8500_REGU_VAUX2_SEL_REG 0x0420
+#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421
+#define AB8500_REGU_CTRL2_SPARE_REG 0x0422
+
+/*
+ * Regu control2 Vmod register offsets
+ */
+#define AB8500_REGU_VMOD_REGU_REG 0x0440
+#define AB8500_REGU_VMOD_SEL1_REG 0x0441
+#define AB8500_REGU_VMOD_SEL2_REG 0x0442
+#define AB8500_REGU_CTRL_DISCH_REG 0x0443
+#define AB8500_REGU_CTRL_DISCH2_REG 0x0444
+
+/*
+ * Sim control register offsets
+ * Bank:0x4
+ */
+#define AB8500_SIM_REG1_SGR1L_REG 0x0480
+#define AB8500_SIM_REG1_SGR1U_REG 0x0481
+#define AB8500_SIM_REG2_SCR1L_REG 0x0482
+#define AB8500_SIM_REG2_SCR1U_REG 0x0483
+#define AB8500_SIM_REG3_SCTRLRL_REG 0x0484
+#define AB8500_SIM_REG3_SCTRLRU_REG 0x0485
+#define AB8500_SIM_ISOUICCINT_SRC_REG 0x0486
+#define AB8500_SIM_ISOUICCINT_LATCH_REG 0x0487
+#define AB8500_SIM_ISOUICCINT_MASK_REG 0x0488
+#define AB8500_SIM_REG4_USBUICC_REG 0x0489
+#define AB8500_SIM_SDELAYSEL_REG 0x048A
+#define AB8500_SIM_USBUICC_CTRL 0x048B /* bit 3 only for ED */
+
+/*
+ * USB/ULPI register offsets
+ * Bank : 0x5
+ */
+#define AB8500_USB_LINE_STAT_REG 0x0580
+#define AB8500_USB_LINE_CTRL1_REG 0x0581
+#define AB8500_USB_LINE_CTRL2_REG 0x0582
+#define AB8500_USB_LINE_CTRL3_REG 0x0583
+#define AB8500_USB_LINE_CTRL4_REG 0x0584
+#define AB8500_USB_LINE_CTRL5_REG 0x0585
+#define AB8500_USB_OTG_CTRL_REG 0x0587
+#define AB8500_USB_OTG_STAT_REG 0x0588
+#define AB8500_USB_OTG_STAT_REG 0x0588
+#define AB8500_USB_CTRL_SPARE_REG 0x0589
+#define AB8500_USB_PHY_CTRL_REG 0x058A /*only in Cut1.0*/
+
+/*
+ * TVOUT / CTRL register offsets
+ * Bank : 0x06
+ */
+#define AB8500_DENC_CONF0_REG 0x0600
+#define AB8500_DENC_CONF1_REG 0x0601
+#define AB8500_DENC_CONF2_REG 0x0602
+#define AB8500_DENC_CONF3_REG 0x0603
+#define AB8500_DENC_CONF4_REG 0x0604
+#define AB8500_DENC_CONF5_REG 0x0605
+#define AB8500_DENC_CONF6_REG 0x0606
+#define AB8500_DENC_CONF6_SOFT_RST_MASK 0x80
+#define AB8500_DENC_CONF6_SOFT_RST_SHIFT 7
+#define AB8500_DENC_CONF6_SOFT_RST_OFF 0x0
+#define AB8500_DENC_CONF6_SOFT_RST_ON 0x1
+#define AB8500_DENC_CONF7_REG 0x0607
+#define AB8500_DENC_CONF8_REG 0x0608
+#define AB8500_TVOUT_CTRL_REG 0x0680
+#define AB8500_TVOUT_CTRL2_REG 0x0681
+/*
+ * DBI register offsets
+ * Bank : 0x07
+ */
+#define AB8500_DBI_REG1_REG 0x0700
+#define AB8500_DBI_REG2_REG 0x0701
+/*
+ * ECI regsiter offsets
+ * Bank : 0x08
+ */
+#define AB8500_ECI_CTRL_REG 0x0800
+#define AB8500_ECI_HOOKLEVEL_REG 0x0801
+#define AB8500_ECI_DATAOUT_REG 0x0802
+#define AB8500_ECI_DATAIN_REG 0x0803
+/*
+ * AV Connector register offsets
+ * Bank : 0x08
+ */
+#define AB8500_AV_CONN_REG 0x0840
+/*
+ * Accessory detection register offsets
+ * Bank : 0x08
+ */
+#define AB8500_ACC_DET_DB1_REG 0x0880
+#define AB8500_ACC_DET_DB2_REG 0x0881
+/*
+ * GPADC register offsets
+ * Bank : 0x0A
+ */
+#define AB8500_GPADC_CTRL1_REG 0x0A00
+#define AB8500_GPADC_CTRL2_REG 0x0A01
+#define AB8500_GPADC_CTRL3_REG 0x0A02
+#define AB8500_GPADC_AUTO_TIMER_REG 0x0A03
+#define AB8500_GPADC_STAT_REG 0x0A04
+#define AB8500_GPADC_MANDATAL_REG 0x0A05
+#define AB8500_GPADC_MANDATAH_REG 0x0A06
+#define AB8500_GPADC_AUTODATAL_REG 0x0A07
+#define AB8500_GPADC_AUTODATAH_REG 0x0A08
+#define AB8500_GPADC_MUX_CTRL_REG 0x0A09
+/*
+ * Charger / status register offfsets
+ * Bank : 0x0B
+ */
+#define AB8500_CH_STATUS1_REG 0x0B00
+#define AB8500_CH_STATUS2_REG 0x0B01
+#define AB8500_CH_USBCH_STAT1_REG 0x0B02
+#define AB8500_CH_USBCH_STAT2_REG 0x0B03
+#define AB8500_CH_FSM_STAT_REG 0x0B04
+#define AB8500_CH_STAT_REG 0x0B05
+/*
+ * Charger / control register offfsets
+ * Bank : 0x0B
+ */
+#define AB8500_CH_VOLT_LVL_REG 0x0B40
+#define AB8500_CH_VOLT_LVL_MAX_REG 0x0B41 /*Only in Cut1.0*/
+#define AB8500_CH_OPT_CRNTLVL_REG 0x0B42 /*Only in Cut1.0*/
+#define AB8500_CH_OPT_CRNTLVL_MAX_REG 0x0B43 /*Only in Cut1.0*/
+#define AB8500_CH_WD_TIMER_REG 0x0B44 /*Only in Cut1.0*/
+#define AB8500_CH_WD_CTRL_REG 0x0B45 /*Only in Cut1.0*/
+#define AB8500_CHARG_WD_CTRL 0x0B51
+#define AB8500_LED_INDICATOR_PWM_CTRL 0x0B53
+#define AB8500_LED_INDICATOR_PWM_DUTY 0x0B54
+#define AB8500_BATT_OVV 0x0B55
+/*
+ * Charger / main control register offfsets
+ * Bank : 0x0B
+ */
+#define AB8500_MCH_CTRL1 0x0B80
+#define AB8500_MCH_CTRL2 0x0B81
+#define AB8500_MCH_IPT_CURLVL_REG 0x0B82
+#define AB8500_CH_WD_REG 0x0B83
+/*
+ * Charger / USB control register offsets
+ * Bank : 0x0B
+ */
+#define AB8500_USBCH_CTRL1_REG 0x0BC0
+#define AB8500_USBCH_CTRL2_REG 0x0BC1
+#define AB8500_USBCH_IPT_CRNTLVL_REG 0x0BC2
+/*
+ * Gas Gauge register offsets
+ * Bank : 0x0C
+ */
+#define AB8500_GASG_CC_CTRL_REG 0x0C00
+#define AB8500_GASG_CC_ACCU1_REG 0x0C01
+#define AB8500_GASG_CC_ACCU2_REG 0x0C02
+#define AB8500_GASG_CC_ACCU3_REG 0x0C03
+#define AB8500_GASG_CC_ACCU4_REG 0x0C04
+#define AB8500_GASG_CC_SMPL_CNTRL_REG 0x0C05
+#define AB8500_GASG_CC_SMPL_CNTRH_REG 0x0C06
+#define AB8500_GASG_CC_SMPL_CNVL_REG 0x0C07
+#define AB8500_GASG_CC_SMPL_CNVH_REG 0x0C08
+#define AB8500_GASG_CC_CNTR_AVGOFF_REG 0x0C09
+#define AB8500_GASG_CC_OFFSET_REG 0x0C0A
+/*
+ * Audio
+ * Bank : 0x0D
+ * Not a part of this file. Should be part of Audio codec driver
+ */
+
+/*
+ * Interrupt register offsets
+ * Bank : 0x0E
+ */
+#define AB8500_IT_SOURCE1_REG 0x0E00
+#define AB8500_IT_SOURCE2_REG 0x0E01
+#define AB8500_IT_SOURCE3_REG 0x0E02
+#define AB8500_IT_SOURCE4_REG 0x0E03
+#define AB8500_IT_SOURCE5_REG 0x0E04
+#define AB8500_IT_SOURCE6_REG 0x0E05
+
+/* available only in 1.0 */
+#define AB8500_IT_SOURCE7_REG 0x0E06
+#define AB8500_IT_SOURCE8_REG 0x0E07
+#define AB8500_IT_SOURCE19_REG 0x0E12
+
+#define AB8500_IT_SOURCE20_REG 0x0E13
+#define AB8500_IT_SOURCE21_REG 0x0E14
+#define AB8500_IT_SOURCE22_REG 0x0E15
+#define AB8500_IT_SOURCE23_REG 0x0E16
+#define AB8500_IT_SOURCE24_REG 0x0E17
+
+/*
+ * latch registers
+ */
+#define AB8500_IT_LATCH1_REG 0x0E20
+#define AB8500_IT_LATCH2_REG 0x0E21
+#define AB8500_IT_LATCH3_REG 0x0E22
+#define AB8500_IT_LATCH4_REG 0x0E23
+#define AB8500_IT_LATCH5_REG 0x0E24
+#define AB8500_IT_LATCH6_REG 0x0E25
+
+/* available only in 1.0 */
+#define AB8500_IT_LATCH7_REG 0x0E26
+#define AB8500_IT_LATCH8_REG 0x0E27
+#define AB8500_IT_LATCH9_REG 0x0E28
+#define AB8500_IT_LATCH10_REG 0x0E29
+#define AB8500_IT_LATCH19_REG 0x0E32
+
+#define AB8500_IT_LATCH20_REG 0x0E33
+#define AB8500_IT_LATCH21_REG 0x0E34
+#define AB8500_IT_LATCH22_REG 0x0E35
+#define AB8500_IT_LATCH23_REG 0x0E36
+#define AB8500_IT_LATCH24_REG 0x0E37
+
+/*
+ * mask registers
+ */
+
+#define AB8500_IT_MASK1_REG 0x0E40
+#define AB8500_IT_MASK2_REG 0x0E41
+#define AB8500_IT_MASK3_REG 0x0E42
+#define AB8500_IT_MASK4_REG 0x0E43
+#define AB8500_IT_MASK5_REG 0x0E44
+#define AB8500_IT_MASK6_REG 0x0E45
+
+
+/* available only in 1.0 */
+#define AB8500_IT_MASK7_REG 0x0E46
+#define AB8500_IT_MASK8_REG 0x0E47
+#define AB8500_IT_MASK9_REG 0x0E48
+#define AB8500_IT_MASK10_REG 0x0E49
+#define AB8500_IT_MASK11_REG 0x0E4A
+#define AB8500_IT_MASK12_REG 0x0E4B
+#define AB8500_IT_MASK13_REG 0x0E4C
+#define AB8500_IT_MASK14_REG 0x0E4D
+#define AB8500_IT_MASK15_REG 0x0E4E
+#define AB8500_IT_MASK16_REG 0x0E4F
+#define AB8500_IT_MASK17_REG 0x0E50
+#define AB8500_IT_MASK18_REG 0x0E51
+#define AB8500_IT_MASK19_REG 0x0E52
+
+#define AB8500_IT_MASK20_REG 0x0E53
+#define AB8500_IT_MASK21_REG 0x0E54
+#define AB8500_IT_MASK22_REG 0x0E55
+#define AB8500_IT_MASK23_REG 0x0E56
+#define AB8500_IT_MASK24_REG 0x0E57
+
+/*
+ * RTC bank register offsets
+ * Bank : 0xF
+ */
+#define AB8500_RTC_SWITCHOFF_STAT_REG 0x0F00
+#define AB8500_RTC_CC_CONF_REG 0x0F01
+#define AB8500_RTC_READ_REQ_REG 0x0F02
+#define AB8500_RTC_WATCH_TSECMID_REG 0x0F03
+#define AB8500_RTC_WATCH_TSECHI_REG 0x0F04
+#define AB8500_RTC_WATCH_TMIN_LOW_REG 0x0F05
+#define AB8500_RTC_WATCH_TMIN_MID_REG 0x0F06
+#define AB8500_RTC_WATCH_TMIN_HI_REG 0x0F07
+#define AB8500_RTC_ALRM_MIN_LOW_REG 0x0F08
+#define AB8500_RTC_ALRM_MIN_MID_REG 0x0F09
+#define AB8500_RTC_ALRM_MIN_HI_REG 0x0F0A
+#define AB8500_RTC_STAT_REG 0x0F0B
+#define AB8500_RTC_BKUP_CHG_REG 0x0F0C
+#define AB8500_RTC_FORCE_BKUP_REG 0x0F0D
+#define AB8500_RTC_CALIB_REG 0x0F0E
+#define AB8500_RTC_SWITCH_STAT_REG 0x0F0F
+
+/*
+ * Misc block GPIO register offsets - Not for ED
+ * Bank : 0x10
+ */
+/* available only in 1.0 */
+#define AB8500_GPIO_SEL1_REG 0x01000
+#define AB8500_GPIO_SEL2_REG 0x01001
+#define AB8500_GPIO_SEL3_REG 0x01002
+#define AB8500_GPIO_SEL4_REG 0x01003
+#define AB8500_GPIO_SEL5_REG 0x01004
+#define AB8500_GPIO_SEL6_REG 0x01005
+#define AB8500_GPIO_DIR1_REG 0x01010
+#define AB8500_GPIO_DIR2_REG 0x01011
+#define AB8500_GPIO_DIR3_REG 0x01012
+#define AB8500_GPIO_DIR4_REG 0x01013
+#define AB8500_GPIO_DIR5_REG 0x01014
+#define AB8500_GPIO_DIR6_REG 0x01015
+
+#define AB8500_GPIO_OUT1_REG 0x01020
+#define AB8500_GPIO_OUT2_REG 0x01021
+#define AB8500_GPIO_OUT3_REG 0x01022
+#define AB8500_GPIO_OUT4_REG 0x01023
+#define AB8500_GPIO_OUT5_REG 0x01024
+#define AB8500_GPIO_OUT6_REG 0x01025
+
+#define AB8500_GPIO_PUD1_REG 0x01030
+#define AB8500_GPIO_PUD2_REG 0x01031
+#define AB8500_GPIO_PUD3_REG 0x01032
+#define AB8500_GPIO_PUD4_REG 0x01033
+#define AB8500_GPIO_PUD5_REG 0x01034
+#define AB8500_GPIO_PUD6_REG 0x01035
+
+#define AB8500_GPIO_IN1_REG 0x01040
+#define AB8500_GPIO_IN2_REG 0x01041
+#define AB8500_GPIO_IN3_REG 0x01042
+#define AB8500_GPIO_IN4_REG 0x01043
+#define AB8500_GPIO_IN5_REG 0x01044
+#define AB8500_GPIO_IN6_REG 0x01045
+#define AB8500_GPIO_ALT_FUNC 0x01050
+
+/*
+ * PWM Out generators
+ * Bank: 0x10
+ */
+#define AB8500_PWM_OUT_CTRL1_REG 0x1060
+#define AB8500_PWM_OUT_CTRL2_REG 0x1061
+#define AB8500_PWM_OUT_CTRL3_REG 0x1062
+#define AB8500_PWM_OUT_CTRL4_REG 0x1063
+#define AB8500_PWM_OUT_CTRL5_REG 0x1064
+#define AB8500_PWM_OUT_CTRL6_REG 0x1065
+#define AB8500_PWM_OUT_CTRL7_REG 0x1066
+
+#define AB8500_I2C_PAD_CTRL_REG 0x1067
+#define AB8500_REV_REG 0x1080
+
+/*
+ * Misc, Debug Test Configuration register
+ * Bank : 0x11
+ */
+#define AB8500_DEBUG_TESTMODE_REG 0x01100
+
+/* only in 1.0 */
+#define AB8500_I2C_TRIG1_ADR_REG 0x1101
+#define AB8500_I2C_TRIG1_ID_REG 0x1102
+#define AB8500_I2C_TRIG2_ADR_REG 0x1103
+#define AB8500_I2C_TRIG3_ID_REG 0x1104
+#define AB8500_I2C_NOACCESS_SUP_REG 0x1105
+
+/* Offsets in TurnOnstatus register
+ */
+
+#define AB8500_MAX_INT 192
+#define AB8500_MAX_FUTURE_USE 105
+
+#define AB8500_MAX_INT_SOURCE 11
+#define AB8500_MAX_INT_LATCH 13
+#define AB8500_MAX_INT_MASK 21
+
+/**
+ * struct ab8500_device - Stw4500 device structure
+ * @cs_en: pointer chip select enable
+ * @cs_dis: pointer to chip select disable
+ *
+ * Stw4500 Internal device structure
+ */
+struct ab8500_device {
+ void (*cs_en) (void);
+ void (*cs_dis) (void);
+ u16 ssp_controller;
+};
+
+/*struct t_ab8500_context;*/
+
+/**
+ * struct client_callbacks - Client callbacks
+ * @callback: callback handler
+ * @data: private data for the handler
+ *
+ * Stw4500 maintains a internal data structure for the registered
+ * callback
+ */
+struct client_callbacks {
+ void (*callback)(void *data);
+ void *data;
+};
+
+/**
+ * struct client_signals - Client signals
+ * @pid: pid of process
+ * @signal: signal to be delivered
+ *
+ * AB8500 maintains an internal data structure for the delivery of
+ * required signals to registered processes
+ */
+struct client_signals {
+ struct pid *pid;
+ u32 signal;
+};
+
+/**
+ * struct ab8500 - AB8500 Internal data structure
+ * @ab8500_master: Pointer to the spi_master
+ * @ab8500_board_info: Pointer to the board information structure
+ * @ab8500_spi: Pointer to the spi_device strcture
+ * @spi_transfer: Pointer SPI data transfer structure spi_transfer
+ * @spi_message: SPI message pointer of type spi_message
+ * @ab8500_device: AB8500 internal data structure
+ * @ssp_wrbuf: SSP write data buffer of size 4 bytes
+ * @ssp_rdbuf: SSP read data buffer of size 4 bytes
+ * @work: work queue scheduled in the interrupt handler
+ * @c_callback: Array of client's callback handler
+ * @ab8500_cfg_lock: synchronization primitive to protect the data
+ * @ab8500_sem: synchronization primitive used in the non-interrupt context
+ * @irq: interrupt number of ab8500
+ * @revision: revision number of ab8500 silicon
+ *
+ * Supports only SPI interface. The device can also be accessed
+ * through I2C in the successive version of U8500.
+ */
+struct ab8500 {
+ struct spi_master *ab8500_master;
+ struct spi_board_info *ab8500_board_info;
+ struct spi_device *ab8500_spi;
+ struct spi_transfer *ab8500_xfer;
+ struct spi_message *ab8500_msg;
+ struct ab8500_device *board;
+ u32 ssp_wrbuf[4];
+ u32 ssp_rdbuf[4];
+ struct client_callbacks c_callback[184];
+ struct client_signals c_signals[184];
+ struct work_struct work;
+ spinlock_t ab8500_cfg_lock;
+ spinlock_t ab8500_cfgsig_lock;
+ struct semaphore ab8500_sem;
+ unsigned char irq;
+ unsigned char revision;
+};
+
+int ab8500_get_version(void);
+int ab8500_write(u8 block, u32 adr, u8 data);
+int ab8500_read(u8 block, u32 adr);
+int ab8500_set_callback_handler(int int_no, void *callback_handler, void *data);
+int ab8500_remove_callback_handler(int int_no);
+void ab8500_int_mask(int int_no);
+void ab8500_int_unmask(int int_no);
+int ab8500_set_signal_handler(int int_no, int sig_no);
+int ab8500_remove_signal_handler(int int_no);
+#endif /* AB8500_H_ */
diff --git a/arch/arm/mach-ux500/include/mach/ab8500_codec.h b/arch/arm/mach-ux500/include/mach/ab8500_codec.h
new file mode 100755
index 00000000000..b10f28b1a1d
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/ab8500_codec.h
@@ -0,0 +1,435 @@
+/*****************************************************************************/
+/**
+* © ST-Ericsson, 2009 - All rights reserved
+* Reproduction and Communication of this document is strictly prohibited
+* unless specifically authorized in writing by ST-Ericsson
+*
+* \brief Public header file for AB8500 Codec
+* \author ST-Ericsson
+*/
+/*****************************************************************************/
+
+#ifndef _AB8500_CODEC_H_
+#define _AB8500_CODEC_H_
+
+/*---------------------------------------------------------------------
+ * Includes
+ *--------------------------------------------------------------------*/
+#include "hcl_defs.h"
+#include "debug.h"
+
+/*---------------------------------------------------------------------
+ * Define
+ *--------------------------------------------------------------------*/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+typedef enum
+{
+ AB8500_CODEC_OK,
+ AB8500_CODEC_ERROR,
+ AB8500_CODEC_UNSUPPORTED_FEATURE,
+ AB8500_CODEC_INVALID_PARAMETER,
+ AB8500_CODEC_CONFIG_NOT_COHERENT,
+ AB8500_CODEC_TRANSACTION_FAILED
+} t_ab8500_codec_error;
+
+
+typedef enum
+{
+ AB8500_CODEC_DIRECTION_IN,
+ AB8500_CODEC_DIRECTION_OUT,
+ AB8500_CODEC_DIRECTION_INOUT
+} t_ab8500_codec_direction;
+
+typedef enum
+{
+ AB8500_CODEC_MASTER_MODE_DISABLE,
+ AB8500_CODEC_MASTER_MODE_ENABLE
+}t_ab8500_codec_master_mode;
+
+typedef enum
+{
+ AB8500_CODEC_AUDIO_INTERFACE_0,
+ AB8500_CODEC_AUDIO_INTERFACE_1
+}t_ab8500_codec_audio_interface;
+
+
+typedef enum
+{
+ AB8500_CODEC_MODE_HIFI,
+ AB8500_CODEC_MODE_VOICE,
+ AB8500_CODEC_MODE_MANUAL_SETTING
+} t_ab8500_codec_mode;
+
+typedef enum
+{
+ AB8500_CODEC_DEST_HEADSET,
+ AB8500_CODEC_DEST_EARPIECE,
+ AB8500_CODEC_DEST_HANDSFREE,
+ AB8500_CODEC_DEST_VIBRATOR_L,
+ AB8500_CODEC_DEST_VIBRATOR_R,
+ AB8500_CODEC_DEST_ALL
+} t_ab8500_codec_dest;
+
+typedef enum
+{
+ AB8500_CODEC_SRC_LINEIN,
+ AB8500_CODEC_SRC_MICROPHONE_1A,
+ AB8500_CODEC_SRC_MICROPHONE_1B,
+ AB8500_CODEC_SRC_MICROPHONE_2,
+ AB8500_CODEC_SRC_D_MICROPHONE_1,
+ AB8500_CODEC_SRC_D_MICROPHONE_2,
+ AB8500_CODEC_SRC_D_MICROPHONE_3,
+ AB8500_CODEC_SRC_D_MICROPHONE_4,
+ AB8500_CODEC_SRC_D_MICROPHONE_5,
+ AB8500_CODEC_SRC_D_MICROPHONE_6,
+ AB8500_CODEC_SRC_ALL
+} t_ab8500_codec_src;
+
+typedef enum
+{
+ AB8500_CODEC_SLOT0,
+ AB8500_CODEC_SLOT1,
+ AB8500_CODEC_SLOT2,
+ AB8500_CODEC_SLOT3,
+ AB8500_CODEC_SLOT4,
+ AB8500_CODEC_SLOT5,
+ AB8500_CODEC_SLOT6,
+ AB8500_CODEC_SLOT7,
+ AB8500_CODEC_SLOT8,
+ AB8500_CODEC_SLOT9,
+ AB8500_CODEC_SLOT10,
+ AB8500_CODEC_SLOT11,
+ AB8500_CODEC_SLOT12,
+ AB8500_CODEC_SLOT13,
+ AB8500_CODEC_SLOT14,
+ AB8500_CODEC_SLOT15,
+ AB8500_CODEC_SLOT16,
+ AB8500_CODEC_SLOT17,
+ AB8500_CODEC_SLOT18,
+ AB8500_CODEC_SLOT19,
+ AB8500_CODEC_SLOT20,
+ AB8500_CODEC_SLOT21,
+ AB8500_CODEC_SLOT22,
+ AB8500_CODEC_SLOT23,
+ AB8500_CODEC_SLOT24,
+ AB8500_CODEC_SLOT25,
+ AB8500_CODEC_SLOT26,
+ AB8500_CODEC_SLOT27,
+ AB8500_CODEC_SLOT28,
+ AB8500_CODEC_SLOT29,
+ AB8500_CODEC_SLOT30,
+ AB8500_CODEC_SLOT31,
+ AB8500_CODEC_SLOT_UNDEFINED
+} t_ab8500_codec_slot;
+
+
+
+typedef enum
+{
+ AB8500_CODEC_DA_CHANNEL_NUMBER_1,
+ AB8500_CODEC_DA_CHANNEL_NUMBER_2,
+ AB8500_CODEC_DA_CHANNEL_NUMBER_3,
+ AB8500_CODEC_DA_CHANNEL_NUMBER_4,
+ AB8500_CODEC_DA_CHANNEL_NUMBER_5,
+ AB8500_CODEC_DA_CHANNEL_NUMBER_6,
+ AB8500_CODEC_DA_CHANNEL_NUMBER_UNDEFINED
+}t_ab8500_codec_da_channel_number;
+
+
+typedef enum
+{
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT1,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT2,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT3,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT4,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT5,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT6,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT7,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT8,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_ZEROS,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_IS_TRISTATE = 15,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_UNDEFINED
+} t_ab8500_codec_cr31_to_cr46_ad_data_allocation;
+
+
+typedef enum
+{
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT00,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT01,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT02,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT03,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT04,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT05,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT06,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT07,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT08,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT09,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT10,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT11,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT12,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT13,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT14,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT15,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT16,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT17,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT18,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT19,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT20,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT21,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT22,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT23,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT24,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT25,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT26,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT27,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT28,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT29,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT30,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT31,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT_UNDEFINED
+} t_ab8500_codec_cr51_to_cr56_sltoda;
+
+typedef enum
+{
+ AB8500_CODEC_SRC_STATE_DISABLE,
+ AB8500_CODEC_SRC_STATE_ENABLE
+}t_ab8500_codec_src_state;
+
+typedef enum
+{
+ AB8500_CODEC_DEST_STATE_DISABLE,
+ AB8500_CODEC_DEST_STATE_ENABLE
+}t_ab8500_codec_dest_state;
+
+/* CR104 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr104_bfifoint;
+
+
+/* CR105 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr105_bfifotx;
+
+/* CR106 - 6:4 */
+typedef enum
+{
+ AB8500_CODEC_CR106_BFIFOFSEXT_NO_EXTRA_CLK,
+ AB8500_CODEC_CR106_BFIFOFSEXT_1SLOT_EXTRA_CLK,
+ AB8500_CODEC_CR106_BFIFOFSEXT_2SLOT_EXTRA_CLK,
+ AB8500_CODEC_CR106_BFIFOFSEXT_3SLOT_EXTRA_CLK,
+ AB8500_CODEC_CR106_BFIFOFSEXT_4SLOT_EXTRA_CLK,
+ AB8500_CODEC_CR106_BFIFOFSEXT_5SLOT_EXTRA_CLK,
+ AB8500_CODEC_CR106_BFIFOFSEXT_6SLOT_EXTRA_CLK
+} t_ab8500_codec_cr106_bfifofsext;
+
+/* CR106 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR106_BFIFOMSK_AD_DATA0_UNMASKED,
+ AB8500_CODEC_CR106_BFIFOMSK_AD_DATA0_MASKED
+} t_ab8500_codec_cr106_bfifomsk;
+
+/* CR106 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR106_BFIFOMSTR_SLAVE_MODE,
+ AB8500_CODEC_CR106_BFIFOMSTR_MASTER_MODE
+} t_ab8500_codec_cr106_bfifomstr;
+
+/* CR106 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR106_BFIFOSTRT_STOPPED,
+ AB8500_CODEC_CR106_BFIFOSTRT_RUNNING
+} t_ab8500_codec_cr106_bfifostrt;
+
+
+/* CR107 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr107_bfifosampnr;
+
+
+/* CR108 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr108_bfifowakeup;
+
+
+typedef struct
+{
+ t_ab8500_codec_cr104_bfifoint cr104_bfifoint;
+ t_ab8500_codec_cr105_bfifotx cr105_bfifotx;
+ t_ab8500_codec_cr106_bfifofsext cr106_bfifofsext;
+ t_ab8500_codec_cr106_bfifomsk cr106_bfifomsk;
+ t_ab8500_codec_cr106_bfifomstr cr106_bfifomstr;
+ t_ab8500_codec_cr106_bfifostrt cr106_bfifostrt;
+ t_ab8500_codec_cr107_bfifosampnr cr107_bfifosampnr;
+ t_ab8500_codec_cr108_bfifowakeup cr108_bfifowakeup;
+} t_ab8500_codec_burst_fifo_config;
+
+/************************************************************/
+/*---------------------------------------------------------------------
+ * Exported APIs
+ *--------------------------------------------------------------------*/
+/* Initialization */
+t_ab8500_codec_error AB8500_CODEC_Init(IN t_uint8 slave_address_of_codec);
+t_ab8500_codec_error AB8500_CODEC_Reset(void);
+
+/* Audio Codec basic configuration */
+t_ab8500_codec_error AB8500_CODEC_SetModeAndDirection(IN t_ab8500_codec_direction ab8500_codec_direction, IN t_ab8500_codec_mode ab8500_codec_mode_in, IN t_ab8500_codec_mode ab8500_codec_mode_out);
+t_ab8500_codec_error AB8500_CODEC_SelectInput(IN t_ab8500_codec_src ab8500_codec_src);
+t_ab8500_codec_error AB8500_CODEC_SelectOutput(IN t_ab8500_codec_dest ab8500_codec_dest);
+
+/* Burst FIFO configuration */
+t_ab8500_codec_error AB8500_CODEC_ConfigureBurstFifo(IN t_ab8500_codec_burst_fifo_config const *const p_burst_fifo_config);
+t_ab8500_codec_error AB8500_CODEC_EnableBurstFifo(void);
+t_ab8500_codec_error AB8500_CODEC_DisableBurstFifo(void);
+
+/* Audio Codec Master mode configuration */
+t_ab8500_codec_error AB8500_CODEC_SetMasterMode(IN t_ab8500_codec_master_mode mode);
+
+/* APIs to be implemented by user */
+t_ab8500_codec_error AB8500_CODEC_Write(IN t_uint8 register_offset, IN t_uint8 count, IN t_uint8 *p_data);
+t_ab8500_codec_error AB8500_CODEC_Read(IN t_uint8 register_offset, IN t_uint8 count, IN t_uint8 *p_dummy_data, IN t_uint8 *p_data);
+
+/* Volume Management */
+t_ab8500_codec_error AB8500_CODEC_SetSrcVolume(IN t_ab8500_codec_src src_device, IN t_uint8 in_left_volume, IN t_uint8 in_right_volume);
+t_ab8500_codec_error AB8500_CODEC_SetDestVolume(IN t_ab8500_codec_dest dest_device, IN t_uint8 out_left_volume, IN t_uint8 out_right_volume);
+
+/* Power management */
+t_ab8500_codec_error AB8500_CODEC_PowerDown(void);
+t_ab8500_codec_error AB8500_CODEC_PowerUp(void);
+
+/* Interface Management */
+t_ab8500_codec_error AB8500_CODEC_SelectInterface(IN t_ab8500_codec_audio_interface audio_interface);
+t_ab8500_codec_error AB8500_CODEC_GetInterface(OUT t_ab8500_codec_audio_interface *p_audio_interface);
+
+/* Slot Allocation */
+t_ab8500_codec_error AB8500_CODEC_ADSlotAllocation(IN t_ab8500_codec_slot ad_slot, IN t_ab8500_codec_cr31_to_cr46_ad_data_allocation value);
+t_ab8500_codec_error AB8500_CODEC_DASlotAllocation(IN t_ab8500_codec_da_channel_number channel_number, IN t_ab8500_codec_cr51_to_cr56_sltoda slot);
+
+/* Loopback Management */
+t_ab8500_codec_error AB8500_CODEC_SetAnalogLoopback(IN t_uint8 out_left_volume, IN t_uint8 out_right_volume);
+t_ab8500_codec_error AB8500_CODEC_RemoveAnalogLoopback(void);
+
+/* Bypass Management */
+t_ab8500_codec_error AB8500_CODEC_EnableBypassMode(void);
+t_ab8500_codec_error AB8500_CODEC_DisableBypassMode(void);
+
+/* Power Control Management */
+t_ab8500_codec_error AB8500_CODEC_SrcPowerControl(IN t_ab8500_codec_src src_device, t_ab8500_codec_src_state state);
+t_ab8500_codec_error AB8500_CODEC_DestPowerControl(IN t_ab8500_codec_dest dest_device, t_ab8500_codec_dest_state state);
+
+/* Version Management */
+t_ab8500_codec_error AB8500_CODEC_GetVersion(OUT t_version *p_version);
+
+#if 0
+/* Debug management */
+t_ab8500_codec_error AB8500_CODEC_SetDbgLevel(IN t_dbg_level dbg_level);
+t_ab8500_codec_error AB8500_CODEC_GetDbgLevel(OUT t_dbg_level *p_dbg_level);
+#endif
+
+/*
+** following is added by $kardad$
+*/
+
+/* duplicate copy of enum from msp.h */
+/* for MSPConfiguration.in_clock_freq parameter to select msp clock freq */
+typedef enum {
+ CODEC_MSP_INPUT_FREQ_1MHZ = 1024,
+ CODEC_MSP_INPUT_FREQ_2MHZ = 2048,
+ CODEC_MSP_INPUT_FREQ_3MHZ = 3072,
+ CODEC_MSP_INPUT_FREQ_4MHZ = 4096,
+ CODEC_MSP_INPUT_FREQ_5MHZ = 5760,
+ CODEC_MSP_INPUT_FREQ_6MHZ = 6144,
+ CODEC_MSP_INPUT_FREQ_8MHZ = 8192,
+ CODEC_MSP_INPUT_FREQ_11MHZ = 11264,
+ CODEC_MSP_INPUT_FREQ_12MHZ = 12288,
+ CODEC_MSP_INPUT_FREQ_16MHZ = 16384,
+ CODEC_MSP_INPUT_FREQ_22MHZ = 22579,
+ CODEC_MSP_INPUT_FREQ_24MHZ = 24576,
+ CODEC_MSP_INPUT_FREQ_48MHZ = 49152
+} codec_msp_in_clock_freq_type;
+
+/* msp clock source internal/external for srg_clock_sel */
+typedef enum {
+ CODEC_MSP_APB_CLOCK = 0,
+ CODEC_MSP_SCK_CLOCK = 2,
+ CODEC_MSP_SCK_SYNC_CLOCK = 3
+} codec_msp_srg_clock_sel_type;
+
+/* Sample rate supported by Codec */
+
+typedef enum {
+ CODEC_FREQUENCY_DONT_CHANGE = -100,
+ CODEC_SAMPLING_FREQ_RESET = -1,
+ CODEC_SAMPLING_FREQ_MINLIMIT = 7,
+ CODEC_SAMPLING_FREQ_8KHZ = 8, /*default */
+ CODEC_SAMPLING_FREQ_11KHZ = 11,
+ CODEC_SAMPLING_FREQ_12KHZ = 12,
+ CODEC_SAMPLING_FREQ_16KHZ = 16,
+ CODEC_SAMPLING_FREQ_22KHZ = 22,
+ CODEC_SAMPLING_FREQ_24KHZ = 24,
+ CODEC_SAMPLING_FREQ_32KHZ = 32,
+ CODEC_SAMPLING_FREQ_44KHZ = 44,
+ CODEC_SAMPLING_FREQ_48KHZ = 48,
+ CODEC_SAMPLING_FREQ_64KHZ = 64, /*the frequencies below this line are not supported in stw5094A */
+ CODEC_SAMPLING_FREQ_88KHZ = 88,
+ CODEC_SAMPLING_FREQ_96KHZ = 96,
+ CODEC_SAMPLING_FREQ_128KHZ = 128,
+ CODEC_SAMPLING_FREQ_176KHZ = 176,
+ CODEC_SAMPLING_FREQ_192KHZ = 192,
+ CODEC_SAMPLING_FREQ_MAXLIMIT = 193
+} t_codec_sample_frequency;
+
+#define RESET -1
+#define DEFAULT -100
+/***********************************************************/
+/*
+** following stuff is added to compile code without debug print support $kardad$
+*/
+
+#define DBGEXIT(cr)
+#define DBGEXIT0(cr)
+#define DBGEXIT1(cr,ch,p1)
+#define DBGEXIT2(cr,ch,p1,p2)
+#define DBGEXIT3(cr,ch,p1,p2,p3)
+#define DBGEXIT4(cr,ch,p1,p2,p3,p4)
+#define DBGEXIT5(cr,ch,p1,p2,p3,p4,p5)
+#define DBGEXIT6(cr,ch,p1,p2,p3,p4,p5,p6)
+
+#define DBGENTER()
+#define DBGENTER0()
+#define DBGENTER1(ch,p1)
+#define DBGENTER2(ch,p1,p2)
+#define DBGENTER3(ch,p1,p2,p3)
+#define DBGENTER4(ch,p1,p2,p3,p4)
+#define DBGENTER5(ch,p1,p2,p3,p4,p5)
+#define DBGENTER6(ch,p1,p2,p3,p4,p5,p6)
+
+#define DBGPRINT(dbg_level,dbg_string)
+#define DBGPRINTHEX(dbg_level,dbg_string,uint32)
+#define DBGPRINTDEC(dbg_level,dbg_string,uint32)
+/***********************************************************/
+
+/*---------------------------------------------------------------------
+ * PRIVATE APIs
+ *--------------------------------------------------------------------*/
+PRIVATE t_ab8500_codec_error ab8500_codec_ADSlotAllocationSwitch1(IN t_ab8500_codec_slot ad_slot, IN t_ab8500_codec_cr31_to_cr46_ad_data_allocation value);
+PRIVATE t_ab8500_codec_error ab8500_codec_ADSlotAllocationSwitch2(IN t_ab8500_codec_slot ad_slot, IN t_ab8500_codec_cr31_to_cr46_ad_data_allocation value);
+PRIVATE t_ab8500_codec_error ab8500_codec_ADSlotAllocationSwitch3(IN t_ab8500_codec_slot ad_slot, IN t_ab8500_codec_cr31_to_cr46_ad_data_allocation value);
+PRIVATE t_ab8500_codec_error ab8500_codec_ADSlotAllocationSwitch4(IN t_ab8500_codec_slot ad_slot, IN t_ab8500_codec_cr31_to_cr46_ad_data_allocation value);
+PRIVATE t_ab8500_codec_error ab8500_codec_SrcPowerControlSwitch1(IN t_ab8500_codec_src src_device, t_ab8500_codec_src_state state);
+PRIVATE t_ab8500_codec_error ab8500_codec_SrcPowerControlSwitch2(IN t_ab8500_codec_src src_device, t_ab8500_codec_src_state state);
+PRIVATE t_ab8500_codec_error ab8500_codec_SetModeAndDirectionUpdateCR(void);
+PRIVATE t_ab8500_codec_error ab8500_codec_SetSrcVolumeUpdateCR(void);
+PRIVATE t_ab8500_codec_error ab8500_codec_SetDestVolumeUpdateCR(void);
+PRIVATE t_ab8500_codec_error ab8500_codec_ProgramDirectionIN(void);
+PRIVATE t_ab8500_codec_error ab8500_codec_ProgramDirectionOUT(void);
+PRIVATE t_ab8500_codec_error ab8500_codec_DestPowerControlUpdateCR(void);
+
+#ifdef __cplusplus
+} /* allow C++ to use these headers*/
+#endif /* __cplusplus*/
+#endif /* _AB8500_CODEC_H_*/
+
+/* End of file ab8500_codec.h*/
+
diff --git a/arch/arm/mach-ux500/include/mach/ab8500_codec_p.h b/arch/arm/mach-ux500/include/mach/ab8500_codec_p.h
new file mode 100755
index 00000000000..415d5f73dc0
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/ab8500_codec_p.h
@@ -0,0 +1,3371 @@
+/*****************************************************************************/
+/**
+* © ST-Ericsson, 2009 - All rights reserved
+* Reproduction and Communication of this document is strictly prohibited
+* unless specifically authorized in writing by ST-Ericsson
+ *
+* \brief Private Header file for AB8500 CODEC
+* \author ST-Ericsson
+ */
+/*****************************************************************************/
+
+#ifndef _AB8500_CODECP_H_
+#define _AB8500_CODECP_H_
+
+/*----------------------------------------------------------------------------
+ * Includes
+ *---------------------------------------------------------------------------*/
+#include "hcl_defs.h"
+
+#define AB8500_CODEC_HCL_VERSION_ID 2
+#define AB8500_CODEC_HCL_MAJOR_ID 0
+#define AB8500_CODEC_HCL_MINOR_ID 0
+
+#define AB8500_CODEC_MASK_ONE_BIT 0x1UL
+#define AB8500_CODEC_MASK_TWO_BITS 0x3UL
+#define AB8500_CODEC_MASK_THREE_BITS 0x7UL
+#define AB8500_CODEC_MASK_FOUR_BITS 0xFUL
+#define AB8500_CODEC_MASK_FIVE_BITS 0x1FUL
+#define AB8500_CODEC_MASK_SIX_BITS 0x3FUL
+#define AB8500_CODEC_MASK_SEVEN_BITS 0x7FUL
+#define AB8500_CODEC_MASK_EIGHT_BITS 0xFFUL
+
+#define AB8500_CODEC_WRITE_BITS(reg, val, bit_nb, pos) (reg) = ((t_uint8) ((((reg) & (~(bit_nb << pos))) | (((val) & bit_nb) << pos))))
+
+
+#define AB8500_CODEC_BLOCK 0x0D
+
+#define AB8500_CODEC_MASK_TWO_MS_BITS 0xC0UL
+#define AB8500_CODEC_MASK_SIX_LS_BITS 0x3FUL
+
+/* Genepi AudioCodec Control Registers */
+
+#define AB8500_CODEC_CR0 0x00
+#define AB8500_CODEC_CR1 0x01
+#define AB8500_CODEC_CR2 0x02
+#define AB8500_CODEC_CR3 0x03
+#define AB8500_CODEC_CR4 0x04
+#define AB8500_CODEC_CR5 0x05
+#define AB8500_CODEC_CR6 0x06
+#define AB8500_CODEC_CR7 0x07
+#define AB8500_CODEC_CR8 0x08
+#define AB8500_CODEC_CR9 0x09
+#define AB8500_CODEC_CR10 0x0A
+#define AB8500_CODEC_CR11 0x0B
+#define AB8500_CODEC_CR12 0x0C
+#define AB8500_CODEC_CR13 0x0D
+#define AB8500_CODEC_CR14 0x0E
+#define AB8500_CODEC_CR15 0x0F
+#define AB8500_CODEC_CR16 0x10
+#define AB8500_CODEC_CR17 0x11
+#define AB8500_CODEC_CR18 0x12
+#define AB8500_CODEC_CR19 0x13
+#define AB8500_CODEC_CR20 0x14
+#define AB8500_CODEC_CR21 0x15
+#define AB8500_CODEC_CR22 0x16
+#define AB8500_CODEC_CR23 0x17
+#define AB8500_CODEC_CR24 0x18
+#define AB8500_CODEC_CR25 0x19
+#define AB8500_CODEC_CR26 0x1A
+#define AB8500_CODEC_CR27 0x1B
+#define AB8500_CODEC_CR28 0x1C
+#define AB8500_CODEC_CR29 0x1D
+#define AB8500_CODEC_CR30 0x1E
+#define AB8500_CODEC_CR31 0x1F
+#define AB8500_CODEC_CR32 0x20
+#define AB8500_CODEC_CR33 0x21
+#define AB8500_CODEC_CR34 0x22
+#define AB8500_CODEC_CR35 0x23
+#define AB8500_CODEC_CR36 0x24
+#define AB8500_CODEC_CR37 0x25
+#define AB8500_CODEC_CR38 0x26
+#define AB8500_CODEC_CR39 0x27
+#define AB8500_CODEC_CR40 0x28
+#define AB8500_CODEC_CR41 0x29
+#define AB8500_CODEC_CR42 0x2A
+#define AB8500_CODEC_CR43 0x2B
+#define AB8500_CODEC_CR44 0x2C
+#define AB8500_CODEC_CR45 0x2D
+#define AB8500_CODEC_CR46 0x2E
+#define AB8500_CODEC_CR47 0x2F
+#define AB8500_CODEC_CR48 0x30
+#define AB8500_CODEC_CR49 0x31
+#define AB8500_CODEC_CR50 0x32
+#define AB8500_CODEC_CR51 0x33
+#define AB8500_CODEC_CR52 0x34
+#define AB8500_CODEC_CR53 0x35
+#define AB8500_CODEC_CR54 0x36
+#define AB8500_CODEC_CR55 0x37
+#define AB8500_CODEC_CR56 0x38
+#define AB8500_CODEC_CR57 0x39
+#define AB8500_CODEC_CR58 0x3A
+#define AB8500_CODEC_CR59 0x3B
+#define AB8500_CODEC_CR60 0x3C
+#define AB8500_CODEC_CR61 0x3D
+#define AB8500_CODEC_CR62 0x3E
+#define AB8500_CODEC_CR63 0x3F
+#define AB8500_CODEC_CR64 0x40
+#define AB8500_CODEC_CR65 0x41
+#define AB8500_CODEC_CR66 0x42
+#define AB8500_CODEC_CR67 0x43
+#define AB8500_CODEC_CR68 0x44
+#define AB8500_CODEC_CR69 0x45
+#define AB8500_CODEC_CR70 0x46
+#define AB8500_CODEC_CR71 0x47
+#define AB8500_CODEC_CR72 0x48
+#define AB8500_CODEC_CR73 0x49
+#define AB8500_CODEC_CR74 0x4A
+#define AB8500_CODEC_CR75 0x4B
+#define AB8500_CODEC_CR76 0x4C
+#define AB8500_CODEC_CR77 0x4D
+#define AB8500_CODEC_CR78 0x4E
+#define AB8500_CODEC_CR79 0x4F
+#define AB8500_CODEC_CR80 0x50
+#define AB8500_CODEC_CR81 0x51
+#define AB8500_CODEC_CR82 0x52
+#define AB8500_CODEC_CR83 0x53
+#define AB8500_CODEC_CR84 0x54
+#define AB8500_CODEC_CR85 0x55
+#define AB8500_CODEC_CR86 0x56
+#define AB8500_CODEC_CR87 0x57
+#define AB8500_CODEC_CR88 0x58
+#define AB8500_CODEC_CR89 0x59
+#define AB8500_CODEC_CR90 0x5A
+#define AB8500_CODEC_CR91 0x5B
+#define AB8500_CODEC_CR92 0x5C
+#define AB8500_CODEC_CR93 0x5D
+#define AB8500_CODEC_CR94 0x5E
+#define AB8500_CODEC_CR95 0x5F
+#define AB8500_CODEC_CR96 0x60
+#define AB8500_CODEC_CR97 0x61
+#define AB8500_CODEC_CR98 0x62
+#define AB8500_CODEC_CR99 0x63
+#define AB8500_CODEC_CR100 0x64
+#define AB8500_CODEC_CR101 0x65
+#define AB8500_CODEC_CR102 0x66
+#define AB8500_CODEC_CR103 0x67
+#define AB8500_CODEC_CR104 0x68
+#define AB8500_CODEC_CR105 0x69
+#define AB8500_CODEC_CR106 0x6A
+#define AB8500_CODEC_CR107 0x6B
+#define AB8500_CODEC_CR108 0x6C
+#define AB8500_CODEC_CR109 0x6D
+
+
+/* CR0-CR0x0000 */
+#define AB8500_CODEC_CR0_POWERUP 7
+#define AB8500_CODEC_CR0_ENAANA 3
+
+/* CR1-CR0x0001 */
+#define AB8500_CODEC_CR1_SWRESET 7
+
+/* CR2-CR0x0002 */
+#define AB8500_CODEC_CR2_ENAD1 7
+#define AB8500_CODEC_CR2_ENAD2 6
+#define AB8500_CODEC_CR2_ENAD3 5
+#define AB8500_CODEC_CR2_ENAD4 4
+#define AB8500_CODEC_CR2_ENAD5 3
+#define AB8500_CODEC_CR2_ENAD6 2
+
+/* CR3-CR0x0003 */
+#define AB8500_CODEC_CR3_ENDA1 7
+#define AB8500_CODEC_CR3_ENDA2 6
+#define AB8500_CODEC_CR3_ENDA3 5
+#define AB8500_CODEC_CR3_ENDA4 4
+#define AB8500_CODEC_CR3_ENDA5 3
+#define AB8500_CODEC_CR3_ENDA6 2
+
+/* CR4-CR0x0004 */
+#define AB8500_CODEC_CR4_LOWPOWHS 7
+#define AB8500_CODEC_CR4_LOWPOWDACHS 5
+#define AB8500_CODEC_CR4_LOWPOWEAR 4
+#define AB8500_CODEC_CR4_EAR_SEL_CM 2
+#define AB8500_CODEC_CR4_HS_HP_DIS 1
+#define AB8500_CODEC_CR4_EAR_HP_DIS 0
+
+/* CR5-CR0x0005 */
+#define AB8500_CODEC_CR5_ENMIC1 7
+#define AB8500_CODEC_CR5_ENMIC2 6
+#define AB8500_CODEC_CR5_ENLINL 5
+#define AB8500_CODEC_CR5_ENLINR 4
+#define AB8500_CODEC_CR5_MUTMIC1 3
+#define AB8500_CODEC_CR5_MUTMIC2 2
+#define AB8500_CODEC_CR5_MUTELINL 1
+#define AB8500_CODEC_CR5_MUTELINR 0
+
+/* CR6-CR0x0006 */
+#define AB8500_CODEC_CR6_ENDMIC1 7
+#define AB8500_CODEC_CR6_ENDMIC2 6
+#define AB8500_CODEC_CR6_ENDMIC3 5
+#define AB8500_CODEC_CR6_ENDMIC4 4
+#define AB8500_CODEC_CR6_ENDMIC5 3
+#define AB8500_CODEC_CR6_ENDMIC6 2
+
+/* CR7-CR0x0007 */
+#define AB8500_CODEC_CR7_MIC1SEL 7
+#define AB8500_CODEC_CR7_LINRSEL 6
+#define AB8500_CODEC_CR7_ENDRVHSL 5
+#define AB8500_CODEC_CR7_ENDRVHSR 4
+#define AB8500_CODEC_CR7_ENADCMIC 2
+#define AB8500_CODEC_CR7_ENADCLINL 1
+#define AB8500_CODEC_CR7_ENADCLINR 0
+
+/* CR8-CR0x0008 */
+#define AB8500_CODEC_CR8_CP_DIS_PLDWN 7
+#define AB8500_CODEC_CR8_ENEAR 6
+#define AB8500_CODEC_CR8_ENHSL 5
+#define AB8500_CODEC_CR8_ENHSR 4
+#define AB8500_CODEC_CR8_ENHFL 3
+#define AB8500_CODEC_CR8_ENHFR 2
+#define AB8500_CODEC_CR8_ENVIBL 1
+#define AB8500_CODEC_CR8_ENVIBR 0
+
+/* CR9-CR0x0009 */
+#define AB8500_CODEC_CR9_ENADACEAR 6
+#define AB8500_CODEC_CR9_ENADACHSL 5
+#define AB8500_CODEC_CR9_ENADACHSR 4
+#define AB8500_CODEC_CR9_ENADACHFL 3
+#define AB8500_CODEC_CR9_ENADACHFR 2
+#define AB8500_CODEC_CR9_ENADACVIBL 1
+#define AB8500_CODEC_CR9_ENADACVIBR 0
+
+/* CR10-CR0x000A */
+#define AB8500_CODEC_CR10_MUTEEAR 6
+#define AB8500_CODEC_CR10_MUTEHSL 5
+#define AB8500_CODEC_CR10_MUTEHSR 4
+#define AB8500_CODEC_CR10_MUTEHFL 3
+#define AB8500_CODEC_CR10_MUTEHFR 2
+#define AB8500_CODEC_CR10_MUTEVIBL 1
+#define AB8500_CODEC_CR10_MUTEVIBR 0
+
+/* CR11-CR0x000B */
+#define AB8500_CODEC_CR11_ENSHORTPWD 7
+#define AB8500_CODEC_CR11_EARSHORTDIS 6
+#define AB8500_CODEC_CR11_HSLSHORTDIS 5
+#define AB8500_CODEC_CR11_HSRSHORTDIS 4
+#define AB8500_CODEC_CR11_HFLSHORTDIS 3
+#define AB8500_CODEC_CR11_HFRSHORTDIS 2
+#define AB8500_CODEC_CR11_VIBLSHORTDIS 1
+#define AB8500_CODEC_CR11_VIBRSHORTDIS 0
+
+/* CR12-CR0x000C */
+#define AB8500_CODEC_CR12_ENCPHS 7
+#define AB8500_CODEC_CR12_HSAUTOTIME 4
+#define AB8500_CODEC_CR12_HSAUTOENSEL 1
+#define AB8500_CODEC_CR12_HSAUTOEN 0
+
+/* CR13-CR0x000D */
+#define AB8500_CODEC_CR13_ENVDET_HTHRESH 4
+#define AB8500_CODEC_CR13_ENVDET_LTHRESH 0
+
+/* CR14-CR0x000E */
+#define AB8500_CODEC_CR14_SMPSLVEN 7
+#define AB8500_CODEC_CR14_ENVDETSMPSEN 6
+#define AB8500_CODEC_CR14_CPLVEN 5
+#define AB8500_CODEC_CR14_ENVDETCPEN 4
+#define AB8500_CODEC_CR14_ENVDET_TIME 0
+
+/* CR15-CR0x000F */
+#define AB8500_CODEC_CR15_PWMTOVIBL 7
+#define AB8500_CODEC_CR15_PWMTOVIBR 6
+#define AB8500_CODEC_CR15_PWMLCTRL 5
+#define AB8500_CODEC_CR15_PWMRCTRL 4
+#define AB8500_CODEC_CR15_PWMNLCTRL 3
+#define AB8500_CODEC_CR15_PWMPLCTRL 2
+#define AB8500_CODEC_CR15_PWMNRCTRL 1
+#define AB8500_CODEC_CR15_PWMPRCTRL 0
+
+/* CR16-CR0x0010 */
+#define AB8500_CODEC_CR16_PWMNLPOL 7
+#define AB8500_CODEC_CR16_PWMNLDUTYCYCLE 0
+
+/* CR17-CR0x0011 */
+#define AB8500_CODEC_CR17_PWMPLPOL 7
+#define AB8500_CODEC_CR17_PWMLPDUTYCYCLE 0
+
+/* CR18-CR0x0012 */
+#define AB8500_CODEC_CR18_PWMNRPOL 7
+#define AB8500_CODEC_CR18_PWMNRDUTYCYCLE 0
+
+/* CR19-CR0x0013 */
+#define AB8500_CODEC_CR19_PWMPRPOL 7
+#define AB8500_CODEC_CR19_PWMRPDUTYCYCLE 0
+
+/* CR20-CR0x0014 */
+#define AB8500_CODEC_CR20_EN_SE_MIC1 7
+#define AB8500_CODEC_CR20_MIC1_GAIN 0
+
+/* CR21-CR0x0015 */
+#define AB8500_CODEC_CR21_EN_SE_MIC2 7
+#define AB8500_CODEC_CR21_MIC2_GAIN 0
+
+/* CR22-CR0x0016 */
+#define AB8500_CODEC_CR22_HSL_GAIN 5
+#define AB8500_CODEC_CR22_LINL_GAIN 0
+
+/* CR23-CR0x0017 */
+#define AB8500_CODEC_CR23_HSR_GAIN 5
+#define AB8500_CODEC_CR23_LINR_GAIN 0
+
+/* CR24-CR0x0018 */
+#define AB8500_CODEC_CR24_LINTOHSL_GAIN 0
+
+/* CR25-CR0x0019 */
+#define AB8500_CODEC_CR25_LINTOHSR_GAIN 0
+
+/* CR26-CR0x001A */
+#define AB8500_CODEC_CR26_AD1NH 7
+#define AB8500_CODEC_CR26_AD2NH 6
+#define AB8500_CODEC_CR26_AD3NH 5
+#define AB8500_CODEC_CR26_AD4NH 4
+#define AB8500_CODEC_CR26_AD1_VOICE 3
+#define AB8500_CODEC_CR26_AD2_VOICE 2
+#define AB8500_CODEC_CR26_AD3_VOICE 1
+#define AB8500_CODEC_CR26_AD4_VOICE 0
+
+/* CR27-CR0x001B */
+#define AB8500_CODEC_CR27_EN_MASTGEN 7
+#define AB8500_CODEC_CR27_IF1_BITCLK_OSR 5
+#define AB8500_CODEC_CR27_ENFS_BITCLK1 4
+#define AB8500_CODEC_CR27_IF0_BITCLK_OSR 1
+#define AB8500_CODEC_CR27_ENFS_BITCLK0 0
+
+/* CR28-CR0x001C */
+#define AB8500_CODEC_CR28_FSYNC0P 6
+#define AB8500_CODEC_CR28_BITCLK0P 5
+#define AB8500_CODEC_CR28_IF0DEL 4
+#define AB8500_CODEC_CR28_IF0FORMAT 2
+#define AB8500_CODEC_CR28_IF0WL 0
+
+/* CR29-CR0x001D */
+#define AB8500_CODEC_CR29_IF0DATOIF1AD 7
+#define AB8500_CODEC_CR29_IF0CKTOIF1CK 6
+#define AB8500_CODEC_CR29_IF1MASTER 5
+#define AB8500_CODEC_CR29_IF1DATOIF0AD 3
+#define AB8500_CODEC_CR29_IF1CKTOIF0CK 2
+#define AB8500_CODEC_CR29_IF0MASTER 1
+#define AB8500_CODEC_CR29_IF0BFIFOEN 0
+
+/* CR30-CR0x001E */
+#define AB8500_CODEC_CR30_FSYNC1P 6
+#define AB8500_CODEC_CR30_BITCLK1P 5
+#define AB8500_CODEC_CR30_IF1DEL 4
+#define AB8500_CODEC_CR30_IF1FORMAT 2
+#define AB8500_CODEC_CR30_IF1WL 0
+
+/* CR31-CR0x001F */
+#define AB8500_CODEC_CR31_ADOTOSLOT1 4
+#define AB8500_CODEC_CR31_ADOTOSLOT0 0
+
+/* CR32-CR0x0020 */
+#define AB8500_CODEC_CR32_ADOTOSLOT3 4
+#define AB8500_CODEC_CR32_ADOTOSLOT2 0
+
+/* CR33-CR0x0021 */
+#define AB8500_CODEC_CR33_ADOTOSLOT5 4
+#define AB8500_CODEC_CR33_ADOTOSLOT4 0
+
+/* CR34-CR0x0022 */
+#define AB8500_CODEC_CR34_ADOTOSLOT7 4
+#define AB8500_CODEC_CR34_ADOTOSLOT6 0
+
+/* CR35-CR0x0023 */
+#define AB8500_CODEC_CR35_ADOTOSLOT9 4
+#define AB8500_CODEC_CR35_ADOTOSLOT8 0
+
+/* CR36-CR0x0024 */
+#define AB8500_CODEC_CR36_ADOTOSLOT11 4
+#define AB8500_CODEC_CR36_ADOTOSLOT10 0
+
+/* CR37-CR0x0025 */
+#define AB8500_CODEC_CR37_ADOTOSLOT13 4
+#define AB8500_CODEC_CR37_ADOTOSLOT12 0
+
+/* CR38-CR0x0026 */
+#define AB8500_CODEC_CR38_ADOTOSLOT15 4
+#define AB8500_CODEC_CR38_ADOTOSLOT14 0
+
+/* CR39-CR0x0027 */
+#define AB8500_CODEC_CR39_ADOTOSLOT17 4
+#define AB8500_CODEC_CR39_ADOTOSLOT16 0
+
+/* CR40-CR0x0028 */
+#define AB8500_CODEC_CR40_ADOTOSLOT19 4
+#define AB8500_CODEC_CR40_ADOTOSLOT18 0
+
+/* CR41-CR0x0029 */
+#define AB8500_CODEC_CR41_ADOTOSLOT21 4
+#define AB8500_CODEC_CR41_ADOTOSLOT20 0
+
+/* CR42-CR0x002A */
+#define AB8500_CODEC_CR42_ADOTOSLOT23 4
+#define AB8500_CODEC_CR42_ADOTOSLOT22 0
+
+/* CR43-CR0x002B */
+#define AB8500_CODEC_CR43_ADOTOSLOT25 4
+#define AB8500_CODEC_CR43_ADOTOSLOT24 0
+
+/* CR44-CR0x002C */
+#define AB8500_CODEC_CR44_ADOTOSLOT27 4
+#define AB8500_CODEC_CR44_ADOTOSLOT26 0
+
+/* CR45-CR0x002D */
+#define AB8500_CODEC_CR45_ADOTOSLOT29 4
+#define AB8500_CODEC_CR45_ADOTOSLOT28 0
+
+/* CR46-CR0x002E */
+#define AB8500_CODEC_CR46_ADOTOSLOT31 4
+#define AB8500_CODEC_CR46_ADOTOSLOT30 0
+
+/* CR47-CR0x002F */
+#define AB8500_CODEC_CR47_HIZ_SL7 7
+#define AB8500_CODEC_CR47_HIZ_SL6 6
+#define AB8500_CODEC_CR47_HIZ_SL5 5
+#define AB8500_CODEC_CR47_HIZ_SL4 4
+#define AB8500_CODEC_CR47_HIZ_SL3 3
+#define AB8500_CODEC_CR47_HIZ_SL2 2
+#define AB8500_CODEC_CR47_HIZ_SL1 1
+#define AB8500_CODEC_CR47_HIZ_SL0 0
+
+/* CR48-CR0x0030 */
+#define AB8500_CODEC_CR48_HIZ_SL15 7
+#define AB8500_CODEC_CR48_HIZ_SL14 6
+#define AB8500_CODEC_CR48_HIZ_SL13 5
+#define AB8500_CODEC_CR48_HIZ_SL12 4
+#define AB8500_CODEC_CR48_HIZ_SL11 3
+#define AB8500_CODEC_CR48_HIZ_SL10 2
+#define AB8500_CODEC_CR48_HIZ_SL9 1
+#define AB8500_CODEC_CR48_HIZ_SL8 0
+
+/* CR49-CR0x0031 */
+#define AB8500_CODEC_CR49_HIZ_SL23 7
+#define AB8500_CODEC_CR49_HIZ_SL22 6
+#define AB8500_CODEC_CR49_HIZ_SL21 5
+#define AB8500_CODEC_CR49_HIZ_SL20 4
+#define AB8500_CODEC_CR49_HIZ_SL19 3
+#define AB8500_CODEC_CR49_HIZ_SL18 2
+#define AB8500_CODEC_CR49_HIZ_SL17 1
+#define AB8500_CODEC_CR49_HIZ_SL16 0
+
+/* CR50-CR0x0032 */
+#define AB8500_CODEC_CR50_HIZ_SL31 7
+#define AB8500_CODEC_CR50_HIZ_SL30 6
+#define AB8500_CODEC_CR50_HIZ_SL29 5
+#define AB8500_CODEC_CR50_HIZ_SL28 4
+#define AB8500_CODEC_CR50_HIZ_SL27 3
+#define AB8500_CODEC_CR50_HIZ_SL26 2
+#define AB8500_CODEC_CR50_HIZ_SL25 1
+#define AB8500_CODEC_CR50_HIZ_SL24 0
+
+/* CR51-CR0x0033 */
+#define AB8500_CODEC_CR51_DA12_VOICE 7
+#define AB8500_CODEC_CR51_SLDAI1TOSLADO1 5
+#define AB8500_CODEC_CR51_SLTODA1 0
+
+/* CR52-CR0x0034 */
+#define AB8500_CODEC_CR52_SLDAI1TOSLADO2 5
+#define AB8500_CODEC_CR52_SLTODA2 0
+
+/* CR53-CR0x0035 */
+#define AB8500_CODEC_CR53_DA34_VOICE 7
+#define AB8500_CODEC_CR53_SLDAI1TOSLADO3 5
+#define AB8500_CODEC_CR53_SLTODA3 0
+
+/* CR54-CR0x0036 */
+#define AB8500_CODEC_CR54_SLDAI1TOSLADO4 5
+#define AB8500_CODEC_CR54_SLTODA4 0
+
+/* CR55-CR0x0037 */
+#define AB8500_CODEC_CR55_DA56_VOICE 7
+#define AB8500_CODEC_CR55_SLDAI1TOSLADO5 5
+#define AB8500_CODEC_CR55_SLTODA5 0
+
+/* CR56-CR0x0038 */
+#define AB8500_CODEC_CR56_SLDAI1TOSLADO6 5
+#define AB8500_CODEC_CR56_SLTODA6 0
+
+/* CR57-CR0x0039 */
+#define AB8500_CODEC_CR57_BFIFULL_MSK 6
+#define AB8500_CODEC_CR57_BFIEMPT_MSK 5
+#define AB8500_CODEC_CR57_DACHAN_MSK 4
+#define AB8500_CODEC_CR57_GAIN_MSK 3
+#define AB8500_CODEC_CR57_DSPAD_MSK 2
+#define AB8500_CODEC_CR57_DSPDA_MSK 1
+#define AB8500_CODEC_CR57_STFIR_MSK 0
+
+/* CR58-CR0x003A */
+#define AB8500_CODEC_CR58_BFIFULL_EV 6
+#define AB8500_CODEC_CR58_BFIEMPT_EV 5
+#define AB8500_CODEC_CR58_DACHAN_EV 4
+#define AB8500_CODEC_CR58_GAIN_EV 3
+#define AB8500_CODEC_CR58_DSPAD_EV 2
+#define AB8500_CODEC_CR58_DSPDA_EV 1
+#define AB8500_CODEC_CR58_STFIR_EV 0
+
+/* CR59-CR0x003B */
+#define AB8500_CODEC_CR59_VSSREADY_MSK 7
+#define AB8500_CODEC_CR59_SHRTVIBL_MSK 6
+#define AB8500_CODEC_CR59_SHRTVIBR_MSK 5
+#define AB8500_CODEC_CR59_SHRTHFL_MSK 4
+#define AB8500_CODEC_CR59_SHRTHFR_MSK 3
+#define AB8500_CODEC_CR59_SHRTHSL_MSK 2
+#define AB8500_CODEC_CR59_SHRTHSR_MSK 1
+#define AB8500_CODEC_CR59_SHRTEAR_MSK 0
+
+/* CR60-CR0x003C */
+#define AB8500_CODEC_CR60_VSSREADY_EV 7
+#define AB8500_CODEC_CR60_SHRTVIBL_EV 6
+#define AB8500_CODEC_CR60_SHRTVIBR_EV 5
+#define AB8500_CODEC_CR60_SHRTHFL_EV 4
+#define AB8500_CODEC_CR60_SHRTHFR_EV 3
+#define AB8500_CODEC_CR60_SHRTHSL_EV 2
+#define AB8500_CODEC_CR60_SHRTHSR_EV 1
+#define AB8500_CODEC_CR60_SHRTEAR_EV 0
+
+/* CR61-CR0x003D */
+#define AB8500_CODEC_CR61_REVISION 2
+#define AB8500_CODEC_CR61_FADE_SPEED 0
+
+/* CR62-CR0x003E */
+#define AB8500_CODEC_CR62_DMIC1SINC3 5
+#define AB8500_CODEC_CR62_DMIC2SINC3 4
+#define AB8500_CODEC_CR62_DMIC3SINC3 3
+#define AB8500_CODEC_CR62_DMIC4SINC3 2
+#define AB8500_CODEC_CR62_DMIC5SINC3 1
+#define AB8500_CODEC_CR62_DMIC6SINC3 0
+
+/* CR63-CR0x003F */
+#define AB8500_CODEC_CR63_DATOHSLEN 7
+#define AB8500_CODEC_CR63_DATOHSREN 6
+#define AB8500_CODEC_CR63_AD1SEL 5
+#define AB8500_CODEC_CR63_AD2SEL 4
+#define AB8500_CODEC_CR63_AD3SEL 3
+#define AB8500_CODEC_CR63_AD5SEL 2
+#define AB8500_CODEC_CR63_AD6SEL 1
+#define AB8500_CODEC_CR63_ANCSEL 0
+
+/* CR64-CR0x0040 */
+#define AB8500_CODEC_CR64_DATOHFREN 7
+#define AB8500_CODEC_CR64_DATOHFLEN 6
+#define AB8500_CODEC_CR64_HFRSEL 5
+#define AB8500_CODEC_CR64_HFLSEL 4
+#define AB8500_CODEC_CR64_STFIR1SEL 2
+#define AB8500_CODEC_CR64_STFIR2SEL 0
+
+/* CR65-CR0x0041 */
+#define AB8500_CODEC_CR65_FADEDIS_AD1 6
+#define AB8500_CODEC_CR65_AD1GAIN 0
+
+/* CR66-CR0x0042 */
+#define AB8500_CODEC_CR66_FADEDIS_AD2 6
+#define AB8500_CODEC_CR66_AD2GAIN 0
+
+/* CR67-CR0x0043 */
+#define AB8500_CODEC_CR67_FADEDIS_AD3 6
+#define AB8500_CODEC_CR67_AD3GAIN 0
+
+/* CR68-CR0x0044 */
+#define AB8500_CODEC_CR68_FADEDIS_AD4 6
+#define AB8500_CODEC_CR68_AD4GAIN 0
+
+/* CR69-CR0x0045 */
+#define AB8500_CODEC_CR69_FADEDIS_AD5 6
+#define AB8500_CODEC_CR69_AD5GAIN 0
+
+/* CR70-CR0x0046 */
+#define AB8500_CODEC_CR70_FADEDIS_AD6 6
+#define AB8500_CODEC_CR70_AD6GAIN 0
+
+/* CR71-CR0x0047 */
+#define AB8500_CODEC_CR71_FADEDIS_DA1 6
+#define AB8500_CODEC_CR71_DA1GAIN 0
+
+/* CR72-CR0x0048 */
+#define AB8500_CODEC_CR72_FADEDIS_DA2 6
+#define AB8500_CODEC_CR72_DA2GAIN 0
+
+/* CR73-CR0x0049 */
+#define AB8500_CODEC_CR73_FADEDIS_DA3 6
+#define AB8500_CODEC_CR73_DA3GAIN 0
+
+/* CR74-CR0x004A */
+#define AB8500_CODEC_CR74_FADEDIS_DA4 6
+#define AB8500_CODEC_CR74_DA4GAIN 0
+
+/* CR75-CR0x004B */
+#define AB8500_CODEC_CR75_FADEDIS_DA5 6
+#define AB8500_CODEC_CR75_DA5GAIN 0
+
+/* CR76-CR0x004C */
+#define AB8500_CODEC_CR76_FADEDIS_DA6 6
+#define AB8500_CODEC_CR76_DA6GAIN 0
+
+/* CR77-CR0x004D */
+#define AB8500_CODEC_CR77_FADEDIS_AD1L 6
+#define AB8500_CODEC_CR77_AD1LBGAIN 0
+
+/* CR78-CR0x004E */
+#define AB8500_CODEC_CR78_FADEDIS_AD2L 6
+#define AB8500_CODEC_CR78_AD2LBGAIN 0
+
+/* CR79-CR0x004F */
+#define AB8500_CODEC_CR79_HSSINC1 7
+#define AB8500_CODEC_CR79_FADEDIS_HSL 4
+#define AB8500_CODEC_CR79_HSLDGAIN 0
+
+/* CR80-CR0x0050 */
+#define AB8500_CODEC_CR80_FADEDIS_HSR 4
+#define AB8500_CODEC_CR80_HSRDGAIN 0
+
+/* CR81-CR0x0051 */
+#define AB8500_CODEC_CR81_STFIR1GAIN 0
+
+/* CR82-CR0x0052 */
+#define AB8500_CODEC_CR82_STFIR2GAIN 0
+
+/* CR83-CR0x0053 */
+#define AB8500_CODEC_CR83_ENANC 2
+#define AB8500_CODEC_CR83_ANCIIRINIT 1
+#define AB8500_CODEC_CR83_ANCFIRUPDATE 0
+
+/* CR84-CR0x0054 */
+#define AB8500_CODEC_CR84_ANCINSHIFT 0
+
+/* CR85-CR0x0055 */
+#define AB8500_CODEC_CR85_ANCFIROUTSHIFT 0
+
+/* CR86-CR0x0056 */
+#define AB8500_CODEC_CR86_ANCSHIFTOUT 0
+
+/* CR87-CR0x0057 */
+#define AB8500_CODEC_CR87_ANCFIRCOEFF_MSB 0
+
+/* CR88-CR0x0058 */
+#define AB8500_CODEC_CR88_ANCFIRCOEFF_LSB 0
+
+/* CR89-CR0x0059 */
+#define AB8500_CODEC_CR89_ANCIIRCOEFF_MSB 0
+
+/* CR90-CR0x005A */
+#define AB8500_CODEC_CR90_ANCIIRCOEFF_LSB 0
+
+/* CR91-CR0x005B */
+#define AB8500_CODEC_CR91_ANCWARPDEL_MSB 0
+
+/* CR92-CR0x005C */
+#define AB8500_CODEC_CR92_ANCWARPDEL_LSB 0
+
+/* CR93-CR0x005D */
+#define AB8500_CODEC_CR93_ANCFIRPEAK_MSB 0
+
+/* CR94-CR0x005E */
+#define AB8500_CODEC_CR94_ANCFIRPEAK_LSB 0
+
+/* CR95-CR0x005F */
+#define AB8500_CODEC_CR95_ANCIIRPEAK_MSB 0
+
+/* CR96-CR0x0060 */
+#define AB8500_CODEC_CR96_ANCIIRPEAK_LSB 0
+
+/* CR97-CR0x0061 */
+#define AB8500_CODEC_CR97_STFIR_SET 7
+#define AB8500_CODEC_CR97_STFIR_ADDR 0
+
+/* CR98-CR0x0062 */
+#define AB8500_CODEC_CR98_STFIR_COEFF_MSB 0
+
+/* CR99-CR0x0063 */
+#define AB8500_CODEC_CR99_STFIR_COEFF_LSB 0
+
+/* CR100-CR0x0064 */
+#define AB8500_CODEC_CR100_ENSTFIRS 2
+#define AB8500_CODEC_CR100_STFIRSTOIF1 1
+#define AB8500_CODEC_CR100_STFIR_BUSY 0
+
+/* CR101-CR0x0065 */
+#define AB8500_CODEC_CR101_PARLHF 7
+#define AB8500_CODEC_CR101_PARLVIB 6
+#define AB8500_CODEC_CR101_CLASSDVIBLSWAPEN 3
+#define AB8500_CODEC_CR101_CLASSDVIBRSWAPEN 2
+#define AB8500_CODEC_CR101_CLASSDHFLSWAPEN 1
+#define AB8500_CODEC_CR101_CLASSDHFRSWAPEN 0
+
+/* CR102-CR0x0066 */
+#define AB8500_CODEC_CR102_CLASSD_FIRBYP 4
+#define AB8500_CODEC_CR102_CLASSD_HIGHVOLEN 0
+
+/* CR103-CR0x0067 */
+#define AB8500_CODEC_CR103_CLASSD_DITHERHPGAIN 4
+#define AB8500_CODEC_CR103_CLASSD_DITHERWGAIN 0
+
+/* CR104-CR0x0068 */
+#define AB8500_CODEC_CR104_BFIFOINT 0
+
+/* CR105-CR0x0069 */
+#define AB8500_CODEC_CR105_BFIFOTX 0
+
+/* CR106-CR0x006A */
+#define AB8500_CODEC_CR106_BFIFOFSEXT 4
+#define AB8500_CODEC_CR106_BFIFOMSK 2
+#define AB8500_CODEC_CR106_BFIFOMSTR 1
+#define AB8500_CODEC_CR106_BFIFOSTRT 0
+
+/* CR107-CR0x006B */
+#define AB8500_CODEC_CR107_BFIFOSAMPNR 0
+
+/* CR108-CR0x006C */
+#define AB8500_CODEC_CR108_BFIFOWAKEUP 0
+
+/* CR109-CR0x006D */
+#define AB8500_CODEC_CR109_BFIFOSAMPLES 0
+
+
+
+/* For SetVolume API*/
+#define AB8500_CODEC_MAX_VOLUME 100
+
+/* Analog MIC1 & MIC2 */
+#define AB8500_CODEC_MIC_VOLUME_MAX 31
+#define AB8500_CODEC_MIC_VOLUME_MEDIUM 15
+#define AB8500_CODEC_MIC_VOLUME_MIN 0
+
+/* Line-in */
+#define AB8500_CODEC_LINEIN_VOLUME_MAX 31
+#define AB8500_CODEC_LINEIN_VOLUME_MEDIUM 15
+#define AB8500_CODEC_LINEIN_VOLUME_MIN 0
+
+/* HeadSet */
+#define AB8500_CODEC_HEADSET_VOLUME_MAX 0
+#define AB8500_CODEC_HEADSET_VOLUME_MEDIUM 3
+#define AB8500_CODEC_HEADSET_VOLUME_MIN 7
+
+/* HeadSet Digital */
+#define AB8500_CODEC_HEADSET_D_VOLUME_MAX 0
+#define AB8500_CODEC_HEADSET_D_VOLUME_MEDIUM 7
+#define AB8500_CODEC_HEADSET_D_VOLUME_MIN 15
+
+/* Digital AD Path */
+#define AB8500_CODEC_AD_D_VOLUME_MAX 0
+#define AB8500_CODEC_AD_D_VOLUME_MEDIUM 31
+#define AB8500_CODEC_AD_D_VOLUME_MIN 63
+
+/* Digital DA Path */
+#define AB8500_CODEC_DA_D_VOLUME_MAX 0
+#define AB8500_CODEC_DA_D_VOLUME_MEDIUM 31
+#define AB8500_CODEC_DA_D_VOLUME_MIN 63
+
+/* EarPiece Digital */
+#define AB8500_CODEC_EARPIECE_D_VOLUME_MAX 0
+#define AB8500_CODEC_EARPIECE_D_VOLUME_MEDIUM 7
+#define AB8500_CODEC_EARPIECE_D_VOLUME_MIN 15
+
+/* AD1 loopback to HFL & HFR Digital */
+#define AB8500_CODEC_AD_LB_TO_HF_L_R_VOLUME_MAX 0
+#define AB8500_CODEC_AD_LB_TO_HF_L_R_VOLUME_MEDIUM 31
+#define AB8500_CODEC_AD_LB_TO_HF_L_R_VOLUME_MIN 63
+
+/* Line-in to HSL & HSR */
+#define AB8500_CODEC_LINEIN_TO_HS_L_R_VOLUME_MAX 0
+#define AB8500_CODEC_LINEIN_TO_HS_L_R_VOLUME_MEDIUM 9
+#define AB8500_CODEC_LINEIN_TO_HS_L_R_VOLUME_MIN 18
+#define AB8500_CODEC_LINEIN_TO_HS_L_R_LOOP_OPEN 19
+
+/* Vibrator */
+#define AB8500_CODEC_VIBRATOR_VOLUME_MAX 100
+#define AB8500_CODEC_VIBRATOR_VOLUME_MEDIUM 50
+#define AB8500_CODEC_VIBRATOR_VOLUME_MIN 0
+
+
+/* CR0 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR0_POWERUP_OFF,
+ AB8500_CODEC_CR0_POWERUP_ON
+} t_ab8500_codec_cr0_powerup;
+
+/* CR0 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR0_ENAANA_OFF,
+ AB8500_CODEC_CR0_ENAANA_ON
+} t_ab8500_codec_cr0_enaana;
+
+
+/* CR1 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR1_SWRESET_DISABLED,
+ AB8500_CODEC_CR1_SWRESET_ENABLED
+} t_ab8500_codec_cr1_swreset;
+
+
+/* CR2 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR2_ENAD1_DISABLED,
+ AB8500_CODEC_CR2_ENAD1_ENABLED
+} t_ab8500_codec_cr2_enad1;
+
+/* CR2 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR2_ENAD2_DISABLED,
+ AB8500_CODEC_CR2_ENAD2_ENABLED
+} t_ab8500_codec_cr2_enad2;
+
+/* CR2 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR2_ENAD3_DISABLED,
+ AB8500_CODEC_CR2_ENAD3_ENABLED
+} t_ab8500_codec_cr2_enad3;
+
+/* CR2 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR2_ENAD4_DISABLED,
+ AB8500_CODEC_CR2_ENAD4_ENABLED
+} t_ab8500_codec_cr2_enad4;
+
+/* CR2 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR2_ENAD5_DISABLED,
+ AB8500_CODEC_CR2_ENAD5_ENABLED
+} t_ab8500_codec_cr2_enad5;
+
+/* CR2 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR2_ENAD6_DISABLED,
+ AB8500_CODEC_CR2_ENAD6_ENABLED
+} t_ab8500_codec_cr2_enad6;
+
+
+/* CR3 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR3_ENDA1_DISABLED,
+ AB8500_CODEC_CR3_ENDA1_ENABLED
+} t_ab8500_codec_cr3_enda1;
+
+/* CR3 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR3_ENDA2_DISABLED,
+ AB8500_CODEC_CR3_ENDA2_ENABLED
+} t_ab8500_codec_cr3_enda2;
+
+/* CR3 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR3_ENDA3_DISABLED,
+ AB8500_CODEC_CR3_ENDA3_ENABLED
+} t_ab8500_codec_cr3_enda3;
+
+/* CR3 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR3_ENDA4_DISABLED,
+ AB8500_CODEC_CR3_ENDA4_ENABLED
+} t_ab8500_codec_cr3_enda4;
+
+/* CR3 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR3_ENDA5_DISABLED,
+ AB8500_CODEC_CR3_ENDA5_ENABLED
+} t_ab8500_codec_cr3_enda5;
+
+/* CR3 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR3_ENDA6_DISABLED,
+ AB8500_CODEC_CR3_ENDA6_ENABLED
+} t_ab8500_codec_cr3_enda6;
+
+
+/* CR4 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR4_LOWPOWHS_NORMAL,
+ AB8500_CODEC_CR4_LOWPOWHS_LP
+} t_ab8500_codec_cr4_lowpowhs;
+
+/* CR4 - 6:5 */
+typedef enum
+{
+ AB8500_CODEC_CR4_LOWPOWDACHS_NORMAL,
+ AB8500_CODEC_CR4_LOWPOWDACHS_DRIVERS_LP,
+ AB8500_CODEC_CR4_LOWPOWDACHS_LP,
+ AB8500_CODEC_CR4_LOWPOWDACHS_BOTH_LP
+} t_ab8500_codec_cr4_lowpowdachs;
+
+/* CR4 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR4_LOWPOWEAR_NORMAL,
+ AB8500_CODEC_CR4_LOWPOWEAR_LP
+} t_ab8500_codec_cr4_lowpowear;
+
+/* CR4 - 3:2 */
+typedef enum
+{
+ AB8500_CODEC_CR4_EAR_SEL_CM_0_95V,
+ AB8500_CODEC_CR4_EAR_SEL_CM_1_1V,
+ AB8500_CODEC_CR4_EAR_SEL_CM_1_27V,
+ AB8500_CODEC_CR4_EAR_SEL_CM_1_58V
+} t_ab8500_codec_cr4_ear_sel_cm;
+
+/* CR4 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR4_HS_HP_DIS_FILTER_ENABLED,
+ AB8500_CODEC_CR4_HS_HP_DIS_FILTER_DISABLED
+} t_ab8500_codec_cr4_hs_hp_dis;
+
+/* CR4 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR4_EAR_HP_DIS_FILTER_ENABLED,
+ AB8500_CODEC_CR4_EAR_HP_DIS_FILTER_DISABLED
+} t_ab8500_codec_cr4_ear_hp_dis;
+
+
+/* CR5 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR5_ENMIC1_DISABLED,
+ AB8500_CODEC_CR5_ENMIC1_ENABLED
+} t_ab8500_codec_cr5_enmic1;
+
+/* CR5 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR5_ENMIC2_DISABLED,
+ AB8500_CODEC_CR5_ENMIC2_ENABLED
+} t_ab8500_codec_cr5_enmic2;
+
+/* CR5 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR5_ENLINL_DISABLED,
+ AB8500_CODEC_CR5_ENLINL_ENABLED
+} t_ab8500_codec_cr5_enlinl;
+
+/* CR5 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR5_ENLINR_DISABLED,
+ AB8500_CODEC_CR5_ENLINR_ENABLED
+} t_ab8500_codec_cr5_enlinr;
+
+/* CR5 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR5_MUTMIC1_DISABLED,
+ AB8500_CODEC_CR5_MUTMIC1_ENABLED
+} t_ab8500_codec_cr5_mutmic1;
+
+/* CR5 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR5_MUTMIC2_DISABLED,
+ AB8500_CODEC_CR5_MUTMIC2_ENABLED
+} t_ab8500_codec_cr5_mutmic2;
+
+/* CR5 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR5_MUTLINL_DISABLED,
+ AB8500_CODEC_CR5_MUTLINL_ENABLED
+} t_ab8500_codec_cr5_mutlinl;
+
+/* CR5 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR5_MUTLINR_DISABLED,
+ AB8500_CODEC_CR5_MUTLINR_ENABLED
+} t_ab8500_codec_cr5_mutlinr;
+
+
+/* CR6 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR6_ENDMIC1_DISABLED,
+ AB8500_CODEC_CR6_ENDMIC1_ENABLED
+} t_ab8500_codec_cr6_endmic1;
+
+/* CR6 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR6_ENDMIC2_DISABLED,
+ AB8500_CODEC_CR6_ENDMIC2_ENABLED
+} t_ab8500_codec_cr6_endmic2;
+
+/* CR6 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR6_ENDMIC3_DISABLED,
+ AB8500_CODEC_CR6_ENDMIC3_ENABLED
+} t_ab8500_codec_cr6_endmic3;
+
+/* CR6 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR6_ENDMIC4_DISABLED,
+ AB8500_CODEC_CR6_ENDMIC4_ENABLED
+} t_ab8500_codec_cr6_endmic4;
+
+/* CR6 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR6_ENDMIC5_DISABLED,
+ AB8500_CODEC_CR6_ENDMIC5_ENABLED
+} t_ab8500_codec_cr6_endmic5;
+
+/* CR6 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR6_ENDMIC6_DISABLED,
+ AB8500_CODEC_CR6_ENDMIC6_ENABLED
+} t_ab8500_codec_cr6_endmic6;
+
+
+/* CR7 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR7_MIC1SEL_MIC1A,
+ AB8500_CODEC_CR7_MIC1SEL_MIC1B
+} t_ab8500_codec_cr7_mic1sel;
+
+/* CR7 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR7_LINRSEL_MIC2,
+ AB8500_CODEC_CR7_LINRSEL_LINR
+} t_ab8500_codec_cr7_linrsel;
+
+/* CR7 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR7_ENDRVHSL_DISABLED,
+ AB8500_CODEC_CR7_ENDRVHSL_ENABLED
+} t_ab8500_codec_cr7_endrvhsl;
+
+/* CR7 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR7_ENDRVHSR_DISABLED,
+ AB8500_CODEC_CR7_ENDRVHSR_ENABLED
+} t_ab8500_codec_cr7_endrvhsr;
+
+/* CR7 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR7_ENADCMIC_DISABLED,
+ AB8500_CODEC_CR7_ENADCMIC_ENABLED
+} t_ab8500_codec_cr7_enadcmic;
+
+/* CR7 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR7_ENADCLINL_DISABLED,
+ AB8500_CODEC_CR7_ENADCLINL_ENABLED
+} t_ab8500_codec_cr7_enadclinl;
+
+/* CR7 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR7_ENADCLINR_DISABLED,
+ AB8500_CODEC_CR7_ENADCLINR_ENABLED
+} t_ab8500_codec_cr7_enadclinr;
+
+
+/* CR8 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR8_CP_DIS_PLDWN_ENABLED,
+ AB8500_CODEC_CR8_CP_DIS_PLDWN_DISABLED
+} t_ab8500_codec_cr8_cp_dis_pldwn;
+
+/* CR8 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR8_ENEAR_DISABLED,
+ AB8500_CODEC_CR8_ENEAR_ENABLED
+} t_ab8500_codec_cr8_enear;
+
+/* CR8 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR8_ENHSL_DISABLED,
+ AB8500_CODEC_CR8_ENHSL_ENABLED
+} t_ab8500_codec_cr8_enhsl;
+
+/* CR8 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR8_ENHSR_DISABLED,
+ AB8500_CODEC_CR8_ENHSR_ENABLED
+} t_ab8500_codec_cr8_enhsr;
+
+/* CR8 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR8_ENHFL_DISABLED,
+ AB8500_CODEC_CR8_ENHFL_ENABLED
+} t_ab8500_codec_cr8_enhfl;
+
+/* CR8 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR8_ENHFR_DISABLED,
+ AB8500_CODEC_CR8_ENHFR_ENABLED
+} t_ab8500_codec_cr8_enhfr;
+
+/* CR8 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR8_ENVIBL_DISABLED,
+ AB8500_CODEC_CR8_ENVIBL_ENABLED
+} t_ab8500_codec_cr8_envibl;
+
+/* CR8 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR8_ENVIBR_DISABLED,
+ AB8500_CODEC_CR8_ENVIBR_ENABLED
+} t_ab8500_codec_cr8_envibr;
+
+
+/* CR9 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR9_ENDACEAR_DISABLED,
+ AB8500_CODEC_CR9_ENDACEAR_ENABLED
+} t_ab8500_codec_cr9_endacear;
+
+/* CR9 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR9_ENDACHSL_DISABLED,
+ AB8500_CODEC_CR9_ENDACHSL_ENABLED
+} t_ab8500_codec_cr9_endachsl;
+
+/* CR9 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR9_ENDACHSR_DISABLED,
+ AB8500_CODEC_CR9_ENDACHSR_ENABLED
+} t_ab8500_codec_cr9_endachsr;
+
+/* CR9 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR9_ENDACHFL_DISABLED,
+ AB8500_CODEC_CR9_ENDACHFL_ENABLED
+} t_ab8500_codec_cr9_endachfl;
+
+/* CR9 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR9_ENDACHFR_DISABLED,
+ AB8500_CODEC_CR9_ENDACHFR_ENABLED
+} t_ab8500_codec_cr9_endachfr;
+
+/* CR9 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR9_ENDACVIBL_DISABLED,
+ AB8500_CODEC_CR9_ENDACVIBL_ENABLED
+} t_ab8500_codec_cr9_endacvibl;
+
+/* CR9 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR9_ENDACVIBR_DISABLED,
+ AB8500_CODEC_CR9_ENDACVIBR_ENABLED
+} t_ab8500_codec_cr9_endacvibr;
+
+
+/* CR10 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR10_MUTEEAR_DISABLED,
+ AB8500_CODEC_CR10_MUTEEAR_ENABLED
+} t_ab8500_codec_cr10_muteear;
+
+/* CR10 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR10_MUTEHSL_DISABLED,
+ AB8500_CODEC_CR10_MUTEHSL_ENABLED
+} t_ab8500_codec_cr10_mutehsl;
+
+/* CR10 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR10_MUTEHSR_DISABLED,
+ AB8500_CODEC_CR10_MUTEHSR_ENABLED
+} t_ab8500_codec_cr10_mutehsr;
+
+/* CR10 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR10_MUTEHFL_DISABLED,
+ AB8500_CODEC_CR10_MUTEHFL_ENABLED
+} t_ab8500_codec_cr10_mutehfl;
+
+/* CR10 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR10_MUTEHFR_DISABLED,
+ AB8500_CODEC_CR10_MUTEHFR_ENABLED
+} t_ab8500_codec_cr10_mutehfr;
+
+/* CR10 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR10_MUTEVIBL_DISABLED,
+ AB8500_CODEC_CR10_MUTEVIBL_ENABLED
+} t_ab8500_codec_cr10_mutevibl;
+
+/* CR10 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR10_MUTEVIBR_DISABLED,
+ AB8500_CODEC_CR10_MUTEVIBR_ENABLED
+} t_ab8500_codec_cr10_mutevibr;
+
+
+/* CR11 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR11_EARSHORTPWD_DISABLED,
+ AB8500_CODEC_CR11_EARSHORTPWD_ENABLED
+} t_ab8500_codec_cr11_earshortpwd;
+
+/* CR11 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR11_EARSHORTDIS_ENABLED,
+ AB8500_CODEC_CR11_EARSHORTDIS_DISABLED
+} t_ab8500_codec_cr11_earshortdis;
+
+/* CR11 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR11_HSLSHORTDIS_ENABLED,
+ AB8500_CODEC_CR11_HSLSHORTDIS_DISABLED
+} t_ab8500_codec_cr11_hslshortdis;
+
+/* CR11 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR11_HSRSHORTDIS_ENABLED,
+ AB8500_CODEC_CR11_HSRSHORTDIS_DISABLED
+} t_ab8500_codec_cr11_hsrshortdis;
+
+/* CR11 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR11_HFLSHORTDIS_ENABLED,
+ AB8500_CODEC_CR11_HFLSHORTDIS_DISABLED
+} t_ab8500_codec_cr11_hflshortdis;
+
+/* CR11 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR11_HFRSHORTDIS_ENABLED,
+ AB8500_CODEC_CR11_HFRSHORTDIS_DISABLED
+} t_ab8500_codec_cr11_hfrshortdis;
+
+/* CR11 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR11_VIBLSHORTDIS_ENABLED,
+ AB8500_CODEC_CR11_VIBLSHORTDIS_DISABLED
+} t_ab8500_codec_cr11_viblshortdis;
+
+/* CR11 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR11_VIBRSHORTDIS_ENABLED,
+ AB8500_CODEC_CR11_VIBRSHORTDIS_DISABLED
+} t_ab8500_codec_cr11_vibrshortdis;
+
+
+/* CR12 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR12_ENCPHS_DISABLED,
+ AB8500_CODEC_CR12_ENCPHS_ENABLED
+} t_ab8500_codec_cr12_encphs;
+
+/* CR12 - 6:4 */
+typedef enum
+{
+ AB8500_CODEC_CR12_HSAUTOTIME_6_6USEC,
+ AB8500_CODEC_CR12_HSAUTOTIME_13_3USEC,
+ AB8500_CODEC_CR12_HSAUTOTIME_26_6USEC,
+ AB8500_CODEC_CR12_HSAUTOTIME_53_2USEC,
+ AB8500_CODEC_CR12_HSAUTOTIME_106_4USEC,
+ AB8500_CODEC_CR12_HSAUTOTIME_212_8USEC,
+ AB8500_CODEC_CR12_HSAUTOTIME_425_6USEC,
+ AB8500_CODEC_CR12_HSAUTOTIME_851_2USEC,
+} t_ab8500_codec_cr12_hsautotime;
+
+/* CR12 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR12_HSAUTOENSEL_DISABLED,
+ AB8500_CODEC_CR12_HSAUTOENSEL_ENABLED
+} t_ab8500_codec_cr12_hsautoensel;
+
+/* CR12 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR12_HSAUTOEN_DISABLED,
+ AB8500_CODEC_CR12_HSAUTOEN_ENABLED
+} t_ab8500_codec_cr12_hsautoen;
+
+
+/* CR13 - 7:4 */
+typedef enum
+{
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_25,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_50,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_100,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_150,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_200,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_250,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_300,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_350,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_400,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_450,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_500,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_550,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_600,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_650,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_700,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_750
+} t_ab8500_codec_cr13_envdet_hthresh;
+
+/* CR13 - 3:0 */
+typedef enum
+{
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_25,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_50,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_100,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_150,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_200,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_250,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_300,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_350,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_400,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_450,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_500,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_550,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_600,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_650,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_700,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_750
+} t_ab8500_codec_cr13_envdet_lthresh;
+
+
+/* CR14 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR14_SMPSLVEN_HIGHVOLTAGE,
+ AB8500_CODEC_CR14_SMPSLVEN_LOWVOLTAGE
+} t_ab8500_codec_cr14_smpslven;
+
+/* CR14 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR14_ENVDETSMPSEN_DISABLED,
+ AB8500_CODEC_CR14_ENVDETSMPSEN_ENABLED
+} t_ab8500_codec_cr14_envdetsmpsen;
+
+/* CR14 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR14_CPLVEN_HIGHVOLTAGE,
+ AB8500_CODEC_CR14_CPLVEN_LOWVOLTAGE
+} t_ab8500_codec_cr14_cplven;
+
+/* CR14 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR14_ENVDETCPEN_DISABLED,
+ AB8500_CODEC_CR14_ENVDETCPEN_ENABLED
+} t_ab8500_codec_cr14_envdetcpen;
+
+/* CR14 - 3:0 */
+typedef enum
+{
+ AB8500_CODEC_CR14_ENVET_TIME_27USEC,
+ AB8500_CODEC_CR14_ENVET_TIME_53USEC,
+ AB8500_CODEC_CR14_ENVET_TIME_106USEC,
+ AB8500_CODEC_CR14_ENVET_TIME_212USEC,
+ AB8500_CODEC_CR14_ENVET_TIME_424USEC,
+ AB8500_CODEC_CR14_ENVET_TIME_848USEC,
+ AB8500_CODEC_CR14_ENVET_TIME_1MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_3MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_6MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_13MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_27MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_54MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_109MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_218MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_436MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_872MSEC,
+} t_ab8500_codec_cr14_envet_time;
+
+
+/* CR15 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR15_PWMTOVIBL_DA_PATH,
+ AB8500_CODEC_CR15_PWMTOVIBL_PWM
+} t_ab8500_codec_cr15_pwmtovibl;
+
+/* CR15 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR15_PWMTOVIBR_DA_PATH,
+ AB8500_CODEC_CR15_PWMTOVIBR_PWM
+} t_ab8500_codec_cr15_pwmtovibr;
+
+/* CR15 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR15_PWMLCTRL_PWMNPLGPOL,
+ AB8500_CODEC_CR15_PWMLCTRL_PWMNPLDUTYCYCLE
+} t_ab8500_codec_cr15_pwmlctrl;
+
+/* CR15 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR15_PWMRCTRL_PWMNPRGPOL,
+ AB8500_CODEC_CR15_PWMRCTRL_PWMNPRDUTYCYCLE
+} t_ab8500_codec_cr15_pwmrctrl;
+
+/* CR15 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR15_PWMNLCTRL_PWMNLGPOL,
+ AB8500_CODEC_CR15_PWMNLCTRL_PWMNLDUTYCYCLE
+} t_ab8500_codec_cr15_pwmnlctrl;
+
+/* CR15 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR15_PWMPLCTRL_PWMPLGPOL,
+ AB8500_CODEC_CR15_PWMPLCTRL_PWMPLDUTYCYCLE
+} t_ab8500_codec_cr15_pwmplctrl;
+
+/* CR15 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR15_PWMNRCTRL_PWMNRGPOL,
+ AB8500_CODEC_CR15_PWMNRCTRL_PWMNRDUTYCYCLE
+} t_ab8500_codec_cr15_pwmnrctrl;
+
+/* CR15 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR15_PWMPRCTRL_PWMPRGPOL,
+ AB8500_CODEC_CR15_PWMPRCTRL_PWMPRDUTYCYCLE
+} t_ab8500_codec_cr15_pwmprctrl;
+
+
+/* CR16 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR16_PWMNLPOL_GNDVIB,
+ AB8500_CODEC_CR16_PWMNLPOL_VINVIB
+} t_ab8500_codec_cr16_pwmnlpol;
+
+/* CR16 - 6:0 */
+typedef t_uint8 t_ab8500_codec_cr16_pwmnldutycycle;
+
+
+/* CR17 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR17_PWMPLPOL_GNDVIB,
+ AB8500_CODEC_CR17_PWMPLPOL_VINVIB
+} t_ab8500_codec_cr17_pwmplpol;
+
+/* CR17 - 6:0 */
+typedef t_uint8 t_ab8500_codec_cr17_pwmpldutycycle;
+
+
+/* CR18 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR18_PWMNRPOL_GNDVIB,
+ AB8500_CODEC_CR18_PWMNRPOL_VINVIB
+} t_ab8500_codec_cr18_pwmnrpol;
+
+/* CR18 - 6:0 */
+typedef t_uint8 t_ab8500_codec_cr18_pwmnrdutycycle;
+
+
+/* CR19 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR19_PWMPRPOL_GNDVIB,
+ AB8500_CODEC_CR19_PWMPRPOL_VINVIB
+} t_ab8500_codec_cr19_pwmprpol;
+
+/* CR19 - 6:0 */
+typedef t_uint8 t_ab8500_codec_cr19_pwmprdutycycle;
+
+
+/* CR20 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR20_EN_SE_MIC1_DIFFERENTIAL,
+ AB8500_CODEC_CR20_EN_SE_MIC1_SINGLE
+} t_ab8500_codec_cr20_en_se_mic1;
+
+/* CR20 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr20_mic1_gain;
+
+
+/* CR21 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR21_EN_SE_MIC2_DIFFERENTIAL,
+ AB8500_CODEC_CR21_EN_SE_MIC2_SINGLE
+} t_ab8500_codec_cr21_en_se_mic2;
+
+/* CR21 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr21_mic2_gain;
+
+
+/* CR22 - 7:5 */
+typedef t_uint8 t_ab8500_codec_cr22_hsl_gain;
+
+/* CR22 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr22_linl_gain;
+
+
+/* CR23 - 7:5 */
+typedef t_uint8 t_ab8500_codec_cr23_hsr_gain;
+
+/* CR23 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr23_linr_gain;
+
+
+/* CR24 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr24_lintohsl_gain;
+
+
+/* CR25 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr25_lintohsr_gain;
+
+
+/* CR26 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR26_AD1NH_FILTER_ENABLED,
+ AB8500_CODEC_CR26_AD1NH_FILTER_DISABLED
+} t_ab8500_codec_cr26_ad1nh;
+
+/* CR26 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR26_AD2NH_FILTER_ENABLED,
+ AB8500_CODEC_CR26_AD2NH_FILTER_DISABLED
+} t_ab8500_codec_cr26_ad2nh;
+
+/* CR26 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR26_AD3NH_FILTER_ENABLED,
+ AB8500_CODEC_CR26_AD3NH_FILTER_DISABLED
+} t_ab8500_codec_cr26_ad3nh;
+
+/* CR26 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR26_AD4NH_FILTER_ENABLED,
+ AB8500_CODEC_CR26_AD4NH_FILTER_DISABLED
+} t_ab8500_codec_cr26_ad4nh;
+
+/* CR26 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR26_AD1_VOICE_AUDIOFILTER,
+ AB8500_CODEC_CR26_AD1_VOICE_LOWLATENCYFILTER
+} t_ab8500_codec_cr26_ad1_voice;
+
+/* CR26 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR26_AD2_VOICE_AUDIOFILTER,
+ AB8500_CODEC_CR26_AD2_VOICE_LOWLATENCYFILTER
+} t_ab8500_codec_cr26_ad2_voice;
+
+/* CR26 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR26_AD3_VOICE_AUDIOFILTER,
+ AB8500_CODEC_CR26_AD3_VOICE_LOWLATENCYFILTER
+} t_ab8500_codec_cr26_ad3_voice;
+
+/* CR26 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR26_AD4_VOICE_AUDIOFILTER,
+ AB8500_CODEC_CR26_AD4_VOICE_LOWLATENCYFILTER
+} t_ab8500_codec_cr26_ad4_voice;
+
+
+/* CR27 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR27_EN_MASTGEN_DISABLED,
+ AB8500_CODEC_CR27_EN_MASTGEN_ENABLED
+} t_ab8500_codec_cr27_en_mastgen;
+
+/* CR27 - 6:5 */
+typedef enum
+{
+ AB8500_CODEC_CR27_IF1_BITCLK_OSR_32,
+ AB8500_CODEC_CR27_IF1_BITCLK_OSR_64,
+ AB8500_CODEC_CR27_IF1_BITCLK_OSR_128,
+ AB8500_CODEC_CR27_IF1_BITCLK_OSR_256
+} t_ab8500_codec_cr27_if1_bitclk_osr;
+
+/* CR27 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR27_ENFS_BITCLK1_DISABLED,
+ AB8500_CODEC_CR27_ENFS_BITCLK1_ENABLED
+} t_ab8500_codec_cr27_enfs_bitclk1;
+
+/* CR27 - 2:1 */
+typedef enum
+{
+ AB8500_CODEC_CR27_IF0_BITCLK_OSR_32,
+ AB8500_CODEC_CR27_IF0_BITCLK_OSR_64,
+ AB8500_CODEC_CR27_IF0_BITCLK_OSR_128,
+ AB8500_CODEC_CR27_IF0_BITCLK_OSR_256
+} t_ab8500_codec_cr27_if0_bitclk_osr;
+
+/* CR27 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR27_ENFS_BITCLK0_DISABLED,
+ AB8500_CODEC_CR27_ENFS_BITCLK0_ENABLED
+} t_ab8500_codec_cr27_enfs_bitclk0;
+
+
+/* CR28 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR28_FSYNC0P_RISING_EDGE,
+ AB8500_CODEC_CR28_FSYNC0P_FALLING_EDGE
+} t_ab8500_codec_cr28_fsync0p;
+
+/* CR28 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR28_BITCLK0P_RISING_EDGE,
+ AB8500_CODEC_CR28_BITCLK0P_FALLING_EDGE
+} t_ab8500_codec_cr28_bitclk0p;
+
+/* CR28 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR28_IF0DEL_NOT_DELAYED,
+ AB8500_CODEC_CR28_IF0DEL_DELAYED
+} t_ab8500_codec_cr28_if0del;
+
+/* CR28 - 3:2 */
+typedef enum
+{
+ AB8500_CODEC_CR28_IF0FORMAT_DISABLED,
+ AB8500_CODEC_CR28_IF0FORMAT_TDM,
+ AB8500_CODEC_CR28_IF0FORMAT_I2S_LEFTALIGNED
+} t_ab8500_codec_cr28_if0format;
+
+/* CR28 - 1:0 */
+typedef enum
+{
+ AB8500_CODEC_CR28_IF0WL_16BITS,
+ AB8500_CODEC_CR28_IF0WL_20BITS,
+ AB8500_CODEC_CR28_IF0WL_24BITS,
+ AB8500_CODEC_CR28_IF0WL_32BITS
+} t_ab8500_codec_cr28_if0wl;
+
+
+/* CR29 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR29_IF0DATOIF1AD_NOTSENT,
+ AB8500_CODEC_CR29_IF0DATOIF1AD_SENT
+} t_ab8500_codec_cr29_if0datoif1ad;
+
+/* CR29 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR29_IF0CKTOIF1CK_NOTSENT,
+ AB8500_CODEC_CR29_IF0CKTOIF1CK_SENT
+} t_ab8500_codec_cr29_if0cktoif1ck;
+
+/* CR29 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR29_IF1MASTER_FS1CK1_INPUT,
+ AB8500_CODEC_CR29_IF1MASTER_FS1CK1_OUTPUT
+} t_ab8500_codec_cr29_if1master;
+
+/* CR29 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR29_IF1DATOIF0AD_NOTSENT,
+ AB8500_CODEC_CR29_IF1DATOIF0AD_SENT
+} t_ab8500_codec_cr29_if1datoif0ad;
+
+/* CR29 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR29_IF1CKTOIF0CK_NOTSENT,
+ AB8500_CODEC_CR29_IF1CKTOIF0CK_SENT
+} t_ab8500_codec_cr29_if1cktoif0ck;
+
+/* CR29 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR29_IF0MASTER_FS0CK0_INPUT,
+ AB8500_CODEC_CR29_IF0MASTER_FS0CK0_OUTPUT
+} t_ab8500_codec_cr29_if0master;
+
+/* CR29 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR29_IF0BFIFOEN_NORMAL_MODE,
+ AB8500_CODEC_CR29_IF0BFIFOEN_BURST_MODE
+} t_ab8500_codec_cr29_if0bfifoen;
+
+
+/* CR30 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR30_FSYNC1P_RISING_EDGE,
+ AB8500_CODEC_CR30_FSYNC1P_FALLING_EDGE
+} t_ab8500_codec_cr30_fsync1p;
+
+/* CR30 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR30_BITCLK1P_RISING_EDGE,
+ AB8500_CODEC_CR30_BITCLK1P_FALLING_EDGE
+} t_ab8500_codec_cr30_bitclk1p;
+
+/* CR30 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR30_IF1DEL_NOT_DELAYED,
+ AB8500_CODEC_CR30_IF1DEL_DELAYED
+} t_ab8500_codec_cr30_if1del;
+
+/* CR30 - 3:2 */
+typedef enum
+{
+ AB8500_CODEC_CR30_IF1FORMAT_DISABLED,
+ AB8500_CODEC_CR30_IF1FORMAT_TDM,
+ AB8500_CODEC_CR30_IF1FORMAT_I2S_LEFTALIGNED
+} t_ab8500_codec_cr30_if1format;
+
+/* CR30 - 1:0 */
+typedef enum
+{
+ AB8500_CODEC_CR30_IF1WL_16BITS,
+ AB8500_CODEC_CR30_IF1WL_20BITS,
+ AB8500_CODEC_CR30_IF1WL_24BITS,
+ AB8500_CODEC_CR30_IF1WL_32BITS
+} t_ab8500_codec_cr30_if1wl;
+
+
+/* CR31:46 - 7:4 or 3:0 */
+/* In ab8500_codec.h */
+
+
+/* CR47:50 - 7/6/5/4/3/2/1/0 */
+typedef enum
+{
+ AB8500_CODEC_CR47_TO_CR50_HIZ_SL_LOW_IMPEDANCE,
+ AB8500_CODEC_CR47_TO_CR50_HIZ_SL_HIGH_IMPEDANCE,
+} t_ab8500_codec_cr47_to_cr50_hiz_sl;
+
+
+/* CR51 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR51_DA12_VOICE_AUDIOFILTER,
+ AB8500_CODEC_CR51_DA12_VOICE_LOWLATENCYFILTER
+} t_ab8500_codec_cr51_da12_voice;
+
+/* CR51 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR51_SLDAI1TOSLADO1_NOT_LOOPEDBACK,
+ AB8500_CODEC_CR51_SLDAI1TOSLADO1_LOOPEDBACK
+} t_ab8500_codec_cr51_sldai1toslado1;
+
+
+/* CR51:56 - 4:0 */
+/* In ab8500_codec.h */
+
+
+/* CR52 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR52_SLDAI2TOSLADO2_NOT_LOOPEDBACK,
+ AB8500_CODEC_CR52_SLDAI2TOSLADO2_LOOPEDBACK
+} t_ab8500_codec_cr52_sldai2toslado2;
+
+
+/* CR53 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR53_DA34_VOICE_AUDIOFILTER,
+ AB8500_CODEC_CR53_DA34_VOICE_LOWLATENCYFILTER
+} t_ab8500_codec_cr53_da34_voice;
+
+/* CR53 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR53_SLDAI3TOSLADO3_NOT_LOOPEDBACK,
+ AB8500_CODEC_CR53_SLDAI3TOSLADO3_LOOPEDBACK
+} t_ab8500_codec_cr53_sldai3toslado3;
+
+
+/* CR54 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR54_SLDAI4TOSLADO4_NOT_LOOPEDBACK,
+ AB8500_CODEC_CR54_SLDAI4TOSLADO4_LOOPEDBACK
+} t_ab8500_codec_cr54_sldai4toslado4;
+
+
+/* CR55 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR55_DA56_VOICE_AUDIOFILTER,
+ AB8500_CODEC_CR55_DA56_VOICE_LOWLATENCYFILTER
+} t_ab8500_codec_cr55_da56_voice;
+
+/* CR55 - 6:5 */
+typedef enum
+{
+ AB8500_CODEC_CR55_SLDAI5TOSLADO5_NOT_LOOPEDBACK,
+ AB8500_CODEC_CR55_SLDAI5TOSLADO5_DA_IN1_LOOPEDBACK,
+ AB8500_CODEC_CR55_SLDAI5TOSLADO5_DA_IN3_LOOPEDBACK,
+ AB8500_CODEC_CR55_SLDAI5TOSLADO5_DA_IN5_LOOPEDBACK
+} t_ab8500_codec_cr55_sldai5toslado5;
+
+
+/* CR56 - 6:5 */
+typedef enum
+{
+ AB8500_CODEC_CR56_SLDAI6TOSLADO7_NOT_LOOPEDBACK,
+ AB8500_CODEC_CR56_SLDAI6TOSLADO7_DA_IN2_LOOPEDBACK,
+ AB8500_CODEC_CR56_SLDAI6TOSLADO7_DA_IN4_LOOPEDBACK,
+ AB8500_CODEC_CR56_SLDAI6TOSLADO7_DA_IN6_LOOPEDBACK
+} t_ab8500_codec_cr56_sldai6toslado7;
+
+
+/* CR57 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR57_BFIFULL_MSK_MASKED,
+ AB8500_CODEC_CR57_BFIFULL_MSK_ENABLED
+} t_ab8500_codec_cr57_bfifull_msk;
+
+/* CR57 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR57_BFIEMPT_MSK_MASKED,
+ AB8500_CODEC_CR57_BFIEMPT_MSK_ENABLED
+} t_ab8500_codec_cr57_bfiempt_msk;
+
+/* CR57 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR57_DACHAN_MSK_MASKED,
+ AB8500_CODEC_CR57_DACHAN_MSK_ENABLED
+} t_ab8500_codec_cr57_dachan_msk;
+
+/* CR57 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR57_GAIN_MSK_MASKED,
+ AB8500_CODEC_CR57_GAIN_MSK_ENABLED
+} t_ab8500_codec_cr57_gain_msk;
+
+/* CR57 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR57_DSPAD_MSK_MASKED,
+ AB8500_CODEC_CR57_DSPAD_MSK_ENABLED
+} t_ab8500_codec_cr57_dspad_msk;
+
+/* CR57 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR57_DSPDA_MSK_MASKED,
+ AB8500_CODEC_CR57_DSPDA_MSK_ENABLED
+} t_ab8500_codec_cr57_dspda_msk;
+
+/* CR57 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR57_STFIR_MSK_MASKED,
+ AB8500_CODEC_CR57_STFIR_MSK_ENABLED
+} t_ab8500_codec_cr57_stfir_msk;
+
+
+/* CR58 - Read Only */
+/* CR58 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR58_BFIFULL_EV_NOT_FULL,
+ AB8500_CODEC_CR58_BFIFULL_EV_FULL
+} t_ab8500_codec_cr58_bfifull_ev;
+
+/* CR58 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR58_BFIEMPT_EV_NOT_EMPTY,
+ AB8500_CODEC_CR58_BFIEMPT_EV_EMPTY
+} t_ab8500_codec_cr58_bfiempt_ev;
+
+/* CR58 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR58_DACHAN_EV_NO_SATURATION,
+ AB8500_CODEC_CR58_DACHAN_EV_SATURATION
+} t_ab8500_codec_cr58_dachan_ev;
+
+/* CR58 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR58_GAIN_EV_NO_SATURATION,
+ AB8500_CODEC_CR58_GAIN_EV_SATURATION
+} t_ab8500_codec_cr58_gain_ev;
+
+/* CR58 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR58_DSPAD_EV_NO_SATURATION,
+ AB8500_CODEC_CR58_DSPAD_EV_SATURATION
+} t_ab8500_codec_cr58_dspad_ev;
+
+/* CR58 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR58_DSPDA_EV_NO_SATURATION,
+ AB8500_CODEC_CR58_DSPDA_EV_SATURATION
+} t_ab8500_codec_cr58_dspda_ev;
+
+/* CR58 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR58_STFIR_EV_NO_SATURATION,
+ AB8500_CODEC_CR58_STFIR_EV_SATURATION
+} t_ab8500_codec_cr58_stfir_ev;
+
+
+/* CR59 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR59_VSSREADY_MSK_MASKED,
+ AB8500_CODEC_CR59_VSSREADY_MSK_ENABLED
+} t_ab8500_codec_cr59_vssready_msk;
+
+/* CR59 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR59_SHRTVIBL_MSK_MASKED,
+ AB8500_CODEC_CR59_SHRTVIBL_MSK_ENABLED
+} t_ab8500_codec_cr59_shrtvibl_msk;
+
+/* CR59 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR59_SHRTVIBR_MSK_MASKED,
+ AB8500_CODEC_CR59_SHRTVIBR_MSK_ENABLED
+} t_ab8500_codec_cr59_shrtvibr_msk;
+
+/* CR59 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR59_SHRTHFL_MSK_MASKED,
+ AB8500_CODEC_CR59_SHRTHFL_MSK_ENABLED
+} t_ab8500_codec_cr59_shrthfl_msk;
+
+/* CR59 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR59_SHRTHFR_MSK_MASKED,
+ AB8500_CODEC_CR59_SHRTHFR_MSK_ENABLED
+} t_ab8500_codec_cr59_shrthfr_msk;
+
+/* CR59 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR59_SHRTHSL_MSK_MASKED,
+ AB8500_CODEC_CR59_SHRTHSL_MSK_ENABLED
+} t_ab8500_codec_cr59_shrthsl_msk;
+
+/* CR59 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR59_SHRTHSR_MSK_MASKED,
+ AB8500_CODEC_CR59_SHRTHSR_MSK_ENABLED
+} t_ab8500_codec_cr59_shrthsr_msk;
+
+/* CR59 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR59_SHRTEAR_MSK_MASKED,
+ AB8500_CODEC_CR59_SHRTEAR_MSK_ENABLED
+} t_ab8500_codec_cr59_shrtear_msk;
+
+
+/* CR60 - Read Only */
+/* CR60 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR60_VSSREADY_EV_NOT_READY,
+ AB8500_CODEC_CR60_VSSREADY_EV_READY
+} t_ab8500_codec_cr60_vssready_ev;
+
+/* CR60 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR60_SHRTVIBL_EV_NO_SHORTCIRCUIT,
+ AB8500_CODEC_CR60_SHRTVIBL_EV_SHORTCIRCUIT
+} t_ab8500_codec_cr60_shrtvibl_ev;
+
+/* CR60 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR60_SHRTVIBR_EV_NO_SHORTCIRCUIT,
+ AB8500_CODEC_CR60_SHRTVIBR_EV_SHORTCIRCUIT
+} t_ab8500_codec_cr60_shrtvibr_ev;
+
+/* CR60 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR60_SHRTHFL_EV_NO_SHORTCIRCUIT,
+ AB8500_CODEC_CR60_SHRTHFL_EV_SHORTCIRCUIT
+} t_ab8500_codec_cr60_shrthfl_ev;
+
+/* CR60 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR60_SHRTHFR_EV_NO_SHORTCIRCUIT,
+ AB8500_CODEC_CR60_SHRTHFR_EV_SHORTCIRCUIT
+} t_ab8500_codec_cr60_shrthfr_ev;
+
+/* CR60 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR60_SHRTHSL_EV_NO_SHORTCIRCUIT,
+ AB8500_CODEC_CR60_SHRTHSL_EV_SHORTCIRCUIT
+} t_ab8500_codec_cr60_shrthsl_ev;
+
+/* CR60 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR60_SHRTHSR_EV_NO_SHORTCIRCUIT,
+ AB8500_CODEC_CR60_SHRTHSR_EV_SHORTCIRCUIT
+} t_ab8500_codec_cr60_shrthsr_ev;
+
+/* CR60 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR60_SHRTEAR_EV_NO_SHORTCIRCUIT,
+ AB8500_CODEC_CR60_SHRTEAR_EV_SHORTCIRCUIT
+} t_ab8500_codec_cr60_shrtear_ev;
+
+
+/* CR61 - 6:2 - Read Only */
+typedef enum
+{
+ AB8500_CODEC_CR61_REVISION_1_0,
+ AB8500_CODEC_CR61_REVISION_TBD
+} t_ab8500_codec_cr61_revision;
+
+/* CR61 - 1:0 */
+typedef enum
+{
+ AB8500_CODEC_CR61_FADE_SPEED_1MS,
+ AB8500_CODEC_CR61_FADE_SPEED_4MS,
+ AB8500_CODEC_CR61_FADE_SPEED_8MS,
+ AB8500_CODEC_CR61_FADE_SPEED_16MS
+} t_ab8500_codec_cr61_fade_speed;
+
+
+/* CR62 - Read Only */
+/* CR62 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR62_DMIC1SINC3_SINC5_SELECTED,
+ AB8500_CODEC_CR62_DMIC1SINC3_SINC3_SELECTED
+} t_ab8500_codec_cr62_dmic1sinc3;
+
+/* CR62 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR62_DMIC2SINC3_SINC5_SELECTED,
+ AB8500_CODEC_CR62_DMIC2SINC3_SINC3_SELECTED
+} t_ab8500_codec_cr62_dmic2sinc3;
+
+/* CR62 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR62_DMIC3SINC3_SINC5_SELECTED,
+ AB8500_CODEC_CR62_DMIC3SINC3_SINC3_SELECTED
+} t_ab8500_codec_cr62_dmic3sinc3;
+
+/* CR62 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR62_DMIC4SINC3_SINC5_SELECTED,
+ AB8500_CODEC_CR62_DMIC4SINC3_SINC3_SELECTED
+} t_ab8500_codec_cr62_dmic4sinc3;
+
+/* CR62 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR62_DMIC5SINC3_SINC5_SELECTED,
+ AB8500_CODEC_CR62_DMIC5SINC3_SINC3_SELECTED
+} t_ab8500_codec_cr62_dmic5sinc3;
+
+/* CR62 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR62_DMIC6SINC3_SINC5_SELECTED,
+ AB8500_CODEC_CR62_DMIC6SINC3_SINC3_SELECTED
+} t_ab8500_codec_cr62_dmic6sinc3;
+
+
+/* CR63 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR63_DATOHSLEN_DISABLED,
+ AB8500_CODEC_CR63_DATOHSLEN_ENABLED
+} t_ab8500_codec_cr63_datohslen;
+
+/* CR63 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR63_DATOHSREN_DISABLED,
+ AB8500_CODEC_CR63_DATOHSREN_ENABLED
+} t_ab8500_codec_cr63_datohsren;
+
+/* CR63 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR63_AD1SEL_LINLADL_SELECTED,
+ AB8500_CODEC_CR63_AD1SEL_DMIC1_SELECTED
+} t_ab8500_codec_cr63_ad1sel;
+
+/* CR63 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR63_AD2SEL_LINRADR_SELECTED,
+ AB8500_CODEC_CR63_AD2SEL_DMIC2_SELECTED
+} t_ab8500_codec_cr63_ad2sel;
+
+/* CR63 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR63_AD3SEL_ADMO_SELECTED,
+ AB8500_CODEC_CR63_AD3SEL_DMIC3_SELECTED
+} t_ab8500_codec_cr63_ad3sel;
+
+/* CR63 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR63_AD5SEL_AMADR_SELECTED,
+ AB8500_CODEC_CR63_AD5SEL_DMIC5_SELECTED
+} t_ab8500_codec_cr63_ad5sel;
+
+/* CR63 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR63_AD6SEL_ADMO_SELECTED,
+ AB8500_CODEC_CR63_AD6SEL_DMIC6_SELECTED
+} t_ab8500_codec_cr63_ad6sel;
+
+/* CR63 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR63_ANCSEL_NOT_MIXED_IN_EAR,
+ AB8500_CODEC_CR63_ANCSEL_MIXED_IN_EAR
+} t_ab8500_codec_cr63_ancsel;
+
+
+/* CR64 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR64_DATOHFREN_NOT_MIXED_TO_HFR,
+ AB8500_CODEC_CR64_DATOHFREN_MIXED_TO_HFR
+} t_ab8500_codec_cr64_datohfren;
+
+/* CR64 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR64_DATOHFLEN_NOT_MIXED_TO_HFL,
+ AB8500_CODEC_CR64_DATOHFLEN_MIXED_TO_HFL
+} t_ab8500_codec_cr64_datohflen;
+
+/* CR64 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR64_HFRSEL_DA4_MIXED_TO_HFR,
+ AB8500_CODEC_CR64_HFRSEL_ANC_MIXED_TO_HFR
+} t_ab8500_codec_cr64_hfrsel;
+
+/* CR64 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR64_HFLSEL_DA3_MIXED_TO_HFL,
+ AB8500_CODEC_CR64_HFLSEL_ANC_MIXED_TO_HFL
+} t_ab8500_codec_cr64_hflsel;
+
+/* CR64 - 3:2 */
+typedef enum
+{
+ AB8500_CODEC_CR64_STFIR1SEL_AD_OUT1_SELECTED,
+ AB8500_CODEC_CR64_STFIR1SEL_AD_OUT3_SELECTED,
+ AB8500_CODEC_CR64_STFIR1SEL_DA_IN1_SELECTED
+} t_ab8500_codec_cr64_stfir1sel;
+
+/* CR64 - 1:0 */
+typedef enum
+{
+ AB8500_CODEC_CR64_STFIR2SEL_AD_OUT2_SELECTED,
+ AB8500_CODEC_CR64_STFIR2SEL_AD_OUT4_SELECTED,
+ AB8500_CODEC_CR64_STFIR2SEL_DA_IN2_SELECTED
+} t_ab8500_codec_cr64_stfir2sel;
+
+
+/* CR65 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR65_FADEDIS_AD1_ENABLED,
+ AB8500_CODEC_CR65_FADEDIS_AD1_DISABLED
+} t_ab8500_codec_cr65_fadedis_ad1;
+
+/* CR65 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr65_ad1gain;
+
+
+/* CR66 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR66_FADEDIS_AD2_ENABLED,
+ AB8500_CODEC_CR66_FADEDIS_AD2_DISABLED
+} t_ab8500_codec_cr66_fadedis_ad2;
+
+/* CR66 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr66_ad2gain;
+
+
+/* CR67 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR67_FADEDIS_AD3_ENABLED,
+ AB8500_CODEC_CR67_FADEDIS_AD3_DISABLED
+} t_ab8500_codec_cr67_fadedis_ad3;
+
+/* CR67 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr67_ad3gain;
+
+
+/* CR68 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR68_FADEDIS_AD4_ENABLED,
+ AB8500_CODEC_CR68_FADEDIS_AD4_DISABLED
+} t_ab8500_codec_cr68_fadedis_ad4;
+
+/* CR68 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr68_ad4gain;
+
+
+/* CR69 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR69_FADEDIS_AD5_ENABLED,
+ AB8500_CODEC_CR69_FADEDIS_AD5_DISABLED
+} t_ab8500_codec_cr69_fadedis_ad5;
+
+/* CR69 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr69_ad5gain;
+
+
+/* CR70 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR70_FADEDIS_AD6_ENABLED,
+ AB8500_CODEC_CR70_FADEDIS_AD6_DISABLED
+} t_ab8500_codec_cr70_fadedis_ad6;
+
+/* CR70 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr70_ad6gain;
+
+
+/* CR71 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR71_FADEDIS_DA1_ENABLED,
+ AB8500_CODEC_CR71_FADEDIS_DA1_DISABLED
+} t_ab8500_codec_cr71_fadedis_da1;
+
+/* CR71 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr71_da1gain;
+
+
+/* CR72 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR72_FADEDIS_DA2_ENABLED,
+ AB8500_CODEC_CR72_FADEDIS_DA2_DISABLED
+} t_ab8500_codec_cr72_fadedis_da2;
+
+/* CR72 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr72_da2gain;
+
+
+/* CR73 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR73_FADEDIS_DA3_ENABLED,
+ AB8500_CODEC_CR73_FADEDIS_DA3_DISABLED
+} t_ab8500_codec_cr73_fadedis_da3;
+
+/* CR73 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr73_da3gain;
+
+
+/* CR74 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR74_FADEDIS_DA4_ENABLED,
+ AB8500_CODEC_CR74_FADEDIS_DA4_DISABLED
+} t_ab8500_codec_cr74_fadedis_da4;
+
+/* CR74 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr74_da4gain;
+
+
+/* CR75 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR75_FADEDIS_DA5_ENABLED,
+ AB8500_CODEC_CR75_FADEDIS_DA5_DISABLED
+} t_ab8500_codec_cr75_fadedis_da5;
+
+/* CR75 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr75_da5gain;
+
+
+/* CR76 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR76_FADEDIS_DA6_ENABLED,
+ AB8500_CODEC_CR76_FADEDIS_DA6_DISABLED
+} t_ab8500_codec_cr76_fadedis_da6;
+
+/* CR76 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr76_da6gain;
+
+
+/* CR77 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR77_FADEDIS_AD1L_TO_HFL_ENABLED,
+ AB8500_CODEC_CR77_FADEDIS_AD1L_TO_HFL_DISABLED
+} t_ab8500_codec_cr77_fadedis_ad1l;
+
+/* CR77 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr77_ad1lbgain_to_hfl;
+
+
+/* CR78 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR78_FADEDIS_AD2L_TO_HFR_ENABLED,
+ AB8500_CODEC_CR78_FADEDIS_AD2L_TO_HFR_DISABLED
+} t_ab8500_codec_cr78_fadedis_ad2l;
+
+/* CR78 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr78_ad2lbgain_to_hfr;
+
+
+/* CR79 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR79_HSSINC1_SINC3_CHOOSEN,
+ AB8500_CODEC_CR79_HSSINC1_SINC1_CHOOSEN
+} t_ab8500_codec_cr79_hssinc1;
+
+/* CR79 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR79_FADEDIS_HSL_ENABLED,
+ AB8500_CODEC_CR79_FADEDIS_HSL_DISABLED
+} t_ab8500_codec_cr79_fadedis_hsl;
+
+/* CR79 - 3:0 */
+typedef t_uint8 t_ab8500_codec_cr79_hsldgain;
+
+
+/* CR80 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR80_FADEDIS_HSR_ENABLED,
+ AB8500_CODEC_CR80_FADEDIS_HSR_DISABLED
+} t_ab8500_codec_cr80_fadedis_hsr;
+
+/* CR80 - 3:0 */
+typedef t_uint8 t_ab8500_codec_cr80_hsrdgain;
+
+
+/* CR81 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr81_stfir1gain;
+
+
+/* CR82 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr82_stfir2gain;
+
+
+/* CR83 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR83_ENANC_DISABLED,
+ AB8500_CODEC_CR83_ENANC_ENABLED
+} t_ab8500_codec_cr83_enanc;
+
+/* CR83 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR83_ANCIIRINIT_NOT_STARTED,
+ AB8500_CODEC_CR83_ANCIIRINIT_STARTED
+} t_ab8500_codec_cr83_anciirinit;
+
+/* CR83 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR83_ANCFIRUPDATE_RESETTED,
+ AB8500_CODEC_CR83_ANCFIRUPDATE_NOT_RESETTED
+} t_ab8500_codec_cr83_ancfirupdate;
+
+
+/* CR84 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr84_ancinshift;
+
+
+/* CR85 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr85_ancfiroutshift;
+
+
+/* CR86 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr86_ancshiftout;
+
+
+/* CR87 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr87_ancfircoeff_msb;
+
+
+/* CR88 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr88_ancfircoeff_lsb;
+
+
+/* CR89 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr89_anciircoeff_msb;
+
+
+/* CR90 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr90_anciircoeff_lsb;
+
+
+/* CR91 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr91_ancwarpdel_msb;
+
+
+/* CR92 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr92_ancwarpdel_lsb;
+
+
+/* CR93 - Read Only */
+/* CR93 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr93_ancfirpeak_msb;
+
+
+/* CR94 - Read Only */
+/* CR94 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr94_ancfirpeak_lsb;
+
+
+/* CR95 - Read Only */
+/* CR95 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr95_anciirpeak_msb;
+
+
+/* CR96 - Read Only */
+/* CR96 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr96_anciirpeak_lsb;
+
+
+/* CR97 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR97_STFIR_SET_LAST_NOT_APPLIED,
+ AB8500_CODEC_CR97_STFIR_SET_LAST_APPLIED
+} t_ab8500_codec_cr97_stfir_set;
+
+/* CR97 - 6:0 */
+typedef t_uint8 t_ab8500_codec_cr97_stfir_addr;
+
+
+/* CR98 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr98_stfir_coeff_msb;
+
+
+/* CR99 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr99_stfir_coeff_lsb;
+
+
+/* CR100 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR100_ENSTFIRS_DISABLED,
+ AB8500_CODEC_CR100_ENSTFIRS_ENABLED
+} t_ab8500_codec_cr100_enstfirs;
+
+/* CR100 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR100_STFIRSTOIF1_AUD_IF0_DATA_RATE,
+ AB8500_CODEC_CR100_STFIRSTOIF1_AUD_IF1_DATA_RATE
+} t_ab8500_codec_cr100_stfirstoif1;
+
+/* CR100 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR100_STFIR_BUSY_READY,
+ AB8500_CODEC_CR100_STFIR_BUSY_NOT_READY
+} t_ab8500_codec_cr100_stfir_busy;
+
+
+/* CR101 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR101_PARLHF_INDEPENDENT,
+ AB8500_CODEC_CR101_PARLHF_BRIDGED
+} t_ab8500_codec_cr101_parlhf;
+
+/* CR101 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR101_PARLVIB_INDEPENDENT,
+ AB8500_CODEC_CR101_PARLVIB_BRIDGED
+} t_ab8500_codec_cr101_parlvib;
+
+/* CR101 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR101_CLASSD_VIBLSWAPEN_DISABLED,
+ AB8500_CODEC_CR101_CLASSD_VIBLSWAPEN_ENABLED
+} t_ab8500_codec_cr101_classd_viblswapen;
+
+/* CR101 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR101_CLASSD_VIBRSWAPEN_DISABLED,
+ AB8500_CODEC_CR101_CLASSD_VIBRSWAPEN_ENABLED
+} t_ab8500_codec_cr101_classd_vibrswapen;
+
+/* CR101 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR101_CLASSD_HFLSWAPEN_DISABLED,
+ AB8500_CODEC_CR101_CLASSD_HFLSWAPEN_ENABLED
+} t_ab8500_codec_cr101_classd_hflswapen;
+
+/* CR101 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR101_CLASSD_HFRSWAPEN_DISABLED,
+ AB8500_CODEC_CR101_CLASSD_HFRSWAPEN_ENABLED
+} t_ab8500_codec_cr101_classd_hfrswapen;
+
+
+/* CR102 - 7:4 */
+typedef enum
+{
+ AB8500_CODEC_CR102_CLASSD_FIRBYP_ALL_ENABLED = 0,
+ AB8500_CODEC_CR102_CLASSD_FIRBYP_HFL_BYPASSED = 1,
+ AB8500_CODEC_CR102_CLASSD_FIRBYP_HFR_BYPASSED = 2,
+ AB8500_CODEC_CR102_CLASSD_FIRBYP_VIBL_BYPASSED = 4,
+ AB8500_CODEC_CR102_CLASSD_FIRBYP_VIBR_BYPASSED = 8
+} t_ab8500_codec_cr102_classd_firbyp;
+
+/* CR102 - 3:0 */
+typedef enum
+{
+ AB8500_CODEC_CR102_CLASSD_HIGHVOLEN_DISABLED = 0,
+ AB8500_CODEC_CR102_CLASSD_HIGHVOLEN_HFL_HIGHVOL = 1,
+ AB8500_CODEC_CR102_CLASSD_HIGHVOLEN_HFR_HIGHVOL = 2,
+ AB8500_CODEC_CR102_CLASSD_HIGHVOLEN_VIBL_HIGHVOL = 4,
+ AB8500_CODEC_CR102_CLASSD_HIGHVOLEN_VIBR_HIGHVOL = 8
+} t_ab8500_codec_cr102_classd_highvolen;
+
+
+/* CR103 - 7:4 */
+typedef t_uint8 t_ab8500_codec_cr103_classd_ditherhpgain;
+
+/* CR103 - 3:0 */
+typedef t_uint8 t_ab8500_codec_cr103_classd_ditherwgain;
+
+
+/* CR104 - 5:0 */
+/* In ab8500_codec.h */
+
+
+/* CR105 - 7:0 */
+/* In ab8500_codec.h */
+
+
+/* CR106 - 6:4 */
+/* In ab8500_codec.h */
+
+
+/* CR106 - 2 */
+/* In ab8500_codec.h */
+
+
+/* CR106 - 1 */
+/* In ab8500_codec.h */
+
+
+/* CR106 - 0 */
+/* In ab8500_codec.h */
+
+
+/* CR107 - 7:0 */
+/* In ab8500_codec.h */
+
+
+/* CR108 - 7:0 */
+/* In ab8500_codec.h */
+
+
+/* CR109 - Read Only */
+/* CR109 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr109_bfifosamples;
+
+
+
+/*configuration structure for AB8500 Codec*/
+typedef struct
+{
+ /* CR0 */
+ t_ab8500_codec_cr0_powerup cr0_powerup;
+ t_ab8500_codec_cr0_enaana cr0_enaana;
+
+ /* CR1 */
+ t_ab8500_codec_cr1_swreset cr1_swreset;
+
+ /* CR2 */
+ t_ab8500_codec_cr2_enad1 cr2_enad1;
+ t_ab8500_codec_cr2_enad2 cr2_enad2;
+ t_ab8500_codec_cr2_enad3 cr2_enad3;
+ t_ab8500_codec_cr2_enad4 cr2_enad4;
+ t_ab8500_codec_cr2_enad5 cr2_enad5;
+ t_ab8500_codec_cr2_enad6 cr2_enad6;
+
+ /* CR3 */
+ t_ab8500_codec_cr3_enda1 cr3_enda1;
+ t_ab8500_codec_cr3_enda2 cr3_enda2;
+ t_ab8500_codec_cr3_enda3 cr3_enda3;
+ t_ab8500_codec_cr3_enda4 cr3_enda4;
+ t_ab8500_codec_cr3_enda5 cr3_enda5;
+ t_ab8500_codec_cr3_enda6 cr3_enda6;
+
+ /* CR4 */
+ t_ab8500_codec_cr4_lowpowhs cr4_lowpowhs;
+ t_ab8500_codec_cr4_lowpowdachs cr4_lowpowdachs;
+ t_ab8500_codec_cr4_lowpowear cr4_lowpowear;
+ t_ab8500_codec_cr4_ear_sel_cm cr4_ear_sel_cm;
+ t_ab8500_codec_cr4_hs_hp_dis cr4_hs_hp_dis;
+ t_ab8500_codec_cr4_ear_hp_dis cr4_ear_hp_dis;
+
+ /* CR5 */
+ t_ab8500_codec_cr5_enmic1 cr5_enmic1;
+ t_ab8500_codec_cr5_enmic2 cr5_enmic2;
+ t_ab8500_codec_cr5_enlinl cr5_enlinl;
+ t_ab8500_codec_cr5_enlinr cr5_enlinr;
+ t_ab8500_codec_cr5_mutmic1 cr5_mutmic1;
+ t_ab8500_codec_cr5_mutmic2 cr5_mutmic2;
+ t_ab8500_codec_cr5_mutlinl cr5_mutlinl;
+ t_ab8500_codec_cr5_mutlinr cr5_mutlinr;
+
+ /* CR6 */
+ t_ab8500_codec_cr6_endmic1 cr6_endmic1;
+ t_ab8500_codec_cr6_endmic2 cr6_endmic2;
+ t_ab8500_codec_cr6_endmic3 cr6_endmic3;
+ t_ab8500_codec_cr6_endmic4 cr6_endmic4;
+ t_ab8500_codec_cr6_endmic5 cr6_endmic5;
+ t_ab8500_codec_cr6_endmic6 cr6_endmic6;
+
+ /* CR7 */
+ t_ab8500_codec_cr7_mic1sel cr7_mic1sel;
+ t_ab8500_codec_cr7_linrsel cr7_linrsel;
+ t_ab8500_codec_cr7_endrvhsl cr7_endrvhsl;
+ t_ab8500_codec_cr7_endrvhsr cr7_endrvhsr;
+ t_ab8500_codec_cr7_enadcmic cr7_enadcmic;
+ t_ab8500_codec_cr7_enadclinl cr7_enadclinl;
+ t_ab8500_codec_cr7_enadclinr cr7_enadclinr;
+
+ /* CR8 */
+ t_ab8500_codec_cr8_cp_dis_pldwn cr8_cp_dis_pldwn;
+ t_ab8500_codec_cr8_enear cr8_enear;
+ t_ab8500_codec_cr8_enhsl cr8_enhsl;
+ t_ab8500_codec_cr8_enhsr cr8_enhsr;
+ t_ab8500_codec_cr8_enhfl cr8_enhfl;
+ t_ab8500_codec_cr8_enhfr cr8_enhfr;
+ t_ab8500_codec_cr8_envibl cr8_envibl;
+ t_ab8500_codec_cr8_envibr cr8_envibr;
+
+ /* CR9 */
+ t_ab8500_codec_cr9_endacear cr9_endacear;
+ t_ab8500_codec_cr9_endachsl cr9_endachsl;
+ t_ab8500_codec_cr9_endachsr cr9_endachsr;
+ t_ab8500_codec_cr9_endachfl cr9_endachfl;
+ t_ab8500_codec_cr9_endachfr cr9_endachfr;
+ t_ab8500_codec_cr9_endacvibl cr9_endacvibl;
+ t_ab8500_codec_cr9_endacvibr cr9_endacvibr;
+
+ /* CR10 */
+ t_ab8500_codec_cr10_muteear cr10_muteear;
+ t_ab8500_codec_cr10_mutehsl cr10_mutehsl;
+ t_ab8500_codec_cr10_mutehsr cr10_mutehsr;
+ t_ab8500_codec_cr10_mutehfl cr10_mutehfl;
+ t_ab8500_codec_cr10_mutehfr cr10_mutehfr;
+ t_ab8500_codec_cr10_mutevibl cr10_mutevibl;
+ t_ab8500_codec_cr10_mutevibr cr10_mutevibr;
+
+ /* CR11 */
+ t_ab8500_codec_cr11_earshortpwd cr11_earshortpwd;
+ t_ab8500_codec_cr11_earshortdis cr11_earshortdis;
+ t_ab8500_codec_cr11_hslshortdis cr11_hslshortdis;
+ t_ab8500_codec_cr11_hsrshortdis cr11_hsrshortdis;
+ t_ab8500_codec_cr11_hflshortdis cr11_hflshortdis;
+ t_ab8500_codec_cr11_hfrshortdis cr11_hfrshortdis;
+ t_ab8500_codec_cr11_viblshortdis cr11_viblshortdis;
+ t_ab8500_codec_cr11_vibrshortdis cr11_vibrshortdis;
+
+ /* CR12 */
+ t_ab8500_codec_cr12_encphs cr12_encphs;
+ t_ab8500_codec_cr12_hsautotime cr12_hsautotime;
+ t_ab8500_codec_cr12_hsautoensel cr12_hsautoensel;
+ t_ab8500_codec_cr12_hsautoen cr12_hsautoen;
+
+ /* CR13 */
+ t_ab8500_codec_cr13_envdet_hthresh cr13_envdet_hthresh;
+ t_ab8500_codec_cr13_envdet_lthresh cr13_envdet_lthresh;
+
+ /* CR14 */
+ t_ab8500_codec_cr14_smpslven cr14_smpslven;
+ t_ab8500_codec_cr14_envdetsmpsen cr14_envdetsmpsen;
+ t_ab8500_codec_cr14_cplven cr14_cplven;
+ t_ab8500_codec_cr14_envdetcpen cr14_envdetcpen;
+ t_ab8500_codec_cr14_envet_time cr14_envet_time;
+
+
+ /* CR15 */
+ t_ab8500_codec_cr15_pwmtovibl cr15_pwmtovibl;
+ t_ab8500_codec_cr15_pwmtovibr cr15_pwmtovibr;
+ t_ab8500_codec_cr15_pwmlctrl cr15_pwmlctrl;
+ t_ab8500_codec_cr15_pwmrctrl cr15_pwmrctrl;
+ t_ab8500_codec_cr15_pwmnlctrl cr15_pwmnlctrl;
+ t_ab8500_codec_cr15_pwmplctrl cr15_pwmplctrl;
+ t_ab8500_codec_cr15_pwmnrctrl cr15_pwmnrctrl;
+ t_ab8500_codec_cr15_pwmprctrl cr15_pwmprctrl;
+
+
+ /* CR16 */
+ t_ab8500_codec_cr16_pwmnlpol cr16_pwmnlpol;
+ t_ab8500_codec_cr16_pwmnldutycycle cr16_pwmnldutycycle;
+
+
+ /* CR17 */
+ t_ab8500_codec_cr17_pwmplpol cr17_pwmplpol;
+ t_ab8500_codec_cr17_pwmpldutycycle cr17_pwmpldutycycle;
+
+
+ /* CR18 */
+ t_ab8500_codec_cr18_pwmnrpol cr18_pwmnrpol;
+ t_ab8500_codec_cr18_pwmnrdutycycle cr18_pwmnrdutycycle;
+
+
+ /* CR19 */
+ t_ab8500_codec_cr19_pwmprpol cr19_pwmprpol;
+ t_ab8500_codec_cr19_pwmprdutycycle cr19_pwmprdutycycle;
+
+
+ /* CR20 */
+ t_ab8500_codec_cr20_en_se_mic1 cr20_en_se_mic1;
+ t_ab8500_codec_cr20_mic1_gain cr20_mic1_gain;
+
+
+ /* CR21 */
+ t_ab8500_codec_cr21_en_se_mic2 cr21_en_se_mic2;
+ t_ab8500_codec_cr21_mic2_gain cr21_mic2_gain;
+
+
+ /* CR22 */
+ t_ab8500_codec_cr22_hsl_gain cr22_hsl_gain;
+ t_ab8500_codec_cr22_linl_gain cr22_linl_gain;
+
+
+ /* CR23 */
+ t_ab8500_codec_cr23_hsr_gain cr23_hsr_gain;
+ t_ab8500_codec_cr23_linr_gain cr23_linr_gain;
+
+
+ /* CR24 */
+ t_ab8500_codec_cr24_lintohsl_gain cr24_lintohsl_gain;
+
+
+ /* CR25 */
+ t_ab8500_codec_cr25_lintohsr_gain cr25_lintohsr_gain;
+
+
+ /* CR26 */
+ t_ab8500_codec_cr26_ad1nh cr26_ad1nh;
+ t_ab8500_codec_cr26_ad2nh cr26_ad2nh;
+ t_ab8500_codec_cr26_ad3nh cr26_ad3nh;
+ t_ab8500_codec_cr26_ad4nh cr26_ad4nh;
+ t_ab8500_codec_cr26_ad1_voice cr26_ad1_voice;
+ t_ab8500_codec_cr26_ad2_voice cr26_ad2_voice;
+ t_ab8500_codec_cr26_ad3_voice cr26_ad3_voice;
+ t_ab8500_codec_cr26_ad4_voice cr26_ad4_voice;
+
+
+ /* CR27 */
+ t_ab8500_codec_cr27_en_mastgen cr27_en_mastgen;
+ t_ab8500_codec_cr27_if1_bitclk_osr cr27_if1_bitclk_osr;
+ t_ab8500_codec_cr27_enfs_bitclk1 cr27_enfs_bitclk1;
+ t_ab8500_codec_cr27_if0_bitclk_osr cr27_if0_bitclk_osr;
+ t_ab8500_codec_cr27_enfs_bitclk0 cr27_enfs_bitclk0;
+
+ /* CR28 */
+ t_ab8500_codec_cr28_fsync0p cr28_fsync0p;
+ t_ab8500_codec_cr28_bitclk0p cr28_bitclk0p;
+ t_ab8500_codec_cr28_if0del cr28_if0del;
+ t_ab8500_codec_cr28_if0format cr28_if0format;
+ t_ab8500_codec_cr28_if0wl cr28_if0wl;
+
+
+ /* CR29 */
+ t_ab8500_codec_cr29_if0datoif1ad cr29_if0datoif1ad;
+ t_ab8500_codec_cr29_if0cktoif1ck cr29_if0cktoif1ck;
+ t_ab8500_codec_cr29_if1master cr29_if1master;
+ t_ab8500_codec_cr29_if1datoif0ad cr29_if1datoif0ad;
+ t_ab8500_codec_cr29_if1cktoif0ck cr29_if1cktoif0ck;
+ t_ab8500_codec_cr29_if0master cr29_if0master;
+ t_ab8500_codec_cr29_if0bfifoen cr29_if0bfifoen;
+
+
+ /* CR30 */
+ t_ab8500_codec_cr30_fsync1p cr30_fsync1p;
+ t_ab8500_codec_cr30_bitclk1p cr30_bitclk1p;
+ t_ab8500_codec_cr30_if1del cr30_if1del;
+ t_ab8500_codec_cr30_if1format cr30_if1format;
+ t_ab8500_codec_cr30_if1wl cr30_if1wl;
+
+
+ /* CR31 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr31_adotoslot1;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr31_adotoslot0;
+
+
+ /* CR32 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr32_adotoslot3;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr32_adotoslot2;
+
+
+ /* CR33 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr33_adotoslot5;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr33_adotoslot4;
+
+
+ /* CR34 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr34_adotoslot7;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr34_adotoslot6;
+
+
+ /* CR35 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr35_adotoslot9;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr35_adotoslot8;
+
+
+ /* CR36 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr36_adotoslot11;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr36_adotoslot10;
+
+
+ /* CR37 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr37_adotoslot13;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr37_adotoslot12;
+
+
+ /* CR38 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr38_adotoslot15;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr38_adotoslot14;
+
+
+ /* CR39 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr39_adotoslot17;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr39_adotoslot16;
+
+
+ /* CR40 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr40_adotoslot19;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr40_adotoslot18;
+
+
+ /* CR41 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr41_adotoslot21;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr41_adotoslot20;
+
+
+ /* CR42 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr42_adotoslot23;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr42_adotoslot22;
+
+
+ /* CR43 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr43_adotoslot25;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr43_adotoslot24;
+
+
+ /* CR44 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr44_adotoslot27;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr44_adotoslot26;
+
+
+ /* CR45 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr45_adotoslot29;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr45_adotoslot28;
+
+
+ /* CR46 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr46_adotoslot31;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr46_adotoslot30;
+
+
+ /* CR47 */
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl7;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl6;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl5;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl4;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl3;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl2;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl1;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl0;
+
+
+ /* CR48 */
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl15;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl14;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl13;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl12;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl11;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl10;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl9;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl8;
+
+
+ /* CR49 */
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl23;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl22;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl21;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl20;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl19;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl18;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl17;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl16;
+
+
+ /* CR50 */
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl31;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl30;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl29;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl28;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl27;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl26;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl25;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl24;
+
+
+ /* CR51 */
+ t_ab8500_codec_cr51_da12_voice cr51_da12_voice;
+ t_ab8500_codec_cr51_sldai1toslado1 cr51_sldai1toslado1;
+ t_ab8500_codec_cr51_to_cr56_sltoda cr51_sltoda1;
+
+
+ /* CR52 */
+ t_ab8500_codec_cr52_sldai2toslado2 cr52_sldai2toslado2;
+ t_ab8500_codec_cr51_to_cr56_sltoda cr52_sltoda2;
+
+
+ /* CR53 */
+ t_ab8500_codec_cr53_da34_voice cr53_da34_voice;
+ t_ab8500_codec_cr53_sldai3toslado3 cr53_sldai3toslado3;
+ t_ab8500_codec_cr51_to_cr56_sltoda cr53_sltoda3;
+
+ /* CR54 */
+ t_ab8500_codec_cr54_sldai4toslado4 cr54_sldai4toslado4;
+ t_ab8500_codec_cr51_to_cr56_sltoda cr54_sltoda4;
+
+
+ /* CR55 */
+ t_ab8500_codec_cr55_da56_voice cr55_da56_voice;
+ t_ab8500_codec_cr55_sldai5toslado5 cr55_sldai5toslado5;
+ t_ab8500_codec_cr51_to_cr56_sltoda cr55_sltoda5;
+
+
+ /* CR56 */
+ t_ab8500_codec_cr56_sldai6toslado7 cr56_sldai6toslado7;
+ t_ab8500_codec_cr51_to_cr56_sltoda cr56_sltoda6;
+
+
+ /* CR57 */
+ t_ab8500_codec_cr57_bfifull_msk cr57_bfifull_msk;
+ t_ab8500_codec_cr57_bfiempt_msk cr57_bfiempt_msk;
+ t_ab8500_codec_cr57_dachan_msk cr57_dachan_msk;
+ t_ab8500_codec_cr57_gain_msk cr57_gain_msk;
+ t_ab8500_codec_cr57_dspad_msk cr57_dspad_msk;
+ t_ab8500_codec_cr57_dspda_msk cr57_dspda_msk;
+ t_ab8500_codec_cr57_stfir_msk cr57_stfir_msk;
+
+
+ /* CR58 */
+ t_ab8500_codec_cr58_bfifull_ev cr58_bfifull_ev;
+ t_ab8500_codec_cr58_bfiempt_ev cr58_bfiempt_ev;
+ t_ab8500_codec_cr58_dachan_ev cr58_dachan_ev;
+ t_ab8500_codec_cr58_gain_ev cr58_gain_ev;
+ t_ab8500_codec_cr58_dspad_ev cr58_dspad_ev;
+ t_ab8500_codec_cr58_dspda_ev cr58_dspda_ev;
+ t_ab8500_codec_cr58_stfir_ev cr58_stfir_ev;
+
+
+ /* CR59 */
+ t_ab8500_codec_cr59_vssready_msk cr59_vssready_msk;
+ t_ab8500_codec_cr59_shrtvibl_msk cr59_shrtvibl_msk;
+ t_ab8500_codec_cr59_shrtvibr_msk cr59_shrtvibr_msk;
+ t_ab8500_codec_cr59_shrthfl_msk cr59_shrthfl_msk;
+ t_ab8500_codec_cr59_shrthfr_msk cr59_shrthfr_msk;
+ t_ab8500_codec_cr59_shrthsl_msk cr59_shrthsl_msk;
+ t_ab8500_codec_cr59_shrthsr_msk cr59_shrthsr_msk;
+ t_ab8500_codec_cr59_shrtear_msk cr59_shrtear_msk;
+
+
+ /* CR60 */
+ t_ab8500_codec_cr60_vssready_ev cr60_vssready_ev;
+ t_ab8500_codec_cr60_shrtvibl_ev cr60_shrtvibl_ev;
+ t_ab8500_codec_cr60_shrtvibr_ev cr60_shrtvibr_ev;
+ t_ab8500_codec_cr60_shrthfl_ev cr60_shrthfl_ev;
+ t_ab8500_codec_cr60_shrthfr_ev cr60_shrthfr_ev;
+ t_ab8500_codec_cr60_shrthsl_ev cr60_shrthsl_ev;
+ t_ab8500_codec_cr60_shrthsr_ev cr60_shrthsr_ev;
+ t_ab8500_codec_cr60_shrtear_ev cr60_shrtear_ev;
+
+
+ /* CR61 */
+ t_ab8500_codec_cr61_revision cr61_revision;
+ t_ab8500_codec_cr61_fade_speed cr61_fade_speed;
+
+
+ /* CR62 */
+ t_ab8500_codec_cr62_dmic1sinc3 cr62_dmic1sinc3;
+ t_ab8500_codec_cr62_dmic2sinc3 cr62_dmic2sinc3;
+ t_ab8500_codec_cr62_dmic3sinc3 cr62_dmic3sinc3;
+ t_ab8500_codec_cr62_dmic4sinc3 cr62_dmic4sinc3;
+ t_ab8500_codec_cr62_dmic5sinc3 cr62_dmic5sinc3;
+ t_ab8500_codec_cr62_dmic6sinc3 cr62_dmic6sinc3;
+
+
+ /* CR63 */
+ t_ab8500_codec_cr63_datohslen cr63_datohslen;
+ t_ab8500_codec_cr63_datohsren cr63_datohsren;
+ t_ab8500_codec_cr63_ad1sel cr63_ad1sel;
+ t_ab8500_codec_cr63_ad2sel cr63_ad2sel;
+ t_ab8500_codec_cr63_ad3sel cr63_ad3sel;
+ t_ab8500_codec_cr63_ad5sel cr63_ad5sel;
+ t_ab8500_codec_cr63_ad6sel cr63_ad6sel;
+ t_ab8500_codec_cr63_ancsel cr63_ancsel;
+
+
+ /* CR64 */
+ t_ab8500_codec_cr64_datohfren cr64_datohfren;
+ t_ab8500_codec_cr64_datohflen cr64_datohflen;
+ t_ab8500_codec_cr64_hfrsel cr64_hfrsel;
+ t_ab8500_codec_cr64_hflsel cr64_hflsel;
+ t_ab8500_codec_cr64_stfir1sel cr64_stfir1sel;
+ t_ab8500_codec_cr64_stfir2sel cr64_stfir2sel;
+
+
+ /* CR65 */
+ t_ab8500_codec_cr65_fadedis_ad1 cr65_fadedis_ad1;
+ t_ab8500_codec_cr65_ad1gain cr65_ad1gain;
+
+
+ /* CR66 */
+ t_ab8500_codec_cr66_fadedis_ad2 cr66_fadedis_ad2;
+ t_ab8500_codec_cr66_ad2gain cr66_ad2gain;
+
+
+ /* CR67 */
+ t_ab8500_codec_cr67_fadedis_ad3 cr67_fadedis_ad3;
+ t_ab8500_codec_cr67_ad3gain cr67_ad3gain;
+
+
+ /* CR68 */
+ t_ab8500_codec_cr68_fadedis_ad4 cr68_fadedis_ad4;
+ t_ab8500_codec_cr68_ad4gain cr68_ad4gain;
+
+
+ /* CR69 */
+ t_ab8500_codec_cr69_fadedis_ad5 cr69_fadedis_ad5;
+ t_ab8500_codec_cr69_ad5gain cr69_ad5gain;
+
+
+ /* CR70 */
+ t_ab8500_codec_cr70_fadedis_ad6 cr70_fadedis_ad6;
+ t_ab8500_codec_cr70_ad6gain cr70_ad6gain;
+
+
+ /* CR71 */
+ t_ab8500_codec_cr71_fadedis_da1 cr71_fadedis_da1;
+ t_ab8500_codec_cr71_da1gain cr71_da1gain;
+
+
+ /* CR72 */
+ t_ab8500_codec_cr72_fadedis_da2 cr72_fadedis_da2;
+ t_ab8500_codec_cr72_da2gain cr72_da2gain;
+
+
+ /* CR73 */
+ t_ab8500_codec_cr73_fadedis_da3 cr73_fadedis_da3;
+ t_ab8500_codec_cr73_da3gain cr73_da3gain;
+
+
+ /* CR74 */
+ t_ab8500_codec_cr74_fadedis_da4 cr74_fadedis_da4;
+ t_ab8500_codec_cr74_da4gain cr74_da4gain;
+
+
+ /* CR75 */
+ t_ab8500_codec_cr75_fadedis_da5 cr75_fadedis_da5;
+ t_ab8500_codec_cr75_da5gain cr75_da5gain;
+
+
+ /* CR76 */
+ t_ab8500_codec_cr76_fadedis_da6 cr76_fadedis_da6;
+ t_ab8500_codec_cr76_da6gain cr76_da6gain;
+
+
+ /* CR77 */
+ t_ab8500_codec_cr77_fadedis_ad1l cr77_fadedis_ad1l;
+ t_ab8500_codec_cr77_ad1lbgain_to_hfl cr77_ad1lbgain_to_hfl;
+
+
+ /* CR78 */
+ t_ab8500_codec_cr78_fadedis_ad2l cr78_fadedis_ad2l;
+ t_ab8500_codec_cr78_ad2lbgain_to_hfr cr78_ad2lbgain_to_hfr;
+
+
+ /* CR79 */
+ t_ab8500_codec_cr79_hssinc1 cr79_hssinc1;
+ t_ab8500_codec_cr79_fadedis_hsl cr79_fadedis_hsl;
+ t_ab8500_codec_cr79_hsldgain cr79_hsldgain;
+
+
+ /* CR80 */
+ t_ab8500_codec_cr80_fadedis_hsr cr80_fadedis_hsr;
+ t_ab8500_codec_cr80_hsrdgain cr80_hsrdgain;
+
+
+ /* CR81 */
+ t_ab8500_codec_cr81_stfir1gain cr81_stfir1gain;
+
+
+ /* CR82 */
+ t_ab8500_codec_cr82_stfir2gain cr82_stfir2gain;
+
+
+ /* CR83 */
+ t_ab8500_codec_cr83_enanc cr83_enanc;
+ t_ab8500_codec_cr83_anciirinit cr83_anciirinit;
+ t_ab8500_codec_cr83_ancfirupdate cr83_ancfirupdate;
+
+
+ /* CR84 */
+ t_ab8500_codec_cr84_ancinshift cr84_ancinshift;
+
+
+ /* CR85 */
+ t_ab8500_codec_cr85_ancfiroutshift cr85_ancfiroutshift;
+
+
+ /* CR86 */
+ t_ab8500_codec_cr86_ancshiftout cr86_ancshiftout;
+
+
+ /* CR87 */
+ t_ab8500_codec_cr87_ancfircoeff_msb cr87_ancfircoeff_msb;
+
+
+ /* CR88 */
+ t_ab8500_codec_cr88_ancfircoeff_lsb cr88_ancfircoeff_lsb;
+
+
+ /* CR89 */
+ t_ab8500_codec_cr89_anciircoeff_msb cr89_anciircoeff_msb;
+
+
+ /* CR90 */
+ t_ab8500_codec_cr90_anciircoeff_lsb cr90_anciircoeff_lsb;
+
+
+ /* CR91 */
+ t_ab8500_codec_cr91_ancwarpdel_msb cr91_ancwarpdel_msb;
+
+
+ /* CR92 */
+ t_ab8500_codec_cr92_ancwarpdel_lsb cr92_ancwarpdel_lsb;
+
+
+ /* CR93 */
+ t_ab8500_codec_cr93_ancfirpeak_msb cr93_ancfirpeak_msb;
+
+
+ /* CR94 */
+ t_ab8500_codec_cr94_ancfirpeak_lsb cr94_ancfirpeak_lsb;
+
+
+ /* CR95 */
+ t_ab8500_codec_cr95_anciirpeak_msb cr95_anciirpeak_msb;
+
+
+ /* CR96 */
+ t_ab8500_codec_cr96_anciirpeak_lsb cr96_anciirpeak_lsb;
+
+
+ /* CR97 */
+ t_ab8500_codec_cr97_stfir_set cr97_stfir_set;
+ t_ab8500_codec_cr97_stfir_addr cr97_stfir_addr;
+
+
+ /* CR98 */
+ t_ab8500_codec_cr98_stfir_coeff_msb cr98_stfir_coeff_msb;
+
+
+ /* CR99 */
+ t_ab8500_codec_cr99_stfir_coeff_lsb cr99_stfir_coeff_lsb;
+
+
+ /* CR100 */
+ t_ab8500_codec_cr100_enstfirs cr100_enstfirs;
+ t_ab8500_codec_cr100_stfirstoif1 cr100_stfirstoif1;
+ t_ab8500_codec_cr100_stfir_busy cr100_stfir_busy;
+
+
+ /* CR101 */
+ t_ab8500_codec_cr101_parlhf cr101_parlhf;
+ t_ab8500_codec_cr101_parlvib cr101_parlvib;
+ t_ab8500_codec_cr101_classd_viblswapen cr101_classd_viblswapen;
+ t_ab8500_codec_cr101_classd_vibrswapen cr101_classd_vibrswapen;
+ t_ab8500_codec_cr101_classd_hflswapen cr101_classd_hflswapen;
+ t_ab8500_codec_cr101_classd_hfrswapen cr101_classd_hfrswapen;
+
+
+ /* CR102 */
+ t_ab8500_codec_cr102_classd_firbyp cr102_classd_firbyp;
+ t_ab8500_codec_cr102_classd_highvolen cr102_classd_highvolen;
+
+
+ /* CR103 */
+ t_ab8500_codec_cr103_classd_ditherhpgain cr103_classd_ditherhpgain;
+ t_ab8500_codec_cr103_classd_ditherwgain cr103_classd_ditherwgain;
+
+
+ /* CR104 */
+ t_ab8500_codec_cr104_bfifoint cr104_bfifoint;
+
+
+ /* CR105 */
+ t_ab8500_codec_cr105_bfifotx cr105_bfifotx;
+
+
+ /* CR106 */
+ t_ab8500_codec_cr106_bfifofsext cr106_bfifofsext;
+ t_ab8500_codec_cr106_bfifomsk cr106_bfifomsk;
+ t_ab8500_codec_cr106_bfifomstr cr106_bfifomstr;
+ t_ab8500_codec_cr106_bfifostrt cr106_bfifostrt;
+
+
+ /* CR107 */
+ t_ab8500_codec_cr107_bfifosampnr cr107_bfifosampnr;
+
+
+ /* CR108 */
+ t_ab8500_codec_cr108_bfifowakeup cr108_bfifowakeup;
+
+
+ /* CR109 */
+ t_ab8500_codec_cr109_bfifosamples cr109_bfifosamples;
+
+
+} t_ab8500_codec_configuration;
+
+
+typedef struct
+{
+ t_uint8 slave_address_of_ab8500_codec;
+ t_ab8500_codec_direction ab8500_codec_direction;
+ t_ab8500_codec_mode ab8500_codec_mode_in;
+ t_ab8500_codec_mode ab8500_codec_mode_out;
+ t_ab8500_codec_audio_interface audio_interface;
+ t_ab8500_codec_src ab8500_codec_src;
+ t_ab8500_codec_dest ab8500_codec_dest;
+ t_uint8 in_left_volume;
+ t_uint8 in_right_volume;
+ t_uint8 out_left_volume;
+ t_uint8 out_right_volume;
+
+ t_ab8500_codec_configuration ab8500_codec_configuration;
+} t_ab8500_codec_system_context;
+#endif /* _AB8500_CODECP_H_ */
+
+/* End of file AB8500_CODECP.h */
+
+
diff --git a/arch/arm/mach-ux500/include/mach/ab8500_gpadc.h b/arch/arm/mach-ux500/include/mach/ab8500_gpadc.h
new file mode 100644
index 00000000000..150ff10173e
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/ab8500_gpadc.h
@@ -0,0 +1,28 @@
+/*
+ * ab8500_gpadc.c - AB8500 GPADC Driver
+ *
+ * Copyright (C) 2010 ST-Ericsson
+ * Licensed under GPLv2.
+ *
+ * Author: Arun R Murthy <arun.murthy@stericsson.com>
+ */
+
+#ifndef _AB8500_GPADC_H
+#define _Ab8500_GPADC_H
+
+/* GPADC source: From datasheer(ADCSwSel[4:0] in GPADCCtrl2) */
+#define BAT_CTRL 0x01
+#define ACC_DETECT1 0x04
+#define ACC_DETECT2 0x05
+#define MAIN_BAT_V 0x08
+#define BK_BAT_V 0x0C
+#define VBUS_V 0x09
+#define MAIN_CHARGER_V 0x03
+#define MAIN_CHARGER_C 0x0A
+#define USB_CHARGER_C 0x0B
+#define DIE_TEMP 0x0D
+#define BTEMP_BALL 0x02
+
+int ab8500_gpadc_conversion(int input);
+
+#endif /* _AB8500_GPADC_H */
diff --git a/arch/arm/mach-ux500/include/mach/av8100.h b/arch/arm/mach-ux500/include/mach/av8100.h
new file mode 100755
index 00000000000..a4afebf3c8c
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/av8100.h
@@ -0,0 +1,531 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms:
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __AV8100_H
+#define __AV8100_H
+
+#ifdef _cplusplus
+extern "C" {
+#endif /* _cplusplus */
+
+typedef enum av8100_error
+{
+ AV8100_OK = 0x0,
+ AV8100_INVALID_COMMAND = 0x1,
+ AV8100_INVALID_INTERFACE = 0x2,
+ AV8100_INVALID_IOCTL = 0x3,
+ AV8100_COMMAND_FAIL = 0x4,
+ AV8100_FWDOWNLOAD_FAIL = 0x5,
+ AV8100_FAIL = 0xFF,
+}av8100_error;
+
+typedef enum interface
+{
+ I2C_INTERFACE = 0x0,
+ DSI_INTERFACE = 0x1,
+}interface;
+
+/** AV8100 - DSI dcs command set */
+typedef enum
+{
+ DCS_VSYNC_START = 0x1,
+ DCS_VSYNC_END = 0x11,
+ DCS_HSYNC_START = 0x21,
+ DCS_HSYNC_END = 0x31,
+ DCS_SHORT_WRITE = 0x15,
+ DCS_LONG_WRITE = 0x39,
+ DCS_RGB565_PACKED = 0xE,
+ DCS_RGB666_PACKED = 0x1E,
+ DCS_RGB666_UNPACKED = 0x2E,
+ DCS_RGB888_PACKED = 0x3E,
+ DCS_RAM_WRITE = 0x3C,
+ DCS_RAM_WRITE_CONTINUE = 0x2C,
+ DCS_FW_DOWNLOAD = 0xDB,
+ DCS_WRITE_UC = 0xDC,
+ DCS_READ_UC = 0xDB,
+ DCS_NEXT_FILED_TYPE = 0xDA,
+ DCS_EXEC_UC = 0xDD,
+}dsi_dcs_command_type;
+
+/** AV8100 Operating modes */
+typedef enum
+{
+ AV8100_OPMODE_SHUTDOWN = 0x1,
+ AV8100_OPMODE_STANDBY,
+ AV8100_OPMODE_SCAN,
+ AV8100_OPMODE_INIT,
+ AV8100_OPMODE_IDLE,
+ AV8100_OPMODE_VIDEO
+}av8100_operating_mode;
+
+/** AV8100 status */
+#define AV8100_PLUGIN_NONE 0x00
+#define AV8100_HDMI_PLUGIN 0x01
+#define AV8100_CVBS_PLUGIN 0x02
+
+/** AV8100 Command Type */
+typedef enum
+{
+ AV8100_COMMAND_VIDEO_INPUT_FORMAT = 0x1,
+ AV8100_COMMAND_AUDIO_INPUT_FORMAT = 0x2,
+ AV8100_COMMAND_VIDEO_OUTPUT_FORMAT = 0x3,
+ AV8100_COMMAND_VIDEO_SCALING_FORMAT,
+ AV8100_COMMAND_COLORSPACECONVERSION,
+ AV8100_COMMAND_CEC_MESSAGEWRITE,
+ AV8100_COMMAND_CEC_MESSAGEREAD_BACK,
+ AV8100_COMMAND_DENC,
+ AV8100_COMMAND_HDMI,
+ AV8100_COMMAND_HDCP_SENDKEY,
+ AV8100_COMMAND_HDCP_MANAGEMENT,
+ AV8100_COMMAND_INFOFRAMES,
+ AV8100_COMMAND_EDID_SECTIONREADBACK,
+ AV8100_COMMAND_PATTERNGENERATOR,
+
+}av8100_command_type;
+
+/** AV8100 Command Type */
+typedef enum
+{
+ AV8100_COMMAND_VIDEO_INPUT_FORMAT_SIZE = 0x17,
+ AV8100_COMMAND_AUDIO_INPUT_FORMAT_SIZE = 0x8,
+ AV8100_COMMAND_VIDEO_OUTPUT_FORMAT_SIZE = 0x18,
+ AV8100_COMMAND_VIDEO_SCALING_FORMAT_SIZE = 0x9,
+ AV8100_COMMAND_COLORSPACECONVERSION_SIZE = 0x21,
+ AV8100_COMMAND_CEC_MESSAGEWRITE_SIZE = 0x14,
+ AV8100_COMMAND_CEC_MESSAGEREAD_BACK_SIZE = 0x14,
+ AV8100_COMMAND_DENC_SIZE = 0x5,
+ AV8100_COMMAND_HDMI_SIZE = 0x4,
+ AV8100_COMMAND_HDCP_SENDKEY_SIZE = 0x9,
+ AV8100_COMMAND_HDCP_MANAGEMENT_SIZE = 0x4,
+ AV8100_COMMAND_INFOFRAMES_SIZE = 0x22,
+ AV8100_COMMAND_EDID_SECTIONREADBACK_SIZE = 0x81,
+ AV8100_COMMAND_PATTERNGENERATOR_SIZE = 0x4,
+}av8100_command_size;
+
+/** AV8100 structures register & command definitions */
+
+/** AV8100 Internal registers ~ Register 0x0 to 0xF */
+/** Internal registers for I2C operations */
+
+typedef enum
+{
+ STANDBY_REG = 0x0,
+ AV8100_5_VOLT_TIME_REG = 0x1,
+ STANDBY_INTERRUPT_MASK_REG = 0x2,
+ STANDBY_PENDING_INTERRUPT_REG = 0x3,
+ GENERAL_INTERRUPT_MASK_REG = 0x4,
+ GENERAL_INTERRUPT_REG = 0x5,
+ GENERAL_STATUS_REG = 0x6,
+ GPIO_CONFIGURATION_REG = 0x7,
+ GENERAL_CONTROL_REG = 0x8,
+ FIRMWARE_DOWNLOAD_ENTRY_REG = 0xF
+}internal_reg;
+
+struct av8100_registers_internal
+{
+ volatile char standby;
+ volatile char av8100_5_volt_time;
+ volatile char standby_interrupt_mask;
+ volatile char standby_pending_interrupt;
+ volatile char general_interrupt_mask;
+ volatile char general_interrupt;
+ volatile char general_status;
+ volatile char gpio_configuration;
+ volatile char general_control;
+ volatile char firmware_download_entry;
+};
+
+/** AV8100 Video Input Format Command */
+struct av8100_video_input_format_command
+{
+
+ volatile char Identifier;
+ volatile char Mode;
+ volatile char Pixel_format;
+ volatile char Htotal[2];
+ volatile char Hactive[2];
+ volatile char Vtotal[2];
+ volatile char Vactive[2];
+ volatile char Videomode;
+ volatile char Number_DSI;
+ volatile char Virtualchannelcommandmode;
+ volatile char Virtualchannelvideomode;
+ volatile char Linenumber[2];
+ volatile char Tearingeffect;
+ volatile char Master_Clock_frequency[4];
+};
+
+/** AV8100 Audio Input Format Command */
+struct av8100_audio_input_format_command
+{
+
+ volatile char Identifier;
+ volatile char I2SOrTDM;
+ volatile char NumberofI2SentriesFreq;
+ volatile char BitFormat;
+ volatile char LPCMOrCompress;
+ volatile char SlaveOrMaster;
+ volatile char Mute;
+
+};
+
+/** AV8100 Video Output Format Command */
+struct av8100_video_output_format_command
+{
+
+ volatile char Identifier;
+ volatile char Formatter;
+ volatile char VSYNCpolarity;
+ volatile char HSYNCpolarity;
+ volatile char Htotal[2];
+ volatile char Hactive[2];
+ volatile char Vtotal[2];
+ volatile char Vactive[2];
+ volatile char HSYNCstart[2];
+ volatile char HSYNClength[2];
+ volatile char VSYNCstart[2];
+ volatile char VSYNClength[2];
+ volatile char Pixelfrequency[4];
+};
+
+/** AV8100 Video Video Scaling Format Command */
+struct av8100_video_scaling_format_command
+{
+ volatile char Identifier;
+ volatile char Hstart[2];
+ volatile char Hstop[2];
+ volatile char Vstart[2];
+ volatile char Vstop[2];
+};
+
+/** AV8100 Video Colorspace Conversion Command */
+struct av8100_colorspace_conversion_command
+{
+ volatile char Identifier;
+ volatile char C0[2];
+ volatile char C1[2];
+ volatile char C2[2];
+ volatile char C3[2];
+ volatile char C4[2];
+ volatile char C5[2];
+ volatile char C6[2];
+ volatile char C7[2];
+ volatile char C8[21];
+ volatile char AOFFSET[2];
+ volatile char BOFFSET[2];
+ volatile char COFFSET[2];
+ volatile char AMINIMUM;
+ volatile char AMAXIMUM;
+ volatile char BMINIMUM;
+ volatile char BMAXIMUM;
+ volatile char CMINIMUM;
+ volatile char CMAXIMUM;
+};
+
+/** AV8100 Video CEC message */
+struct av8100_CEC_message
+{
+ volatile char Identifier;
+ volatile char PhysicaladdressAB;
+ volatile char PhysicaladdressCD;
+ volatile char Bufferlength;
+ volatile char BufferData[16];
+};
+
+/** AV8100 Video CEC message Readback Command */
+struct av8100_CEC_message_readback_command
+{
+ volatile char Identifier;
+};
+
+/** AV8100 Video DENC Command */
+struct av8100_DENC_command
+{
+ volatile char Identifier;
+ volatile char CVBSvideoformatoutputchoice ;
+ volatile char Standardselection;
+ volatile char ON_OFF;
+ volatile char Macrovision_ON_OFF;
+};
+
+/** AV8100 Video HDMI Command */
+struct av8100_HDMI_command
+{
+ volatile char Identifier;
+ volatile char OFF_ON_AVMUTE;
+ volatile char HDMI_DVI;
+ volatile char DVIcontrolbit;
+};
+
+/** AV8100 Video HDCP sendkey Command */
+struct av8100_HDCP_sendkey_command
+{
+ volatile char Identifier;
+ volatile char Keynumber;
+ volatile char Key[7];
+};
+
+/** AV8100 Video HDCP management Command */
+struct av8100_HDCP_management_command
+{
+ volatile char Identifier;
+ volatile char RequestHDCPauthentication;
+ volatile char Requestencryptedtransmission;
+ volatile char OESS_EESS;
+};
+
+/** AV8100 Video Infoframe Command */
+struct av8100_Infoframe_command
+{
+ volatile char Identifier;
+ volatile char Infoframetype;
+ volatile char Infoframedata[30];
+ volatile char InfoframeCRC;
+};
+
+/** AV8100 Video EDID section readback Command */
+struct av8100_EDIDsectionreadback_command
+{
+ volatile char Identifier;
+ volatile char EDIDaddress;
+ volatile char EDIDblocknumber;
+};
+
+/** AV8100 Video Pattern Generator Command */
+struct av8100_PatternGenerator_command
+{
+ volatile char Identifier;
+ volatile char Testtypeselection;
+ volatile char VideoPatterngeneratorselection;
+ volatile char AudioSound;
+};
+
+/** AV8100 Video Command return */
+struct av8100_command_return
+{
+ volatile char Identifier;
+ volatile char OK_FAIL;
+};
+
+/** AV8100 Video CEC messgae readback command */
+struct av8100_EDID_section_readback
+{
+ volatile char Identifier;
+ volatile char OK_FAIL;
+ volatile char EDID[128];
+};
+
+typedef enum{
+ AV8100_AUDIO_I2S_MODE,
+ AV8100_AUDIO_I2SDELAYED_MODE, /* I2S Mode by default*/
+ AV8100_AUDIO_TDM_MODE /* 8 Channels by default*/
+} av8100_audio_if_format;
+
+typedef enum{
+ AV8100_AUDIO_MUTE_DISABLE,
+ AV8100_AUDIO_MUTE_ENABLE
+} av8100_audio_mute;
+
+typedef enum{
+ AV8100_AUDIO_SLAVE,
+ AV8100_AUDIO_MASTER
+} av8100_audio_if_mode;
+
+typedef enum{
+ AV8100_AUDIO_LPCM_MODE,
+ AV8100_AUDIO_COMPRESS_MODE
+} av8100_audio_format;
+
+typedef enum{
+ AV8100_AUDIO_16BITS,
+ AV8100_AUDIO_20BITS,
+ AV8100_AUDIO_24BITS
+} av8100_audio_word_length;
+
+typedef enum{
+ AV8100_AUDIO_FREQ_32KHZ,
+ AV8100_AUDIO_FREQ_44_1KHZ,
+ AV8100_AUDIO_FREQ_48KHZ,
+ AV8100_AUDIO_FREQ_64KHZ,
+ AV8100_AUDIO_FREQ_88_2KHZ,
+ AV8100_AUDIO_FREQ_96KHZ,
+ AV8100_AUDIO_FREQ_128KHZ,
+ AV8100_AUDIO_FREQ_176_1KHZ,
+ AV8100_AUDIO_FREQ_192KHZ
+} av8100_sample_freq;
+
+
+typedef enum{
+ AV8100_PATTERN_AUDIO_OFF,
+ AV8100_PATTERN_AUDIO_ON,
+ AV8100_PATTERN_AUDIO_I2S_MEM
+} av8100_pattern_audio;
+
+typedef enum{
+ AV8100_PATTERN_OFF,
+ AV8100_PATTERN_GENERATOR,
+ AV8100_PRODUCTION_TESTING
+} av8100_pattern_type;
+
+typedef enum{
+ AV8100_NO_PATTERN,
+ AV8100_PATTERN_VGA,
+ AV8100_PATTERN_720P,
+ AV8100_PATTERN_1080P
+} av8100_pattern_format;
+
+typedef enum{
+ AV8100_HDMI_OFF,
+ AV8100_HDMI_ON,
+ AV8100_HDMI_AVMUTE
+} av8100_hdmi_mode;
+
+typedef enum{
+ AV8100_HDMI,
+ AV8100_DVI
+} av8100_hdmi_format;
+
+typedef enum{
+ AV8100_DVI_CTRL_CTL0,
+ AV8100_DVI_CTRL_CTL1,
+ AV8100_DVI_CTRL_CTL2
+} av8100_DVI_format;
+
+typedef enum{
+ AV8100_SYNC_POSITIVE,
+ AV8100_SYNC_NEGATIVE
+} av8100_video_sync_pol;
+
+typedef enum{
+
+ AV8100_INPUT_PIX_RGB565,
+ AV8100_INPUT_PIX_RGB666,
+ AV8100_INPUT_PIX_RGB666P,
+ AV8100_INPUT_PIX_RGB888,
+ AV8100_INPUT_PIX_YCBCR422
+} av8100_pixel_format;
+
+typedef enum{
+ AV8100_TE_OFF, /* NO TE*/
+ AV8100_TE_DSI_LANE, /* TE generated on DSI lane */
+ AV8100_TE_IT_LINE, /* TE generated on IT line (GPIO) */
+ AV8100_TE_DSI_IT /* TE generatedon both DSI lane & IT line*/
+} av8100_te_config;
+
+typedef enum{
+
+ AV8100_DATA_LANES_USED_0, /* 0 DSI data lane connected*/
+ AV8100_DATA_LANES_USED_1, /* 1 DSI data lane connected */
+ AV8100_DATA_LANES_USED_2, /* 2 DSI data lane connected */
+ AV8100_DATA_LANES_USED_3, /* 3 DSI data lane connected */
+ AV8100_DATA_LANES_USED_4 /* 4 DSI data lane connected */
+} av8100_dsi_nb_data_lane;
+
+typedef enum{
+
+ AV8100_VIDEO_INTERLACE,
+ AV8100_VIDEO_PROGRESSIVE
+} av8100_video_mode;
+
+typedef enum{
+
+ AV8100_HDMI_DSI_OFF,
+ AV8100_HDMI_DSI_COMMAND_MODE,
+ AV8100_HDMI_DSI_VIDEO_MODE
+} av8100_dsi_mode;
+
+/* AV8100 video modes */
+typedef enum{
+ AV8100_CUSTOM,
+ AV8100_CEA1_640X480P_59_94HZ,
+ AV8100_CEA2_3_720X480P_59_94HZ, // new
+ AV8100_CEA4_1280X720P_60HZ,
+ AV8100_CEA5_1920X1080I_60HZ,
+ AV8100_CEA6_7_NTSC_60HZ, //new
+ AV8100_CEA14_15_480p_60HZ, //new
+ AV8100_CEA16_1920X1080P_60HZ, //new
+ AV8100_CEA17_18_720X576P_50HZ, //new
+ AV8100_CEA19_1280X720P_50HZ,
+ AV8100_CEA20_1920X1080I_50HZ,
+ AV8100_CEA21_22_576I_PAL_50HZ, //new
+ AV8100_CEA29_30_576P_50HZ, //new
+ AV8100_CEA31_1920x1080P_50Hz, //new
+ AV8100_CEA32_1920X1080P_24HZ,
+ AV8100_CEA33_1920X1080P_25HZ,
+ AV8100_CEA34_1920X1080P_30HZ,
+ AV8100_CEA60_1280X720P_24HZ,
+ AV8100_CEA61_1280X720P_25HZ,
+ AV8100_CEA62_1280X720P_30HZ,
+ AV8100_VESA9_800X600P_60_32HZ,
+ AV8100_VESA14_848X480P_60HZ,
+ AV8100_VESA16_1024X768P_60HZ,
+ AV8100_VESA22_1280X768P_59_99HZ,
+ AV8100_VESA23_1280X768P_59_87HZ,
+ AV8100_VESA27_1280X800P_59_91HZ,
+ AV8100_VESA28_1280X800P_59_81HZ,
+ AV8100_VESA39_1360X768P_60_02HZ,
+ AV8100_VESA81_1366X768P_59_79HZ,
+ AV8100_VIDEO_OUTPUT_CEA_VESA_MAX
+} av8100_output_CEA_VESA;
+
+/** AV8100 internal register access structure*/
+struct av8100_register
+{
+ char value;
+ char offset;
+};
+
+/** AV8100 command configuration registers access structure*/
+struct av8100_command_register
+{
+ unsigned char cmd_id; /* input */
+ unsigned char buf_len; /* input, output */
+ unsigned char buf[128]; /* input, output */
+ unsigned char return_status; /* output */
+};
+
+/* IOCTL return status */
+#define HDMI_COMMAND_RETURN_STATUS_OK 0
+#define HDMI_COMMAND_RETURN_STATUS_FAIL 1
+
+#define HDMI_REQUEST_FOR_REVOCATION_LIST_INPUT 2
+#define HDMI_CEC_MESSAGE_READBACK_MAXSIZE 16
+
+/** AV8100 status structure*/
+struct av8100_status
+{
+ char av8100_state;
+ char av8100_plugin_status;
+};
+
+/** Maximum size of the structure need to passed to AV8100 */
+
+#define AV8100_IOC_MAGIC 0xcc
+
+/** IOCTL Operations for accessing information from AV8100 */
+
+#define IOC_AV8100_READ_REGISTER _IOWR(AV8100_IOC_MAGIC,1,struct av8100_register)
+#define IOC_AV8100_WRITE_REGISTER _IOWR(AV8100_IOC_MAGIC,2,struct av8100_register)
+#define IOC_AV8100_SEND_CONFIGURATION_COMMAND _IOWR(AV8100_IOC_MAGIC,3,struct av8100_command_register)
+//#define IOC_AV8100_READ_CONFIGURATION_COMMAND _IOWR(AV8100_IOC_MAGIC,4,struct av8100_command_register)
+#define IOC_AV8100_GET_STATUS _IOWR(AV8100_IOC_MAGIC,4,struct av8100_status)
+#define IOC_AV8100_ENABLE _IOWR(AV8100_IOC_MAGIC,5,struct av8100_status)
+#define IOC_AV8100_DISABLE _IOWR(AV8100_IOC_MAGIC,6,struct av8100_status)
+#define IOC_AV8100_SET_VIDEO_FORMAT _IOWR(AV8100_IOC_MAGIC,7,struct av8100_status)
+#define IOC_AV8100_HDMI_ON _IOWR(AV8100_IOC_MAGIC,8,struct av8100_status)
+#define IOC_AV8100_HDMI_OFF _IOWR(AV8100_IOC_MAGIC,9,struct av8100_status)
+
+#define AV8100_IOC_MAXNR (1)
+
+#ifdef _cplusplus
+}
+#endif /* _cplusplus */
+
+#endif /* !defined(__AV8100_H) */
diff --git a/arch/arm/mach-ux500/include/mach/av8100_fw.h b/arch/arm/mach-ux500/include/mach/av8100_fw.h
new file mode 100755
index 00000000000..94c913dddb5
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/av8100_fw.h
@@ -0,0 +1,1050 @@
+/*---------------------------------------------------------------------------*/
+/* © copyright STEricsson,2009. All rights reserved. For */
+/* information, STEricsson reserves the right to license */
+/* this software concurrently under separate license conditions. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it */
+/* under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, */
+/* or (at your option)any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */
+/* the GNU Lesser General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*---------------------------------------------------------------------------*/
+
+/* AV8100 Firmware version : V3.02 */
+#define fw_size 16384
+char ReceiveTab[fw_size];
+char TransmitTab[fw_size];
+char av8100_fw_buff[fw_size] = {
+0x80,0xfe,0xcb,0xfe,0xbc,0xc2,0x73,0xc4,0x73,0xc4,0xc9,0xc5,0x72,0xc3,0xce,0xc5,
+0x16,0xc7,0xd0,0xc8,0xe5,0xc8,0xf6,0xc8,0x08,0xc9,0x1b,0xc9,0x20,0xc9,0x25,0xc9,
+0x2a,0xc9,0x2f,0xc9,0x44,0xc9,0x7e,0xc9,0xfa,0xc9,0xb6,0xc2,0xb6,0xc2,0xb7,0xc2,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x81,0xea,0xad,0xec,0xad,
+0x38,0x20,0x1b,0x72,0x80,0x81,0x4d,0x51,0x4d,0x51,0x4d,0x51,0x4d,0x51,0x4d,0x51,
+0x4d,0x51,0xb4,0x20,0xf4,0x2a,0x5a,0x90,0x82,0xfe,0xcd,0x80,0x00,0xaf,0x72,0x93,
+0xa3,0x20,0x5f,0x90,0x80,0x80,0x97,0x90,0x8d,0x20,0x0f,0xab,0x01,0xa6,0x88,0x89,
+0x90,0x96,0xad,0x97,0x90,0x9a,0xad,0x8b,0x93,0x9e,0xad,0x97,0x90,0xa2,0xad,0x80,
+0xb7,0xa6,0xad,0x81,0xb7,0xaa,0xad,0x82,0xb7,0xae,0xad,0x26,0x31,0x20,0x08,0x72,
+0x82,0xb7,0x21,0xa6,0x81,0xb7,0xc2,0xa6,0x80,0xb7,0x01,0xa6,0xb4,0x20,0xf5,0x2a,
+0x5a,0x90,0x80,0x00,0xa7,0x72,0x93,0xcc,0xad,0x49,0x27,0x97,0x90,0x5d,0x90,0xd4,
+0xad,0x82,0xb7,0xd8,0xad,0x81,0xb7,0xdc,0xad,0x80,0xb7,0xe0,0xad,0xff,0xae,0x90,
+0x81,0x59,0x29,0xea,0x26,0x5a,0xfb,0x38,0x20,0x07,0x72,0x4d,0x38,0x20,0x1a,0x72,
+0x49,0x00,0x38,0x20,0x05,0x72,0xbc,0xff,0xcd,0x08,0xae,0xf3,0x20,0x79,0x24,0x49,
+0x44,0x24,0x49,0x23,0x24,0x49,0x0b,0xad,0x82,0xfe,0xcd,0x9e,0x82,0xfe,0xcd,0x9f,
+0x5b,0x82,0xfe,0xcd,0x80,0xb6,0x82,0xfe,0xcd,0x81,0xb6,0x82,0xfe,0xcd,0x82,0xb6,
+0x82,0xad,0x9f,0x90,0x86,0xad,0x85,0x90,0x84,0x42,0x8c,0x20,0x9f,0x90,0x01,0xab,
+0x0f,0xa6,0x2a,0x31,0x20,0x08,0x72,0xfb,0x38,0x20,0x07,0x72,0x4d,0x38,0x20,0x1a,
+0x72,0xbc,0xff,0xcd,0xfb,0x38,0x20,0x07,0x72,0x30,0x20,0x10,0x72,0x31,0x20,0x1e,
+0x72,0x30,0x20,0x1c,0x72,0x95,0x05,0xa0,0x9e,0x52,0xc0,0xcc,0x5f,0x90,0x5f,0x4f,
+0x07,0x38,0x20,0x05,0x72,0x0c,0x39,0x20,0x05,0x72,0x81,0x41,0x29,0x38,0x20,0x18,
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+0x4d,0xae,0xff,0xcd,0x4d,0xae,0xff,0xcd,0x38,0x20,0x1b,0x72,0x4d,0x4d,0x4d,0x4d,
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+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x81,0xa5,0xbe,0x84,0xa3,
+0xb7,0xa4,0xd6,0x92,0x5c,0xa2,0xb7,0xa4,0xd6,0x92,0x5c,0xa1,0xb7,0xa4,0xd6,0x92,
+0x01,0xae,0xa0,0xb7,0xa4,0xc6,0x92,0x88,0xa5,0xbf,0x81,0xa0,0xb7,0xa4,0xc2,0x92,
+0xa0,0xb6,0xa1,0xb7,0xa4,0xd2,0x92,0x5a,0xa1,0xb6,0xa2,0xb7,0xa4,0xd2,0x92,0x5a,
+0xa2,0xb6,0xa3,0xb7,0xa4,0xd0,0x92,0xa3,0xb6,0x03,0xae,0xa5,0xbf,0x81,0xa3,0xb7,
+0xa4,0xda,0x92,0x5c,0xa3,0xb6,0xa2,0xb7,0xa4,0xda,0x92,0x5c,0xa2,0xb6,0xa1,0xb7,
+0xa4,0xda,0x92,0x01,0xae,0xa1,0xb6,0xa0,0xb7,0xa4,0xca,0x92,0xa0,0xb6,0xa5,0xbf,
+0x81,0xa5,0xbe,0xe9,0x26,0x4a,0xa4,0x00,0x66,0x72,0x5c,0xa4,0x00,0x66,0x72,0x5c,
+0xa4,0x00,0x66,0x72,0x01,0xae,0xa4,0x00,0x34,0x72,0xa5,0xbf,0x1b,0x27,0x4d,0xb1,
+0xfa,0xcc,0xa0,0xfb,0xcd,0x81,0xa5,0xbe,0xe9,0x26,0x4a,0xa4,0x00,0x39,0x72,0xa4,
+0x00,0x69,0x72,0x5a,0xa4,0x00,0x69,0x72,0x5a,0xa4,0x00,0x68,0x72,0x03,0xae,0xa5,
+0xbf,0x1b,0x27,0x4d,0x81,0xa0,0xb7,0xa4,0xc9,0x92,0xa0,0xb6,0xa1,0xb7,0xa4,0xd9,
+0x92,0x5a,0xa1,0xb6,0xa2,0xb7,0xa4,0xd9,0x92,0x5a,0xa2,0xb6,0xa3,0xb7,0xa4,0xdb,
+0x92,0xa3,0xb6,0x03,0xae,0xa5,0xbf,0xb1,0xfa,0xcc,0x39,0xfb,0xcd,0x81,0x01,0xa6,
+0x02,0x20,0xff,0xa6,0x04,0x24,0x08,0x27,0xa4,0xd1,0x92,0xa3,0xb6,0xa5,0x3c,0x09,
+0x26,0xa4,0xd1,0x92,0xa2,0xb6,0xa5,0x3c,0x12,0x26,0xa4,0xd1,0x92,0xa1,0xb6,0xa5,
+0x3c,0x23,0x26,0xa4,0xd1,0x92,0xa0,0xb6,0xa5,0x3f,0x81,0xa0,0x3c,0x02,0x24,0xa1,
+0xb7,0xa1,0xb9,0x9f,0xa2,0xb7,0xa2,0xbb,0x42,0x93,0x0f,0x27,0x4d,0x84,0xf7,0xfa,
+0xcd,0xa8,0xb6,0x05,0x27,0xa7,0xbe,0xa3,0xb7,0xa2,0xbf,0x42,0x93,0xa8,0xb6,0xa1,
+0xb7,0xa0,0xbf,0x42,0xa7,0xb6,0x89,0xa8,0xb7,0x81,0xa0,0x3f,0xa1,0x3f,0xa2,0xbf,
+0xa3,0xb7,0x81,0xa5,0xbe,0x84,0xa4,0xd7,0x92,0xa3,0xb6,0x5c,0xa4,0xd7,0x92,0xa2,
+0xb6,0x5c,0xa4,0xd7,0x92,0xa1,0xb6,0x01,0xae,0xa4,0xc7,0x92,0xa0,0xb6,0x88,0xa5,
+0xbf,0x81,0xa5,0xbe,0xa4,0xd7,0x92,0xa3,0xb6,0x5c,0xa4,0xd7,0x92,0xa2,0xb6,0x5c,
+0xa4,0xd7,0x92,0xa1,0xb6,0x01,0xae,0xa4,0xc7,0x92,0xa0,0xb6,0xa5,0xbf,0x81,0x01,
+0xa6,0x02,0x27,0x03,0x6d,0x04,0x26,0x02,0x6d,0x08,0x26,0x01,0x6d,0x0e,0x26,0x7d,
+0x81,0x84,0xa3,0xb7,0x03,0xe6,0xa2,0xb7,0x02,0xe6,0xa1,0xb7,0x01,0xe6,0xa0,0xb7,
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+0x72,0x11,0x3f,0x10,0x3f,0x08,0x01,0x5f,0x72,0x56,0x01,0x5f,0x72,0x57,0x01,0x5f,
+0x72,0x7b,0x01,0x5f,0x72,0x7c,0x01,0xff,0x35,0x7e,0x01,0x5f,0x72,0x76,0x01,0x5f,
+0x72,0x9b,0x06,0x20,0x5f,0x72,0x88,0x81,0x84,0xe3,0xad,0xf4,0x25,0x40,0xa1,0x01,
+0x6b,0x4c,0x12,0x6f,0x01,0xee,0x72,0x01,0x6b,0x4f,0x88,0x81,0x05,0x20,0x10,0x72,
+0x15,0x20,0x11,0x72,0x10,0x1e,0x98,0xc2,0xcc,0x8b,0xff,0xa6,0x04,0xae,0x81,0x85,
+0x01,0x7b,0x9a,0x56,0x01,0xc7,0x0f,0xa4,0x56,0x01,0xc6,0x58,0x01,0x4f,0x72,0x56,
+0x01,0x5c,0x72,0x01,0x6b,0x58,0x01,0xd6,0x56,0x01,0xce,0x18,0x27,0x56,0x01,0xc1,
+0x57,0x01,0xc6,0x9b,0x01,0x6b,0x4f,0x88,0x81,0x84,0x9a,0x57,0x01,0xc7,0x0f,0xa4,
+0x57,0x01,0xc6,0x58,0x01,0xd7,0x57,0x01,0x5c,0x72,0x57,0x01,0xce,0x01,0x7b,0x14,
+0x27,0x01,0xe1,0x72,0x58,0x01,0xd6,0x97,0x0f,0xa4,0x4a,0x57,0x01,0xc6,0x9b,0x88,
+};
+
diff --git a/arch/arm/mach-ux500/include/mach/av8100_p.h b/arch/arm/mach-ux500/include/mach/av8100_p.h
new file mode 100755
index 00000000000..f3254cebbf9
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/av8100_p.h
@@ -0,0 +1,188 @@
+/*---------------------------------------------------------------------------*/
+/* © copyright STEricsson,2009. All rights reserved. For */
+/* information, STEricsson reserves the right to license */
+/* this software concurrently under separate license conditions. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it */
+/* under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, */
+/* or (at your option)any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */
+/* the GNU Lesser General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*---------------------------------------------------------------------------*/
+
+#include <mach/av8100.h>
+
+/* defines for av8100_ */
+#define av8100_command_offset 0x10
+#define AV8100_COMMAND_MAX_LENGTH 0x81
+#define GPIO_AV8100_RSTN 196
+#define GPIO_AV8100_INT 192
+#define AV8100_DRIVER_MINOR_NUMBER 240
+
+
+#define HDMI_HOTPLUG_INTERRUPT 0x1
+#define HDMI_HOTPLUG_INTERRUPT_MASK 0xFE
+#define CVBS_PLUG_INTERRUPT 0x2
+#define CVBS_PLUG_INTERRUPT_MASK 0xFD
+#define TE_INTERRUPT_MASK 0x40
+#define UNDER_OVER_FLOW_INTERRUPT_MASK 0x20
+
+#define REG_16_8_LSB(p) (unsigned char)(p & 0xFF)
+#define REG_16_8_MSB(p) (unsigned char)((p & 0xFF00)>>8)
+#define REG_32_8_MSB(p) (unsigned char)((p & 0xFF000000)>>24)
+#define REG_32_8_MMSB(p) (unsigned char)((p & 0x00FF0000)>>16)
+#define REG_32_8_MLSB(p) (unsigned char)((p & 0x0000FF00)>>8)
+#define REG_32_8_LSB(p) (unsigned char)(p & 0x000000FF)
+
+/**
+ * struct av8100_cea - CEA(consumer electronic access) standard structure
+ * @cea_id:
+ * @cea_nb:
+ * @vtotale:
+ **/
+
+ typedef struct {
+ char cea_id[40] ;
+ int cea_nb ;
+ int vtotale;
+ int vactive;
+ int vsbp ;
+ int vslen ;
+ int vsfp;
+ char vpol[5];
+ int htotale;
+ int hactive;
+ int hbp ;
+ int hslen ;
+ int hfp;
+ int frequence;
+ char hpol[5];
+ int reg_line_duration;
+ int blkoel_duration;
+ int uix4;
+ int pll_mult;
+ int pll_div;
+}av8100_cea;
+
+/**
+ * struct av8100_data - av8100_ internal structure
+ * @client: pointer to i2c client
+ * @work: work_struct scheduled during bottom half
+ * @sem: semaphore used for data protection
+ * @device_type: hdmi or cvbs
+ * @edid: extended display identification data
+ **/
+struct av8100_data{
+ struct i2c_client *client;
+ struct work_struct work;
+ struct semaphore sem;
+ char device_type;
+ char edid[127];
+};
+
+/**
+ * struct av8100_platform_data - av8100_ platform data
+ * @irq: irq num
+ **/
+struct av8100_platform_data {
+ unsigned gpio_base;
+ int irq;
+};
+/**
+ * struct av8100_video_input_format_cmd - video input format structure
+ * @dsi_input_mode:
+ * @input_pixel_format:
+ * @total_horizontal_pixel:
+ **/
+typedef struct {
+ av8100_dsi_mode dsi_input_mode;
+ av8100_pixel_format input_pixel_format;
+ unsigned short total_horizontal_pixel; /*number of total horizontal pixels in the frame*/
+ unsigned short total_horizontal_active_pixel; /*number of total horizontal active pixels in the frame*/
+ unsigned short total_vertical_lines; /*number of total vertical lines in the frame*/
+ unsigned short total_vertical_active_lines; /*number of total vertical active lines*/
+ av8100_video_mode video_mode;
+ av8100_dsi_nb_data_lane nb_data_lane;
+ unsigned char nb_virtual_ch_command_mode;
+ unsigned char nb_virtual_ch_video_mode;
+ unsigned short TE_line_nb; /* Tearing effect line number*/
+ av8100_te_config TE_config;
+ unsigned long master_clock_freq; /* Master clock frequency in HZ */
+} av8100_video_input_format_cmd;
+/**
+ * struct av8100_video_output_format_cmd - video output format structure
+ * @dsi_input_mode:
+ * @input_pixel_format:
+ * @total_horizontal_pixel:
+ **/
+typedef struct {
+ av8100_output_CEA_VESA video_output_cea_vesa;
+ av8100_video_sync_pol vsync_polarity;
+ av8100_video_sync_pol hsync_polarity;
+ unsigned short total_horizontal_pixel; /*number of total horizontal pixels in the frame*/
+ unsigned short total_horizontal_active_pixel; /*number of total horizontal active pixels in the frame*/
+ unsigned short total_vertical_in_half_lines; /*number of total vertical lines in the frame*/
+ unsigned short total_vertical_active_in_half_lines; /*number of total vertical active lines*/
+ unsigned short hsync_start_in_pixel;
+ unsigned short hsync_length_in_pixel;
+ unsigned short vsync_start_in_half_line;
+ unsigned short vsync_length_in_half_line;
+ unsigned long pixel_clock_freq_Hz;
+} av8100_video_output_format_cmd;
+/**
+ * struct av8100_pattern_generator_cmd - pattern generator format structure
+ * @pattern_type:
+ * @pattern_video_format:
+ * @pattern_audio_mode:
+ **/
+typedef struct {
+ av8100_pattern_type pattern_type;
+ av8100_pattern_format pattern_video_format;
+ av8100_pattern_audio pattern_audio_mode;
+} av8100_pattern_generator_cmd;
+/**
+ * struct av8100_audio_input_format_cmd - audio input format structure
+ * @audio_input_if_format:
+ * @i2s_input_nb:
+ * @sample_audio_freq:
+ **/
+typedef struct {
+ av8100_audio_if_format audio_input_if_format; /* mode of the MSP*/
+ unsigned char i2s_input_nb; /* 0, 1 2 3 4*/
+ av8100_sample_freq sample_audio_freq;
+ av8100_audio_word_length audio_word_lg;
+ av8100_audio_format audio_format;
+ av8100_audio_if_mode audio_if_mode;
+ av8100_audio_mute audio_mute;
+} av8100_audio_input_format_cmd;
+/**
+ * struct av8100_video_scaling_format_cmd - video scaling format structure
+ * @h_start_in_pixel:
+ * @h_stop_in_pixel:
+ * @v_start_in_line:
+ **/
+typedef struct {
+ unsigned short h_start_in_pixel;
+ unsigned short h_stop_in_pixel;
+ unsigned short v_start_in_line;
+ unsigned short v_stop_in_line;
+} av8100_video_scaling_format_cmd;
+/**
+ * struct av8100_hdmi_cmd - hdmi command structure
+ * @hdmi_mode:
+ * @hdmi_format:
+ * @dvi_format:
+ **/
+typedef struct {
+ av8100_hdmi_mode hdmi_mode;
+ av8100_hdmi_format hdmi_format;
+ av8100_DVI_format dvi_format; /* used only if HDMI_format = DVI*/
+} av8100_hdmi_cmd;
+/* STWav8100 Private functions */
diff --git a/arch/arm/mach-ux500/include/mach/bit_mask.h b/arch/arm/mach-ux500/include/mach/bit_mask.h
new file mode 100755
index 00000000000..9487dff5242
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/bit_mask.h
@@ -0,0 +1,110 @@
+/*---------------------------------------------------------------------------*/
+/* Copyright (C) STEricsson 2009. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it */
+/* under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, */
+/* or (at your option)any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */
+/* the GNU Lesser General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*---------------------------------------------------------------------------*/
+
+#ifndef _BITMASK_H_
+#define _BITMASK_H_
+
+/*-----------------------------------------------------------------------------
+ * Bit mask definition
+ *---------------------------------------------------------------------------*/
+#define TRUE 0x1
+#define FALSE 0x0
+#define MASK_NULL8 0x00
+#define MASK_NULL16 0x0000
+#define MASK_NULL32 0x00000000
+#define MASK_ALL8 0xFF
+#define MASK_ALL16 0xFFFF
+#define MASK_ALL32 0xFFFFFFFF
+
+#define MASK_BIT0 (1UL<<0)
+#define MASK_BIT1 (1UL<<1)
+#define MASK_BIT2 (1UL<<2)
+#define MASK_BIT3 (1UL<<3)
+#define MASK_BIT4 (1UL<<4)
+#define MASK_BIT5 (1UL<<5)
+#define MASK_BIT6 (1UL<<6)
+#define MASK_BIT7 (1UL<<7)
+#define MASK_BIT8 (1UL<<8)
+#define MASK_BIT9 (1UL<<9)
+#define MASK_BIT10 (1UL<<10)
+#define MASK_BIT11 (1UL<<11)
+#define MASK_BIT12 (1UL<<12)
+#define MASK_BIT13 (1UL<<13)
+#define MASK_BIT14 (1UL<<14)
+#define MASK_BIT15 (1UL<<15)
+#define MASK_BIT16 (1UL<<16)
+#define MASK_BIT17 (1UL<<17)
+#define MASK_BIT18 (1UL<<18)
+#define MASK_BIT19 (1UL<<19)
+#define MASK_BIT20 (1UL<<20)
+#define MASK_BIT21 (1UL<<21)
+#define MASK_BIT22 (1UL<<22)
+#define MASK_BIT23 (1UL<<23)
+#define MASK_BIT24 (1UL<<24)
+#define MASK_BIT25 (1UL<<25)
+#define MASK_BIT26 (1UL<<26)
+#define MASK_BIT27 (1UL<<27)
+#define MASK_BIT28 (1UL<<28)
+#define MASK_BIT29 (1UL<<29)
+#define MASK_BIT30 (1UL<<30)
+#define MASK_BIT31 (1UL<<31)
+
+/*-----------------------------------------------------------------------------
+ * quartet shift definition
+ *---------------------------------------------------------------------------*/
+#define MASK_QUARTET (0xFUL)
+#define SHIFT_QUARTET0 0
+#define SHIFT_QUARTET1 4
+#define SHIFT_QUARTET2 8
+#define SHIFT_QUARTET3 12
+#define SHIFT_QUARTET4 16
+#define SHIFT_QUARTET5 20
+#define SHIFT_QUARTET6 24
+#define SHIFT_QUARTET7 28
+#define MASK_QUARTET0 (MASK_QUARTET << SHIFT_QUARTET0)
+#define MASK_QUARTET1 (MASK_QUARTET << SHIFT_QUARTET1)
+#define MASK_QUARTET2 (MASK_QUARTET << SHIFT_QUARTET2)
+#define MASK_QUARTET3 (MASK_QUARTET << SHIFT_QUARTET3)
+#define MASK_QUARTET4 (MASK_QUARTET << SHIFT_QUARTET4)
+#define MASK_QUARTET5 (MASK_QUARTET << SHIFT_QUARTET5)
+#define MASK_QUARTET6 (MASK_QUARTET << SHIFT_QUARTET6)
+#define MASK_QUARTET7 (MASK_QUARTET << SHIFT_QUARTET7)
+
+/*-----------------------------------------------------------------------------
+ * Byte shift definition
+ *---------------------------------------------------------------------------*/
+#define MASK_BYTE (0xFFUL)
+#define SHIFT_BYTE0 0
+#define SHIFT_BYTE1 8
+#define SHIFT_BYTE2 16
+#define SHIFT_BYTE3 24
+#define MASK_BYTE0 (MASK_BYTE << SHIFT_BYTE0)
+#define MASK_BYTE1 (MASK_BYTE << SHIFT_BYTE1)
+#define MASK_BYTE2 (MASK_BYTE << SHIFT_BYTE2)
+#define MASK_BYTE3 (MASK_BYTE << SHIFT_BYTE3)
+
+/*-----------------------------------------------------------------------------
+ * Halfword shift definition
+ *---------------------------------------------------------------------------*/
+#define MASK_HALFWORD (0xFFFFUL)
+#define SHIFT_HALFWORD0 0
+#define SHIFT_HALFWORD1 16
+#define MASK_HALFWORD0 (MASK_HALFWORD << SHIFT_HALFWORD0)
+#define MASK_HALFWORD1 (MASK_HALFWORD << SHIFT_HALFWORD1)
+
+#endif
+
diff --git a/arch/arm/mach-ux500/include/mach/bits.h b/arch/arm/mach-ux500/include/mach/bits.h
new file mode 100755
index 00000000000..0f0e4edd1cc
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/bits.h
@@ -0,0 +1,64 @@
+/*----------------------------------------------------------------------------------*/
+/* copyright STMicroelectronics, 2007. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it under */
+/* the terms of the GNU General Public License as published by the Free */
+/* Software Foundation; either version 2.1 of the License, or (at your option) */
+/* any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but WITHOUT */
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS */
+/* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*----------------------------------------------------------------------------------*/
+
+
+
+/* DO NOT EDIT!! - this file automatically generated
+ * from .s file by awk -f s2h.awk
+ */
+/* Bit field definitions
+ * Copyright (C) ARM Limited 1998. All rights reserved.
+ */
+
+#ifndef __bits_h
+#define __bits_h 1
+
+#define BIT0 0x00000001
+#define BIT1 0x00000002
+#define BIT2 0x00000004
+#define BIT3 0x00000008
+#define BIT4 0x00000010
+#define BIT5 0x00000020
+#define BIT6 0x00000040
+#define BIT7 0x00000080
+#define BIT8 0x00000100
+#define BIT9 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+
+#endif
+
+/* END */
diff --git a/arch/arm/mach-ux500/include/mach/clkdev.h b/arch/arm/mach-ux500/include/mach/clkdev.h
new file mode 100755
index 00000000000..04b37a89801
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
new file mode 100644
index 00000000000..474f6d3d968
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_DB5500_REGS_H
+#define __MACH_DB5500_REGS_H
+
+#define U5500_PER1_BASE 0xA0020000
+#define U5500_PER2_BASE 0xA0010000
+#define U5500_PER3_BASE 0x80140000
+#define U5500_PER4_BASE 0x80150000
+#define U5500_PER5_BASE 0x80100000
+#define U5500_PER6_BASE 0x80120000
+
+#define U5500_GIC_DIST_BASE 0xA0411000
+#define U5500_GIC_CPU_BASE 0xA0410100
+#define U5500_DMA_BASE 0x90030000
+#define U5500_MCDE_BASE 0xA0400000
+#define U5500_MODEM_BASE 0xB0000000
+#define U5500_L2CC_BASE 0xA0412000
+#define U5500_SCU_BASE 0xA0410000
+#define U5500_DSI1_BASE 0xA0401000
+#define U5500_DSI2_BASE 0xA0402000
+#define U5500_SIA_BASE 0xA0100000
+#define U5500_SVA_BASE 0x80200000
+#define U5500_HSEM_BASE 0xA0000000
+#define U5500_NAND0_BASE 0x60000000
+#define U5500_NAND1_BASE 0x70000000
+#define U5500_TWD_BASE 0xa0410600
+#define U5500_B2R2_BASE 0xa0200000
+
+#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000)
+#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000)
+#define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000)
+#define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000)
+#define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000)
+#define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000)
+#define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000)
+#define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000)
+
+#define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000)
+#define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000)
+#define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000)
+
+#define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000)
+#define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000)
+#define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000)
+#define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000)
+
+#define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000)
+#define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000)
+#define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000)
+#define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000)
+#define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000)
+#define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000)
+#define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000)
+#define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000)
+#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000)
+#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000)
+#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000)
+
+#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000)
+#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000)
+#define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000)
+#define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000)
+#define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000)
+#define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000)
+#define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000)
+#define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000)
+#define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000)
+#define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000)
+#define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000)
+#define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000)
+#define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000)
+#define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000)
+#define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000)
+#define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000)
+#define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000)
+
+#define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000)
+#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000)
+#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000)
+#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000)
+#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5000)
+#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000)
+#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000)
+#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000)
+#define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000)
+#define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000)
+#define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000)
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
new file mode 100644
index 00000000000..e3d62b94ffc
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_DB8500_REGS_H
+#define __MACH_DB8500_REGS_H
+
+#define U8500_PER3_BASE 0x80000000
+#define U8500_STM_BASE 0x80100000
+#define U8500_STM_REG_BASE (U8500_STM_BASE+0xF000)
+#define U8500_PER2_BASE 0x80110000
+#define U8500_PER1_BASE 0x80120000
+#define U8500_B2R2_BASE 0x80130000
+#define U8500_HSEM_BASE 0x80140000
+#define U8500_PER4_BASE 0x80150000
+
+#define U8500_PER6_BASE 0xa03c0000
+#define U8500_PER5_BASE 0xa03e0000
+#define U8500_PER7_BASE_ED 0xa03d0000
+
+#define U8500_SVA_BASE 0xa0100000
+#define U8500_SIA_BASE 0xa0200000
+
+#define U8500_SGA_BASE 0xa0300000
+#define U8500_MCDE_BASE 0xa0350000
+#define U8500_DMA_BASE_ED 0xa0362000
+#define U8500_DMA_BASE 0x801C0000 /* v1 */
+
+#define U8500_SCU_BASE 0xa0410000
+#define U8500_GIC_CPU_BASE 0xa0410100
+#define U8500_TWD_BASE 0xa0410600
+#define U8500_GIC_DIST_BASE 0xa0411000
+#define U8500_L2CC_BASE 0xa0412000
+
+#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
+#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000)
+#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000)
+#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000)
+
+/* per7 base addressess */
+#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000)
+#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000)
+#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000)
+#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000)
+#define U8500_CLKRST7_BASE (U8500_PER7_BASE_ED + 0xf000)
+
+#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
+#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
+
+/* per6 base addressess */
+#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
+#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
+#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
+#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */
+#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */
+#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */
+#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
+#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
+#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
+
+/* per5 base addressess */
+#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
+#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
+
+/* per4 base addressess */
+#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000)
+#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000)
+#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000)
+#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000)
+#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000)
+#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
+#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
+#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000)
+
+/* per3 base addresses */
+#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
+#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
+#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
+#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
+#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
+#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
+#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
+#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
+#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
+
+/* per2 base addressess */
+#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
+#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
+#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
+#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
+#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
+#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
+#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
+#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
+#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
+#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
+#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
+#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
+
+/* per1 base addresses */
+#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
+#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
+#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
+#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
+#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
+#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
+#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000)
+#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000)
+#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
+
+#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
new file mode 100755
index 00000000000..9cec503ff01
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * Debugging macro include header
+ *
+ * Copyright (C) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <mach/hardware.h>
+
+ .macro addruart,rx
+ mrc p15, 0, \rx, c1, c0
+ tst \rx, #1 @MMU enabled?
+ ldreq \rx, =UX500_UART2_BASE @ no, physical address
+ ldrne \rx, =IO_ADDRESS(UX500_UART2_BASE) @ yes, virtual address
+ .endm
+
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ux500/include/mach/debug.h b/arch/arm/mach-ux500/include/mach/debug.h
new file mode 100755
index 00000000000..3567d7f5b38
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/debug.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2009 STMicroelectronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+#ifndef __INC_DBG_H
+#define __INC_DBG_H
+
+/* Store a submitter ID, unique for each HCL. */
+
+struct driver_debug_st {
+ int mtd;
+ int gpio;
+ int mmc;
+ int ssp;
+ int mtu;
+ int msp;
+ int spi;
+ int touch;
+ int dma;
+ int rtc;
+ int acodec;
+ int tourg;
+ int alsa;
+ int keypad;
+ int mcde;
+ int power;
+ int i2c;
+ int hsi;
+};
+
+#define stm_error(format, arg...) printk(KERN_ERR DRIVER_DEBUG_PFX ":ERROR " format "\n" , ## arg)
+#define stm_warn(format, arg...) printk(KERN_WARNING DRIVER_DEBUG_PFX ":WARNING " format "\n" , ## arg)
+#define stm_info(format, arg...) printk(KERN_INFO DRIVER_DEBUG_PFX ":INFO" format "\n" , ## arg)
+
+
+#define stm_dbg(debug, format, arg...) (!(DRIVER_DEBUG)) ? ({do {} while(0); }) : debug == 1 ? (printk(DRIVER_DBG DRIVER_DEBUG_PFX ": " format "\n" , ## arg)) : ({do {} while (0); })
+
+#define stm_dbg2(debug, format, arg...) (!(DRIVER_DEBUG)) ? ({do {} while(0); }) : debug == 2 ? (printk(DRIVER_DBG DRIVER_DEBUG_PFX ": " format "\n" , ## arg)) : ({do {} while (0); })
+
+#define stm_dbg3(debug, format, arg...) (!(DRIVER_DEBUG)) ? ({do {} while(0); }) : debug == 3 ? (printk(DRIVER_DBG DRIVER_DEBUG_PFX ": " format "\n" , ## arg)) : ({do {} while (0); })
+
+#define stm_dbg4(format, arg...) (DRIVER_DEBUG & 1) ? (printk(DRIVER_DBG DRIVER_DEBUG_PFX ": " format "\n" , ## arg)) : ({do {} while (0); })
+
+extern struct driver_debug_st DBG_ST;
+#endif
+
+/* __INC_DBG_H */
+
+/* End of file - debug.h */
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
new file mode 100644
index 00000000000..0ffc1a05c3d
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_DEVICES_H__
+#define __ASM_ARCH_DEVICES_H__
+
+struct platform_device;
+struct amba_device;
+
+void __init u8500_register_device(struct platform_device *dev, void *data);
+void __init u8500_register_amba_device(struct amba_device *dev, void *data);
+
+extern struct amba_device u5500_gpio0_device;
+extern struct amba_device u5500_gpio1_device;
+extern struct amba_device u5500_gpio2_device;
+extern struct amba_device u5500_gpio3_device;
+extern struct amba_device u5500_gpio4_device;
+
+extern struct amba_device u8500_gpio0_device;
+extern struct amba_device u8500_gpio1_device;
+extern struct amba_device u8500_gpio2_device;
+extern struct amba_device u8500_gpio3_device;
+
+extern struct platform_device u8500_msp0_device;
+extern struct platform_device u8500_msp1_device;
+extern struct platform_device u8500_msp2_device;
+extern struct amba_device u8500_msp2_spi_device;
+extern struct platform_device u8500_i2c0_device;
+extern struct platform_device ux500_i2c1_device;
+extern struct platform_device ux500_i2c2_device;
+extern struct platform_device ux500_i2c3_device;
+extern struct platform_device u8500_i2c4_device;
+extern struct platform_device u8500_mcde2_device;
+extern struct platform_device u8500_mcde3_device;
+extern struct platform_device u8500_mcde1_device;
+extern struct platform_device u8500_mcde0_device;
+extern struct platform_device u8500_hsit_device;
+extern struct platform_device u8500_hsir_device;
+extern struct platform_device u8500_shrm_device;
+extern struct platform_device ux500_b2r2_device;
+extern struct platform_device u8500_pmem_device;
+extern struct platform_device u8500_pmem_mio_device;
+extern struct platform_device u8500_pmem_hwb_device;
+extern struct amba_device ux500_rtc_device;
+extern struct platform_device ux500_dma_device;
+extern struct amba_device u8500_ssp0_device;
+extern struct amba_device u8500_ssp1_device;
+extern struct amba_device ux500_spi0_device;
+extern struct amba_device ux500_sdi4_device;
+extern struct amba_device ux500_sdi0_device;
+extern struct amba_device ux500_sdi1_device;
+extern struct amba_device ux500_sdi2_device;
+extern struct platform_device u8500_ab8500_device;
+extern struct platform_device ux500_musb_device;
+extern struct amba_device ux500_uart0_device;
+extern struct amba_device ux500_uart1_device;
+extern struct amba_device ux500_uart2_device;
+
+/*
+ * Do not use inside drivers. Check it in the board file and alter platform
+ * data.
+ */
+extern int platform_id;
+#define MOP500_PLATFORM_ID 0
+#define HREF_PLATFORM_ID 1
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/dma.h b/arch/arm/mach-ux500/include/mach/dma.h
new file mode 100755
index 00000000000..269dd4c8108
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/dma.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2009 ST-Ericsson.
+ * Copyright 2009 STMicroelectronics.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+#ifndef __INC_ASM_ARCH_DMA_H
+#define __INC_ASM_ARCH_DMA_H
+
+#define MAX_DMA_CHANNELS 32
+#ifndef __ASSEMBLY__
+#include <asm/scatterlist.h>
+
+typedef unsigned int dmach_t;
+typedef unsigned int dmamode_t;
+
+enum dma_flow_controller {
+ DMA_IS_FLOW_CNTLR,
+ PERIPH_IS_FLOW_CNTLR
+};
+enum {
+ DMA_FALSE,
+ DMA_TRUE
+};
+
+enum dma_xfer_dir {
+ MEM_TO_MEM,
+ MEM_TO_PERIPH,
+ PERIPH_TO_MEM,
+ PERIPH_TO_PERIPH
+};
+
+enum dma_endianess {
+ DMA_LITTLE_ENDIAN,
+ DMA_BIG_ENDIAN
+};
+enum dma_event {
+ XFER_COMPLETE,
+ XFER_ERROR
+};
+typedef void (*dma_callback_t)(void *data, enum dma_event event);
+
+#include <mach/dma_40-8500.h>
+
+/**
+ * struct stm_dma_pipe_info - Structure to be filled by client drivers.
+ *
+ * @reserve_channel: Whether you want to reserve the channel
+ * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
+ * @flow_cntlr: who is flow controller (Device or DMA)
+ * @phys_chan_id: physical channel ID on which this channel will execute
+ * @data: data of callback handler
+ * @callback: callback handler registered by client
+ * @channel_type: std/ext, basic/log/operational, priority, security
+ * @src_dev_type: Src device type
+ * @dst_dev_type: Dest device type
+ * @src_addr: Source address
+ * @dst_addr: Dest address
+ * @src_info: Parameters for Source half channel
+ * @dst_info: Parameters for Dest half channel
+ *
+ *
+ * This structure has to be filled by the client drivers, before requesting
+ * a DMA pipe. This information is used by the Driver to allocate or
+ * reserve an appropriate DMA channel for this client.
+ *
+ */
+struct stm_dma_pipe_info {
+ unsigned int reserve_channel;
+ enum dma_xfer_dir dir;
+ enum dma_flow_controller flow_cntlr;
+ enum dma_chan_id phys_chan_id;
+ void *data;
+ dma_callback_t callback;
+ unsigned int channel_type;
+ enum dma_src_dev_type src_dev_type;
+ enum dma_dest_dev_type dst_dev_type;
+ void *src_addr;
+ void *dst_addr;
+ struct dma_half_channel_info src_info;
+ struct dma_half_channel_info dst_info;
+};
+
+extern int stm_configure_dma_channel(int channel,
+ struct stm_dma_pipe_info *info);
+extern int stm_request_dma(int *channel, struct stm_dma_pipe_info *info);
+extern void stm_free_dma(int channel);
+extern int stm_set_callback_handler(int channel, void *callback_handler,
+ void *data);
+extern int stm_enable_dma(int channel);
+extern void stm_disable_dma(int channel);
+extern int stm_pause_dma(int channel);
+extern void stm_unpause_dma(int channel);
+extern void stm_set_dma_addr(int channel, void *src_addr , void *dst_addr);
+extern void stm_set_dma_count(int channel, int count);
+extern void stm_set_dma_sg(int channel, struct scatterlist *sg,
+ int nr_sg, int type);
+
+extern int stm_dma_residue(int channel);
+
+#endif /*__ASSEMBLY__*/
+#endif /* __INC_ASM_ARCH_DMA_H */
+/* End of file - dma.h */
+
diff --git a/arch/arm/mach-ux500/include/mach/dma_40-8500.h b/arch/arm/mach-ux500/include/mach/dma_40-8500.h
new file mode 100755
index 00000000000..7e0c15c7752
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/dma_40-8500.h
@@ -0,0 +1,788 @@
+/*----------------------------------------------------------------------------*/
+/* copyright STMicroelectronics, 2008. */
+/* */
+/* This program is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU General Public License as published by */
+/* the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, */
+/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS */
+/* FOR A PARTICULAR PURPOSE. See the GNU General Public License for */
+/* more details. */
+/* */
+/* You should have received a copy of the GNU General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*----------------------------------------------------------------------------*/
+
+#ifndef __INC_ARCH_ARM_SOC_DMA_H
+#define __INC_ARCH_ARM_SOC_DMA_H
+#include <linux/spinlock.h>
+
+/******************************************************************************/
+#define MEM_WRITE_BITS(reg, val, mask, sb) \
+ ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
+#define MEM_READ_BITS(reg, mask, sb) \
+ (((reg) & (mask)) >> (sb))
+
+#define REG_WR_BITS_1(reg, val, mask, sb) \
+ iowrite32(((val)<<(sb) | (~mask)), reg)
+#define REG_WR_BITS(reg, val, mask, sb) \
+ iowrite32(((ioread32(reg) & ~(mask)) | (((val)<<(sb)) & (mask))), reg)
+#define REG_RD_BITS(reg, mask, sb) (((ioread32(reg)) & (mask)) >> (sb))
+/******************************************************************************/
+#define FULL32_MASK 0xFFFFFFFF
+#define NO_SHIFT 0
+#define MAX_PHYSICAL_CHANNELS 32
+#define MAX_AVAIL_PHY_CHANNELS 8
+#define MAX_LOGICAL_CHANNELS 128
+#define NUM_CHANNELS (MAX_LOGICAL_CHANNELS + MAX_PHYSICAL_CHANNELS)
+/******************************************************************************/
+
+#define PHYSICAL_RESOURCE_TYPE_POS(i) (2*(i / 2))
+#define PHYSICAL_RESOURCE_TYPE_MASK(i) (0x3UL << PHYSICAL_RESOURCE_TYPE_POS(i))
+
+#define PHYSICAL_RESOURCE_CHANNEL_MODE_POS(i) (2*(i / 2))
+#define PHYSICAL_RESOURCE_CHANNEL_MODE_MASK(i) \
+ (0x3UL << PHYSICAL_RESOURCE_CHANNEL_MODE_POS(i))
+
+
+#define PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS(i) (2*(i / 2))
+#define PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_MASK(i) \
+ (0x3UL << PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS(i))
+
+#define PHYSICAL_RESOURCE_SECURE_MODE_POS(i) (2*(i / 2))
+#define PHYSICAL_RESOURCE_SECURE_MODE_MASK(i) \
+ (0x3UL << PHYSICAL_RESOURCE_SECURE_MODE_POS(i))
+
+#define ACT_PHY_RES_POS(i) (2*(i / 2))
+#define ACT_PHY_RES_MASK(i) (0x3UL << ACT_PHY_RES_POS(i))
+
+#define ACTIVATE_RESOURCE_MODE_POS(i) (2*(i / 2))
+#define ACTIVATE_RESOURCE_MODE_MASK(i) (0x3UL << ACTIVATE_RESOURCE_MODE_POS(i))
+
+/*****************************************************************************
+ Standard basic Channel configuration macros - start
+******************************************************************************/
+
+/* Standard channel parameters - basic mode */
+/* (Source and Destination config regs have */
+/* similar bit descriptions and hence same mask) */
+/*---------------------------------------------------------------------------*/
+#define SREG_CFG_PHY_MST_POS 15
+#define SREG_CFG_PHY_TIM_POS 14
+#define SREG_CFG_PHY_EIM_POS 13
+#define SREG_CFG_PHY_PEN_POS 12
+#define SREG_CFG_PHY_PSIZE_POS 10
+#define SREG_CFG_PHY_ESIZE_POS 8
+#define SREG_CFG_PHY_PRI_POS 7
+#define SREG_CFG_PHY_LBE_POS 6
+#define SREG_CFG_PHY_TM_POS 4
+#define SREG_CFG_PHY_EVTL_POS 0
+
+#define SREG_CFG_PHY_MST_MASK (0x1UL << SREG_CFG_PHY_MST_POS)
+#define SREG_CFG_PHY_TIM_MASK (0x1UL << SREG_CFG_PHY_TIM_POS)
+#define SREG_CFG_PHY_EIM_MASK (0x1UL << SREG_CFG_PHY_EIM_POS)
+#define SREG_CFG_PHY_PEN_MASK (0x1UL << SREG_CFG_PHY_PEN_POS)
+#define SREG_CFG_PHY_PSIZE_MASK (0x3UL << SREG_CFG_PHY_PSIZE_POS)
+#define SREG_CFG_PHY_ESIZE_MASK (0x3UL << SREG_CFG_PHY_ESIZE_POS)
+#define SREG_CFG_PHY_PRI_MASK (0x1UL << SREG_CFG_PHY_PRI_POS)
+#define SREG_CFG_PHY_LBE_MASK (0x1UL << SREG_CFG_PHY_LBE_POS)
+#define SREG_CFG_PHY_TM_MASK (0x3UL << SREG_CFG_PHY_TM_POS)
+#define SREG_CFG_PHY_EVTL_MASK (0xFUL << SREG_CFG_PHY_EVTL_POS)
+
+/* Standard channel parameters - basic mode (element register) */
+/*---------------------------------------------------------------------------*/
+#define SREG_ELEM_PHY_ECNT_POS 16
+#define SREG_ELEM_PHY_EIDX_POS 0
+
+#define SREG_ELEM_PHY_ECNT_MASK (0xFFFFUL << SREG_ELEM_PHY_ECNT_POS)
+#define SREG_ELEM_PHY_EIDX_MASK (0xFFFFUL << SREG_ELEM_PHY_EIDX_POS)
+
+/* Standard channel parameters - basic mode (Pointer register) */
+/*---------------------------------------------------------------------------*/
+#define SREG_PTR_PHYS_PTR_MASK (0xFFFFFFFFUL)
+
+/* Standard channel parameters - basic mode (Link register) */
+/*---------------------------------------------------------------------------*/
+#define SREG_LNK_PHY_TCP_POS 0
+#define SREG_LNK_PHY_LMP_POS 1
+#define SREG_LNK_PHY_PRE_POS 2
+/* Source destination link address. Contains the
+ * 29-bit byte word aligned address of the reload area.
+ */
+#define SREG_LNK_PHYS_LNK_MASK (0xFFFFFFF8UL)
+#define SREG_LNK_PHYS_TCP_MASK (0x1UL << SREG_LNK_PHY_TCP_POS)
+#define SREG_LNK_PHYS_LMP_MASK (0x1UL << SREG_LNK_PHY_LMP_POS)
+#define SREG_LNK_PHYS_PRE_MASK (0x1UL << SREG_LNK_PHY_PRE_POS)
+/******************************************************************************/
+/* Standard basic Channel configuration macros end */
+/******************************************************************************/
+
+/****************************************************************************/
+/* Standard basic Channel LOGICAL mode - start */
+/****************************************************************************/
+/*Configuration register */
+/*--------------------------------------------------------------------------*/
+
+#define SREG_CFG_LOG_MST_POS 15
+#define SREG_CFG_LOG_TIM_POS 14
+#define SREG_CFG_LOG_EIM_POS 13
+#define SREG_CFG_LOG_INCR_POS 12
+#define SREG_CFG_LOG_PSIZE_POS 10
+#define SREG_CFG_LOG_ESIZE_POS 8
+#define SREG_CFG_LOG_PRI_POS 7
+#define SREG_CFG_LOG_LBE_POS 6
+#define SREG_CFG_LOG_GIM_POS 5
+#define SREG_CFG_LOG_MFU_POS 4
+
+#define SREG_CFG_LOG_MST_MASK (0x1UL << SREG_CFG_LOG_MST_POS)
+#define SREG_CFG_LOG_TIM_MASK (0x1UL << SREG_CFG_LOG_TIM_POS)
+#define SREG_CFG_LOG_EIM_MASK (0x1UL << SREG_CFG_LOG_EIM_POS)
+#define SREG_CFG_LOG_INCR_MASK (0x1UL << SREG_CFG_LOG_INCR_POS)
+#define SREG_CFG_LOG_PSIZE_MASK (0x3UL << SREG_CFG_LOG_PSIZE_POS)
+#define SREG_CFG_LOG_ESIZE_MASK (0x3UL << SREG_CFG_LOG_ESIZE_POS)
+#define SREG_CFG_LOG_PRI_MASK (0x1UL << SREG_CFG_LOG_PRI_POS)
+#define SREG_CFG_LOG_LBE_MASK (0x1UL << SREG_CFG_LOG_LBE_POS)
+#define SREG_CFG_LOG_GIM_MASK (0x1UL << SREG_CFG_LOG_GIM_POS)
+#define SREG_CFG_LOG_MFU_MASK (0x1UL << SREG_CFG_LOG_MFU_POS)
+
+/*Element register*/
+
+#define SREG_ELEM_LOG_ECNT_POS 16
+#define SREG_ELEM_LOG_LIDX_POS 8
+#define SREG_ELEM_LOG_LOS_POS 1
+#define SREG_ELEM_LOG_TCP_POS 0
+
+#define SREG_ELEM_LOG_ECNT_MASK (0xFFFFUL << SREG_ELEM_LOG_ECNT_POS)
+#define SREG_ELEM_LOG_LIDX_MASK (0xFFUL << SREG_ELEM_LOG_LIDX_POS)
+#define SREG_ELEM_LOG_LOS_MASK (0x7FUL << SREG_ELEM_LOG_LOS_POS)
+#define SREG_ELEM_LOG_TCP_MASK (0x1UL << SREG_ELEM_LOG_TCP_POS)
+
+/*Pointer register */
+#define SREG_PTR_LOG_PTR_MASK (0xFFFFFFFFUL)
+
+/*Link registeri */
+#define DEACTIVATE_EVENTLINE 0x0
+#define ACTIVATE_EVENTLINE 0x1
+#define EVENTLINE_POS(i) (2*i)
+#define EVENTLINE_MASK(i) (0x3UL << EVENTLINE_POS(i))
+
+/* Standard basic Channel LOGICAL params in memory*/
+#define MEM_LCSP0_ECNT_POS 16
+#define MEM_LCSP0_SPTR_POS 0
+
+#define MEM_LCSP0_ECNT_MASK (0xFFFFUL << MEM_LCSP0_ECNT_POS)
+#define MEM_LCSP0_SPTR_MASK (0xFFFFUL << MEM_LCSP0_SPTR_POS)
+
+#define MEM_LCSP1_SPTR_POS 16
+
+#define MEM_LCSP1_SCFG_MST_POS 15
+#define MEM_LCSP1_SCFG_TIM_POS 14
+#define MEM_LCSP1_SCFG_EIM_POS 13
+#define MEM_LCSP1_SCFG_INCR_POS 12
+#define MEM_LCSP1_SCFG_PSIZE_POS 10
+#define MEM_LCSP1_SCFG_ESIZE_POS 8
+
+#define MEM_LCSP1_SLOS_POS 1
+#define MEM_LCSP1_STCP_POS 0
+
+#define MEM_LCSP1_SPTR_MASK (0xFFFFUL << MEM_LCSP1_SPTR_POS)
+
+#define MEM_LCSP1_SCFG_MST_MASK (0x1UL << MEM_LCSP1_SCFG_MST_POS)
+#define MEM_LCSP1_SCFG_TIM_MASK (0x1UL << MEM_LCSP1_SCFG_TIM_POS)
+#define MEM_LCSP1_SCFG_EIM_MASK (0x1UL << MEM_LCSP1_SCFG_EIM_POS)
+#define MEM_LCSP1_SCFG_INCR_MASK (0x1UL << MEM_LCSP1_SCFG_INCR_POS)
+#define MEM_LCSP1_SCFG_PSIZE_MASK (0x3UL << MEM_LCSP1_SCFG_PSIZE_POS)
+#define MEM_LCSP1_SCFG_ESIZE_MASK (0x3UL << MEM_LCSP1_SCFG_ESIZE_POS)
+
+#define MEM_LCSP1_SLOS_MASK (0x7FUL << MEM_LCSP1_SLOS_POS)
+#define MEM_LCSP1_STCP_MASK (0x1UL << MEM_LCSP1_STCP_POS)
+
+#define MEM_LCSP2_ECNT_POS 16
+#define MEM_LCSP2_DPTR_POS 0
+
+#define MEM_LCSP2_ECNT_MASK (0xFFFFUL << MEM_LCSP2_ECNT_POS)
+#define MEM_LCSP2_DPTR_MASK (0xFFFFUL << MEM_LCSP2_DPTR_POS)
+
+#define MEM_LCSP3_DPTR_POS 16
+
+#define MEM_LCSP3_DCFG_MST_POS 15
+#define MEM_LCSP3_DCFG_TIM_POS 14
+#define MEM_LCSP3_DCFG_EIM_POS 13
+#define MEM_LCSP3_DCFG_INCR_POS 12
+#define MEM_LCSP3_DCFG_PSIZE_POS 10
+#define MEM_LCSP3_DCFG_ESIZE_POS 8
+
+#define MEM_LCSP3_DLOS_POS 1
+#define MEM_LCSP3_DTCP_POS 0
+
+#define MEM_LCSP3_DPTR_MASK (0xFFFFUL << MEM_LCSP3_DPTR_POS)
+
+#define MEM_LCSP3_DCFG_MST_MASK (0x1UL << MEM_LCSP3_DCFG_MST_POS)
+#define MEM_LCSP3_DCFG_TIM_MASK (0x1UL << MEM_LCSP3_DCFG_TIM_POS)
+#define MEM_LCSP3_DCFG_EIM_MASK (0x1UL << MEM_LCSP3_DCFG_EIM_POS)
+#define MEM_LCSP3_DCFG_INCR_MASK (0x1UL << MEM_LCSP3_DCFG_INCR_POS)
+#define MEM_LCSP3_DCFG_PSIZE_MASK (0x3UL << MEM_LCSP3_DCFG_PSIZE_POS)
+#define MEM_LCSP3_DCFG_ESIZE_MASK (0x3UL << MEM_LCSP3_DCFG_ESIZE_POS)
+
+#define MEM_LCSP3_DLOS_MASK (0x7FUL << MEM_LCSP3_DLOS_POS)
+#define MEM_LCSP3_DTCP_MASK (0x1UL << MEM_LCSP3_DTCP_POS)
+#define DMA_INFINITE_XFER (0x80000000)
+#define CONFIG_USB_U8500_EVENT_LINES
+/******************************************************************************/
+
+/* Logical Standard Channel Parameters */
+
+struct std_log_memory_param {
+ u32 dmac_lcsp0;
+ u32 dmac_lcsp1;
+ u32 dmac_lcsp2;
+ u32 dmac_lcsp3;
+};
+
+struct std_src_log_memory_param {
+ u32 dmac_lcsp0;
+ u32 dmac_lcsp1;
+};
+
+struct std_dest_log_memory_param {
+ u32 dmac_lcsp2;
+ u32 dmac_lcsp3;
+};
+
+enum channel_command {
+ STOP_CHANNEL = 0x1,
+ RUN_CHANNEL = 0x2,
+ SUSPEND_REQ = 0x2,
+ SUSPENDED = 0x3
+};
+
+/* Standard Channel parameter register offsets */
+#define CHAN_REG_SSCFG 0x00
+#define CHAN_REG_SSELT 0x04
+#define CHAN_REG_SSPTR 0x08
+#define CHAN_REG_SSLNK 0x0C
+#define CHAN_REG_SDCFG 0x10
+#define CHAN_REG_SDELT 0x14
+#define CHAN_REG_SDPTR 0x18
+#define CHAN_REG_SDLNK 0x1C
+
+/* DMA Register Offsets */
+#define DREG_GCC 0x000
+#define DREG_PRTYP 0x004
+#define DREG_PRSME 0x008
+#define DREG_PRSMO 0x00C
+#define DREG_PRMSE 0x010
+#define DREG_PRMSO 0x014
+#define DREG_PRMOE 0x018
+#define DREG_PRMOO 0x01C
+#define DREG_LCPA 0x020
+#define DREG_LCLA 0x024
+#define DREG_SLCPA 0x028
+#define DREG_SLCLA 0x02C
+#define DREG_SSEG(j) (0x030 + j*4)
+#define DREG_SCEG(j) (0x040 + j*4)
+#define DREG_ACTIVE 0x050
+#define DREG_ACTIVO 0x054
+#define DREG_FSEB1 0x058
+#define DREG_FSEB2 0x05C
+#define DREG_PCMIS 0x060
+#define DREG_PCICR 0x064
+#define DREG_PCTIS 0x068
+#define DREG_PCEIS 0x06C
+#define DREG_SPCMIS 0x070
+#define DREG_SPCICR 0x074
+#define DREG_SPCTIS 0x078
+#define DREG_SPCEIS 0x07C
+#define DREG_LCMIS(j) (0x080 + j*4)
+#define DREG_LCICR(j) (0x090 + j*4)
+#define DREG_LCTIS(j) (0x0A0 + j*4)
+#define DREG_LCEIS(j) (0x0B0 + j*4)
+#define DREG_SLCMIS(j) (0x0C0 + j*4)
+#define DREG_SLCICR(j) (0x0D0 + j*4)
+#define DREG_SLCTIS(j) (0x0E0 + j*4)
+#define DREG_SLCEIS(j) (0x0F0 + j*4)
+#define DREG_STFU 0xFC8
+#define DREG_ICFG 0xFCC
+#define DREG_MPLUG(j) (0xFD0 + j*4)
+#define DREG_PERIPHID(j) (0xFE0 + j*4)
+#define DREG_CELLID(j) (0xFF0 + j*4)
+
+/*
+ * LLI related structures
+*/
+
+struct dma_lli_info {
+ u32 reg_cfg;
+ u32 reg_elt;
+ u32 reg_ptr;
+ u32 reg_lnk;
+};
+
+struct dma_logical_src_lli_info {
+ u32 dmac_lcsp0;
+ u32 dmac_lcsp1;
+};
+
+struct dma_logical_dest_lli_info {
+ u32 dmac_lcsp2;
+ u32 dmac_lcsp3;
+};
+
+/*****************************************************************************/
+enum dma_toggle_endianess {
+ DO_NOT_CHANGE_ENDIANESS,
+ CHANGE_ENDIANESS
+};
+
+enum dma_master_id {
+ DMA_MASTER_0,
+ DMA_MASTER_1
+};
+
+/******************************************************************/
+/*Description of bitfields of channel_type variable in info structure*/
+
+#define INFO_CH_TYPE_POS 0
+#define STANDARD_CHANNEL (0x1 << INFO_CH_TYPE_POS)
+#define EXTENDED_CHANNEL (0x2 << INFO_CH_TYPE_POS)
+
+#define INFO_PRIO_TYPE_POS 2
+#define HIGH_PRIORITY_CHANNEL (0x1 << INFO_PRIO_TYPE_POS)
+#define LOW_PRIORITY_CHANNEL (0x2 << INFO_PRIO_TYPE_POS)
+
+#define INFO_SEC_TYPE_POS 4
+#define SECURE_CHANNEL (0x1 << INFO_SEC_TYPE_POS)
+#define NON_SECURE_CHANNEL (0x2 << INFO_SEC_TYPE_POS)
+
+#define INFO_CH_MODE_TYPE_POS 6
+#define CHANNEL_IN_PHYSICAL_MODE (0x1 << INFO_CH_MODE_TYPE_POS)
+#define CHANNEL_IN_LOGICAL_MODE (0x2 << INFO_CH_MODE_TYPE_POS)
+#define CHANNEL_IN_OPERATION_MODE (0x3 << INFO_CH_MODE_TYPE_POS)
+
+#define INFO_CH_MODE_OPTION_POS 8
+#define PCHAN_BASIC_MODE (0x1 << INFO_CH_MODE_OPTION_POS)
+#define PCHAN_MODULO_MODE (0x2 << INFO_CH_MODE_OPTION_POS)
+#define PCHAN_DOUBLE_DEST_MODE (0x3 << INFO_CH_MODE_OPTION_POS)
+#define LCHAN_SRC_PHY_DEST_LOG (0x1 << INFO_CH_MODE_OPTION_POS)
+#define LCHAN_SRC_LOG_DEST_PHS (0x2 << INFO_CH_MODE_OPTION_POS)
+#define LCHAN_SRC_LOG_DEST_LOG (0x3 << INFO_CH_MODE_OPTION_POS)
+
+#define INFO_LINK_TYPE_POS 9
+#define LINK_PRE (0x0 << INFO_LINK_TYPE_POS)
+#define LINK_POST (0x1 << INFO_LINK_TYPE_POS)
+
+#define INFO_TIM_POS 10
+#define NO_TIM_FOR_LINK (0x0 << INFO_TIM_POS)
+#define TIM_FOR_LINK (0x1 << INFO_TIM_POS)
+
+/******************************************************************/
+
+enum dma_phys_res_type {
+ DMA_STANDARD = 0x1,
+ DMA_EXTENDED = 0x2
+};
+
+enum dma_chan_priority {
+ DMA_LOW_PRIORITY = 0x1,
+ DMA_HIGH_PRIORITY = 0x2
+};
+
+enum dma_chan_security {
+ DMA_SECURE_CHAN = 0x1,
+ DMA_NONSECURE_CHAN = 0x2
+};
+
+enum dma_channel_mode_option {
+ BASIC_MODE = 0x1,
+ MODULO_MODE = 0x2,
+ DOUBLE_DESTINATION_MODE = 0x3,
+
+ SRC_PHY_DEST_LOG = 0x1,
+ SRC_LOG_DEST_PHS = 0x2,
+ SRC_LOG_DEST_LOG = 0x3
+};
+
+enum dma_channel_mode {
+ DMA_CHAN_IN_PHYS_MODE = 0x1,
+ DMA_CHAN_IN_LOG_MODE = 0x2,
+ DMA_CHAN_IN_OPERATION_MODE = 0x3
+};
+
+enum dma_event_group {
+ DMA_EVENT_GROUP_0,
+ DMA_EVENT_GROUP_1,
+ DMA_EVENT_GROUP_2,
+ DMA_EVENT_GROUP_3,
+ DMA_NO_EVENT_GROUP
+};
+
+enum dma_half_chan {
+ DMA_SRC_HALF_CHANNEL,
+ DMA_DEST_HALF_CHANNEL
+};
+
+enum dma_addr_inc {
+ DMA_ADR_NOINC,
+ DMA_ADR_INC
+};
+
+enum dma_command {
+ DMA_STOP,
+ DMA_RUN,
+ DMA_SUSPEND_REQ,
+ DMA_SUSPENDED
+};
+
+enum dma_chan_status {
+ DMA_ONGOING_EXCHANGE,
+ DMA_SUSPENDED_EXCHANGE,
+ DMA_HALTED_EXCHANGE,
+ DMA_STATUS_UNKNOWN = -1
+};
+
+enum dma_chan_id {
+ DMA_CHAN_0,
+ DMA_CHAN_1,
+ DMA_CHAN_2,
+ DMA_CHAN_3,
+ DMA_CHAN_4,
+ DMA_CHAN_5,
+ DMA_CHAN_6,
+ DMA_CHAN_7,
+ DMA_CHAN_NOT_ALLOCATED = -1
+};
+
+enum dma_src_dev_type {
+ DMA_DEV_SPI0_RX = 0,
+ DMA_DEV_SD_MMC0_RX,
+ DMA_DEV_SD_MMC1_RX,
+ DMA_DEV_SD_MMC2_RX,
+ DMA_DEV_I2C1_RX,
+ DMA_DEV_I2C3_RX,
+ DMA_DEV_I2C2_RX,
+ DMA_DEV_SSP0_RX = 8,
+ DMA_DEV_SSP1_RX,
+ DMA_DEV_MCDE_RX,
+ DMA_DEV_UART2_RX,
+ DMA_DEV_UART1_RX,
+ DMA_DEV_UART0_RX,
+ DMA_DEV_MSP2_RX,
+ DMA_DEV_I2C0_RX, /*15*/
+#ifndef CONFIG_USB_U8500_EVENT_LINES
+ DMA_DEV_USB_OTG_IEP_8 ,
+ DMA_DEV_USB_OTG_IEP_1_9 ,
+ DMA_DEV_USB_OTG_IEP_2_10 ,
+ DMA_DEV_USB_OTG_IEP_3_11 ,
+#else
+ DMA_DEV_USB_OTG_IEP_7_15 ,
+ DMA_DEV_USB_OTG_IEP_6_14 ,
+ DMA_DEV_USB_OTG_IEP_5_13 ,
+ DMA_DEV_USB_OTG_IEP_4_12 ,
+#endif
+ DMA_DEV_SLIM0_CH0_RX_HSI_RX_CH0,
+ DMA_DEV_SLIM0_CH1_RX_HSI_RX_CH1,
+ DMA_DEV_SLIM0_CH2_RX_HSI_RX_CH2,
+ DMA_DEV_SLIM0_CH3_RX_HSI_RX_CH3,
+ DMA_DEV_SRC_SXA0_RX_TX,
+ DMA_DEV_SRC_SXA1_RX_TX,
+ DMA_DEV_SRC_SXA2_RX_TX,
+ DMA_DEV_SRC_SXA3_RX_TX,
+ DMA_DEV_SD_MM2_RX,
+ DMA_DEV_SD_MM0_RX,
+ DMA_DEV_MSP1_RX,
+ DMA_SLIM0_CH0_RX,
+ DMA_DEV_MSP0_RX = DMA_SLIM0_CH0_RX,
+ DMA_DEV_SD_MM1_RX,
+ DMA_DEV_SPI2_RX,
+ DMA_DEV_I2C3_RX2,
+ DMA_DEV_SPI1_RX,
+#ifndef CONFIG_USB_U8500_EVENT_LINES
+ DMA_DEV_USB_OTG_IEP_4_12 ,
+ DMA_DEV_USB_OTG_IEP_5_13 ,
+ DMA_DEV_USB_OTG_IEP_6_14 ,
+ DMA_DEV_USB_OTG_IEP_7_15 ,
+#else
+ DMA_DEV_USB_OTG_IEP_3_11 ,
+ DMA_DEV_USB_OTG_IEP_2_10 ,
+ DMA_DEV_USB_OTG_IEP_1_9 ,
+ DMA_DEV_USB_OTG_IEP_8 ,
+#endif
+ DMA_DEV_SPI3_RX,
+ DMA_DEV_SD_MM3_RX,
+ DMA_DEV_SD_MM4_RX,
+ DMA_DEV_SD_MM5_RX,
+ DMA_DEV_SRC_SXA4_RX_TX,
+ DMA_DEV_SRC_SXA5_RX_TX,
+ DMA_DEV_SRC_SXA6_RX_TX,
+ DMA_DEV_SRC_SXA7_RX_TX,
+ DMA_DEV_CAC1_RX,
+ DMA_DEV_MSHC_RX = 51,
+ DMA_DEV_SLIM1_CH0_RX_HSI_RX_CH4,
+ DMA_DEV_SLIM1_CH1_RX_HSI_RX_CH5,
+ DMA_DEV_SLIM1_CH2_RX_HSI_RX_CH6,
+ DMA_DEV_SLIM1_CH3_RX_HSI_RX_CH7,
+ DMA_DEV_CAC0_RX = 61,
+ DMA_DEV_SRC_MEMORY = 64,
+};
+
+enum dma_dest_dev_type {
+ DMA_DEV_SPI0_TX = 0,
+ DMA_DEV_SD_MMC0_TX,
+ DMA_DEV_SD_MMC1_TX,
+ DMA_DEV_SD_MMC2_TX,
+ DMA_DEV_I2C1_TX,
+ DMA_DEV_I2C3_TX,
+ DMA_DEV_I2C2_TX,
+ DMA_DEV_SSP0_TX = 8,
+ DMA_DEV_SSP1_TX,
+ DMA_DEV_UART2_TX = 11,
+ DMA_DEV_UART1_TX,
+ DMA_DEV_UART0_TX,
+ DMA_DEV_MSP2_TX,
+ DMA_DEV_I2C0_TX,
+#ifndef CONFIG_USB_U8500_EVENT_LINES
+ DMA_DEV_USB_OTG_OEP_8 ,
+ DMA_DEV_USB_OTG_OEP_1_9 ,
+ DMA_DEV_USB_OTG_OEP_2_10 ,
+ DMA_DEV_USB_OTG_OEP_3_11 ,
+#else
+ DMA_DEV_USB_OTG_OEP_7_15 ,
+ DMA_DEV_USB_OTG_OEP_6_14 ,
+ DMA_DEV_USB_OTG_OEP_5_13 ,
+ DMA_DEV_USB_OTG_OEP_4_12 ,
+#endif
+ DMA_DEV_SLIM0_CH0_TX_HSI_TX_CH0,
+ DMA_DEV_SLIM0_CH1_TX_HSI_TX_CH1,
+ DMA_DEV_SLIM0_CH2_TX_HSI_TX_CH2,
+ DMA_DEV_SLIM0_CH3_TX_HSI_TX_CH3,
+ DMA_DEV_DST_SXA0_RX_TX,
+ DMA_DEV_DST_SXA1_RX_TX,
+ DMA_DEV_DST_SXA2_RX_TX,
+ DMA_DEV_DST_SXA3_RX_TX,
+ DMA_DEV_SD_MM2_TX,
+ DMA_DEV_SD_MM0_TX,
+ DMA_DEV_MSP1_TX,
+ DMA_SLIM0_CH0_TX,
+ DMA_DEV_MSP0_TX = DMA_SLIM0_CH0_TX,
+ DMA_DEV_SD_MM1_TX,
+ DMA_DEV_SPI2_TX,
+ DMA_DEV_I2C3_TX2,
+ DMA_DEV_SPI1_TX,
+#ifndef CONFIG_USB_U8500_EVENT_LINES
+ DMA_DEV_USB_OTG_OEP_4_12 ,
+ DMA_DEV_USB_OTG_OEP_5_13 ,
+ DMA_DEV_USB_OTG_OEP_6_14 ,
+ DMA_DEV_USB_OTG_OEP_7_15 ,
+#else
+ DMA_DEV_USB_OTG_OEP_3_11 ,
+ DMA_DEV_USB_OTG_OEP_2_10 ,
+ DMA_DEV_USB_OTG_OEP_1_9 ,
+ DMA_DEV_USB_OTG_OEP_8 ,
+#endif
+ DMA_DEV_SPI3_TX,
+ DMA_DEV_SD_MM3_TX,
+ DMA_DEV_SD_MM4_TX,
+ DMA_DEV_SD_MM5_TX,
+ DMA_DEV_DST_SXA4_RX_TX,
+ DMA_DEV_DST_SXA5_RX_TX,
+ DMA_DEV_DST_SXA6_RX_TX,
+ DMA_DEV_DST_SXA7_RX_TX,
+ DMA_DEV_CAC1_TX,
+ DMA_DEV_CAC1_TX_HAC1_TX,
+ DMA_DEV_HAC1_TX,
+ DMA_DEV_MSHC_TX,
+ DMA_DEV_SLIM1_CH0_TX_HSI_TX_CH4,
+ DMA_DEV_SLIM1_CH1_TX_HSI_TX_CH5,
+ DMA_DEV_SLIM1_CH2_TX_HSI_TX_CH6,
+ DMA_DEV_SLIM1_CH3_TX_HSI_TX_CH7,
+ DMA_DEV_CAC0_TX = 61,
+ DMA_DEV_CAC0_TX_HAC0_TX,
+ DMA_DEV_HAC0_TX,
+ DMA_DEV_DEST_MEMORY = 64,
+};
+
+enum dma_half_chan_sync {
+ DMA_NO_SYNC,
+ DMA_PACKET_SYNC,
+ DMA_FRAME_SYNC,
+ DMA_BLOCK_SYNC
+};
+
+enum half_channel_type {
+ PHYSICAL_HALF_CHANNEL = 0x1,
+ LOGICAL_HALF_CHANNEL,
+};
+
+enum periph_data_width {
+ DMA_BYTE_WIDTH,
+ DMA_HALFWORD_WIDTH,
+ DMA_WORD_WIDTH,
+ DMA_DOUBLEWORD_WIDTH
+};
+
+enum dma_burst_size {
+ DMA_BURST_SIZE_1,
+ DMA_BURST_SIZE_4,
+ DMA_BURST_SIZE_8,
+ DMA_BURST_SIZE_16,
+ DMA_NO_BURST
+};
+
+enum dma_buffer_type {
+ SINGLE_BUFFERED,
+ DOUBLE_BUFFERED
+};
+
+enum dma_link_type {
+ POSTLINK,
+ PRELINK
+};
+
+struct dma_half_channel_info {
+ enum half_channel_type half_chan_type;
+ enum dma_endianess endianess;
+ enum periph_data_width data_width;
+ enum dma_burst_size burst_size;
+ enum dma_buffer_type buffer_type;
+ enum dma_event_group event_group;
+ enum dma_addr_inc addr_inc;
+ u32 event_line;
+};
+
+/**
+ * struct dma_channel_info - Data structure to
+ * manage state of a DMA channel.
+ *
+ * @device_id: Name of the device
+ * @pipe_id: Pipe Id allocated to the client driver.
+ * @channel_id: Channel Id allocated for the client,
+ * used internally by DMA Driver(when interrupt comes)
+ * (there are 128 Logical + 32 Physical). Max is 160 channels
+ * @active: Is the channel active at this point?
+ * 1 - active, 0- inactive
+ * @invalid: Has configuration been updated since we last updated
+ * the registers? invalid = 1 (need to update)
+ * @phys_chan_id:physical channel ID on which this channel will execute
+ * @src_addr: Src address for single DMA
+ * @dst_addr: Dest address for single DMA
+ * @xfer_len: Length of transfer expressed in Bytes
+ * @current_sg: Pointer to current SG element being used for xfer(only active
+ * if TIM_MASK is set)
+ * @lli_interrupt: 1 if interrupts generated for each LLI
+ * @sgcount_src: Number of SG items in source sg list
+ * @lli_block_id_src: Block id for LLI pool used for source half channel
+ * @sg_src: Head Pointer to SG list for source half channel
+ * @sgcount_dest: Number of SG items in Dest sg list
+ * @lli_block_id_dest: Block id for LLI pool used for Dest half channel
+ * @sg_dest: Head Pointer to SG list for Destination half channel
+ * @sg_block_id_src: Block id for SG pool used for SRC half channel
+ * @sg_block_id_dest: Block id for SG pool used for DEST half channel
+ * @link_type: Whether prelink or postlink
+ * @reserve_channel: whether channel is reserved.
+ * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
+ * @flow_cntlr: who is the flow controller DMA or Peripheral
+ * @data: Pointer to data of callback function
+ * @callback: Pointer to callback function
+ * @pr_type: Physical resource type : standard or extended
+ * @chan_mode: Mode of Physical resource
+ * For std channel: Physical,Logical,Operation
+ * @mode_option: Further options of mode selected above
+ * @priority: Priority for this channel
+ * @security: security for this channel
+ * @bytes_xfred: Number of Bytes xfered till now
+ * @ch_status:
+ * @src_dev_type: Device type of Source
+ * @dst_dev_type: Device type of Dest
+ * @src_info: Parameters describing source half channel
+ * @dst_info: Parameters describing dest half channel
+ * This is a private data structure of DMA driver used to maintain
+ * state information of a particular channel
+ */
+struct dma_channel_info {
+ const char *device_id;
+ u32 src_cfg;
+ u32 dst_cfg;
+ u32 dmac_lcsp3;
+ u32 dmac_lcsp1;
+ int pipe_id;
+ int channel_id;
+ int active;
+ int invalid;
+ enum dma_chan_id phys_chan_id;
+ void *src_addr;
+ void *dst_addr;
+ u32 xfer_len;
+ u32 src_xfer_elem;
+ u32 dst_xfer_elem;
+ struct scatterlist *current_sg;
+ /*For Scatter Gather DMA */
+ int lli_interrupt;
+ int sgcount_src;
+ int lli_block_id_src;
+ struct scatterlist *sg_src;
+ int sgcount_dest;
+ int lli_block_id_dest;
+ struct scatterlist *sg_dest;
+ int sg_block_id_src;
+ int sg_block_id_dest;
+
+ enum dma_link_type link_type;
+ unsigned int reserve_channel;
+ enum dma_xfer_dir dir;
+ enum dma_flow_controller flow_cntlr;
+
+ void *data;
+ dma_callback_t callback;
+
+ enum dma_phys_res_type pr_type;
+ enum dma_channel_mode chan_mode;
+ enum dma_channel_mode_option mode_option;
+ enum dma_chan_priority priority;
+ enum dma_chan_security security;
+
+ int bytes_xfred;
+ enum dma_chan_status ch_status;
+ enum dma_src_dev_type src_dev_type;
+ enum dma_dest_dev_type dst_dev_type;
+ struct dma_half_channel_info src_info;
+ struct dma_half_channel_info dst_info;
+ spinlock_t cfg_lock;
+};
+
+enum res_status {
+ RESOURCE_FREE,
+ RESOURCE_PHYSICAL,
+ RESOURCE_LOGICAL
+};
+
+struct phys_res_status {
+ int count;
+ enum res_status status;
+};
+
+struct phy_res_info {
+ enum res_status status;
+ u32 count;
+ u32 dirty;
+};
+
+#define NUM_LLI_PER_REQUEST 40
+#define NUM_SG_PER_REQUEST 40
+#define NUM_LOGICAL_CHANNEL_PER_PHY_RESOURCE 16
+#define NUM_LLI_PER_LOG_CHANNEL 8
+#define SIXTY_FOUR_KB (64 * 1024)
+
+#define MAX_NUM_OF_ELEM_IN_A_XFER (64*1024)
+/*Number of Fixed size LLI Blocks available for Physical channels */
+#define NUM_PCHAN_LLI_BLOCKS 32
+/*Number of Fixed size SG blocks */
+#define NUM_SG_BLOCKS 32
+/*Maximum Iterations taken before giving up suspending a channel */
+#define MAX_ITERATIONS 500
+
+extern struct driver_debug_st DBG_ST;
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/dsi.h b/arch/arm/mach-ux500/include/mach/dsi.h
new file mode 100755
index 00000000000..553ad998bb1
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/dsi.h
@@ -0,0 +1,777 @@
+/*---------------------------------------------------------------------------*/
+/* Copyright ST Ericsson 2009. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it */
+/* under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, */
+/* or (at your option)any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */
+/* the GNU Lesser General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*---------------------------------------------------------------------------*/
+
+#ifndef _DSI_H_
+#define _DSI_H_
+
+#ifdef _cplusplus
+extern "C" {
+#endif /* _cplusplus */
+#include <mach/mcde.h>
+#ifdef __KERNEL__
+
+#define DSI_DPHY_Z_CALIB_OUT_VALID 0x1
+/*******************************************************************************
+DSI Error Enums
+******************************************************************************/
+
+
+ typedef enum
+ {
+ DSI_OK = 0x1, /** No error.*/
+ DSI_NO_PENDING_EVENT_ERROR = 0x2,
+ DSI_NO_MORE_FILTER_PENDING_EVENT = 0x3,
+ DSI_NO_MORE_PENDING_EVENT = 0x4,
+ DSI_REMAINING_FILTER_PENDING_EVENTS = 0x5,
+ DSI_REMAINING_PENDING_EVENTS = 0x6,
+ DSI_INTERNAL_EVENT = 0x7,
+ DSI_INTERNAL_ERROR = 0x8,
+ DSI_NOT_CONFIGURED = 0x9,
+ DSI_REQUEST_PENDING = 0xA,
+ DSI_PLL_PROGRAM_ERROR = 0xB,
+ DSI_CLOCK_LANE_NOT_READY = 0xC,
+ DSI_DATA_LANE1_NOT_READY = 0xD,
+ DSI_DATA_LANE2_NOT_READY = 0xE,
+ DSI_REQUEST_NOT_APPLICABLE = 0x10,
+ DSI_INVALID_PARAMETER = 0x11,
+ DSI_UNSUPPORTED_FEATURE = 0x12,
+ DSI_UNSUPPORTED_HW = 0x13
+ }dsi_error;
+
+/********************************************************************************
+DSI Interrupt Type Enums
+********************************************************************************/
+#define DSI_NO_INTERRUPT 0x0
+
+typedef enum
+{
+ DSI_IRQ_TYPE_MCTL_MAIN = 0x01,
+ DSI_IRQ_TYPE_CMD_MODE = 0x02,
+ DSI_IRQ_TYPE_DIRECT_CMD_MODE = 0x03,
+ DSI_IRQ_TYPE_DIRECT_CMD_RD_MODE = 0x04,
+ DSI_IRQ_TYPE_VID_MODE = 0x05,
+ DSI_IRQ_TYPE_TG = 0x06,
+ DSI_IRQ_TYPE_DPHY_ERROR = 0x07,
+ DSI_IRQ_TYPE_DPHY_CLK_TRIM_RD = 0x08
+} dsi_irq_type;
+
+
+
+
+/*******************************************************************************
+ DSI Main Setting Registers Enums and structures
+******************************************************************************/
+
+ typedef enum
+ {
+ DSI_INT_MODE_DISABLE = 0x00,
+ DSI_INT_MODE_ENABLE = 0x01
+ }dsi_int_mode;
+
+ typedef enum
+ {
+ DSI_VSG_MODE_DISABLE = 0x00,
+ DSI_VSG_MODE_ENABLE = 0x01
+ }dsi_vsg_ctrl;
+
+ typedef enum
+ {
+ DSI_TVG_MODE_DISABLE = 0x00,
+ DSI_TVG_MODE_ENABLE = 0x01
+ }dsi_tvg_ctrl;
+
+ typedef enum
+ {
+ DSI_TBG_MODE_DISABLE = 0x00,
+ DSI_TBG_MODE_ENABLE = 0x01
+ }dsi_tbg_ctrl;
+
+ typedef enum
+ {
+ DSI_RD_MODE_DISABLE = 0x00,
+ DSI_RD_MODE_ENABLE = 0x01
+ }dsi_rd_ctrl;
+
+
+ typedef enum
+ {
+ DSI_SIGNAL_LOW = 0x0,
+ DSI_SIGNAL_HIGH = 0x1
+ }dsi_signal_state;
+
+ typedef enum
+ {
+ DSI_LINK0 = 0x00,
+ DSI_LINK1 = 0x01,
+ DSI_LINK2 = 0x02
+ }dsi_link;
+
+ typedef enum
+ {
+ DSI_COMMAND_MODE = 0x0,
+ DSI_VIDEO_MODE = 0x1,
+ DSI_INTERFACE_BOTH = 0x2,
+ DSI_INTERFACE_NONE = 0x3
+ }dsi_interface_mode;
+
+ typedef enum
+ {
+ DSI_INTERFACE_1 = 0x0,
+ DSI_INTERFACE_2 = 0x1
+ }dsi_interface;
+
+ typedef enum
+ {
+ DSI_DISABLE = 0x0,
+ DSI_ENABLE = 0x1
+ }dsi_link_state;
+
+ typedef enum
+ {
+ DSI_SIGNAL_RESET = 0x0,
+ DSI_SIGNAL_SET = 0x1
+ }dsi_stall_signal_state;
+
+ typedef enum
+ {
+ DSI_IF1_DISABLE = 0x0,
+ DSI_IF1_ENABLE = 0x1
+ }dsi_if1_state;
+
+ typedef enum
+ {
+ DSI_IF_DISABLE = 0x0,
+ DSI_IF_ENABLE = 0x1
+ }dsi_if_state;
+
+ typedef enum
+ {
+ DSI_PLL_IN_CLK_27 = 0x0,/** from TV PLL*/
+ DSI_PLL_IN_CLK_26 = 0x1 /** from system PLL*/
+ }dsi_pll_clk_in;
+
+ typedef enum
+ {
+ DSI_PLL_STOP = 0x0,
+ DSI_PLL_START = 0x1
+ }dsi_pll_mode;
+
+ typedef enum
+ {
+ DSI_BTA_DISABLE = 0x0,
+ DSI_BTA_ENABLE = 0x1
+ }dsi_bta_mode;
+
+ typedef enum
+ {
+ DSI_ECC_GEN_DISABLE = 0x0,
+ DSI_ECC_GEN_ENABLE = 0x1
+ }dsi_ecc_gen_mode;
+
+ typedef enum
+ {
+ DSI_CHECKSUM_GEN_DISABLE = 0x0,
+ DSI_CHECKSUM_GEN_ENABLE = 0x1
+ }dsi_checksum_gen_mode;
+
+ typedef enum
+ {
+ DSI_EOT_GEN_DISABLE = 0x0,
+ DSI_EOT_GEN_ENABLE = 0x1
+ }dsi_eot_gen_mode;
+
+ typedef enum
+ {
+ DSI_HOST_EOT_GEN_DISABLE = 0x0,
+ DSI_HOST_EOT_GEN_ENABLE = 0x1
+ }dsi_host_eot_gen_mode;
+
+ typedef enum
+ {
+ DSI_LANE_STOP = 0x0,
+ DSI_LANE_START = 0x1
+ }dsi_lane_state;
+ typedef enum
+ {
+ DSI_LANE_DISABLE = 0x0,
+ DSI_LANE_ENABLE = 0x1
+ }dsi_lane_mode;
+ typedef enum
+ {
+ DSI_CLK_CONTINIOUS_HS_DISABLE = 0x0,
+ DSI_CLK_CONTINIOUS_HS_ENABLE = 0x1
+ }dsi_clk_continious_hs_mode;
+ typedef enum
+ {
+ DSI_INTERNAL_PLL = 0x0,
+ DSI_SYSTEM_PLL = 0x1
+ }pll_out_sel; /** DPHY HS bit clock select*/
+ typedef enum
+ {
+ HS_INVERT_DISABLE = 0x0,
+ HS_INVERT_ENABLE = 0x1
+ }dsi_hs_invert_mode;
+ typedef enum
+ {
+ HS_SWAP_PIN_DISABLE = 0x0,
+ HS_SWAP_PIN_ENABLE = 0x1
+ }dsi_swap_pin_mode;
+ typedef enum
+ {
+ DSI_PLL_MASTER = 0x0,
+ DSI_PLL_SLAVE = 0x1
+ }dsi_pll_mode_sel;
+
+ typedef struct
+ {
+ u8 multiplier;
+ u8 division_ratio;
+ dsi_pll_clk_in pll_in_sel;
+ pll_out_sel pll_out_sel;
+ dsi_pll_mode_sel pll_master;
+ }dsi_pll_ctl;
+
+ typedef enum
+ {
+ DSI_REG_TE = 0x00,
+ DSI_IF_TE = 0x01
+ }dsi_te_sel;
+
+ typedef struct
+ {
+ dsi_te_sel te_sel;
+ dsi_interface interface;
+ }dsi_te_en;
+
+ typedef enum
+ {
+ DSI_TE_DISABLE = 0x0,
+ DSI_TE_ENABLE = 0x1
+ }dsi_te_ctrl;
+
+ typedef enum
+ {
+ DSI_CLK_LANE = 0x00,
+ DSI_DATA_LANE1 = 0x01,
+ DSI_DATA_LANE2 = 0x02
+ }dsi_lane;
+
+ typedef enum
+ {
+ DSI_DAT_LANE1 = 0x0,
+ DSI_DAT_LANE2 = 0x1
+ }dsi_data_lane;
+
+ typedef enum
+ {
+ DSI_CLK_LANE_START = 0x00,
+ DSI_CLK_LANE_IDLE = 0x01,
+ DSI_CLK_LANE_HS = 0x02,
+ DSI_CLK_LANE_ULPM = 0x03
+ }dsi_clk_lane_state;
+ typedef enum
+ {
+ DSI_CLK_LANE_LPM = 0x0,
+ DSI_CLK_LANE_HSM = 0x01
+ }dsi_interface_mode_type;
+ typedef enum
+ {
+ DSI_DATA_LANE_START = 0x000,
+ DSI_DATA_LANE_IDLE = 0x001,
+ DSI_DATA_LANE_WRITE = 0x002,
+ DSI_DATA_LANE_ULPM = 0x003,
+ DSI_DATA_LANE_READ = 0x004
+ }dsi_data_lane_state;
+
+ typedef struct
+ {
+ u8 clk_div;
+ u16 hs_tx_timeout;
+ u16 lp_rx_timeout;
+ }dsi_dphy_timeout;
+
+ typedef enum
+ {
+ DSI_PLL_LOCK = 0x01,
+ DSI_CLKLANE_READY = 0x02,
+ DSI_DAT1_READY = 0x04,
+ DSI_DAT2_READY = 0x08,
+ DSI_HSTX_TO_ERROR = 0x10,
+ DSI_LPRX_TO_ERROR = 0x20,
+ DSI_CRS_UNTERM_PCK = 0x40,
+ DSI_VRS_UNTERM_PCK = 0x80
+ }dsi_link_status;
+
+ typedef struct
+ {
+ u16 if_data;
+ dsi_signal_state if_valid;
+ dsi_signal_state if_start;
+ dsi_signal_state if_frame_sync;
+ }dsi_int_read;
+
+ typedef enum
+ {
+ DSI_ERR_SOT_HS_1 = 0x1,
+ DSI_ERR_SOT_HS_2 = 0x2,
+ DSI_ERR_SOTSYNC_1 = 0x4,
+ DSI_ERR_SOTSYNC_2 = 0x8,
+ DSI_ERR_EOTSYNC_1 = 0x10,
+ DSI_ERR_EOTSYNC_2 = 0x20,
+ DSI_ERR_ESC_1 = 0x40,
+ DSI_ERR_ESC_2 = 0x80,
+ DSI_ERR_SYNCESC_1 = 0x100,
+ DSI_ERR_SYNCESC_2 = 0x200,
+ DSI_ERR_CONTROL_1 = 0x400,
+ DSI_ERR_CONTROL_2 = 0x800,
+ DSI_ERR_CONT_LP0_1 = 0x1000,
+ DSI_ERR_CONT_LP0_2 = 0x2000,
+ DSI_ERR_CONT_LP1_1 = 0x4000,
+ DSI_ERR_CONT_LP1_2 = 0x8000,
+ }dsi_dphy_err;
+
+ typedef enum
+ {
+ DSI_VIRTUAL_CHANNEL_0 = 0x0,
+ DSI_VIRTUAL_CHANNEL_1 = 0x1,
+ DSI_VIRTUAL_CHANNEL_2 = 0x2,
+ DSI_VIRTUAL_CHANNEL_3 = 0x3
+ }dsi_virtual_ch;
+
+ typedef enum
+ {
+ DSI_ERR_NO_TE = 0x1,
+ DSI_ERR_TE_MISS = 0x2,
+ DSI_ERR_SDI1_UNDERRUN = 0x4,
+ DSI_ERR_SDI2_UNDERRUN = 0x8,
+ DSI_ERR_UNWANTED_RD = 0x10,
+ DSI_CSM_RUNNING = 0x20
+ }dsi_cmd_mode_sts;
+
+ typedef enum
+ {
+ DSI_COMMAND_DIRECT = 0x0,
+ DSI_COMMAND_GENERIC = 0x1
+ }dsi_cmd_type;
+
+ typedef struct
+ {
+ u16 rd_size;
+ dsi_virtual_ch rd_id;
+ dsi_cmd_type cmd_type;
+ }dsi_cmd_rd_property;
+
+ typedef enum
+ {
+ DSI_CMD_WRITE = 0x0,
+ DSI_CMD_READ = 0x1,
+ DSI_CMD_TE_REQUEST = 0x4,
+ DSI_CMD_TRIGGER_REQUEST = 0x5,
+ DSI_CMD_BTA_REQUEST = 0x6
+ }dsi_cmd_nat;
+
+ typedef enum
+ {
+ DSI_CMD_SHORT = 0x0,
+ DSI_CMD_LONG = 0x1
+ }dsi_cmd_packet;
+
+ typedef struct
+ {
+ u8 rddat0;
+ u8 rddat1;
+ u8 rddat2;
+ u8 rddat3;
+ }dsi_cmd_rddat;
+
+ typedef struct
+ {
+ dsi_cmd_nat cmd_nature;
+ dsi_cmd_packet packet_type;
+ u8 cmd_header;
+ dsi_virtual_ch cmd_id;
+ u8 cmd_size;
+ dsi_link_state cmd_lp_enable;
+ u8 cmd_trigger_val;
+ }dsi_cmd_main_setting;
+
+ typedef enum
+ {
+ DSI_CMD_TRANSMISSION = 0x1,
+ DSI_WRITE_COMPLETED = 0x2,
+ DSI_TRIGGER_COMPLETED = 0x4,
+ DSI_READ_COMPLETED = 0x8,
+ DSI_ACKNOWLEDGE_RECEIVED = 0x10,
+ DSI_ACK_WITH_ERR_RECEIVED = 0x20,
+ DSI_TRIGGER_RECEIVED = 0x40,
+ DSI_TE_RECEIVED = 0x80,
+ DSI_BTA_COMPLETED = 0x100,
+ DSI_BTA_FINISHED = 0x200,
+ DSI_READ_COMPLETED_WITH_ERR = 0x400,
+ DSI_TRIGGER_VAL = 0x7800,
+ DSI_ACK_VAL = 0xFFFF0000
+ }dsi_direct_cmd_sts;
+
+ typedef enum
+ {
+ DSI_TE_256 = 0x00,
+ DSI_TE_512 = 0x01,
+ DSI_TE_1024 = 0x02,
+ DSI_TE_2048 = 0x03
+ }dsi_te_timeout;
+
+ typedef enum
+ {
+ DSI_ARB_MODE_FIXED = 0x0,
+ DSI_ARB_MODE_ROUNDROBIN = 0x1
+ }dsi_arb_mode;
+
+ typedef struct
+ {
+ dsi_arb_mode arb_mode;
+ dsi_interface arb_fixed_if;
+ }dsi_arb_ctl;
+
+ typedef enum
+ {
+ DSI_STARTON_VSYNC = 0x00,
+ DSI_STARTON_VFP = 0x01,
+ }dsi_start_mode;
+
+ typedef enum
+ {
+ DSI_STOPBEFORE_VSYNV = 0x0,
+ DSI_STOPAT_LINEEND = 0x1,
+ DSI_STOPAT_ACTIVELINEEND = 0x2,
+ }dsi_stop_mode;
+
+ typedef enum
+ {
+ DSI_NO_BURST_MODE = 0x0,
+ DSI_BURST_MODE = 0x1,
+ }dsi_burst_mode;
+
+ typedef enum
+ {
+ DSI_VID_MODE_16_PACKED = 0x0,
+ DSI_VID_MODE_18_PACKED = 0x1,
+ DSI_VID_MODE_16_LOOSELY = 0x2,
+ DSI_VID_MODE_18_LOOSELY = 0x3
+ }dsi_vid_pixel_mode;
+
+ typedef enum
+ {
+ DSI_SYNC_PULSE_NOTACTIVE = 0x0,
+ DSI_SYNC_PULSE_ACTIVE = 0x1
+ }dsi_sync_pulse_active;
+
+ typedef enum
+ {
+ DSI_SYNC_PULSE_HORIZONTAL_NOTACTIVE = 0x0,
+ DSI_SYNC_PULSE_HORIZONTAL_ACTIVE = 0x1
+ }dsi_sync_pulse_horizontal;
+
+ typedef enum
+ {
+ DSI_NULL_PACKET = 0x0,
+ DSI_BLANKING_PACKET = 0x1,
+ DSI_LP_MODE = 0x2,
+ }dsi_blanking_packet;
+
+ typedef enum
+ {
+ DSI_RECOVERY_HSYNC = 0x0,
+ DSI_RECOVERY_VSYNC = 0x1,
+ DSI_RECOVERY_STOP = 0x2,
+ DSI_RECOVERY_HSYNC_VSYNC = 0x3
+ }dsi_recovery_mode;
+
+ typedef struct
+ {
+ dsi_start_mode vid_start_mode;
+ dsi_stop_mode vid_stop_mode;
+ dsi_virtual_ch vid_id;
+ u8 header;
+ dsi_vid_pixel_mode vid_pixel_mode;
+ dsi_burst_mode vid_burst_mode;
+ dsi_sync_pulse_active sync_pulse_active;
+ dsi_sync_pulse_horizontal sync_pulse_horizontal;
+ dsi_blanking_packet blkline_mode;
+ dsi_blanking_packet blkeol_mode;
+ dsi_recovery_mode recovery_mode;
+ }dsi_vid_main_ctl;
+
+ typedef struct
+ {
+ u16 vact_length;
+ u8 vfp_length;
+ u8 vbp_length;
+ u8 vsa_length;
+ }dsi_img_vertical_size;
+
+ typedef struct
+ {
+ u8 hsa_length;
+ u8 hbp_length;
+ u16 hfp_length;
+ u16 rgb_size;
+ }dsi_img_horizontal_size;
+
+ typedef struct
+ {
+ u16 line_val;
+ u8 line_pos;
+ u16 horizontal_val;
+ u8 horizontal_pos;
+ }dsi_img_position;
+
+ typedef enum
+ {
+ DSI_VSG_RUNNING = 0x1,
+ DSI_ERR_MISSING_DATA = 0x2,
+ DSI_ERR_MISSING_HSYNC = 0x4,
+ DSI_ERR_MISSING_VSYNC = 0x8,
+ DSI_ERR_SMALL_LENGTH = 0x10,
+ DSI_ERR_SMALL_HEIGHT = 0x20,
+ DSI_ERR_BURSTWRITE = 0x40,
+ DSI_ERR_LINEWRITE = 0x80,
+ DSI_ERR_LONGWRITE = 0x100,
+ DSI_ERR_VRS_WRONG_LENGTH = 0x200
+ }dsi_vid_mode_sts;
+
+ typedef enum
+ {
+ DSI_NULL_PACK = 0x0,
+ DSI_LP = 0x1,
+ }dsi_burst_lp;
+
+ typedef struct
+ {
+ dsi_burst_lp burst_lp;
+ u16 max_burst_limit;
+ u16 max_line_limit;
+ u16 exact_burst_limit;
+ }dsi_vca_setting;
+
+ typedef struct
+ {
+ u16 blkeol_pck;
+ u16 blkline_event_pck;
+ u16 blkline_pulse_pck;
+ u16 vert_balnking_duration;
+ u16 blkeol_duration;
+ }dsi_vid_blanking;
+
+ typedef struct
+ {
+ u8 col_red;
+ u8 col_green;
+ u8 col_blue;
+ u8 pad_val;
+ }dsi_vid_err_color;
+
+ typedef enum
+ {
+ DSI_TVG_MODE_UNIQUECOLOR = 0x0,
+ DSI_TVG_MODE_STRIPES = 0x1,
+ }dsi_tvg_mode;
+
+ typedef enum
+ {
+ DSI_TVG_STOP_FRAMEEND = 0x0,
+ DSI_TVG_STOP_LINEEND = 0x1,
+ DSI_TVG_STOP_IMMEDIATE = 0x2,
+ }dsi_tvg_stop_mode;
+
+
+
+ typedef struct
+ {
+ u8 tvg_stripe_size;
+ dsi_tvg_mode tvg_mode;
+ dsi_tvg_stop_mode stop_mode;
+ }dsi_tvg_control;
+
+ typedef struct
+ {
+ u16 tvg_nbline;
+ u16 tvg_line_size;
+ }dsi_tvg_img_size;
+
+ typedef struct
+ {
+ u8 col_red;
+ u8 col_green;
+ u8 col_blue;
+ }dsi_frame_color;
+
+ typedef enum
+ {
+ DSI_TVG_COLOR1 = 0x0,
+ DSI_TVG_COLOR2 = 0x1
+ }dsi_color_type;
+
+ typedef enum
+ {
+ DSI_TVG_STOPPED = 0x0,
+ DSI_TVG_RUNNING = 0x1
+ }dsi_tvg_state;
+
+ typedef enum
+ {
+ DSI_TVG_STOP = 0x0,
+ DSI_TVG_START = 0x1
+ }dsi_tvg_ctrl_state;
+
+ typedef enum
+ {
+ DSI_TBG_STOPPED = 0x0,
+ DSI_TBG_RUNNING = 0x1
+ }dsi_tbg_state;
+
+ typedef enum
+ {
+ DSI_SEND_1BYTE = 0x0,
+ DSI_SEND_2BYTE = 0x1,
+ DSI_SEND_BURST_STOP_COUNTER = 0x3,
+ DSI_SEND_BURST_STOP = 0x4
+ }dsi_tbg_mode;
+
+ typedef enum
+ {
+ DSI_ERR_FIXED = 0x1,
+ DSI_ERR_UNCORRECTABLE = 0x2,
+ DSI_ERR_CHECKSUM = 0x4,
+ DSI_ERR_UNDECODABLE = 0x8,
+ DSI_ERR_RECEIVE = 0x10,
+ DSI_ERR_OVERSIZE = 0x20,
+ DSI_ERR_WRONG_LENGTH = 0x40,
+ DSI_ERR_MISSING_EOT = 0x80,
+ DSI_ERR_EOT_WITH_ERR = 0x100
+ }dsi_direct_cmd_rd_sts_ctl;
+
+ typedef enum
+ {
+ DSI_TVG_STS = 0x1,
+ DSi_TBG_STS = 0x2
+ }dsi_tg_sts_ctl;
+
+typedef struct
+{
+ dsi_interface_mode dsi_if_mode;
+ dsi_interface dsiInterface;
+ dsi_if1_state dsi_if1_state;
+ dsi_link_state dsi_link_state;
+ dsi_int_mode dsi_int_mode;
+ dsi_interface_mode_type if_mode_type;
+}dsi_link_context;
+
+struct dsi_dphy_static_conf {
+ dsi_hs_invert_mode clocklanehsinvermode;
+ dsi_swap_pin_mode clocklaneswappinmode;
+ dsi_hs_invert_mode datalane1hsinvermode;
+ dsi_swap_pin_mode datalane1swappinmode;
+ dsi_hs_invert_mode datalane2hsinvermode;
+ dsi_swap_pin_mode datalane2swappinmode;
+ u8 ui_x4; /** unit interval time for clock lane*/
+};
+struct dsi_link_conf {
+ dsi_link_state dsiLinkState;
+ dsi_interface dsiInterface;
+ dsi_interface_mode dsiInterfaceMode;
+ dsi_interface_mode_type videoModeType; /** for LP/HS mode for vide mode */
+ dsi_interface_mode_type commandModeType;/** for LP/HS mode for command mode */
+ dsi_lane_mode clockLaneMode;
+ dsi_lane_mode dataLane1Mode;
+ dsi_lane_mode dataLane2Mode;
+ dsi_arb_mode arbMode;
+ dsi_te_ctrl if1TeCtrl;
+ dsi_te_ctrl if2TeCtrl;
+ dsi_te_ctrl regTeCtrl;
+ dsi_bta_mode btaMode;
+ dsi_rd_ctrl rdCtrl;
+ dsi_host_eot_gen_mode hostEotGenMode;
+ dsi_eot_gen_mode displayEotGenMode;
+ dsi_ecc_gen_mode dispEccGenMode;
+ dsi_checksum_gen_mode dispChecksumGenMode;
+ dsi_clk_continious_hs_mode clockContiniousMode;
+ u8 paddingValue;
+};
+#endif /** __KERNEL_ */
+
+u32 dsiconfdphy1(mcde_pll_ref_clk pll_sel, mcde_ch_id chid, dsi_link link);
+u32 dsidisplayinitLPcmdmode(mcde_ch_id chid, dsi_link link);
+
+dsi_error dsisetlinkstate(dsi_link link, dsi_link_state linkState, mcde_ch_id chid);
+u32 dsiLinkInit(struct dsi_link_conf *pdsiLinkConf, struct dsi_dphy_static_conf dphyStaticConf, mcde_ch_id chid, dsi_link link);
+int mcde_dsi_test_LP_directcommand_mode(struct fb_info *info,u32 key);
+int mcde_dsi_start(struct fb_info *info);
+int mcde_dsi_test_dsi_HS_directcommand_mode(struct fb_info *info,u32 key);
+
+int mcde_dsi_read_reg(struct fb_info *info, u32 reg, u32 *value);
+int mcde_dsi_write_reg(struct fb_info *info, u32 reg, u32 value);
+
+dsi_error dsisetPLLcontrol(dsi_link link, mcde_ch_id chid, dsi_pll_ctl pll_ctl);
+dsi_error dsisetPLLmode(dsi_link link, mcde_ch_id chid, dsi_pll_mode mode);
+dsi_error dsigetlinkstatus(dsi_link link, mcde_ch_id chid, u8 *p_status);
+dsi_error dsisetInterface(dsi_link link, mcde_ch_id chid, dsi_if_state state, dsi_interface interface);
+dsi_error dsisetInterface1mode(dsi_link link, dsi_interface_mode mode, mcde_ch_id chid);
+dsi_error dsisetInterfaceInLpm(dsi_link link, mcde_ch_id chid, dsi_interface_mode_type modType, dsi_interface interface);
+dsi_error dsisetTEtimeout(dsi_link link, mcde_ch_id chid, u32 te_timeout);
+dsi_error dsireadset(dsi_link link, dsi_rd_ctrl state, mcde_ch_id chid);
+dsi_error dsisetBTAmode(dsi_link link, dsi_bta_mode mode, mcde_ch_id chid);
+dsi_error dsisetdispEOTGenmode(dsi_link link, dsi_eot_gen_mode mode, mcde_ch_id chid);
+dsi_error dsisetdispHOSTEOTGenmode(dsi_link link, dsi_host_eot_gen_mode mode, mcde_ch_id chid);
+dsi_error dsisetdispCHKSUMGenmode(dsi_link link, dsi_checksum_gen_mode mode, mcde_ch_id chid);
+dsi_error dsisetdispECCGenmode(dsi_link link, dsi_ecc_gen_mode mode, mcde_ch_id chid);
+dsi_error dsisetCLKHSsendingmode(dsi_link link, dsi_clk_continious_hs_mode mode, mcde_ch_id chid);
+dsi_error dsisetpaddingval(dsi_link link, mcde_ch_id chid, u8 padding);
+dsi_error dsisetTE(dsi_link link, dsi_te_en tearing, dsi_te_ctrl state, mcde_ch_id chid);
+dsi_error dsisetlaneULPwaittime(dsi_link link, mcde_ch_id chid, dsi_lane lane, u16 timeout);
+
+dsi_error dsisetlanestate(dsi_link link, mcde_ch_id chid, dsi_lane_state mode, dsi_lane lane);
+dsi_error dsiset_hs_clock(dsi_link link, struct dsi_dphy_static_conf dphyStaticConf, mcde_ch_id chid);
+dsi_error dsisetDPHYtimeout(dsi_link link, mcde_ch_id chid, dsi_dphy_timeout timeout);
+void mcde_dsi_tpodisplay_init(struct fb_info *info);
+void mcde_dsi_taaldisplay_init(struct fb_info *info);
+
+/* following Apis are used by stw5810 driver for configuration */
+u32 dsisenddirectcommand(dsi_interface_mode_type mode_type, u32 cmd_head,u32 cmd_size,u32 cmd1,u32 cmd2,u32 cmd3,u32 cmd4, dsi_link link, mcde_ch_id chid);
+
+u32 dsiLPdcslongwrite(u32 VC_ID, u32 NoOfParam, u32 Param0, u32 Param1,u32 Param2, u32 Param3,
+ u32 Param4,u32 Param5,u32 Param6,u32 Param7,u32 Param8, u32 Param9,u32 Param10,u32 Param11,
+ u32 Param12,u32 Param13,u32 Param14, u32 Param15, mcde_ch_id chid, dsi_link link);
+
+u32 dsiLPdcsshortwrite1parm(u32 VC_ID, u32 Param0,u32 Param1, mcde_ch_id chid, dsi_link link);
+u32 dsiLPdcsshortwritenoparam(u32 VC_ID, u32 Param0, mcde_ch_id chid, dsi_link link);
+
+u32 dsiHSdcslongwrite(u32 VC_ID, u32 NoOfParam, u32 Param0, u32 Param1,u32 Param2, u32 Param3,
+ u32 Param4,u32 Param5,u32 Param6,u32 Param7,u32 Param8, u32 Param9,u32 Param10,u32 Param11,
+ u32 Param12,u32 Param13,u32 Param14, u32 Param15, mcde_ch_id chid, dsi_link link);
+
+u32 dsiHSdcsshortwrite1parm(u32 VC_ID, u32 Param0,u32 Param1, mcde_ch_id chid, dsi_link link);
+u32 dsiHSdcsshortwritenoparam(u32 VC_ID, u32 Param0, mcde_ch_id chid, dsi_link link);
+u32 dsireaddata(u8* byte0, u8* byte1, u8* byte2, u8* byte3, mcde_ch_id chid, dsi_link link);
+
+
+#ifdef _cplusplus
+}
+#endif /* _cplusplus */
+
+#endif /* !defined(_DSI_H_) */
+
+
diff --git a/arch/arm/mach-ux500/include/mach/dsi_reg.h b/arch/arm/mach-ux500/include/mach/dsi_reg.h
new file mode 100755
index 00000000000..a5fc8e39ff2
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/dsi_reg.h
@@ -0,0 +1,495 @@
+/*---------------------------------------------------------------------------*/
+/* Copyright (C) ST Ericsson 2009 */
+/* */
+/* This program is free software; you can redistribute it and/or modify it */
+/* under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, */
+/* or (at your option)any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */
+/* the GNU Lesser General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*---------------------------------------------------------------------------*/
+
+#ifndef _DSIREG_H_
+#define _DSIREG_H_
+
+#ifdef _cplusplus
+extern "C" {
+#endif /* _cplusplus */
+
+#include <linux/types.h>
+
+#define DSI_SET_BIT 0x1
+#define DSI_CLEAR_BIT 0x0
+#define DSI_SET_ALL_BIT 0xFFFFFFFF
+#define DSI_CLEAR_ALL_BIT 0x0
+#define DSI_MCTL_INTMODE_MASK MASK_BIT0
+#define DSI_MCTL_LINKEN_MASK MASK_BIT0
+#define DSI_MCTL_INTERFACE1_MODE_MASK MASK_BIT1
+#define DSI_MCTL_VID_EN_MASK MASK_BIT2
+#define DSI_MCTL_TVG_SEL_MASK MASK_BIT3
+#define DSI_MCTL_TBG_SEL_MASK MASK_BIT4
+#define DSI_MCTL_READEN_MASK MASK_BIT8
+#define DSI_MCTL_BTAEN_MASK MASK_BIT9
+#define DSI_MCTL_DISPECCGEN_MASK MASK_BIT10
+#define DSI_MCTL_DISPCHECKSUMGEN_MASK MASK_BIT11
+#define DSI_MCTL_HOSTEOTGEN_MASK MASK_BIT12
+#define DSI_MCTL_DISPEOTGEN_MASK MASK_BIT13
+#define DSI_PLL_MASTER_MASK MASK_BIT16
+#define DSI_PLL_OUT_SEL_MASK MASK_BIT11
+#define DSI_PLL_IN_SEL_MASK MASK_BIT10
+#define DSI_PLL_DIV_MASK (MASK_BIT7 | MASK_BIT8 | MASK_BIT9)
+#define DSI_PLL_MULT_MASK (MASK_BYTE0 & 0x7F)
+#define DSI_REG_TE_MASK MASK_BIT7
+#define DSI_IF1_TE_MASK MASK_BIT5
+#define DSI_IF2_TE_MASK MASK_BIT6
+#define DSI_LANE2_EN_MASK MASK_BIT0
+#define DSI_FORCE_STOP_MODE_MASK MASK_BIT1
+#define DSI_CLK_CONTINUOUS_MASK MASK_BIT2
+#define DSI_CLK_ULPM_EN_MASK MASK_BIT3
+#define DSI_DAT1_ULPM_EN_MASK MASK_BIT4
+#define DSI_DAT2_ULPM_EN_MASK MASK_BIT5
+#define DSI_WAIT_BURST_MASK (MASK_BIT6 | MASK_BIT7 | MASK_BIT8 | MASK_BIT9)
+#define DSI_CLKLANESTS_MASK (MASK_BIT0 | MASK_BIT1)
+#define DSI_DATALANE1STS_MASK (MASK_BIT2 | MASK_BIT3 | MASK_BIT4)
+#define DSI_DATALANE2STS_MASK (MASK_BIT5 | MASK_BIT6)
+#define DSI_CLK_DIV_MASK MASK_QUARTET0
+#define DSI_HSTX_TO_MASK (MASK_QUARTET1 | MASK_BYTE1 | MASK_BIT16 | MASK_BIT17)
+#define DSI_LPRX_TO_MASK (MASK_BYTE3 | MASK_QUARTET5 | MASK_BIT18 | MASK_BIT18)
+#define DSI_CLK_ULPOUT_MASK (MASK_BYTE0 | MASK_BIT8)
+#define DSI_DATA_ULPOUT_MASK (MASK_QUARTET3 | MASK_BIT9 | MASK_BIT10 | MASK_BIT11 | MASK_BIT16 | MASK_BIT17)
+#define DSI_PLL_START_MASK MASK_BIT0
+#define DSI_CKLANE_EN_MASK MASK_BIT3
+#define DSI_DAT1_EN_MASK MASK_BIT4
+#define DSI_DAT2_EN_MASK MASK_BIT5
+#define DSI_CLK_ULPM_MASK MASK_BIT6
+#define DSI_DAT1_ULPM_MASK MASK_BIT7
+#define DSI_DAT2_ULPM_MASK MASK_BIT8
+#define DSI_IF1_EN_MASK MASK_BIT9
+#define DSI_IF2_EN_MASK MASK_BIT10
+#define DSI_MAIN_STS_MASK MASK_BYTE0
+#define DSI_DPHY_ERROR_MASK MASK_HALFWORD0
+#define DSI_IF_DATA_MASK MASK_HALFWORD0
+#define DSI_IF_VALID_MASK MASK_BIT16
+#define DSI_IF_START_MASK MASK_BIT17
+#define DSI_IF_FRAME_SYNC_MASK MASK_BIT18
+#define DSI_IF_STALL_MASK MASK_BIT0
+#define DSI_INT_VAL_MASK MASK_BIT0
+#define DSI_DIRECT_CMD_RD_STS_MASK (MASK_BYTE0 | MASK_BIT8)
+#define DSI_CMD_MODE_STS_MASK (MASK_QUARTET0 | MASK_BIT4 | MASK_BIT5)
+#define DSI_RD_ID_MASK (MASK_BIT16 | MASK_BIT17 )
+#define DSI_RD_DCSNOTGENERIC_MASK MASK_BIT18
+#define DSI_CMD_NAT_MASK (MASK_BIT0 | MASK_BIT1 | MASK_BIT2)
+#define DSI_CMD_LONGNOTSHORT_MASK MASK_BIT3
+#define DSI_CMD_HEAD_MASK (MASK_QUARTET2 | MASK_BIT12 | MASK_BIT13)
+#define DSI_CMD_ID_MASK (MASK_BIT14 | MASK_BIT15)
+#define DSI_CMD_SIZE_MASK (MASK_QUARTET4 | MASK_BIT20)
+#define DSI_CMD_LP_EN_MASK (MASK_BIT21)
+#define DSI_TRIGGER_VAL_MASK MASK_QUARTET6
+#define DSI_TE_LOWERBIT_MASK MASK_BYTE2
+#define DSI_TE_UPPERBIT_MASK (MASK_BIT24 | MASK_BIT25)
+#define DSI_FIL_VAL_MASK MASK_BYTE1
+#define DSI_ARB_MODE_MASK MASK_BIT6
+#define DSI_ARB_PRI_MASK MASK_BIT7
+#define DSI_START_MODE_MASK (MASK_BIT0 | MASK_BIT1 )
+#define DSI_STOP_MODE_MASK (MASK_BIT2 | MASK_BIT3)
+#define DSI_VID_ID_MASK (MASK_BIT4 | MASK_BIT5)
+#define DSI_HEADER_MASK (MASK_BIT6 | MASK_BIT7 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10 | MASK_BIT11)
+#define DSI_PIXEL_MODE_MASK (MASK_BIT12 | MASK_BIT13)
+#define DSI_BURST_MODE_MASK (MASK_BIT14)
+#define DSI_SYNC_PULSE_ACTIVE_MASK (MASK_BIT15)
+#define DSI_SYNC_PULSE_HORIZONTAL_MASK (MASK_BIT16)
+#define DSI_BLKLINE_MASK (MASK_BIT17 | MASK_BIT18)
+#define DSI_BLKEOL_MASK (MASK_BIT19 | MASK_BIT20)
+#define DSI_RECOVERY_MODE_MASK (MASK_BIT21 | MASK_BIT22)
+#define DSI_VSA_LENGTH_MASK MASK_QUARTET0
+#define DSI_VBP_LENGTH_MASK MASK_QUARTET1
+#define DSI_VFP_LENGTH_MASK MASK_BYTE1
+#define DSI_VACT_LENGTH_MASK (MASK_BYTE2 | MASK_QUARTET6)
+#define DSI_HSA_LENGTH_MASK MASK_BYTE0
+#define DSI_HBP_LENGTH_MASK MASK_BYTE1
+#define DSI_HFP_LENGTH_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
+#define DSI_RGB_SIZE_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
+#define DSI_LINE_POS_MASK (MASK_BIT0 | MASK_BIT1)
+#define DSI_LINE_VAL_MASK (MASK_BIT2 | MASK_BIT3 | MASK_QUARTET1 | MASK_QUARTET2 | MASK_BIT12)
+#define DSI_HORI_POS_MASK (MASK_BIT0 | MASK_BIT1 |MASK_BIT2)
+#define DSI_HORI_VAL_MASK (MASK_BYTE1 | MASK_QUARTET1 | MASK_BIT3)
+#define DSI_VID_MODE_STS_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9)
+#define DSI_BURST_LP_MASK MASK_BIT16
+#define DSI_MAX_BURST_LIMIT_MASK MASK_HALFWORD0
+#define DSI_MAX_LINE_LIMIT_MASK MASK_HALFWORD1
+#define DSI_EXACT_BURST_LIMIT_MASK MASK_HALFWORD0
+#define DSI_BLKLINE_EVENT_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
+#define DSI_BLKEOL_PCK_MASK (MASK_BYTE2 | MASK_BIT15 | MASK_BIT14 | MASK_BIT13 | MASK_BIT24 | MASK_BIT25)
+#define DSI_BLKLINE_PULSE_PCK_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
+#define DSI_BLKEOL_DURATION_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
+#define DSI_VERT_BLANK_DURATION_MASK (MASK_BYTE2 | MASK_BIT15 | MASK_BIT14 | MASK_BIT13 | MASK_BIT24 | MASK_BIT25)
+#define DSI_COL_RED_MASK MASK_BYTE0
+#define DSI_COL_GREEN_MASK MASK_BYTE1
+#define DSI_COL_BLUE_MASK MASK_BYTE2
+#define DSI_PAD_VAL_MASK MASK_BYTE3
+#define DSI_TVG_STRIPE_MASK (MASK_BIT5 | MASK_BIT6 | MASK_BIT7)
+#define DSI_TVG_MODE_MASK (MASK_BIT3 | MASK_BIT4 )
+#define DSI_TVG_STOPMODE_MASK (MASK_BIT1 | MASK_BIT2 )
+#define DSI_TVG_RUN_MASK MASK_BIT0
+#define DSI_TVG_NBLINE_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
+#define DSI_TVG_LINE_SIZE_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
+#define DSI_CMD_MODE_STATUS_MASK (MASK_QUARTET0 | MASK_BIT4 | MASK_BIT5 )
+#define DSI_DIRECT_CMD_STS_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10 )
+#define DSI_DIRECT_CMD_RD_STATUS_MASK (MASK_BYTE0 | MASK_BIT8 )
+#define DSI_VID_MODE_STATUS_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 )
+#define DSI_TG_STS_MASK (MASK_BIT0 | MASK_BIT1)
+#define DSI_CLK_TRIM_RD_MASK MASK_BIT0
+#define DSI_IF1_LPM_EN_MASK MASK_BIT4
+#define DSI_IF2_LPM_EN_MASK MASK_BIT5
+#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT2 MASK_BIT5
+#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT2 MASK_BIT4
+#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT1 MASK_BIT3
+#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT1 MASK_BIT2
+#define DSIMCTL_DPHY_STATIC_HS_INVERT_CLK MASK_BIT1
+#define DSIMCTL_DPHY_STATIC_SWAP_PINS_CLK MASK_BIT0
+#define DSIMCTL_DPHY_STATIC_UI_X4 (MASK_BIT6 | MASK_BIT7 | MASK_QUARTET2)
+
+#define DSI_MCTL_INTERFACE1_MODE_SHIFT 1
+#define DSI_MCTL_VID_EN_SHIF 2
+#define DSI_MCTL_TVG_SEL_SHIFT 3
+#define DSI_MCTL_TBG_SEL_SHIFT 4
+#define DSI_MCTL_READEN_SHIFT 8
+#define DSI_MCTL_BTAEN_SHIFT 9
+#define DSI_MCTL_DISPECCGEN_SHIFT 10
+#define DSI_MCTL_DISPCHECKSUMGEN_SHIFT 11
+#define DSI_MCTL_HOSTEOTGEN_SHIFT 12
+#define DSI_MCTL_DISPEOTGEN_SHIFT 13
+#define DSI_PLL_MASTER_SHIFT 16
+#define DSI_PLL_OUT_SEL_SHIFT 11
+#define DSI_PLL_IN_SEL_SHIFT 10
+#define DSI_MCTL_VID_EN_SHIFT 2
+#define DSI_PLL_DIV_SHIFT 7
+#define DSI_REG_TE_SHIFT 7
+#define DSI_IF1_TE_SHIFT 5
+#define DSI_IF2_TE_SHIFT 6
+#define DSI_FORCE_STOP_MODE_SHIFT 1
+#define DSI_CLK_CONTINUOUS_SHIFT 2
+#define DSI_CLK_ULPM_EN_SHIFT 3
+#define DSI_DAT1_ULPM_EN_SHIFT 4
+#define DSI_DAT2_ULPM_EN_SHIFT 5
+#define DSI_WAIT_BURST_SHIFT 6
+#define DSI_DATALANE1STS_SHIFT 2
+#define DSI_DATALANE2STS_SHIFT 5
+#define DSI_HSTX_TO_SHIFT 4
+#define DSI_LPRX_TO_SHIFT 18
+#define DSI_DATA_ULPOUT_SHIFT 9
+#define DSI_CKLANE_EN_SHIFT 3
+#define DSI_DAT1_EN_SHIFT 4
+#define DSI_DAT2_EN_SHIFT 5
+#define DSI_CLK_ULPM_SHIFT 6
+#define DSI_DAT1_ULPM_SHIFT 7
+#define DSI_DAT2_ULPM_SHIFT 8
+#define DSI_IF1_EN_SHIFT 9
+#define DSI_IF2_EN_SHIFT 10
+#define DSI_IF_VALID_SHIFT 16
+#define DSI_IF_START_SHIFT 17
+#define DSI_IF_FRAME_SYNC_SHIFT 18
+#define DSI_RD_ID_SHIFT 16
+#define DSI_RD_DCSNOTGENERIC_SHIFT 18
+#define DSI_CMD_LONGNOTSHORT_SHIFT 3
+#define DSI_CMD_HEAD_SHIFT 8
+#define DSI_CMD_ID_SHIFT 14
+#define DSI_CMD_SIZE_SHIFT 16
+#define DSI_CMD_LP_EN_SHIFT 21
+#define DSI_TRIGGER_VAL_SHIFT 24
+#define DSI_TE_LOWERBIT_SHIFT 16
+#define DSI_TE_UPPERBIT_SHIFT 24
+#define DSI_FIL_VAL_SHIFT 8
+#define DSI_ARB_MODE_SHIFT 6
+#define DSI_ARB_PRI_SHIFT 7
+#define DSI_STOP_MODE_SHIFT 2
+#define DSI_VID_ID_SHIFT 4
+#define DSI_HEADER_SHIFT 6
+#define DSI_PIXEL_MODE_SHIFT 12
+#define DSI_BURST_MODE_SHIFT 14
+#define DSI_SYNC_PULSE_ACTIVE_SHIFT 15
+#define DSI_SYNC_PULSE_HORIZONTAL_SHIFT 16
+#define DSI_BLKLINE_SHIFT 17
+#define DSI_BLKEOL_SHIFT 19
+#define DSI_RECOVERY_MODE_SHIFT 21
+#define DSI_VBP_LENGTH_SHIFT 4
+#define DSI_VFP_LENGTH_SHIFT 8
+#define DSI_VACT_LENGTH_SHIFT 16
+#define DSI_HBP_LENGTH_SHIFT 8
+#define DSI_HFP_LENGTH_SHIFT 16
+#define DSI_LINE_VAL_SHIFT 2
+#define DSI_HORI_VAL_SHIFT 3
+#define DSI_BURST_LP_SHIFT 16
+#define DSI_MAX_LINE_LIMIT_SHIFT 16
+#define DSI_BLKEOL_PCK_SHIFT 13
+#define DSI_VERT_BLANK_DURATION_SHIFT 13
+#define DSI_COL_GREEN_SHIFT 8
+#define DSI_COL_BLUE_SHIFT 16
+#define DSI_PAD_VAL_SHIFT 24
+#define DSI_TVG_STRIPE_SHIFT 1
+#define DSI_TVG_MODE_SHIFT 3
+#define DSI_TVG_STOPMODE_SHIFT 5
+#define DSI_TVG_NBLINE_SHIFT 16
+#define DSIMCTL_DPHY_STATIC_SWAP_PINS_CLK_SHIFT 0
+#define DSIMCTL_DPHY_STATIC_HS_INVERT_CLK_SHIFT 1
+#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT1_SHIFT 2
+#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT1_SHIFT 3
+#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT2_SHIFT 4
+#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT2_SHIFT 5
+#define DSIMCTL_DPHY_STATIC_UI_X4_SHIFT 6
+#define DSI_IF1_LPM_EN_MASK_SHIFT 4
+#define DSI_IF2_LPM_EN_MASK_SHIFT 5
+
+#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK 0x80
+#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK_SHIFT 7
+
+#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK 0x40
+#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK_SHIFT 6
+
+#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR 0x20
+#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR_SHIFT 5
+
+#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR 0x10
+#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR_SHIFT 4
+
+#define DSI_MCTL_MAIN_STS_DAT2_READY 0x8
+#define DSI_MCTL_MAIN_STS_DAT2_READY_SHIFT 3
+
+#define DSI_MCTL_MAIN_STS_DAT1_READY 0x4
+#define DSI_MCTL_MAIN_STS_DAT1_READY_SHIFT 2
+
+#define DSI_MCTL_MAIN_STS_CLKLANE_READY 0x2
+#define DSI_MCTL_MAIN_STS_CLKLANE_READY_SHIFT 1
+
+#define DSI_MCTL_MAIN_STS_PLL_LOCK 0x1
+#define DSI_MCTL_MAIN_STS_PLL_LOCK_SHIFT 0
+/** Test mode conf */
+
+//**********************************************************************************************************************
+/** - DIRECT_CMD_WRDAT0 */
+//**********************************************************************************************************************
+
+#define DSIDIRECT_CMD_WRDAT0_WRDAT3 (0xFF000000)
+#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT3 (24)
+#define DSIDIRECT_CMD_WRDAT0_WRDAT2 (0xFF0000)
+#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT2 (16)
+#define DSIDIRECT_CMD_WRDAT0_WRDAT1 (0xFF00)
+#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT1 (8)
+#define DSIDIRECT_CMD_WRDAT0_WRDAT0 (0xFF)
+#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT0 (0)
+
+//**********************************************************************************************************************
+/** - DIRECT_CMD_WRDAT1 */
+//**********************************************************************************************************************
+
+#define DSIDIRECT_CMD_WRDAT1_WRDAT7 (0xFF000000)
+#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT7 (24)
+#define DSIDIRECT_CMD_WRDAT1_WRDAT6 (0xFF0000)
+#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT6 (16)
+#define DSIDIRECT_CMD_WRDAT1_WRDAT5 (0xFF00)
+#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT5 (8)
+#define DSIDIRECT_CMD_WRDAT1_WRDAT4 (0xFF)
+#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT4 (0)
+
+
+//**********************************************************************************************************************
+/** - DIRECT_CMD_WRDAT2 */
+//**********************************************************************************************************************
+
+#define DSIDIRECT_CMD_WRDAT2_WRDAT11 (0xFF000000)
+#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT11 (24)
+#define DSIDIRECT_CMD_WRDAT2_WRDAT10 (0xFF0000)
+#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT10 (16)
+#define DSIDIRECT_CMD_WRDAT2_WRDAT9 (0xFF00)
+#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT9 (8)
+#define DSIDIRECT_CMD_WRDAT2_WRDAT8 (0xFF)
+#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT8 (0)
+
+//**********************************************************************************************************************
+/** - DIRECT_CMD_WRDAT3 */
+//**********************************************************************************************************************
+
+#define DSIDIRECT_CMD_WRDAT3_WRDAT15 (0xFF000000)
+#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT15 (24)
+#define DSIDIRECT_CMD_WRDAT3_WRDAT14 (0xFF0000)
+#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT14 (16)
+#define DSIDIRECT_CMD_WRDAT3_WRDAT13 (0xFF00)
+#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT13 (8)
+#define DSIDIRECT_CMD_WRDAT3_WRDAT12 (0xFF)
+#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT12 (0)
+//**********************************************************************************************************************
+/** - DIRECT_CMD_READ */
+//**********************************************************************************************************************
+
+#define DSIDIRECT_CMD_RDAT3 (0xFF000000)
+#define Shift_DSIDIRECT_CMD_RDAT3 (24)
+#define DSIDIRECT_CMD_RDAT2 (0xFF0000)
+#define Shift_DSIDIRECT_CMD_RDAT2 (16)
+#define DSIDIRECT_CMD_RDAT1 (0xFF00)
+#define Shift_DSIDIRECT_CMD_RDAT1 (8)
+#define DSIDIRECT_CMD_RDAT0 (0xFF)
+#define Shift_DSIDIRECT_CMD_RDAT0 (0)
+
+/** TPO COMMAND HEADER */
+#define TPO_CMD_NONE 0x00
+#define TPO_CMD_SWRESET 0x01 /** SWRESET: Software Reset (01h) */
+#define TPO_CMD_SLPOUT 0x11 /** SLPOUT: Sleep Out (11h) */
+#define TPO_CMD_NORON 0x13 /** NORON: Normal Display Mode On (13h) */
+#define TPO_CMD_INVOFF 0x20 /** INVOFF: Display Inversion Off (20h) */
+#define TPO_CMD_INVON 0x21 /** INVOFF: Display Inversion Off (20h) */
+#define TPO_CMD_GAMMA_SET 0x26 /** Gamma set//reset GC0G2.2 */
+
+#define TPO_CMD_DISPOFF 0x28 /** DISPON: Display On (29h) */
+#define TPO_CMD_DISPON 0x29 /** DISPON: Display On (29h) */
+#define TPO_CMD_CASET 0x2A /** CASET :Columen address select */
+#define TPO_CMD_RASET 0x2B /** RASET :Row address select */
+#define TPO_CMD_RAMWR 0x2C /** RAMWR ram write */
+
+#define TPO_CMD_MADCTR 0x36 /** MADCTR: Memory Data Access Control (36h) */
+#define TPO_CMD_IDMOFF 0x38 /** IDMON: Idle Mode On (39h) */
+#define TPO_CMD_IDMON 0x39 /** IDMON: Idle Mode On (39h) */
+#define TPO_CMD_COLMOD 0x3A /** COLMOD: Interface Pixel Format (3Ah). */
+#define TPO_CMD_RAMWR_CONTINUE 0x3C /** Ram write continue */
+#define TPO_CMD_IFMODE 0xB0 /** IFMODE: Set Display Interface Mode (B0h) */
+#define TPO_CMD_DISSET6 0xB7 /** Display Function Setting 6 (B7h) */
+#define TPO_CMD_LPTS_FUNCTION_SET3 0xBC /** LPTS_FUNCTION_SET3 (0xBC) */
+#define TPO_CMD_DSLPOUT 0xCA /** deep sleepout 0xca */
+
+
+#define TPO_CMD_GAMCTRP1 0xE0 /** GAMCTRP1: Set Positive Gamma Correction Characteristics (E0h) */
+#define TPO_CMD_GAMCTRN1 0xE1 /** GAMCTRN1: Set Negative Gamma Correction Characteristics (E1h) */
+#define TPO_CMD_GAMCTRP2 0xE2 /** GAMCTRP2: Gamma (‘+’polarity) Correction Characteristics Setting (E2h) */
+#define TPO_CMD_GAMCTRN2 0xE3 /** GAMCTRN2: Gamma (‘-’polarity) Correction Characteristics Setting (E3h) */
+#define TPO_CMD_GAMCTRP3 0xE4 /** GAMCTRP3: Gamma (‘+’polarity) Correction Characteristics Setting (E4h) */
+#define TPO_CMD_GAMCTRN3 0xE5 /** GAMCTRN3: Gamma (‘-’polarity) Correction Characteristics Setting (E5h) */
+#define TPO_CMD_GAM_R_SEL 0xEA /** GAMMA SELECTION */
+
+
+
+#define VC_ID0 0
+#define VC_ID1 1
+
+
+
+
+struct dsi_link_registers
+{
+ /** Main control registers */
+ volatile u32 mctl_integration_mode;
+ volatile u32 mctl_main_data_ctl;
+ volatile u32 mctl_main_phy_ctl;
+ volatile u32 mctl_pll_ctl;
+ volatile u32 mctl_lane_sts;
+ volatile u32 mctl_dphy_timeout;
+ volatile u32 mctl_ulpout_time;
+ volatile u32 mctl_dphy_static;
+ volatile u32 mctl_main_en;
+ volatile u32 mctl_main_sts;
+ volatile u32 mctl_dphy_err;
+
+ volatile u32 reserved1;
+ /**
+ integration mode registers */
+ volatile u32 int_vid_rddata;
+ volatile u32 int_vid_gnt;
+ volatile u32 int_cmd_rddata;
+ volatile u32 int_cmd_gnt;
+ volatile u32 int_interrupt_ctl;
+ volatile u32 reserved2[3];
+ /**
+ Command mode registers */
+ volatile u32 cmd_mode_ctl;
+ volatile u32 cmd_mode_sts;
+ volatile u32 reserved3[2];
+ /**
+ Direct Command registers */
+ volatile u32 direct_cmd_send;
+ volatile u32 direct_cmd_main_settings;
+ volatile u32 direct_cmd_sts;
+ volatile u32 direct_cmd_rd_init;
+ volatile u32 direct_cmd_wrdat0;
+ volatile u32 direct_cmd_wrdat1;
+ volatile u32 direct_cmd_wrdat2;
+ volatile u32 direct_cmd_wrdat3;
+ volatile u32 direct_cmd_rddat;
+ volatile u32 direct_cmd_rd_property;
+ volatile u32 direct_cmd_rd_sts;
+ volatile u32 reserved4;
+ /**
+ Video mode registers */
+ volatile u32 vid_main_ctl;
+ volatile u32 vid_vsize;
+ volatile u32 vid_hsize1;
+ volatile u32 vid_hsize2;
+ volatile u32 vid_blksize1;
+ volatile u32 vid_blksize2;
+ volatile u32 vid_pck_time;
+ volatile u32 vid_dphy_time;
+ volatile u32 vid_err_color;
+ volatile u32 vid_vpos;
+ volatile u32 vid_hpos;
+ volatile u32 vid_mode_sts;
+ volatile u32 vid_vca_setting1;
+ volatile u32 vid_vca_setting2;
+ /**
+ Test Video Mode regsiter */
+ volatile u32 tvg_ctl;
+ volatile u32 tvg_img_size;
+ volatile u32 tvg_color1;
+ volatile u32 tvg_color2;
+ volatile u32 tvg_sts;
+ volatile u32 reserved5;
+ /**
+ Test Byte generator register */
+ volatile u32 tbg_ctl;
+ volatile u32 tbg_setting;
+ volatile u32 tbg_sts;
+ volatile u32 reserved6;
+ /**
+ Interrupt Enable and Edge detection register */
+ volatile u32 mctl_main_sts_ctl;
+ volatile u32 cmd_mode_sts_ctl;
+ volatile u32 direct_cmd_sts_ctl;
+ volatile u32 direct_cmd_rd_sts_ctl;
+ volatile u32 vid_mode_sts_ctl;
+ volatile u32 tg_sts_ctl;
+ volatile u32 mctl_dphy_err_ctl;
+ volatile u32 dphy_clk_trim_rd_ctl;
+ /**
+ Error/Interrupt Clear Register */
+ volatile u32 mctl_main_sts_clr;
+ volatile u32 cmd_mode_sts_clr;
+ volatile u32 direct_cmd_sts_clr;
+ volatile u32 direct_cmd_rd_sts_clr;
+ volatile u32 vid_mode_sts_clr;
+ volatile u32 tg_sts_clr;
+ volatile u32 mctl_dphy_err_clr;
+ volatile u32 dphy_clk_trim_rd_clr;
+ /**
+ Flag registers */
+ volatile u32 mctl_main_sts_flag;
+ volatile u32 cmd_mode_sts_flag;
+ volatile u32 direct_cmd_sts_flag;
+ volatile u32 direct_cmd_rd_sts_flag;
+ volatile u32 vid_mode_sts_flag;
+ volatile u32 tg_sts_flag;
+ volatile u32 mctl_dphy_err_flag;
+ volatile u32 dphy_clk_trim_rd_flag;
+ volatile u32 dhy_lanes_trim;
+};
+
+
+
+#ifdef _cplusplus
+}
+#endif /* _cplusplus */
+
+#endif /* !defined(_DSI_H_) */
+
+
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
new file mode 100755
index 00000000000..af3998021e2
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/entry-macro.S
@@ -0,0 +1,84 @@
+/*
+ * Low-level IRQ helper macros for U8500 platforms based
+ * heavily on realview platform
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <asm/hardware/gic.h>
+
+ .macro disable_fiq
+ .endm
+
+ .macro get_irqnr_preamble, base, tmp
+ ldr \base, =IO_ADDRESS(U8500_GIC_CPU_BASE)
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
+ /*
+ * The interrupt numbering scheme is defined in the
+ * interrupt controller spec. To wit:
+ *
+ * Interrupts 0-15 are IPI
+ * 16-28 are reserved
+ * 29-31 are local. We allow 30 to be used for the watchdog.
+ * 32-1020 are global
+ * 1021-1022 are reserved
+ * 1023 is "spurious" (no interrupt)
+ *
+ * For now, we ignore all local interrupts so only return an
+ * interrupt if it's between 30 and 1020. The test_for_ipi
+ * routine below will pick up on IPIs.
+ *
+ * A simple read from the controller will tell us the number
+ * of the highest priority enabled interrupt. We then just
+ * need to check whether it is in the
+ * valid range for an IRQ (30-1020 inclusive).
+ */
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+ /* bits 12-10 = src CPU, 9-0 = int # */
+ ldr \irqstat, [\base, #GIC_CPU_INTACK]
+
+ ldr \tmp, =1021
+
+ bic \irqnr, \irqstat, #0x1c00
+
+ cmp \irqnr, #29
+ cmpcc \irqnr, \irqnr
+ cmpne \irqnr, \tmp
+ cmpcs \irqnr, \irqnr
+
+ .endm
+
+ /* We assume that irqstat (the raw value of the IRQ acknowledge
+ * register) is preserved from the macro above.
+ * If there is an IPI, we immediately signal end of interrupt
+ * on the controller, since this requires the original
+ * irqstat value which we won't easily be able to recreate
+ * later.
+ */
+
+ .macro test_for_ipi, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ cmp \irqnr, #16
+ strcc \irqstat, [\base, #GIC_CPU_EOI]
+ cmpcs \irqnr, \irqnr
+ .endm
+
+ /* As above, this assumes that irqstat and base are
+ * preserved..
+ */
+
+ .macro test_for_ltirq, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ mov \tmp, #0
+ cmp \irqnr, #29
+ moveq \tmp, #1
+ streq \irqstat, [\base, #GIC_CPU_EOI]
+ cmp \tmp, #0
+ .endm
diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h
new file mode 100755
index 00000000000..b358f71b8cd
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/gpio.h
@@ -0,0 +1,190 @@
+/*----------------------------------------------------------------------------------*/
+/* copyright STMicroelectronics, 2007. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it under */
+/* the terms of the GNU General Public License as published by the Free */
+/* Software Foundation; either version 2.1 of the License, or (at your option) */
+/* any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but WITHOUT */
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS */
+/* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*----------------------------------------------------------------------------------*/
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H
+
+#ifndef __LINUX_GPIO_H
+#error "Do not include this file directly, include <linux/gpio.h> instead."
+#endif
+
+#define ARCH_NR_GPIOS 309 /* 292+17 for STMPE1601*/
+
+#include <mach/hardware.h>
+#include <asm-generic/gpio.h>
+#include <mach/irqs.h>
+
+/*
+ * Macro to decorate plain GPIO numbers
+ */
+#define GPIO(x) (x)
+#define stm_get_gpio_base(base, offset) base
+/*
+ * Macros to get IRQ number from GPIO pin and vice-versa
+ */
+#define GPIO_TO_IRQ(gpio) (gpio + MAX_CHIP_IRQ)
+#define IRQ_TO_GPIO(irq) (irq - MAX_CHIP_IRQ)
+
+/*
+ * Standard GPIOLIB APIs (additional APIs in include/asm-generic/gpio.h)
+ */
+static inline int gpio_to_irq(unsigned int gpio)
+{
+ if (gpio_is_valid(gpio))
+ return GPIO_TO_IRQ(gpio);
+ else
+ return -EINVAL;
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+ if (irq < NR_IRQS)
+ return IRQ_TO_GPIO(irq);
+ else
+ return -EINVAL;
+}
+
+static inline int gpio_get_value(unsigned int gpio)
+{
+ return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned int gpio, int value)
+{
+ __gpio_set_value(gpio, value);
+}
+
+/*
+ * Special values for gpio_set_value() to enable platform-specific
+ * GPIO configurations, in addition to named values for 0 and 1
+ */
+#define GPIO_LOW 0
+#define GPIO_HIGH 1
+#define GPIO_PULLUP_DIS 0xA
+#define GPIO_PULLUP_EN 0xB
+#define GPIO_ALTF_A 0xAFA /* Alternate function A */
+#define GPIO_ALTF_B 0xAFB /* Alternate function B */
+#define GPIO_ALTF_C 0xAFC /* Alternate function C */
+#define GPIO_RESET 0xAFD /* Input with pull-up/down */
+
+/*
+ * Alternate Function:
+ * refered in altfun_table to pointout particular altfun to be enabled
+ * when using GPIO_ALT_FUNCTION A/B/C enable/disable operation
+ */
+typedef enum {
+ GPIO_ALT_UART_0_MODEM,
+ GPIO_ALT_UART_0_NO_MODEM,
+ GPIO_ALT_UART_1,
+ GPIO_ALT_UART_2,
+ GPIO_ALT_I2C_0,
+ GPIO_ALT_I2C_1,
+ GPIO_ALT_I2C_2,
+ GPIO_ALT_I2C_3,
+ GPIO_ALT_I2C_4,
+ GPIO_ALT_MSP_0,
+ GPIO_ALT_MSP_1,
+ GPIO_ALT_MSP_2,
+ GPIO_ALT_MSP_3,
+ GPIO_ALT_SSP_0,
+ GPIO_ALT_SSP_1,
+ GPIO_ALT_MM_CARD,
+ GPIO_ALT_SD_CARD,
+ GPIO_ALT_DMA_0,
+ GPIO_ALT_DMA_1,
+ GPIO_ALT_HSIR,
+ GPIO_ALT_CCIR656_INPUT,
+ GPIO_ALT_CCIR656_OUTPUT,
+ GPIO_ALT_LCD_PANELA,
+ GPIO_ALT_LCD_PANELB_ED,
+ GPIO_ALT_LCD_PANELB,
+ GPIO_ALT_MDIF,
+ GPIO_ALT_SDRAM,
+ GPIO_ALT_HAMAC_AUDIO_DBG,
+ GPIO_ALT_HAMAC_VIDEO_DBG,
+ GPIO_ALT_CLOCK_RESET,
+ GPIO_ALT_TSP,
+ GPIO_ALT_IRDA,
+ GPIO_ALT_USB_MINIMUM,
+ GPIO_ALT_USB_I2C,
+ GPIO_ALT_OWM,
+ GPIO_ALT_PWL,
+ GPIO_ALT_FSMC,
+ GPIO_ALT_COMP_FLASH,
+ GPIO_ALT_SRAM_NOR_FLASH,
+ GPIO_ALT_FSMC_ADDLINE_0_TO_15,
+ GPIO_ALT_SCROLL_KEY,
+ GPIO_ALT_MSHC,
+ GPIO_ALT_HPI,
+ GPIO_ALT_USB_OTG,
+ GPIO_ALT_SDIO,
+ GPIO_ALT_HSMMC,
+ GPIO_ALT_FSMC_ADD_DATA_0_TO_25,
+ GPIO_ALT_HSIT,
+ GPIO_ALT_NOR,
+ GPIO_ALT_NAND,
+ GPIO_ALT_KEYPAD,
+ GPIO_ALT_VPIP,
+ GPIO_ALT_CAM,
+ GPIO_ALT_CCP1,
+ GPIO_ALT_EMMC,
+ GPIO_ALT_SDMMC,
+ GPIO_ALT_TRACE,
+ GPIO_ALT_MMIO_INIT_BOARD,
+ GPIO_ALT_MMIO_CAM_SET_I2C,
+ GPIO_ALT_MMIO_CAM_SET_EXT_CLK,
+ GPIO_ALT_SDMMC2,
+ GPIO_ALT_TP_SET_EXT_CLK,
+ GPIO_ALT_FUNMAX /* Add new alt func before this */
+
+
+} gpio_alt_function;
+
+/* GPIO pin data*/
+typedef enum {
+ GPIO_DATA_LOW, /* GPIO pin status is low. */
+ GPIO_DATA_HIGH /* GPIO pin status is high. */
+} gpio_data;
+
+struct gpio_altfun_data {
+ gpio_alt_function altfun;
+ int start;
+ int end;
+ int cont;
+ int type;
+ char dev_name[20];
+};
+
+struct clk;
+struct gpio_platform_data {
+ struct gpio_block_data *gpio_data;
+ int gpio_block_size;
+ struct gpio_altfun_data *altfun_table;
+ int altfun_table_size;
+ struct clk *clk; /* FIXME put this somewhere more appropriate */
+};
+
+struct gpio_block_data {
+ u32 block_base;
+ u32 block_size;
+ u32 base_offset;
+ int blocks_per_irq;
+ int irq;
+};
+
+extern int stm_gpio_altfuncenable(gpio_alt_function alt_func);
+extern int stm_gpio_altfuncdisable(gpio_alt_function alt_func);