diff options
| author | Rabin Vincent <rabin.vincent@stericsson.com> | 2010-03-11 11:59:57 +0530 |
|---|---|---|
| committer | John Rigby <john.rigby@linaro.org> | 2010-09-02 22:44:38 -0600 |
| commit | 795b7a2c7638ab660275f6c4b8e7c70e45a92048 (patch) | |
| tree | a2f50cbde0d1b41712b05a513b2cee49c78369e1 /arch/arm/mach-ux500/include/mach | |
| parent | a444ceef7dc20ce466524c5dbec485cabb364ac8 (diff) | |
u8500-clock: pullback changes from mainline
Minor rework of the addresses/offsets being stored, kernel doc comments,
and macros instead of some magic values.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Diffstat (limited to 'arch/arm/mach-ux500/include/mach')
| -rw-r--r-- | arch/arm/mach-ux500/include/mach/db8500-regs.h | 2 | ||||
| -rwxr-xr-x | arch/arm/mach-ux500/include/mach/prcmu-regs.h | 41 |
2 files changed, 1 insertions, 42 deletions
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h index e3d62b94ffc..f0dcaa0cee3 100644 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h @@ -46,7 +46,7 @@ #define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000) #define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000) #define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000) -#define U8500_CLKRST7_BASE (U8500_PER7_BASE_ED + 0xf000) +#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE_ED + 0xf000) #define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) #define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h index 6f4c36cd7f5..c2c8d503553 100755 --- a/arch/arm/mach-ux500/include/mach/prcmu-regs.h +++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h @@ -66,45 +66,4 @@ /* System reset register */ #define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228) -/* Clock management */ -#define PRCM_YYCLKEN0_MGT_SET (_PRCMU_BASE + 0x510) -#define PRCM_YYCLKEN1_MGT_SET (_PRCMU_BASE + 0x514) -#define PRCM_YYCLKEN0_MGT_CLR (_PRCMU_BASE + 0x518) -#define PRCM_YYCLKEN1_MGT_CLR (_PRCMU_BASE + 0x51C) -#define PRCM_YYCLKEN0_MGT_VAL (_PRCMU_BASE + 0x520) -#define PRCM_YYCLKEN1_MGT_VAL (_PRCMU_BASE + 0x524) - -#define PRCM_SVAMMDSPCLK_MGT (_PRCMU_BASE + 0x008) -#define PRCM_SIAMMDSPCLK_MGT (_PRCMU_BASE + 0x00C) -#define PRCM_SGACLK_MGT (_PRCMU_BASE + 0x014) -#define PRCM_UARTCLK_MGT (_PRCMU_BASE + 0x018) -#define PRCM_MSP02CLK_MGT (_PRCMU_BASE + 0x01C) -#define PRCM_MSP1CLK_MGT (_PRCMU_BASE + 0x288) -#define PRCM_I2CCLK_MGT (_PRCMU_BASE + 0x020) -#define PRCM_SDMMCCLK_MGT (_PRCMU_BASE + 0x024) -#define PRCM_SLIMCLK_MGT (_PRCMU_BASE + 0x028) -#define PRCM_PER1CLK_MGT (_PRCMU_BASE + 0x02C) -#define PRCM_PER2CLK_MGT (_PRCMU_BASE + 0x030) -#define PRCM_PER3CLK_MGT (_PRCMU_BASE + 0x034) -#define PRCM_PER5CLK_MGT (_PRCMU_BASE + 0x038) -#define PRCM_PER6CLK_MGT (_PRCMU_BASE + 0x03C) -#define PRCM_PER7CLK_MGT (_PRCMU_BASE + 0x040) -#define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044) -#define PRCM_BMLCLK_MGT (_PRCMU_BASE + 0x04C) -#define PRCM_HSITXCLK_MGT (_PRCMU_BASE + 0x050) -#define PRCM_HSIRXCLK_MGT (_PRCMU_BASE + 0x054) -#define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058) -#define PRCM_APEATCLK_MGT (_PRCMU_BASE + 0x05C) -#define PRCM_APETRACECLK_MGT (_PRCMU_BASE + 0x060) -#define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064) -#define PRCM_IPI2CCLK_MGT (_PRCMU_BASE + 0x068) -#define PRCM_DSIALTCLK_MGT (_PRCMU_BASE + 0x06C) -#define PRCM_DMACLK_MGT (_PRCMU_BASE + 0x074) -#define PRCM_B2R2CLK_MGT (_PRCMU_BASE + 0x078) -#define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07C) -#define PRCM_UNIPROCLK_MGT (_PRCMU_BASE + 0x278) -#define PRCM_SSPCLK_MGT (_PRCMU_BASE + 0x280) -#define PRCM_RNGCLK_MGT (_PRCMU_BASE + 0x284) -#define PRCM_UICCCLK_MGT (_PRCMU_BASE + 0x27C) - #endif /* __MACH_PRCMU__REGS_H */ |