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authorMian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>2010-05-10 18:08:53 +0200
committerJohn Rigby <john.rigby@linaro.org>2010-09-02 22:44:36 -0600
commit3ea2f3a7cd8e2d470bdaba599efb57968d7114a6 (patch)
treec84adc3431887fb0b515ec5265e86905c3cef0f5 /arch/arm/mach-ux500/include/mach
parent747e3fcf01bb45034fe21512fe244d175559b493 (diff)
downloadlinux-2.6.34-ux500-3ea2f3a7cd8e2d470bdaba599efb57968d7114a6.tar.gz
ux500: move mach-u8500 to mach-ux500
Diffstat (limited to 'arch/arm/mach-ux500/include/mach')
-rwxr-xr-xarch/arm/mach-ux500/include/mach/ab8500-dev.h30
-rwxr-xr-xarch/arm/mach-ux500/include/mach/ab8500.h586
-rwxr-xr-xarch/arm/mach-ux500/include/mach/ab8500_codec.h435
-rwxr-xr-xarch/arm/mach-ux500/include/mach/ab8500_codec_p.h3371
-rw-r--r--arch/arm/mach-ux500/include/mach/ab8500_gpadc.h28
-rwxr-xr-xarch/arm/mach-ux500/include/mach/av8100.h531
-rwxr-xr-xarch/arm/mach-ux500/include/mach/av8100_fw.h1050
-rwxr-xr-xarch/arm/mach-ux500/include/mach/av8100_p.h188
-rwxr-xr-xarch/arm/mach-ux500/include/mach/bit_mask.h110
-rwxr-xr-xarch/arm/mach-ux500/include/mach/bits.h64
-rwxr-xr-xarch/arm/mach-ux500/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-ux500/include/mach/db5500-regs.h96
-rw-r--r--arch/arm/mach-ux500/include/mach/db8500-regs.h117
-rwxr-xr-xarch/arm/mach-ux500/include/mach/debug-macro.S20
-rwxr-xr-xarch/arm/mach-ux500/include/mach/debug.h52
-rw-r--r--arch/arm/mach-ux500/include/mach/devices.h72
-rwxr-xr-xarch/arm/mach-ux500/include/mach/dma.h106
-rwxr-xr-xarch/arm/mach-ux500/include/mach/dma_40-8500.h788
-rwxr-xr-xarch/arm/mach-ux500/include/mach/dsi.h777
-rwxr-xr-xarch/arm/mach-ux500/include/mach/dsi_reg.h495
-rwxr-xr-xarch/arm/mach-ux500/include/mach/entry-macro.S84
-rwxr-xr-xarch/arm/mach-ux500/include/mach/gpio.h190
-rwxr-xr-xarch/arm/mach-ux500/include/mach/hardware.h219
-rwxr-xr-xarch/arm/mach-ux500/include/mach/hcl_defs.h252
-rwxr-xr-xarch/arm/mach-ux500/include/mach/hsi-stm.h186
-rwxr-xr-xarch/arm/mach-ux500/include/mach/i2c-stm.h404
-rwxr-xr-xarch/arm/mach-ux500/include/mach/io.h22
-rwxr-xr-xarch/arm/mach-ux500/include/mach/irqs.h109
-rwxr-xr-xarch/arm/mach-ux500/include/mach/isa_ioctl.h51
-rwxr-xr-xarch/arm/mach-ux500/include/mach/kpd.h117
-rw-r--r--arch/arm/mach-ux500/include/mach/mcde-base.h83
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde.h1381
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde_a0.h866
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde_common.h173
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde_ioctls.h737
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde_reg.h794
-rwxr-xr-xarch/arm/mach-ux500/include/mach/memory.h20
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mmc.h341
-rwxr-xr-xarch/arm/mach-ux500/include/mach/msp.h963
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mtu.h59
-rwxr-xr-xarch/arm/mach-ux500/include/mach/prcmu-fw-api.h68
-rwxr-xr-xarch/arm/mach-ux500/include/mach/prcmu-fw-defs_ed.h415
-rwxr-xr-xarch/arm/mach-ux500/include/mach/prcmu-fw-defs_v1.h549
-rwxr-xr-xarch/arm/mach-ux500/include/mach/prcmu-regs.h110
-rwxr-xr-xarch/arm/mach-ux500/include/mach/scu.h25
-rw-r--r--arch/arm/mach-ux500/include/mach/setup.h42
-rwxr-xr-xarch/arm/mach-ux500/include/mach/shrm.h33
-rwxr-xr-xarch/arm/mach-ux500/include/mach/smp.h38
-rwxr-xr-xarch/arm/mach-ux500/include/mach/ste_conn_devices.h227
-rwxr-xr-xarch/arm/mach-ux500/include/mach/stmpe1601.h290
-rwxr-xr-xarch/arm/mach-ux500/include/mach/stmpe2401.h99
-rwxr-xr-xarch/arm/mach-ux500/include/mach/system.h29
-rwxr-xr-xarch/arm/mach-ux500/include/mach/tc35892.h183
-rwxr-xr-xarch/arm/mach-ux500/include/mach/timex.h13
-rwxr-xr-xarch/arm/mach-ux500/include/mach/u8500_acodec_ab8500.h227
-rwxr-xr-xarch/arm/mach-ux500/include/mach/u8500_tsc.h216
-rwxr-xr-xarch/arm/mach-ux500/include/mach/uart.h17
-rwxr-xr-xarch/arm/mach-ux500/include/mach/uncompress.h58
-rwxr-xr-xarch/arm/mach-ux500/include/mach/vmalloc.h18
59 files changed, 18631 insertions, 0 deletions
diff --git a/arch/arm/mach-ux500/include/mach/ab8500-dev.h b/arch/arm/mach-ux500/include/mach/ab8500-dev.h
new file mode 100755
index 00000000000..8b4d69f5d2e
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/ab8500-dev.h
@@ -0,0 +1,30 @@
+/*
+ * ab8500-dev.c - simple userspace interface to ab8500
+ *
+ * Copyright (C) 2009 STEricsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+/*
+ * struct ab8500dev_data - AB8500 /dev structure
+ * @block: bank address
+ * @addr: register address
+ * @data: data to be read/write to
+ *
+ * This supports access to AB8500 chip using normal userspace I/O calls.
+ */
+struct ab8500dev_data {
+ unsigned char block;
+ unsigned char addr;
+ unsigned char data;
+ unsigned char int_no;
+ unsigned char sig_no;
+};
+
+#define AB8500_IOC_MAGIC 'S'
+#define AB8500_GET_REGISTER _IOWR(AB8500_IOC_MAGIC, 1, struct ab8500dev_data)
+#define AB8500_SET_REGISTER _IOW(AB8500_IOC_MAGIC, 2, struct ab8500dev_data)
+#define SET_INT_SIGNAL _IOW(AB8500_IOC_MAGIC, 3, struct ab8500dev_data)
diff --git a/arch/arm/mach-ux500/include/mach/ab8500.h b/arch/arm/mach-ux500/include/mach/ab8500.h
new file mode 100755
index 00000000000..9dc62278731
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/ab8500.h
@@ -0,0 +1,586 @@
+/*
+ * Copyright ST-Ericsson 2009.
+ *
+ * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
+ * Licensed under GPLv2.
+ */
+#ifndef _AB8500_H
+#define _AB8500_H
+
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <mach/hardware.h>
+#include <asm/dma.h>
+#include <mach/dma.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-stm.h>
+#include <mach/prcmu-fw-api.h>
+/*
+ * AB8500 bank addresses
+ */
+#define AB8500_SYS_CTRL1_BLOCK 0x1
+#define AB8500_SYS_CTRL2_BLOCK 0x2
+#define AB8500_REGU_CTRL1 0x3
+#define AB8500_REGU_CTRL2 0x4
+#define AB8500_USB 0x5
+#define AB8500_TVOUT 0x6
+#define AB8500_DBI 0x7
+#define AB8500_ECI_AV_ACC 0x8
+#define AB8500_RESERVED 0x9
+#define STw4550_GPADC 0xA
+#define AB8500_GPADC 0xA
+#define AB8500_CHARGER 0xB
+#define AB8500_GAS_GAUGE 0xC
+#define AB8500_AUDIO 0xD
+#define AB8500_INTERRUPT 0xE
+#define AB8500_RTC 0xF
+#define AB8500_MISC 0x10
+#define AB8500_DEBUG 0x12
+#define AB8500_PROD_TEST 0x13
+#define AB8500_OTP_EMUL 0x15
+
+/*
+ * System control 1 register offsets.
+ * Bank = 0x01
+ */
+#define AB8500_TURNON_STAT_REG 0x0100
+#define AB8500_RESET_STAT_REG 0x0101
+#define AB8500_PONKEY1_PRESS_STAT_REG 0x0102
+
+#define AB8500_FSM_STAT1_REG 0x0140
+#define AB8500_FSM_STAT2_REG 0x0141
+#define AB8500_SYSCLK_REQ_STAT_REG 0x0142
+#define AB8500_USB_STAT1_REG 0x0143
+#define AB8500_USB_STAT2_REG 0x0144
+#define AB8500_STATUS_SPARE1_REG 0x0145
+#define AB8500_STATUS_SPARE2_REG 0x0146
+
+#define AB8500_CTRL1_REG 0x0180
+#define AB8500_CTRL2_REG 0x0181
+
+/*
+ * System control 2 register offsets.
+ * bank = 0x02
+ */
+#define AB8500_CTRL3_REG 0x0200
+#define AB8500_CTRL3_RST_DENC_MASK 0x4
+#define AB8500_CTRL3_RST_DENC_SHIFT 2
+#define AB8500_CTRL3_RST_AUD_MASK 0x2
+#define AB8500_CTRL3_RST_AUD_SHIFT 1
+#define AB8500_MAIN_WDOG_CTRL_REG 0x0201
+#define AB8500_MAIN_WDOG_TIMER_REG 0x0202
+#define AB8500_LOW_BAT_REG 0x0203
+#define AB8500_BATT_OK_REG 0x0204
+#define AB8500_SYSCLK_TIMER_REG 0x0205
+#define AB8500_SMPSCLK_CTRL_REG 0x0206
+#define AB8500_SMPSCLK_SEL1_REG 0x0207
+#define AB8500_SMPSCLK_SEL2_REG 0x0208
+#define AB8500_SMPSCLK_SEL3_REG 0x0209
+#define AB8500_SYSULPCLK_CONF_REG 0x020A
+#define AB8500_SYSULPCLK_CTRL1_REG 0x020B
+#define AB8500_SYSCLK_CTRL_REG 0x020C
+#define AB8500_SYSCLK_REQ1_VALID_REG 0x020D
+#define AB8500_SYSCLK_REQ_VALID_REG 0x020E
+#define AB8500_SYSCTRL_SPARE_REG 0x020F
+#define AB8500_PAD_CONF_REG 0x0210
+
+/*
+ * Regu control1 register offsets (SPI)
+ * Bank = 0x03
+ */
+#define AB8500_REGU_SERIAL_CTRL1_REG 0x0300
+#define AB8500_REGU_SERIAL_CTRL2_REG 0x0301
+#define AB8500_REGU_SERIAL_CTRL3_REG 0x0302
+#define AB8500_REGU_REQ_CTRL1_REG 0x0303
+#define AB8500_REGU_REQ_CTRL2_REG 0x0304
+#define AB8500_REGU_REQ_CTRL3_REG 0x0305
+#define AB8500_REGU_REQ_CTRL4_REG 0x0306
+#define AB8500_REGU_SYSCLK_REQ1HP_VALID1_REG 0x0307
+#define AB8500_REGU_SYSCLK_REQ1HP_VALID2_REG 0x0308
+#define AB8500_REGU_HWHPREQ1_VALID1_REG 0x0309
+#define AB8500_REGU_HWHPREQ1_VALID2_REG 0x030A
+#define AB8500_REGU_HWHPREQ2_VALID1_REG 0x030B
+#define AB8500_REGU_HWHPREQ2_VALID2_REG 0x030C
+#define AB8500_REGU_SWHPREQ_VALID1_REG 0x030D
+#define AB8500_REGU_SWHPREQ_VALID2_REG 0x030E
+
+#define AB8500_REGU_SYSCLK_REQ1_VALID_REG 0x030F /* only for ED*/
+#define AB8500_REGU_SYSCLK_REQ2_VALID_REG 0x0310 /*only for ED*/
+
+#define AB8500_REGU_MISC1_REG 0x0380
+#define AB8500_REGU_OTGSUPPLY_CTRL_REG 0x0381
+#define AB8500_REGU_VUSB_CTRL_REG 0x0382 /* see reg manaul*/
+#define AB8500_REGU_VAUDIO_SUPPLY_REG 0x0383
+#define AB8500_REGU_CTRL1_SPARE_REG 0x0384
+
+ /*
+ * Regu control2 register offsets (SPI/APE I2C)
+ * Bank = 0x04
+ */
+#define AB8500_REGU_ARM_REGU1_REG 0x0400
+#define AB8500_REGU_ARM_REGU2_REG 0x0401
+#define AB8500_REGU_VAPE_REGU_REG 0x0402
+#define AB8500_REGU_VSMPS1_REGU_REG 0x0403
+#define AB8500_REGU_VSMPS2_REGU_REG 0x0404
+#define AB8500_REGU_VSMPS3_REGU_REG 0x0405
+#define AB8500_REGU_VPLLVANA_REGU_REG 0x0406
+#define AB8500_REGU_VREF_DDR_REG 0x0407
+#define AB8500_REGU_EXTSUPPLY_REGU_REG 0x0408
+#define AB8500_REGU_VAUX12_REGU_REG 0x0409
+#define AB8500_REGU_VAUX12_REGU_VAUX1_MASK 0x3
+#define AB8500_REGU_VAUX12_REGU_VAUX1_SHIFT 0
+#define AB8500_REGU_VAUX12_REGU_VAUX1_FORCE_HP 0x1
+#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A
+#define AB8500_REGU_VARM_SEL1_REG 0x040B
+#define AB8500_REGU_VARM_SEL2_REG 0x040C
+#define AB8500_REGU_VARM_SEL3_REG 0x040D
+#define AB8500_REGU_VAPE_SEL1_REG 0x040E
+#define AB8500_REGU_VAPE_SEL2_REG 0x040F
+#define AB8500_REGU_VAPE_SEL3_REG 0x0410
+#define AB8500_REGU_VBB_SEL2_REG 0x0412
+#define AB8500_REGU_VSMPS1_SEL1_REG 0x0413
+#define AB8500_REGU_VSMPS1_SEL2_REG 0x0414
+#define AB8500_REGU_VSMPS1_SEL3_REG 0x0415
+#define AB8500_REGU_VSMPS2_SEL1_REG 0x0417
+#define AB8500_REGU_VSMPS2_SEL2_REG 0x0418
+#define AB8500_REGU_VSMPS2_SEL3_REG 0x0419
+#define AB8500_REGU_VSMPS3_SEL1_REG 0x041B
+#define AB8500_REGU_VSMPS3_SEL2_REG 0x041C
+#define AB8500_REGU_VSMPS3_SEL3_REG 0x041D
+#define AB8500_REGU_VAUX1_SEL_REG 0x041F
+#define AB8500_REGU_VAUX1_SEL_MASK 0xf
+#define AB8500_REGU_VAUX1_SEL_SHIFT 0
+#define AB8500_REGU_VAUX1_SEL_1_5V 0x4
+#define AB8500_REGU_VAUX1_SEL_2_5V 0x8
+#define AB8500_REGU_VAUX2_SEL_REG 0x0420
+#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421
+#define AB8500_REGU_CTRL2_SPARE_REG 0x0422
+
+/*
+ * Regu control2 Vmod register offsets
+ */
+#define AB8500_REGU_VMOD_REGU_REG 0x0440
+#define AB8500_REGU_VMOD_SEL1_REG 0x0441
+#define AB8500_REGU_VMOD_SEL2_REG 0x0442
+#define AB8500_REGU_CTRL_DISCH_REG 0x0443
+#define AB8500_REGU_CTRL_DISCH2_REG 0x0444
+
+/*
+ * Sim control register offsets
+ * Bank:0x4
+ */
+#define AB8500_SIM_REG1_SGR1L_REG 0x0480
+#define AB8500_SIM_REG1_SGR1U_REG 0x0481
+#define AB8500_SIM_REG2_SCR1L_REG 0x0482
+#define AB8500_SIM_REG2_SCR1U_REG 0x0483
+#define AB8500_SIM_REG3_SCTRLRL_REG 0x0484
+#define AB8500_SIM_REG3_SCTRLRU_REG 0x0485
+#define AB8500_SIM_ISOUICCINT_SRC_REG 0x0486
+#define AB8500_SIM_ISOUICCINT_LATCH_REG 0x0487
+#define AB8500_SIM_ISOUICCINT_MASK_REG 0x0488
+#define AB8500_SIM_REG4_USBUICC_REG 0x0489
+#define AB8500_SIM_SDELAYSEL_REG 0x048A
+#define AB8500_SIM_USBUICC_CTRL 0x048B /* bit 3 only for ED */
+
+/*
+ * USB/ULPI register offsets
+ * Bank : 0x5
+ */
+#define AB8500_USB_LINE_STAT_REG 0x0580
+#define AB8500_USB_LINE_CTRL1_REG 0x0581
+#define AB8500_USB_LINE_CTRL2_REG 0x0582
+#define AB8500_USB_LINE_CTRL3_REG 0x0583
+#define AB8500_USB_LINE_CTRL4_REG 0x0584
+#define AB8500_USB_LINE_CTRL5_REG 0x0585
+#define AB8500_USB_OTG_CTRL_REG 0x0587
+#define AB8500_USB_OTG_STAT_REG 0x0588
+#define AB8500_USB_OTG_STAT_REG 0x0588
+#define AB8500_USB_CTRL_SPARE_REG 0x0589
+#define AB8500_USB_PHY_CTRL_REG 0x058A /*only in Cut1.0*/
+
+/*
+ * TVOUT / CTRL register offsets
+ * Bank : 0x06
+ */
+#define AB8500_DENC_CONF0_REG 0x0600
+#define AB8500_DENC_CONF1_REG 0x0601
+#define AB8500_DENC_CONF2_REG 0x0602
+#define AB8500_DENC_CONF3_REG 0x0603
+#define AB8500_DENC_CONF4_REG 0x0604
+#define AB8500_DENC_CONF5_REG 0x0605
+#define AB8500_DENC_CONF6_REG 0x0606
+#define AB8500_DENC_CONF6_SOFT_RST_MASK 0x80
+#define AB8500_DENC_CONF6_SOFT_RST_SHIFT 7
+#define AB8500_DENC_CONF6_SOFT_RST_OFF 0x0
+#define AB8500_DENC_CONF6_SOFT_RST_ON 0x1
+#define AB8500_DENC_CONF7_REG 0x0607
+#define AB8500_DENC_CONF8_REG 0x0608
+#define AB8500_TVOUT_CTRL_REG 0x0680
+#define AB8500_TVOUT_CTRL2_REG 0x0681
+/*
+ * DBI register offsets
+ * Bank : 0x07
+ */
+#define AB8500_DBI_REG1_REG 0x0700
+#define AB8500_DBI_REG2_REG 0x0701
+/*
+ * ECI regsiter offsets
+ * Bank : 0x08
+ */
+#define AB8500_ECI_CTRL_REG 0x0800
+#define AB8500_ECI_HOOKLEVEL_REG 0x0801
+#define AB8500_ECI_DATAOUT_REG 0x0802
+#define AB8500_ECI_DATAIN_REG 0x0803
+/*
+ * AV Connector register offsets
+ * Bank : 0x08
+ */
+#define AB8500_AV_CONN_REG 0x0840
+/*
+ * Accessory detection register offsets
+ * Bank : 0x08
+ */
+#define AB8500_ACC_DET_DB1_REG 0x0880
+#define AB8500_ACC_DET_DB2_REG 0x0881
+/*
+ * GPADC register offsets
+ * Bank : 0x0A
+ */
+#define AB8500_GPADC_CTRL1_REG 0x0A00
+#define AB8500_GPADC_CTRL2_REG 0x0A01
+#define AB8500_GPADC_CTRL3_REG 0x0A02
+#define AB8500_GPADC_AUTO_TIMER_REG 0x0A03
+#define AB8500_GPADC_STAT_REG 0x0A04
+#define AB8500_GPADC_MANDATAL_REG 0x0A05
+#define AB8500_GPADC_MANDATAH_REG 0x0A06
+#define AB8500_GPADC_AUTODATAL_REG 0x0A07
+#define AB8500_GPADC_AUTODATAH_REG 0x0A08
+#define AB8500_GPADC_MUX_CTRL_REG 0x0A09
+/*
+ * Charger / status register offfsets
+ * Bank : 0x0B
+ */
+#define AB8500_CH_STATUS1_REG 0x0B00
+#define AB8500_CH_STATUS2_REG 0x0B01
+#define AB8500_CH_USBCH_STAT1_REG 0x0B02
+#define AB8500_CH_USBCH_STAT2_REG 0x0B03
+#define AB8500_CH_FSM_STAT_REG 0x0B04
+#define AB8500_CH_STAT_REG 0x0B05
+/*
+ * Charger / control register offfsets
+ * Bank : 0x0B
+ */
+#define AB8500_CH_VOLT_LVL_REG 0x0B40
+#define AB8500_CH_VOLT_LVL_MAX_REG 0x0B41 /*Only in Cut1.0*/
+#define AB8500_CH_OPT_CRNTLVL_REG 0x0B42 /*Only in Cut1.0*/
+#define AB8500_CH_OPT_CRNTLVL_MAX_REG 0x0B43 /*Only in Cut1.0*/
+#define AB8500_CH_WD_TIMER_REG 0x0B44 /*Only in Cut1.0*/
+#define AB8500_CH_WD_CTRL_REG 0x0B45 /*Only in Cut1.0*/
+#define AB8500_CHARG_WD_CTRL 0x0B51
+#define AB8500_LED_INDICATOR_PWM_CTRL 0x0B53
+#define AB8500_LED_INDICATOR_PWM_DUTY 0x0B54
+#define AB8500_BATT_OVV 0x0B55
+/*
+ * Charger / main control register offfsets
+ * Bank : 0x0B
+ */
+#define AB8500_MCH_CTRL1 0x0B80
+#define AB8500_MCH_CTRL2 0x0B81
+#define AB8500_MCH_IPT_CURLVL_REG 0x0B82
+#define AB8500_CH_WD_REG 0x0B83
+/*
+ * Charger / USB control register offsets
+ * Bank : 0x0B
+ */
+#define AB8500_USBCH_CTRL1_REG 0x0BC0
+#define AB8500_USBCH_CTRL2_REG 0x0BC1
+#define AB8500_USBCH_IPT_CRNTLVL_REG 0x0BC2
+/*
+ * Gas Gauge register offsets
+ * Bank : 0x0C
+ */
+#define AB8500_GASG_CC_CTRL_REG 0x0C00
+#define AB8500_GASG_CC_ACCU1_REG 0x0C01
+#define AB8500_GASG_CC_ACCU2_REG 0x0C02
+#define AB8500_GASG_CC_ACCU3_REG 0x0C03
+#define AB8500_GASG_CC_ACCU4_REG 0x0C04
+#define AB8500_GASG_CC_SMPL_CNTRL_REG 0x0C05
+#define AB8500_GASG_CC_SMPL_CNTRH_REG 0x0C06
+#define AB8500_GASG_CC_SMPL_CNVL_REG 0x0C07
+#define AB8500_GASG_CC_SMPL_CNVH_REG 0x0C08
+#define AB8500_GASG_CC_CNTR_AVGOFF_REG 0x0C09
+#define AB8500_GASG_CC_OFFSET_REG 0x0C0A
+/*
+ * Audio
+ * Bank : 0x0D
+ * Not a part of this file. Should be part of Audio codec driver
+ */
+
+/*
+ * Interrupt register offsets
+ * Bank : 0x0E
+ */
+#define AB8500_IT_SOURCE1_REG 0x0E00
+#define AB8500_IT_SOURCE2_REG 0x0E01
+#define AB8500_IT_SOURCE3_REG 0x0E02
+#define AB8500_IT_SOURCE4_REG 0x0E03
+#define AB8500_IT_SOURCE5_REG 0x0E04
+#define AB8500_IT_SOURCE6_REG 0x0E05
+
+/* available only in 1.0 */
+#define AB8500_IT_SOURCE7_REG 0x0E06
+#define AB8500_IT_SOURCE8_REG 0x0E07
+#define AB8500_IT_SOURCE19_REG 0x0E12
+
+#define AB8500_IT_SOURCE20_REG 0x0E13
+#define AB8500_IT_SOURCE21_REG 0x0E14
+#define AB8500_IT_SOURCE22_REG 0x0E15
+#define AB8500_IT_SOURCE23_REG 0x0E16
+#define AB8500_IT_SOURCE24_REG 0x0E17
+
+/*
+ * latch registers
+ */
+#define AB8500_IT_LATCH1_REG 0x0E20
+#define AB8500_IT_LATCH2_REG 0x0E21
+#define AB8500_IT_LATCH3_REG 0x0E22
+#define AB8500_IT_LATCH4_REG 0x0E23
+#define AB8500_IT_LATCH5_REG 0x0E24
+#define AB8500_IT_LATCH6_REG 0x0E25
+
+/* available only in 1.0 */
+#define AB8500_IT_LATCH7_REG 0x0E26
+#define AB8500_IT_LATCH8_REG 0x0E27
+#define AB8500_IT_LATCH9_REG 0x0E28
+#define AB8500_IT_LATCH10_REG 0x0E29
+#define AB8500_IT_LATCH19_REG 0x0E32
+
+#define AB8500_IT_LATCH20_REG 0x0E33
+#define AB8500_IT_LATCH21_REG 0x0E34
+#define AB8500_IT_LATCH22_REG 0x0E35
+#define AB8500_IT_LATCH23_REG 0x0E36
+#define AB8500_IT_LATCH24_REG 0x0E37
+
+/*
+ * mask registers
+ */
+
+#define AB8500_IT_MASK1_REG 0x0E40
+#define AB8500_IT_MASK2_REG 0x0E41
+#define AB8500_IT_MASK3_REG 0x0E42
+#define AB8500_IT_MASK4_REG 0x0E43
+#define AB8500_IT_MASK5_REG 0x0E44
+#define AB8500_IT_MASK6_REG 0x0E45
+
+
+/* available only in 1.0 */
+#define AB8500_IT_MASK7_REG 0x0E46
+#define AB8500_IT_MASK8_REG 0x0E47
+#define AB8500_IT_MASK9_REG 0x0E48
+#define AB8500_IT_MASK10_REG 0x0E49
+#define AB8500_IT_MASK11_REG 0x0E4A
+#define AB8500_IT_MASK12_REG 0x0E4B
+#define AB8500_IT_MASK13_REG 0x0E4C
+#define AB8500_IT_MASK14_REG 0x0E4D
+#define AB8500_IT_MASK15_REG 0x0E4E
+#define AB8500_IT_MASK16_REG 0x0E4F
+#define AB8500_IT_MASK17_REG 0x0E50
+#define AB8500_IT_MASK18_REG 0x0E51
+#define AB8500_IT_MASK19_REG 0x0E52
+
+#define AB8500_IT_MASK20_REG 0x0E53
+#define AB8500_IT_MASK21_REG 0x0E54
+#define AB8500_IT_MASK22_REG 0x0E55
+#define AB8500_IT_MASK23_REG 0x0E56
+#define AB8500_IT_MASK24_REG 0x0E57
+
+/*
+ * RTC bank register offsets
+ * Bank : 0xF
+ */
+#define AB8500_RTC_SWITCHOFF_STAT_REG 0x0F00
+#define AB8500_RTC_CC_CONF_REG 0x0F01
+#define AB8500_RTC_READ_REQ_REG 0x0F02
+#define AB8500_RTC_WATCH_TSECMID_REG 0x0F03
+#define AB8500_RTC_WATCH_TSECHI_REG 0x0F04
+#define AB8500_RTC_WATCH_TMIN_LOW_REG 0x0F05
+#define AB8500_RTC_WATCH_TMIN_MID_REG 0x0F06
+#define AB8500_RTC_WATCH_TMIN_HI_REG 0x0F07
+#define AB8500_RTC_ALRM_MIN_LOW_REG 0x0F08
+#define AB8500_RTC_ALRM_MIN_MID_REG 0x0F09
+#define AB8500_RTC_ALRM_MIN_HI_REG 0x0F0A
+#define AB8500_RTC_STAT_REG 0x0F0B
+#define AB8500_RTC_BKUP_CHG_REG 0x0F0C
+#define AB8500_RTC_FORCE_BKUP_REG 0x0F0D
+#define AB8500_RTC_CALIB_REG 0x0F0E
+#define AB8500_RTC_SWITCH_STAT_REG 0x0F0F
+
+/*
+ * Misc block GPIO register offsets - Not for ED
+ * Bank : 0x10
+ */
+/* available only in 1.0 */
+#define AB8500_GPIO_SEL1_REG 0x01000
+#define AB8500_GPIO_SEL2_REG 0x01001
+#define AB8500_GPIO_SEL3_REG 0x01002
+#define AB8500_GPIO_SEL4_REG 0x01003
+#define AB8500_GPIO_SEL5_REG 0x01004
+#define AB8500_GPIO_SEL6_REG 0x01005
+#define AB8500_GPIO_DIR1_REG 0x01010
+#define AB8500_GPIO_DIR2_REG 0x01011
+#define AB8500_GPIO_DIR3_REG 0x01012
+#define AB8500_GPIO_DIR4_REG 0x01013
+#define AB8500_GPIO_DIR5_REG 0x01014
+#define AB8500_GPIO_DIR6_REG 0x01015
+
+#define AB8500_GPIO_OUT1_REG 0x01020
+#define AB8500_GPIO_OUT2_REG 0x01021
+#define AB8500_GPIO_OUT3_REG 0x01022
+#define AB8500_GPIO_OUT4_REG 0x01023
+#define AB8500_GPIO_OUT5_REG 0x01024
+#define AB8500_GPIO_OUT6_REG 0x01025
+
+#define AB8500_GPIO_PUD1_REG 0x01030
+#define AB8500_GPIO_PUD2_REG 0x01031
+#define AB8500_GPIO_PUD3_REG 0x01032
+#define AB8500_GPIO_PUD4_REG 0x01033
+#define AB8500_GPIO_PUD5_REG 0x01034
+#define AB8500_GPIO_PUD6_REG 0x01035
+
+#define AB8500_GPIO_IN1_REG 0x01040
+#define AB8500_GPIO_IN2_REG 0x01041
+#define AB8500_GPIO_IN3_REG 0x01042
+#define AB8500_GPIO_IN4_REG 0x01043
+#define AB8500_GPIO_IN5_REG 0x01044
+#define AB8500_GPIO_IN6_REG 0x01045
+#define AB8500_GPIO_ALT_FUNC 0x01050
+
+/*
+ * PWM Out generators
+ * Bank: 0x10
+ */
+#define AB8500_PWM_OUT_CTRL1_REG 0x1060
+#define AB8500_PWM_OUT_CTRL2_REG 0x1061
+#define AB8500_PWM_OUT_CTRL3_REG 0x1062
+#define AB8500_PWM_OUT_CTRL4_REG 0x1063
+#define AB8500_PWM_OUT_CTRL5_REG 0x1064
+#define AB8500_PWM_OUT_CTRL6_REG 0x1065
+#define AB8500_PWM_OUT_CTRL7_REG 0x1066
+
+#define AB8500_I2C_PAD_CTRL_REG 0x1067
+#define AB8500_REV_REG 0x1080
+
+/*
+ * Misc, Debug Test Configuration register
+ * Bank : 0x11
+ */
+#define AB8500_DEBUG_TESTMODE_REG 0x01100
+
+/* only in 1.0 */
+#define AB8500_I2C_TRIG1_ADR_REG 0x1101
+#define AB8500_I2C_TRIG1_ID_REG 0x1102
+#define AB8500_I2C_TRIG2_ADR_REG 0x1103
+#define AB8500_I2C_TRIG3_ID_REG 0x1104
+#define AB8500_I2C_NOACCESS_SUP_REG 0x1105
+
+/* Offsets in TurnOnstatus register
+ */
+
+#define AB8500_MAX_INT 192
+#define AB8500_MAX_FUTURE_USE 105
+
+#define AB8500_MAX_INT_SOURCE 11
+#define AB8500_MAX_INT_LATCH 13
+#define AB8500_MAX_INT_MASK 21
+
+/**
+ * struct ab8500_device - Stw4500 device structure
+ * @cs_en: pointer chip select enable
+ * @cs_dis: pointer to chip select disable
+ *
+ * Stw4500 Internal device structure
+ */
+struct ab8500_device {
+ void (*cs_en) (void);
+ void (*cs_dis) (void);
+ u16 ssp_controller;
+};
+
+/*struct t_ab8500_context;*/
+
+/**
+ * struct client_callbacks - Client callbacks
+ * @callback: callback handler
+ * @data: private data for the handler
+ *
+ * Stw4500 maintains a internal data structure for the registered
+ * callback
+ */
+struct client_callbacks {
+ void (*callback)(void *data);
+ void *data;
+};
+
+/**
+ * struct client_signals - Client signals
+ * @pid: pid of process
+ * @signal: signal to be delivered
+ *
+ * AB8500 maintains an internal data structure for the delivery of
+ * required signals to registered processes
+ */
+struct client_signals {
+ struct pid *pid;
+ u32 signal;
+};
+
+/**
+ * struct ab8500 - AB8500 Internal data structure
+ * @ab8500_master: Pointer to the spi_master
+ * @ab8500_board_info: Pointer to the board information structure
+ * @ab8500_spi: Pointer to the spi_device strcture
+ * @spi_transfer: Pointer SPI data transfer structure spi_transfer
+ * @spi_message: SPI message pointer of type spi_message
+ * @ab8500_device: AB8500 internal data structure
+ * @ssp_wrbuf: SSP write data buffer of size 4 bytes
+ * @ssp_rdbuf: SSP read data buffer of size 4 bytes
+ * @work: work queue scheduled in the interrupt handler
+ * @c_callback: Array of client's callback handler
+ * @ab8500_cfg_lock: synchronization primitive to protect the data
+ * @ab8500_sem: synchronization primitive used in the non-interrupt context
+ * @irq: interrupt number of ab8500
+ * @revision: revision number of ab8500 silicon
+ *
+ * Supports only SPI interface. The device can also be accessed
+ * through I2C in the successive version of U8500.
+ */
+struct ab8500 {
+ struct spi_master *ab8500_master;
+ struct spi_board_info *ab8500_board_info;
+ struct spi_device *ab8500_spi;
+ struct spi_transfer *ab8500_xfer;
+ struct spi_message *ab8500_msg;
+ struct ab8500_device *board;
+ u32 ssp_wrbuf[4];
+ u32 ssp_rdbuf[4];
+ struct client_callbacks c_callback[184];
+ struct client_signals c_signals[184];
+ struct work_struct work;
+ spinlock_t ab8500_cfg_lock;
+ spinlock_t ab8500_cfgsig_lock;
+ struct semaphore ab8500_sem;
+ unsigned char irq;
+ unsigned char revision;
+};
+
+int ab8500_get_version(void);
+int ab8500_write(u8 block, u32 adr, u8 data);
+int ab8500_read(u8 block, u32 adr);
+int ab8500_set_callback_handler(int int_no, void *callback_handler, void *data);
+int ab8500_remove_callback_handler(int int_no);
+void ab8500_int_mask(int int_no);
+void ab8500_int_unmask(int int_no);
+int ab8500_set_signal_handler(int int_no, int sig_no);
+int ab8500_remove_signal_handler(int int_no);
+#endif /* AB8500_H_ */
diff --git a/arch/arm/mach-ux500/include/mach/ab8500_codec.h b/arch/arm/mach-ux500/include/mach/ab8500_codec.h
new file mode 100755
index 00000000000..b10f28b1a1d
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/ab8500_codec.h
@@ -0,0 +1,435 @@
+/*****************************************************************************/
+/**
+* © ST-Ericsson, 2009 - All rights reserved
+* Reproduction and Communication of this document is strictly prohibited
+* unless specifically authorized in writing by ST-Ericsson
+*
+* \brief Public header file for AB8500 Codec
+* \author ST-Ericsson
+*/
+/*****************************************************************************/
+
+#ifndef _AB8500_CODEC_H_
+#define _AB8500_CODEC_H_
+
+/*---------------------------------------------------------------------
+ * Includes
+ *--------------------------------------------------------------------*/
+#include "hcl_defs.h"
+#include "debug.h"
+
+/*---------------------------------------------------------------------
+ * Define
+ *--------------------------------------------------------------------*/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+typedef enum
+{
+ AB8500_CODEC_OK,
+ AB8500_CODEC_ERROR,
+ AB8500_CODEC_UNSUPPORTED_FEATURE,
+ AB8500_CODEC_INVALID_PARAMETER,
+ AB8500_CODEC_CONFIG_NOT_COHERENT,
+ AB8500_CODEC_TRANSACTION_FAILED
+} t_ab8500_codec_error;
+
+
+typedef enum
+{
+ AB8500_CODEC_DIRECTION_IN,
+ AB8500_CODEC_DIRECTION_OUT,
+ AB8500_CODEC_DIRECTION_INOUT
+} t_ab8500_codec_direction;
+
+typedef enum
+{
+ AB8500_CODEC_MASTER_MODE_DISABLE,
+ AB8500_CODEC_MASTER_MODE_ENABLE
+}t_ab8500_codec_master_mode;
+
+typedef enum
+{
+ AB8500_CODEC_AUDIO_INTERFACE_0,
+ AB8500_CODEC_AUDIO_INTERFACE_1
+}t_ab8500_codec_audio_interface;
+
+
+typedef enum
+{
+ AB8500_CODEC_MODE_HIFI,
+ AB8500_CODEC_MODE_VOICE,
+ AB8500_CODEC_MODE_MANUAL_SETTING
+} t_ab8500_codec_mode;
+
+typedef enum
+{
+ AB8500_CODEC_DEST_HEADSET,
+ AB8500_CODEC_DEST_EARPIECE,
+ AB8500_CODEC_DEST_HANDSFREE,
+ AB8500_CODEC_DEST_VIBRATOR_L,
+ AB8500_CODEC_DEST_VIBRATOR_R,
+ AB8500_CODEC_DEST_ALL
+} t_ab8500_codec_dest;
+
+typedef enum
+{
+ AB8500_CODEC_SRC_LINEIN,
+ AB8500_CODEC_SRC_MICROPHONE_1A,
+ AB8500_CODEC_SRC_MICROPHONE_1B,
+ AB8500_CODEC_SRC_MICROPHONE_2,
+ AB8500_CODEC_SRC_D_MICROPHONE_1,
+ AB8500_CODEC_SRC_D_MICROPHONE_2,
+ AB8500_CODEC_SRC_D_MICROPHONE_3,
+ AB8500_CODEC_SRC_D_MICROPHONE_4,
+ AB8500_CODEC_SRC_D_MICROPHONE_5,
+ AB8500_CODEC_SRC_D_MICROPHONE_6,
+ AB8500_CODEC_SRC_ALL
+} t_ab8500_codec_src;
+
+typedef enum
+{
+ AB8500_CODEC_SLOT0,
+ AB8500_CODEC_SLOT1,
+ AB8500_CODEC_SLOT2,
+ AB8500_CODEC_SLOT3,
+ AB8500_CODEC_SLOT4,
+ AB8500_CODEC_SLOT5,
+ AB8500_CODEC_SLOT6,
+ AB8500_CODEC_SLOT7,
+ AB8500_CODEC_SLOT8,
+ AB8500_CODEC_SLOT9,
+ AB8500_CODEC_SLOT10,
+ AB8500_CODEC_SLOT11,
+ AB8500_CODEC_SLOT12,
+ AB8500_CODEC_SLOT13,
+ AB8500_CODEC_SLOT14,
+ AB8500_CODEC_SLOT15,
+ AB8500_CODEC_SLOT16,
+ AB8500_CODEC_SLOT17,
+ AB8500_CODEC_SLOT18,
+ AB8500_CODEC_SLOT19,
+ AB8500_CODEC_SLOT20,
+ AB8500_CODEC_SLOT21,
+ AB8500_CODEC_SLOT22,
+ AB8500_CODEC_SLOT23,
+ AB8500_CODEC_SLOT24,
+ AB8500_CODEC_SLOT25,
+ AB8500_CODEC_SLOT26,
+ AB8500_CODEC_SLOT27,
+ AB8500_CODEC_SLOT28,
+ AB8500_CODEC_SLOT29,
+ AB8500_CODEC_SLOT30,
+ AB8500_CODEC_SLOT31,
+ AB8500_CODEC_SLOT_UNDEFINED
+} t_ab8500_codec_slot;
+
+
+
+typedef enum
+{
+ AB8500_CODEC_DA_CHANNEL_NUMBER_1,
+ AB8500_CODEC_DA_CHANNEL_NUMBER_2,
+ AB8500_CODEC_DA_CHANNEL_NUMBER_3,
+ AB8500_CODEC_DA_CHANNEL_NUMBER_4,
+ AB8500_CODEC_DA_CHANNEL_NUMBER_5,
+ AB8500_CODEC_DA_CHANNEL_NUMBER_6,
+ AB8500_CODEC_DA_CHANNEL_NUMBER_UNDEFINED
+}t_ab8500_codec_da_channel_number;
+
+
+typedef enum
+{
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT1,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT2,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT3,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT4,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT5,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT6,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT7,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT8,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_ZEROS,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_IS_TRISTATE = 15,
+ AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_UNDEFINED
+} t_ab8500_codec_cr31_to_cr46_ad_data_allocation;
+
+
+typedef enum
+{
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT00,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT01,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT02,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT03,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT04,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT05,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT06,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT07,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT08,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT09,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT10,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT11,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT12,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT13,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT14,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT15,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT16,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT17,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT18,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT19,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT20,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT21,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT22,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT23,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT24,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT25,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT26,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT27,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT28,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT29,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT30,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT31,
+ AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT_UNDEFINED
+} t_ab8500_codec_cr51_to_cr56_sltoda;
+
+typedef enum
+{
+ AB8500_CODEC_SRC_STATE_DISABLE,
+ AB8500_CODEC_SRC_STATE_ENABLE
+}t_ab8500_codec_src_state;
+
+typedef enum
+{
+ AB8500_CODEC_DEST_STATE_DISABLE,
+ AB8500_CODEC_DEST_STATE_ENABLE
+}t_ab8500_codec_dest_state;
+
+/* CR104 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr104_bfifoint;
+
+
+/* CR105 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr105_bfifotx;
+
+/* CR106 - 6:4 */
+typedef enum
+{
+ AB8500_CODEC_CR106_BFIFOFSEXT_NO_EXTRA_CLK,
+ AB8500_CODEC_CR106_BFIFOFSEXT_1SLOT_EXTRA_CLK,
+ AB8500_CODEC_CR106_BFIFOFSEXT_2SLOT_EXTRA_CLK,
+ AB8500_CODEC_CR106_BFIFOFSEXT_3SLOT_EXTRA_CLK,
+ AB8500_CODEC_CR106_BFIFOFSEXT_4SLOT_EXTRA_CLK,
+ AB8500_CODEC_CR106_BFIFOFSEXT_5SLOT_EXTRA_CLK,
+ AB8500_CODEC_CR106_BFIFOFSEXT_6SLOT_EXTRA_CLK
+} t_ab8500_codec_cr106_bfifofsext;
+
+/* CR106 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR106_BFIFOMSK_AD_DATA0_UNMASKED,
+ AB8500_CODEC_CR106_BFIFOMSK_AD_DATA0_MASKED
+} t_ab8500_codec_cr106_bfifomsk;
+
+/* CR106 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR106_BFIFOMSTR_SLAVE_MODE,
+ AB8500_CODEC_CR106_BFIFOMSTR_MASTER_MODE
+} t_ab8500_codec_cr106_bfifomstr;
+
+/* CR106 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR106_BFIFOSTRT_STOPPED,
+ AB8500_CODEC_CR106_BFIFOSTRT_RUNNING
+} t_ab8500_codec_cr106_bfifostrt;
+
+
+/* CR107 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr107_bfifosampnr;
+
+
+/* CR108 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr108_bfifowakeup;
+
+
+typedef struct
+{
+ t_ab8500_codec_cr104_bfifoint cr104_bfifoint;
+ t_ab8500_codec_cr105_bfifotx cr105_bfifotx;
+ t_ab8500_codec_cr106_bfifofsext cr106_bfifofsext;
+ t_ab8500_codec_cr106_bfifomsk cr106_bfifomsk;
+ t_ab8500_codec_cr106_bfifomstr cr106_bfifomstr;
+ t_ab8500_codec_cr106_bfifostrt cr106_bfifostrt;
+ t_ab8500_codec_cr107_bfifosampnr cr107_bfifosampnr;
+ t_ab8500_codec_cr108_bfifowakeup cr108_bfifowakeup;
+} t_ab8500_codec_burst_fifo_config;
+
+/************************************************************/
+/*---------------------------------------------------------------------
+ * Exported APIs
+ *--------------------------------------------------------------------*/
+/* Initialization */
+t_ab8500_codec_error AB8500_CODEC_Init(IN t_uint8 slave_address_of_codec);
+t_ab8500_codec_error AB8500_CODEC_Reset(void);
+
+/* Audio Codec basic configuration */
+t_ab8500_codec_error AB8500_CODEC_SetModeAndDirection(IN t_ab8500_codec_direction ab8500_codec_direction, IN t_ab8500_codec_mode ab8500_codec_mode_in, IN t_ab8500_codec_mode ab8500_codec_mode_out);
+t_ab8500_codec_error AB8500_CODEC_SelectInput(IN t_ab8500_codec_src ab8500_codec_src);
+t_ab8500_codec_error AB8500_CODEC_SelectOutput(IN t_ab8500_codec_dest ab8500_codec_dest);
+
+/* Burst FIFO configuration */
+t_ab8500_codec_error AB8500_CODEC_ConfigureBurstFifo(IN t_ab8500_codec_burst_fifo_config const *const p_burst_fifo_config);
+t_ab8500_codec_error AB8500_CODEC_EnableBurstFifo(void);
+t_ab8500_codec_error AB8500_CODEC_DisableBurstFifo(void);
+
+/* Audio Codec Master mode configuration */
+t_ab8500_codec_error AB8500_CODEC_SetMasterMode(IN t_ab8500_codec_master_mode mode);
+
+/* APIs to be implemented by user */
+t_ab8500_codec_error AB8500_CODEC_Write(IN t_uint8 register_offset, IN t_uint8 count, IN t_uint8 *p_data);
+t_ab8500_codec_error AB8500_CODEC_Read(IN t_uint8 register_offset, IN t_uint8 count, IN t_uint8 *p_dummy_data, IN t_uint8 *p_data);
+
+/* Volume Management */
+t_ab8500_codec_error AB8500_CODEC_SetSrcVolume(IN t_ab8500_codec_src src_device, IN t_uint8 in_left_volume, IN t_uint8 in_right_volume);
+t_ab8500_codec_error AB8500_CODEC_SetDestVolume(IN t_ab8500_codec_dest dest_device, IN t_uint8 out_left_volume, IN t_uint8 out_right_volume);
+
+/* Power management */
+t_ab8500_codec_error AB8500_CODEC_PowerDown(void);
+t_ab8500_codec_error AB8500_CODEC_PowerUp(void);
+
+/* Interface Management */
+t_ab8500_codec_error AB8500_CODEC_SelectInterface(IN t_ab8500_codec_audio_interface audio_interface);
+t_ab8500_codec_error AB8500_CODEC_GetInterface(OUT t_ab8500_codec_audio_interface *p_audio_interface);
+
+/* Slot Allocation */
+t_ab8500_codec_error AB8500_CODEC_ADSlotAllocation(IN t_ab8500_codec_slot ad_slot, IN t_ab8500_codec_cr31_to_cr46_ad_data_allocation value);
+t_ab8500_codec_error AB8500_CODEC_DASlotAllocation(IN t_ab8500_codec_da_channel_number channel_number, IN t_ab8500_codec_cr51_to_cr56_sltoda slot);
+
+/* Loopback Management */
+t_ab8500_codec_error AB8500_CODEC_SetAnalogLoopback(IN t_uint8 out_left_volume, IN t_uint8 out_right_volume);
+t_ab8500_codec_error AB8500_CODEC_RemoveAnalogLoopback(void);
+
+/* Bypass Management */
+t_ab8500_codec_error AB8500_CODEC_EnableBypassMode(void);
+t_ab8500_codec_error AB8500_CODEC_DisableBypassMode(void);
+
+/* Power Control Management */
+t_ab8500_codec_error AB8500_CODEC_SrcPowerControl(IN t_ab8500_codec_src src_device, t_ab8500_codec_src_state state);
+t_ab8500_codec_error AB8500_CODEC_DestPowerControl(IN t_ab8500_codec_dest dest_device, t_ab8500_codec_dest_state state);
+
+/* Version Management */
+t_ab8500_codec_error AB8500_CODEC_GetVersion(OUT t_version *p_version);
+
+#if 0
+/* Debug management */
+t_ab8500_codec_error AB8500_CODEC_SetDbgLevel(IN t_dbg_level dbg_level);
+t_ab8500_codec_error AB8500_CODEC_GetDbgLevel(OUT t_dbg_level *p_dbg_level);
+#endif
+
+/*
+** following is added by $kardad$
+*/
+
+/* duplicate copy of enum from msp.h */
+/* for MSPConfiguration.in_clock_freq parameter to select msp clock freq */
+typedef enum {
+ CODEC_MSP_INPUT_FREQ_1MHZ = 1024,
+ CODEC_MSP_INPUT_FREQ_2MHZ = 2048,
+ CODEC_MSP_INPUT_FREQ_3MHZ = 3072,
+ CODEC_MSP_INPUT_FREQ_4MHZ = 4096,
+ CODEC_MSP_INPUT_FREQ_5MHZ = 5760,
+ CODEC_MSP_INPUT_FREQ_6MHZ = 6144,
+ CODEC_MSP_INPUT_FREQ_8MHZ = 8192,
+ CODEC_MSP_INPUT_FREQ_11MHZ = 11264,
+ CODEC_MSP_INPUT_FREQ_12MHZ = 12288,
+ CODEC_MSP_INPUT_FREQ_16MHZ = 16384,
+ CODEC_MSP_INPUT_FREQ_22MHZ = 22579,
+ CODEC_MSP_INPUT_FREQ_24MHZ = 24576,
+ CODEC_MSP_INPUT_FREQ_48MHZ = 49152
+} codec_msp_in_clock_freq_type;
+
+/* msp clock source internal/external for srg_clock_sel */
+typedef enum {
+ CODEC_MSP_APB_CLOCK = 0,
+ CODEC_MSP_SCK_CLOCK = 2,
+ CODEC_MSP_SCK_SYNC_CLOCK = 3
+} codec_msp_srg_clock_sel_type;
+
+/* Sample rate supported by Codec */
+
+typedef enum {
+ CODEC_FREQUENCY_DONT_CHANGE = -100,
+ CODEC_SAMPLING_FREQ_RESET = -1,
+ CODEC_SAMPLING_FREQ_MINLIMIT = 7,
+ CODEC_SAMPLING_FREQ_8KHZ = 8, /*default */
+ CODEC_SAMPLING_FREQ_11KHZ = 11,
+ CODEC_SAMPLING_FREQ_12KHZ = 12,
+ CODEC_SAMPLING_FREQ_16KHZ = 16,
+ CODEC_SAMPLING_FREQ_22KHZ = 22,
+ CODEC_SAMPLING_FREQ_24KHZ = 24,
+ CODEC_SAMPLING_FREQ_32KHZ = 32,
+ CODEC_SAMPLING_FREQ_44KHZ = 44,
+ CODEC_SAMPLING_FREQ_48KHZ = 48,
+ CODEC_SAMPLING_FREQ_64KHZ = 64, /*the frequencies below this line are not supported in stw5094A */
+ CODEC_SAMPLING_FREQ_88KHZ = 88,
+ CODEC_SAMPLING_FREQ_96KHZ = 96,
+ CODEC_SAMPLING_FREQ_128KHZ = 128,
+ CODEC_SAMPLING_FREQ_176KHZ = 176,
+ CODEC_SAMPLING_FREQ_192KHZ = 192,
+ CODEC_SAMPLING_FREQ_MAXLIMIT = 193
+} t_codec_sample_frequency;
+
+#define RESET -1
+#define DEFAULT -100
+/***********************************************************/
+/*
+** following stuff is added to compile code without debug print support $kardad$
+*/
+
+#define DBGEXIT(cr)
+#define DBGEXIT0(cr)
+#define DBGEXIT1(cr,ch,p1)
+#define DBGEXIT2(cr,ch,p1,p2)
+#define DBGEXIT3(cr,ch,p1,p2,p3)
+#define DBGEXIT4(cr,ch,p1,p2,p3,p4)
+#define DBGEXIT5(cr,ch,p1,p2,p3,p4,p5)
+#define DBGEXIT6(cr,ch,p1,p2,p3,p4,p5,p6)
+
+#define DBGENTER()
+#define DBGENTER0()
+#define DBGENTER1(ch,p1)
+#define DBGENTER2(ch,p1,p2)
+#define DBGENTER3(ch,p1,p2,p3)
+#define DBGENTER4(ch,p1,p2,p3,p4)
+#define DBGENTER5(ch,p1,p2,p3,p4,p5)
+#define DBGENTER6(ch,p1,p2,p3,p4,p5,p6)
+
+#define DBGPRINT(dbg_level,dbg_string)
+#define DBGPRINTHEX(dbg_level,dbg_string,uint32)
+#define DBGPRINTDEC(dbg_level,dbg_string,uint32)
+/***********************************************************/
+
+/*---------------------------------------------------------------------
+ * PRIVATE APIs
+ *--------------------------------------------------------------------*/
+PRIVATE t_ab8500_codec_error ab8500_codec_ADSlotAllocationSwitch1(IN t_ab8500_codec_slot ad_slot, IN t_ab8500_codec_cr31_to_cr46_ad_data_allocation value);
+PRIVATE t_ab8500_codec_error ab8500_codec_ADSlotAllocationSwitch2(IN t_ab8500_codec_slot ad_slot, IN t_ab8500_codec_cr31_to_cr46_ad_data_allocation value);
+PRIVATE t_ab8500_codec_error ab8500_codec_ADSlotAllocationSwitch3(IN t_ab8500_codec_slot ad_slot, IN t_ab8500_codec_cr31_to_cr46_ad_data_allocation value);
+PRIVATE t_ab8500_codec_error ab8500_codec_ADSlotAllocationSwitch4(IN t_ab8500_codec_slot ad_slot, IN t_ab8500_codec_cr31_to_cr46_ad_data_allocation value);
+PRIVATE t_ab8500_codec_error ab8500_codec_SrcPowerControlSwitch1(IN t_ab8500_codec_src src_device, t_ab8500_codec_src_state state);
+PRIVATE t_ab8500_codec_error ab8500_codec_SrcPowerControlSwitch2(IN t_ab8500_codec_src src_device, t_ab8500_codec_src_state state);
+PRIVATE t_ab8500_codec_error ab8500_codec_SetModeAndDirectionUpdateCR(void);
+PRIVATE t_ab8500_codec_error ab8500_codec_SetSrcVolumeUpdateCR(void);
+PRIVATE t_ab8500_codec_error ab8500_codec_SetDestVolumeUpdateCR(void);
+PRIVATE t_ab8500_codec_error ab8500_codec_ProgramDirectionIN(void);
+PRIVATE t_ab8500_codec_error ab8500_codec_ProgramDirectionOUT(void);
+PRIVATE t_ab8500_codec_error ab8500_codec_DestPowerControlUpdateCR(void);
+
+#ifdef __cplusplus
+} /* allow C++ to use these headers*/
+#endif /* __cplusplus*/
+#endif /* _AB8500_CODEC_H_*/
+
+/* End of file ab8500_codec.h*/
+
diff --git a/arch/arm/mach-ux500/include/mach/ab8500_codec_p.h b/arch/arm/mach-ux500/include/mach/ab8500_codec_p.h
new file mode 100755
index 00000000000..415d5f73dc0
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/ab8500_codec_p.h
@@ -0,0 +1,3371 @@
+/*****************************************************************************/
+/**
+* © ST-Ericsson, 2009 - All rights reserved
+* Reproduction and Communication of this document is strictly prohibited
+* unless specifically authorized in writing by ST-Ericsson
+ *
+* \brief Private Header file for AB8500 CODEC
+* \author ST-Ericsson
+ */
+/*****************************************************************************/
+
+#ifndef _AB8500_CODECP_H_
+#define _AB8500_CODECP_H_
+
+/*----------------------------------------------------------------------------
+ * Includes
+ *---------------------------------------------------------------------------*/
+#include "hcl_defs.h"
+
+#define AB8500_CODEC_HCL_VERSION_ID 2
+#define AB8500_CODEC_HCL_MAJOR_ID 0
+#define AB8500_CODEC_HCL_MINOR_ID 0
+
+#define AB8500_CODEC_MASK_ONE_BIT 0x1UL
+#define AB8500_CODEC_MASK_TWO_BITS 0x3UL
+#define AB8500_CODEC_MASK_THREE_BITS 0x7UL
+#define AB8500_CODEC_MASK_FOUR_BITS 0xFUL
+#define AB8500_CODEC_MASK_FIVE_BITS 0x1FUL
+#define AB8500_CODEC_MASK_SIX_BITS 0x3FUL
+#define AB8500_CODEC_MASK_SEVEN_BITS 0x7FUL
+#define AB8500_CODEC_MASK_EIGHT_BITS 0xFFUL
+
+#define AB8500_CODEC_WRITE_BITS(reg, val, bit_nb, pos) (reg) = ((t_uint8) ((((reg) & (~(bit_nb << pos))) | (((val) & bit_nb) << pos))))
+
+
+#define AB8500_CODEC_BLOCK 0x0D
+
+#define AB8500_CODEC_MASK_TWO_MS_BITS 0xC0UL
+#define AB8500_CODEC_MASK_SIX_LS_BITS 0x3FUL
+
+/* Genepi AudioCodec Control Registers */
+
+#define AB8500_CODEC_CR0 0x00
+#define AB8500_CODEC_CR1 0x01
+#define AB8500_CODEC_CR2 0x02
+#define AB8500_CODEC_CR3 0x03
+#define AB8500_CODEC_CR4 0x04
+#define AB8500_CODEC_CR5 0x05
+#define AB8500_CODEC_CR6 0x06
+#define AB8500_CODEC_CR7 0x07
+#define AB8500_CODEC_CR8 0x08
+#define AB8500_CODEC_CR9 0x09
+#define AB8500_CODEC_CR10 0x0A
+#define AB8500_CODEC_CR11 0x0B
+#define AB8500_CODEC_CR12 0x0C
+#define AB8500_CODEC_CR13 0x0D
+#define AB8500_CODEC_CR14 0x0E
+#define AB8500_CODEC_CR15 0x0F
+#define AB8500_CODEC_CR16 0x10
+#define AB8500_CODEC_CR17 0x11
+#define AB8500_CODEC_CR18 0x12
+#define AB8500_CODEC_CR19 0x13
+#define AB8500_CODEC_CR20 0x14
+#define AB8500_CODEC_CR21 0x15
+#define AB8500_CODEC_CR22 0x16
+#define AB8500_CODEC_CR23 0x17
+#define AB8500_CODEC_CR24 0x18
+#define AB8500_CODEC_CR25 0x19
+#define AB8500_CODEC_CR26 0x1A
+#define AB8500_CODEC_CR27 0x1B
+#define AB8500_CODEC_CR28 0x1C
+#define AB8500_CODEC_CR29 0x1D
+#define AB8500_CODEC_CR30 0x1E
+#define AB8500_CODEC_CR31 0x1F
+#define AB8500_CODEC_CR32 0x20
+#define AB8500_CODEC_CR33 0x21
+#define AB8500_CODEC_CR34 0x22
+#define AB8500_CODEC_CR35 0x23
+#define AB8500_CODEC_CR36 0x24
+#define AB8500_CODEC_CR37 0x25
+#define AB8500_CODEC_CR38 0x26
+#define AB8500_CODEC_CR39 0x27
+#define AB8500_CODEC_CR40 0x28
+#define AB8500_CODEC_CR41 0x29
+#define AB8500_CODEC_CR42 0x2A
+#define AB8500_CODEC_CR43 0x2B
+#define AB8500_CODEC_CR44 0x2C
+#define AB8500_CODEC_CR45 0x2D
+#define AB8500_CODEC_CR46 0x2E
+#define AB8500_CODEC_CR47 0x2F
+#define AB8500_CODEC_CR48 0x30
+#define AB8500_CODEC_CR49 0x31
+#define AB8500_CODEC_CR50 0x32
+#define AB8500_CODEC_CR51 0x33
+#define AB8500_CODEC_CR52 0x34
+#define AB8500_CODEC_CR53 0x35
+#define AB8500_CODEC_CR54 0x36
+#define AB8500_CODEC_CR55 0x37
+#define AB8500_CODEC_CR56 0x38
+#define AB8500_CODEC_CR57 0x39
+#define AB8500_CODEC_CR58 0x3A
+#define AB8500_CODEC_CR59 0x3B
+#define AB8500_CODEC_CR60 0x3C
+#define AB8500_CODEC_CR61 0x3D
+#define AB8500_CODEC_CR62 0x3E
+#define AB8500_CODEC_CR63 0x3F
+#define AB8500_CODEC_CR64 0x40
+#define AB8500_CODEC_CR65 0x41
+#define AB8500_CODEC_CR66 0x42
+#define AB8500_CODEC_CR67 0x43
+#define AB8500_CODEC_CR68 0x44
+#define AB8500_CODEC_CR69 0x45
+#define AB8500_CODEC_CR70 0x46
+#define AB8500_CODEC_CR71 0x47
+#define AB8500_CODEC_CR72 0x48
+#define AB8500_CODEC_CR73 0x49
+#define AB8500_CODEC_CR74 0x4A
+#define AB8500_CODEC_CR75 0x4B
+#define AB8500_CODEC_CR76 0x4C
+#define AB8500_CODEC_CR77 0x4D
+#define AB8500_CODEC_CR78 0x4E
+#define AB8500_CODEC_CR79 0x4F
+#define AB8500_CODEC_CR80 0x50
+#define AB8500_CODEC_CR81 0x51
+#define AB8500_CODEC_CR82 0x52
+#define AB8500_CODEC_CR83 0x53
+#define AB8500_CODEC_CR84 0x54
+#define AB8500_CODEC_CR85 0x55
+#define AB8500_CODEC_CR86 0x56
+#define AB8500_CODEC_CR87 0x57
+#define AB8500_CODEC_CR88 0x58
+#define AB8500_CODEC_CR89 0x59
+#define AB8500_CODEC_CR90 0x5A
+#define AB8500_CODEC_CR91 0x5B
+#define AB8500_CODEC_CR92 0x5C
+#define AB8500_CODEC_CR93 0x5D
+#define AB8500_CODEC_CR94 0x5E
+#define AB8500_CODEC_CR95 0x5F
+#define AB8500_CODEC_CR96 0x60
+#define AB8500_CODEC_CR97 0x61
+#define AB8500_CODEC_CR98 0x62
+#define AB8500_CODEC_CR99 0x63
+#define AB8500_CODEC_CR100 0x64
+#define AB8500_CODEC_CR101 0x65
+#define AB8500_CODEC_CR102 0x66
+#define AB8500_CODEC_CR103 0x67
+#define AB8500_CODEC_CR104 0x68
+#define AB8500_CODEC_CR105 0x69
+#define AB8500_CODEC_CR106 0x6A
+#define AB8500_CODEC_CR107 0x6B
+#define AB8500_CODEC_CR108 0x6C
+#define AB8500_CODEC_CR109 0x6D
+
+
+/* CR0-CR0x0000 */
+#define AB8500_CODEC_CR0_POWERUP 7
+#define AB8500_CODEC_CR0_ENAANA 3
+
+/* CR1-CR0x0001 */
+#define AB8500_CODEC_CR1_SWRESET 7
+
+/* CR2-CR0x0002 */
+#define AB8500_CODEC_CR2_ENAD1 7
+#define AB8500_CODEC_CR2_ENAD2 6
+#define AB8500_CODEC_CR2_ENAD3 5
+#define AB8500_CODEC_CR2_ENAD4 4
+#define AB8500_CODEC_CR2_ENAD5 3
+#define AB8500_CODEC_CR2_ENAD6 2
+
+/* CR3-CR0x0003 */
+#define AB8500_CODEC_CR3_ENDA1 7
+#define AB8500_CODEC_CR3_ENDA2 6
+#define AB8500_CODEC_CR3_ENDA3 5
+#define AB8500_CODEC_CR3_ENDA4 4
+#define AB8500_CODEC_CR3_ENDA5 3
+#define AB8500_CODEC_CR3_ENDA6 2
+
+/* CR4-CR0x0004 */
+#define AB8500_CODEC_CR4_LOWPOWHS 7
+#define AB8500_CODEC_CR4_LOWPOWDACHS 5
+#define AB8500_CODEC_CR4_LOWPOWEAR 4
+#define AB8500_CODEC_CR4_EAR_SEL_CM 2
+#define AB8500_CODEC_CR4_HS_HP_DIS 1
+#define AB8500_CODEC_CR4_EAR_HP_DIS 0
+
+/* CR5-CR0x0005 */
+#define AB8500_CODEC_CR5_ENMIC1 7
+#define AB8500_CODEC_CR5_ENMIC2 6
+#define AB8500_CODEC_CR5_ENLINL 5
+#define AB8500_CODEC_CR5_ENLINR 4
+#define AB8500_CODEC_CR5_MUTMIC1 3
+#define AB8500_CODEC_CR5_MUTMIC2 2
+#define AB8500_CODEC_CR5_MUTELINL 1
+#define AB8500_CODEC_CR5_MUTELINR 0
+
+/* CR6-CR0x0006 */
+#define AB8500_CODEC_CR6_ENDMIC1 7
+#define AB8500_CODEC_CR6_ENDMIC2 6
+#define AB8500_CODEC_CR6_ENDMIC3 5
+#define AB8500_CODEC_CR6_ENDMIC4 4
+#define AB8500_CODEC_CR6_ENDMIC5 3
+#define AB8500_CODEC_CR6_ENDMIC6 2
+
+/* CR7-CR0x0007 */
+#define AB8500_CODEC_CR7_MIC1SEL 7
+#define AB8500_CODEC_CR7_LINRSEL 6
+#define AB8500_CODEC_CR7_ENDRVHSL 5
+#define AB8500_CODEC_CR7_ENDRVHSR 4
+#define AB8500_CODEC_CR7_ENADCMIC 2
+#define AB8500_CODEC_CR7_ENADCLINL 1
+#define AB8500_CODEC_CR7_ENADCLINR 0
+
+/* CR8-CR0x0008 */
+#define AB8500_CODEC_CR8_CP_DIS_PLDWN 7
+#define AB8500_CODEC_CR8_ENEAR 6
+#define AB8500_CODEC_CR8_ENHSL 5
+#define AB8500_CODEC_CR8_ENHSR 4
+#define AB8500_CODEC_CR8_ENHFL 3
+#define AB8500_CODEC_CR8_ENHFR 2
+#define AB8500_CODEC_CR8_ENVIBL 1
+#define AB8500_CODEC_CR8_ENVIBR 0
+
+/* CR9-CR0x0009 */
+#define AB8500_CODEC_CR9_ENADACEAR 6
+#define AB8500_CODEC_CR9_ENADACHSL 5
+#define AB8500_CODEC_CR9_ENADACHSR 4
+#define AB8500_CODEC_CR9_ENADACHFL 3
+#define AB8500_CODEC_CR9_ENADACHFR 2
+#define AB8500_CODEC_CR9_ENADACVIBL 1
+#define AB8500_CODEC_CR9_ENADACVIBR 0
+
+/* CR10-CR0x000A */
+#define AB8500_CODEC_CR10_MUTEEAR 6
+#define AB8500_CODEC_CR10_MUTEHSL 5
+#define AB8500_CODEC_CR10_MUTEHSR 4
+#define AB8500_CODEC_CR10_MUTEHFL 3
+#define AB8500_CODEC_CR10_MUTEHFR 2
+#define AB8500_CODEC_CR10_MUTEVIBL 1
+#define AB8500_CODEC_CR10_MUTEVIBR 0
+
+/* CR11-CR0x000B */
+#define AB8500_CODEC_CR11_ENSHORTPWD 7
+#define AB8500_CODEC_CR11_EARSHORTDIS 6
+#define AB8500_CODEC_CR11_HSLSHORTDIS 5
+#define AB8500_CODEC_CR11_HSRSHORTDIS 4
+#define AB8500_CODEC_CR11_HFLSHORTDIS 3
+#define AB8500_CODEC_CR11_HFRSHORTDIS 2
+#define AB8500_CODEC_CR11_VIBLSHORTDIS 1
+#define AB8500_CODEC_CR11_VIBRSHORTDIS 0
+
+/* CR12-CR0x000C */
+#define AB8500_CODEC_CR12_ENCPHS 7
+#define AB8500_CODEC_CR12_HSAUTOTIME 4
+#define AB8500_CODEC_CR12_HSAUTOENSEL 1
+#define AB8500_CODEC_CR12_HSAUTOEN 0
+
+/* CR13-CR0x000D */
+#define AB8500_CODEC_CR13_ENVDET_HTHRESH 4
+#define AB8500_CODEC_CR13_ENVDET_LTHRESH 0
+
+/* CR14-CR0x000E */
+#define AB8500_CODEC_CR14_SMPSLVEN 7
+#define AB8500_CODEC_CR14_ENVDETSMPSEN 6
+#define AB8500_CODEC_CR14_CPLVEN 5
+#define AB8500_CODEC_CR14_ENVDETCPEN 4
+#define AB8500_CODEC_CR14_ENVDET_TIME 0
+
+/* CR15-CR0x000F */
+#define AB8500_CODEC_CR15_PWMTOVIBL 7
+#define AB8500_CODEC_CR15_PWMTOVIBR 6
+#define AB8500_CODEC_CR15_PWMLCTRL 5
+#define AB8500_CODEC_CR15_PWMRCTRL 4
+#define AB8500_CODEC_CR15_PWMNLCTRL 3
+#define AB8500_CODEC_CR15_PWMPLCTRL 2
+#define AB8500_CODEC_CR15_PWMNRCTRL 1
+#define AB8500_CODEC_CR15_PWMPRCTRL 0
+
+/* CR16-CR0x0010 */
+#define AB8500_CODEC_CR16_PWMNLPOL 7
+#define AB8500_CODEC_CR16_PWMNLDUTYCYCLE 0
+
+/* CR17-CR0x0011 */
+#define AB8500_CODEC_CR17_PWMPLPOL 7
+#define AB8500_CODEC_CR17_PWMLPDUTYCYCLE 0
+
+/* CR18-CR0x0012 */
+#define AB8500_CODEC_CR18_PWMNRPOL 7
+#define AB8500_CODEC_CR18_PWMNRDUTYCYCLE 0
+
+/* CR19-CR0x0013 */
+#define AB8500_CODEC_CR19_PWMPRPOL 7
+#define AB8500_CODEC_CR19_PWMRPDUTYCYCLE 0
+
+/* CR20-CR0x0014 */
+#define AB8500_CODEC_CR20_EN_SE_MIC1 7
+#define AB8500_CODEC_CR20_MIC1_GAIN 0
+
+/* CR21-CR0x0015 */
+#define AB8500_CODEC_CR21_EN_SE_MIC2 7
+#define AB8500_CODEC_CR21_MIC2_GAIN 0
+
+/* CR22-CR0x0016 */
+#define AB8500_CODEC_CR22_HSL_GAIN 5
+#define AB8500_CODEC_CR22_LINL_GAIN 0
+
+/* CR23-CR0x0017 */
+#define AB8500_CODEC_CR23_HSR_GAIN 5
+#define AB8500_CODEC_CR23_LINR_GAIN 0
+
+/* CR24-CR0x0018 */
+#define AB8500_CODEC_CR24_LINTOHSL_GAIN 0
+
+/* CR25-CR0x0019 */
+#define AB8500_CODEC_CR25_LINTOHSR_GAIN 0
+
+/* CR26-CR0x001A */
+#define AB8500_CODEC_CR26_AD1NH 7
+#define AB8500_CODEC_CR26_AD2NH 6
+#define AB8500_CODEC_CR26_AD3NH 5
+#define AB8500_CODEC_CR26_AD4NH 4
+#define AB8500_CODEC_CR26_AD1_VOICE 3
+#define AB8500_CODEC_CR26_AD2_VOICE 2
+#define AB8500_CODEC_CR26_AD3_VOICE 1
+#define AB8500_CODEC_CR26_AD4_VOICE 0
+
+/* CR27-CR0x001B */
+#define AB8500_CODEC_CR27_EN_MASTGEN 7
+#define AB8500_CODEC_CR27_IF1_BITCLK_OSR 5
+#define AB8500_CODEC_CR27_ENFS_BITCLK1 4
+#define AB8500_CODEC_CR27_IF0_BITCLK_OSR 1
+#define AB8500_CODEC_CR27_ENFS_BITCLK0 0
+
+/* CR28-CR0x001C */
+#define AB8500_CODEC_CR28_FSYNC0P 6
+#define AB8500_CODEC_CR28_BITCLK0P 5
+#define AB8500_CODEC_CR28_IF0DEL 4
+#define AB8500_CODEC_CR28_IF0FORMAT 2
+#define AB8500_CODEC_CR28_IF0WL 0
+
+/* CR29-CR0x001D */
+#define AB8500_CODEC_CR29_IF0DATOIF1AD 7
+#define AB8500_CODEC_CR29_IF0CKTOIF1CK 6
+#define AB8500_CODEC_CR29_IF1MASTER 5
+#define AB8500_CODEC_CR29_IF1DATOIF0AD 3
+#define AB8500_CODEC_CR29_IF1CKTOIF0CK 2
+#define AB8500_CODEC_CR29_IF0MASTER 1
+#define AB8500_CODEC_CR29_IF0BFIFOEN 0
+
+/* CR30-CR0x001E */
+#define AB8500_CODEC_CR30_FSYNC1P 6
+#define AB8500_CODEC_CR30_BITCLK1P 5
+#define AB8500_CODEC_CR30_IF1DEL 4
+#define AB8500_CODEC_CR30_IF1FORMAT 2
+#define AB8500_CODEC_CR30_IF1WL 0
+
+/* CR31-CR0x001F */
+#define AB8500_CODEC_CR31_ADOTOSLOT1 4
+#define AB8500_CODEC_CR31_ADOTOSLOT0 0
+
+/* CR32-CR0x0020 */
+#define AB8500_CODEC_CR32_ADOTOSLOT3 4
+#define AB8500_CODEC_CR32_ADOTOSLOT2 0
+
+/* CR33-CR0x0021 */
+#define AB8500_CODEC_CR33_ADOTOSLOT5 4
+#define AB8500_CODEC_CR33_ADOTOSLOT4 0
+
+/* CR34-CR0x0022 */
+#define AB8500_CODEC_CR34_ADOTOSLOT7 4
+#define AB8500_CODEC_CR34_ADOTOSLOT6 0
+
+/* CR35-CR0x0023 */
+#define AB8500_CODEC_CR35_ADOTOSLOT9 4
+#define AB8500_CODEC_CR35_ADOTOSLOT8 0
+
+/* CR36-CR0x0024 */
+#define AB8500_CODEC_CR36_ADOTOSLOT11 4
+#define AB8500_CODEC_CR36_ADOTOSLOT10 0
+
+/* CR37-CR0x0025 */
+#define AB8500_CODEC_CR37_ADOTOSLOT13 4
+#define AB8500_CODEC_CR37_ADOTOSLOT12 0
+
+/* CR38-CR0x0026 */
+#define AB8500_CODEC_CR38_ADOTOSLOT15 4
+#define AB8500_CODEC_CR38_ADOTOSLOT14 0
+
+/* CR39-CR0x0027 */
+#define AB8500_CODEC_CR39_ADOTOSLOT17 4
+#define AB8500_CODEC_CR39_ADOTOSLOT16 0
+
+/* CR40-CR0x0028 */
+#define AB8500_CODEC_CR40_ADOTOSLOT19 4
+#define AB8500_CODEC_CR40_ADOTOSLOT18 0
+
+/* CR41-CR0x0029 */
+#define AB8500_CODEC_CR41_ADOTOSLOT21 4
+#define AB8500_CODEC_CR41_ADOTOSLOT20 0
+
+/* CR42-CR0x002A */
+#define AB8500_CODEC_CR42_ADOTOSLOT23 4
+#define AB8500_CODEC_CR42_ADOTOSLOT22 0
+
+/* CR43-CR0x002B */
+#define AB8500_CODEC_CR43_ADOTOSLOT25 4
+#define AB8500_CODEC_CR43_ADOTOSLOT24 0
+
+/* CR44-CR0x002C */
+#define AB8500_CODEC_CR44_ADOTOSLOT27 4
+#define AB8500_CODEC_CR44_ADOTOSLOT26 0
+
+/* CR45-CR0x002D */
+#define AB8500_CODEC_CR45_ADOTOSLOT29 4
+#define AB8500_CODEC_CR45_ADOTOSLOT28 0
+
+/* CR46-CR0x002E */
+#define AB8500_CODEC_CR46_ADOTOSLOT31 4
+#define AB8500_CODEC_CR46_ADOTOSLOT30 0
+
+/* CR47-CR0x002F */
+#define AB8500_CODEC_CR47_HIZ_SL7 7
+#define AB8500_CODEC_CR47_HIZ_SL6 6
+#define AB8500_CODEC_CR47_HIZ_SL5 5
+#define AB8500_CODEC_CR47_HIZ_SL4 4
+#define AB8500_CODEC_CR47_HIZ_SL3 3
+#define AB8500_CODEC_CR47_HIZ_SL2 2
+#define AB8500_CODEC_CR47_HIZ_SL1 1
+#define AB8500_CODEC_CR47_HIZ_SL0 0
+
+/* CR48-CR0x0030 */
+#define AB8500_CODEC_CR48_HIZ_SL15 7
+#define AB8500_CODEC_CR48_HIZ_SL14 6
+#define AB8500_CODEC_CR48_HIZ_SL13 5
+#define AB8500_CODEC_CR48_HIZ_SL12 4
+#define AB8500_CODEC_CR48_HIZ_SL11 3
+#define AB8500_CODEC_CR48_HIZ_SL10 2
+#define AB8500_CODEC_CR48_HIZ_SL9 1
+#define AB8500_CODEC_CR48_HIZ_SL8 0
+
+/* CR49-CR0x0031 */
+#define AB8500_CODEC_CR49_HIZ_SL23 7
+#define AB8500_CODEC_CR49_HIZ_SL22 6
+#define AB8500_CODEC_CR49_HIZ_SL21 5
+#define AB8500_CODEC_CR49_HIZ_SL20 4
+#define AB8500_CODEC_CR49_HIZ_SL19 3
+#define AB8500_CODEC_CR49_HIZ_SL18 2
+#define AB8500_CODEC_CR49_HIZ_SL17 1
+#define AB8500_CODEC_CR49_HIZ_SL16 0
+
+/* CR50-CR0x0032 */
+#define AB8500_CODEC_CR50_HIZ_SL31 7
+#define AB8500_CODEC_CR50_HIZ_SL30 6
+#define AB8500_CODEC_CR50_HIZ_SL29 5
+#define AB8500_CODEC_CR50_HIZ_SL28 4
+#define AB8500_CODEC_CR50_HIZ_SL27 3
+#define AB8500_CODEC_CR50_HIZ_SL26 2
+#define AB8500_CODEC_CR50_HIZ_SL25 1
+#define AB8500_CODEC_CR50_HIZ_SL24 0
+
+/* CR51-CR0x0033 */
+#define AB8500_CODEC_CR51_DA12_VOICE 7
+#define AB8500_CODEC_CR51_SLDAI1TOSLADO1 5
+#define AB8500_CODEC_CR51_SLTODA1 0
+
+/* CR52-CR0x0034 */
+#define AB8500_CODEC_CR52_SLDAI1TOSLADO2 5
+#define AB8500_CODEC_CR52_SLTODA2 0
+
+/* CR53-CR0x0035 */
+#define AB8500_CODEC_CR53_DA34_VOICE 7
+#define AB8500_CODEC_CR53_SLDAI1TOSLADO3 5
+#define AB8500_CODEC_CR53_SLTODA3 0
+
+/* CR54-CR0x0036 */
+#define AB8500_CODEC_CR54_SLDAI1TOSLADO4 5
+#define AB8500_CODEC_CR54_SLTODA4 0
+
+/* CR55-CR0x0037 */
+#define AB8500_CODEC_CR55_DA56_VOICE 7
+#define AB8500_CODEC_CR55_SLDAI1TOSLADO5 5
+#define AB8500_CODEC_CR55_SLTODA5 0
+
+/* CR56-CR0x0038 */
+#define AB8500_CODEC_CR56_SLDAI1TOSLADO6 5
+#define AB8500_CODEC_CR56_SLTODA6 0
+
+/* CR57-CR0x0039 */
+#define AB8500_CODEC_CR57_BFIFULL_MSK 6
+#define AB8500_CODEC_CR57_BFIEMPT_MSK 5
+#define AB8500_CODEC_CR57_DACHAN_MSK 4
+#define AB8500_CODEC_CR57_GAIN_MSK 3
+#define AB8500_CODEC_CR57_DSPAD_MSK 2
+#define AB8500_CODEC_CR57_DSPDA_MSK 1
+#define AB8500_CODEC_CR57_STFIR_MSK 0
+
+/* CR58-CR0x003A */
+#define AB8500_CODEC_CR58_BFIFULL_EV 6
+#define AB8500_CODEC_CR58_BFIEMPT_EV 5
+#define AB8500_CODEC_CR58_DACHAN_EV 4
+#define AB8500_CODEC_CR58_GAIN_EV 3
+#define AB8500_CODEC_CR58_DSPAD_EV 2
+#define AB8500_CODEC_CR58_DSPDA_EV 1
+#define AB8500_CODEC_CR58_STFIR_EV 0
+
+/* CR59-CR0x003B */
+#define AB8500_CODEC_CR59_VSSREADY_MSK 7
+#define AB8500_CODEC_CR59_SHRTVIBL_MSK 6
+#define AB8500_CODEC_CR59_SHRTVIBR_MSK 5
+#define AB8500_CODEC_CR59_SHRTHFL_MSK 4
+#define AB8500_CODEC_CR59_SHRTHFR_MSK 3
+#define AB8500_CODEC_CR59_SHRTHSL_MSK 2
+#define AB8500_CODEC_CR59_SHRTHSR_MSK 1
+#define AB8500_CODEC_CR59_SHRTEAR_MSK 0
+
+/* CR60-CR0x003C */
+#define AB8500_CODEC_CR60_VSSREADY_EV 7
+#define AB8500_CODEC_CR60_SHRTVIBL_EV 6
+#define AB8500_CODEC_CR60_SHRTVIBR_EV 5
+#define AB8500_CODEC_CR60_SHRTHFL_EV 4
+#define AB8500_CODEC_CR60_SHRTHFR_EV 3
+#define AB8500_CODEC_CR60_SHRTHSL_EV 2
+#define AB8500_CODEC_CR60_SHRTHSR_EV 1
+#define AB8500_CODEC_CR60_SHRTEAR_EV 0
+
+/* CR61-CR0x003D */
+#define AB8500_CODEC_CR61_REVISION 2
+#define AB8500_CODEC_CR61_FADE_SPEED 0
+
+/* CR62-CR0x003E */
+#define AB8500_CODEC_CR62_DMIC1SINC3 5
+#define AB8500_CODEC_CR62_DMIC2SINC3 4
+#define AB8500_CODEC_CR62_DMIC3SINC3 3
+#define AB8500_CODEC_CR62_DMIC4SINC3 2
+#define AB8500_CODEC_CR62_DMIC5SINC3 1
+#define AB8500_CODEC_CR62_DMIC6SINC3 0
+
+/* CR63-CR0x003F */
+#define AB8500_CODEC_CR63_DATOHSLEN 7
+#define AB8500_CODEC_CR63_DATOHSREN 6
+#define AB8500_CODEC_CR63_AD1SEL 5
+#define AB8500_CODEC_CR63_AD2SEL 4
+#define AB8500_CODEC_CR63_AD3SEL 3
+#define AB8500_CODEC_CR63_AD5SEL 2
+#define AB8500_CODEC_CR63_AD6SEL 1
+#define AB8500_CODEC_CR63_ANCSEL 0
+
+/* CR64-CR0x0040 */
+#define AB8500_CODEC_CR64_DATOHFREN 7
+#define AB8500_CODEC_CR64_DATOHFLEN 6
+#define AB8500_CODEC_CR64_HFRSEL 5
+#define AB8500_CODEC_CR64_HFLSEL 4
+#define AB8500_CODEC_CR64_STFIR1SEL 2
+#define AB8500_CODEC_CR64_STFIR2SEL 0
+
+/* CR65-CR0x0041 */
+#define AB8500_CODEC_CR65_FADEDIS_AD1 6
+#define AB8500_CODEC_CR65_AD1GAIN 0
+
+/* CR66-CR0x0042 */
+#define AB8500_CODEC_CR66_FADEDIS_AD2 6
+#define AB8500_CODEC_CR66_AD2GAIN 0
+
+/* CR67-CR0x0043 */
+#define AB8500_CODEC_CR67_FADEDIS_AD3 6
+#define AB8500_CODEC_CR67_AD3GAIN 0
+
+/* CR68-CR0x0044 */
+#define AB8500_CODEC_CR68_FADEDIS_AD4 6
+#define AB8500_CODEC_CR68_AD4GAIN 0
+
+/* CR69-CR0x0045 */
+#define AB8500_CODEC_CR69_FADEDIS_AD5 6
+#define AB8500_CODEC_CR69_AD5GAIN 0
+
+/* CR70-CR0x0046 */
+#define AB8500_CODEC_CR70_FADEDIS_AD6 6
+#define AB8500_CODEC_CR70_AD6GAIN 0
+
+/* CR71-CR0x0047 */
+#define AB8500_CODEC_CR71_FADEDIS_DA1 6
+#define AB8500_CODEC_CR71_DA1GAIN 0
+
+/* CR72-CR0x0048 */
+#define AB8500_CODEC_CR72_FADEDIS_DA2 6
+#define AB8500_CODEC_CR72_DA2GAIN 0
+
+/* CR73-CR0x0049 */
+#define AB8500_CODEC_CR73_FADEDIS_DA3 6
+#define AB8500_CODEC_CR73_DA3GAIN 0
+
+/* CR74-CR0x004A */
+#define AB8500_CODEC_CR74_FADEDIS_DA4 6
+#define AB8500_CODEC_CR74_DA4GAIN 0
+
+/* CR75-CR0x004B */
+#define AB8500_CODEC_CR75_FADEDIS_DA5 6
+#define AB8500_CODEC_CR75_DA5GAIN 0
+
+/* CR76-CR0x004C */
+#define AB8500_CODEC_CR76_FADEDIS_DA6 6
+#define AB8500_CODEC_CR76_DA6GAIN 0
+
+/* CR77-CR0x004D */
+#define AB8500_CODEC_CR77_FADEDIS_AD1L 6
+#define AB8500_CODEC_CR77_AD1LBGAIN 0
+
+/* CR78-CR0x004E */
+#define AB8500_CODEC_CR78_FADEDIS_AD2L 6
+#define AB8500_CODEC_CR78_AD2LBGAIN 0
+
+/* CR79-CR0x004F */
+#define AB8500_CODEC_CR79_HSSINC1 7
+#define AB8500_CODEC_CR79_FADEDIS_HSL 4
+#define AB8500_CODEC_CR79_HSLDGAIN 0
+
+/* CR80-CR0x0050 */
+#define AB8500_CODEC_CR80_FADEDIS_HSR 4
+#define AB8500_CODEC_CR80_HSRDGAIN 0
+
+/* CR81-CR0x0051 */
+#define AB8500_CODEC_CR81_STFIR1GAIN 0
+
+/* CR82-CR0x0052 */
+#define AB8500_CODEC_CR82_STFIR2GAIN 0
+
+/* CR83-CR0x0053 */
+#define AB8500_CODEC_CR83_ENANC 2
+#define AB8500_CODEC_CR83_ANCIIRINIT 1
+#define AB8500_CODEC_CR83_ANCFIRUPDATE 0
+
+/* CR84-CR0x0054 */
+#define AB8500_CODEC_CR84_ANCINSHIFT 0
+
+/* CR85-CR0x0055 */
+#define AB8500_CODEC_CR85_ANCFIROUTSHIFT 0
+
+/* CR86-CR0x0056 */
+#define AB8500_CODEC_CR86_ANCSHIFTOUT 0
+
+/* CR87-CR0x0057 */
+#define AB8500_CODEC_CR87_ANCFIRCOEFF_MSB 0
+
+/* CR88-CR0x0058 */
+#define AB8500_CODEC_CR88_ANCFIRCOEFF_LSB 0
+
+/* CR89-CR0x0059 */
+#define AB8500_CODEC_CR89_ANCIIRCOEFF_MSB 0
+
+/* CR90-CR0x005A */
+#define AB8500_CODEC_CR90_ANCIIRCOEFF_LSB 0
+
+/* CR91-CR0x005B */
+#define AB8500_CODEC_CR91_ANCWARPDEL_MSB 0
+
+/* CR92-CR0x005C */
+#define AB8500_CODEC_CR92_ANCWARPDEL_LSB 0
+
+/* CR93-CR0x005D */
+#define AB8500_CODEC_CR93_ANCFIRPEAK_MSB 0
+
+/* CR94-CR0x005E */
+#define AB8500_CODEC_CR94_ANCFIRPEAK_LSB 0
+
+/* CR95-CR0x005F */
+#define AB8500_CODEC_CR95_ANCIIRPEAK_MSB 0
+
+/* CR96-CR0x0060 */
+#define AB8500_CODEC_CR96_ANCIIRPEAK_LSB 0
+
+/* CR97-CR0x0061 */
+#define AB8500_CODEC_CR97_STFIR_SET 7
+#define AB8500_CODEC_CR97_STFIR_ADDR 0
+
+/* CR98-CR0x0062 */
+#define AB8500_CODEC_CR98_STFIR_COEFF_MSB 0
+
+/* CR99-CR0x0063 */
+#define AB8500_CODEC_CR99_STFIR_COEFF_LSB 0
+
+/* CR100-CR0x0064 */
+#define AB8500_CODEC_CR100_ENSTFIRS 2
+#define AB8500_CODEC_CR100_STFIRSTOIF1 1
+#define AB8500_CODEC_CR100_STFIR_BUSY 0
+
+/* CR101-CR0x0065 */
+#define AB8500_CODEC_CR101_PARLHF 7
+#define AB8500_CODEC_CR101_PARLVIB 6
+#define AB8500_CODEC_CR101_CLASSDVIBLSWAPEN 3
+#define AB8500_CODEC_CR101_CLASSDVIBRSWAPEN 2
+#define AB8500_CODEC_CR101_CLASSDHFLSWAPEN 1
+#define AB8500_CODEC_CR101_CLASSDHFRSWAPEN 0
+
+/* CR102-CR0x0066 */
+#define AB8500_CODEC_CR102_CLASSD_FIRBYP 4
+#define AB8500_CODEC_CR102_CLASSD_HIGHVOLEN 0
+
+/* CR103-CR0x0067 */
+#define AB8500_CODEC_CR103_CLASSD_DITHERHPGAIN 4
+#define AB8500_CODEC_CR103_CLASSD_DITHERWGAIN 0
+
+/* CR104-CR0x0068 */
+#define AB8500_CODEC_CR104_BFIFOINT 0
+
+/* CR105-CR0x0069 */
+#define AB8500_CODEC_CR105_BFIFOTX 0
+
+/* CR106-CR0x006A */
+#define AB8500_CODEC_CR106_BFIFOFSEXT 4
+#define AB8500_CODEC_CR106_BFIFOMSK 2
+#define AB8500_CODEC_CR106_BFIFOMSTR 1
+#define AB8500_CODEC_CR106_BFIFOSTRT 0
+
+/* CR107-CR0x006B */
+#define AB8500_CODEC_CR107_BFIFOSAMPNR 0
+
+/* CR108-CR0x006C */
+#define AB8500_CODEC_CR108_BFIFOWAKEUP 0
+
+/* CR109-CR0x006D */
+#define AB8500_CODEC_CR109_BFIFOSAMPLES 0
+
+
+
+/* For SetVolume API*/
+#define AB8500_CODEC_MAX_VOLUME 100
+
+/* Analog MIC1 & MIC2 */
+#define AB8500_CODEC_MIC_VOLUME_MAX 31
+#define AB8500_CODEC_MIC_VOLUME_MEDIUM 15
+#define AB8500_CODEC_MIC_VOLUME_MIN 0
+
+/* Line-in */
+#define AB8500_CODEC_LINEIN_VOLUME_MAX 31
+#define AB8500_CODEC_LINEIN_VOLUME_MEDIUM 15
+#define AB8500_CODEC_LINEIN_VOLUME_MIN 0
+
+/* HeadSet */
+#define AB8500_CODEC_HEADSET_VOLUME_MAX 0
+#define AB8500_CODEC_HEADSET_VOLUME_MEDIUM 3
+#define AB8500_CODEC_HEADSET_VOLUME_MIN 7
+
+/* HeadSet Digital */
+#define AB8500_CODEC_HEADSET_D_VOLUME_MAX 0
+#define AB8500_CODEC_HEADSET_D_VOLUME_MEDIUM 7
+#define AB8500_CODEC_HEADSET_D_VOLUME_MIN 15
+
+/* Digital AD Path */
+#define AB8500_CODEC_AD_D_VOLUME_MAX 0
+#define AB8500_CODEC_AD_D_VOLUME_MEDIUM 31
+#define AB8500_CODEC_AD_D_VOLUME_MIN 63
+
+/* Digital DA Path */
+#define AB8500_CODEC_DA_D_VOLUME_MAX 0
+#define AB8500_CODEC_DA_D_VOLUME_MEDIUM 31
+#define AB8500_CODEC_DA_D_VOLUME_MIN 63
+
+/* EarPiece Digital */
+#define AB8500_CODEC_EARPIECE_D_VOLUME_MAX 0
+#define AB8500_CODEC_EARPIECE_D_VOLUME_MEDIUM 7
+#define AB8500_CODEC_EARPIECE_D_VOLUME_MIN 15
+
+/* AD1 loopback to HFL & HFR Digital */
+#define AB8500_CODEC_AD_LB_TO_HF_L_R_VOLUME_MAX 0
+#define AB8500_CODEC_AD_LB_TO_HF_L_R_VOLUME_MEDIUM 31
+#define AB8500_CODEC_AD_LB_TO_HF_L_R_VOLUME_MIN 63
+
+/* Line-in to HSL & HSR */
+#define AB8500_CODEC_LINEIN_TO_HS_L_R_VOLUME_MAX 0
+#define AB8500_CODEC_LINEIN_TO_HS_L_R_VOLUME_MEDIUM 9
+#define AB8500_CODEC_LINEIN_TO_HS_L_R_VOLUME_MIN 18
+#define AB8500_CODEC_LINEIN_TO_HS_L_R_LOOP_OPEN 19
+
+/* Vibrator */
+#define AB8500_CODEC_VIBRATOR_VOLUME_MAX 100
+#define AB8500_CODEC_VIBRATOR_VOLUME_MEDIUM 50
+#define AB8500_CODEC_VIBRATOR_VOLUME_MIN 0
+
+
+/* CR0 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR0_POWERUP_OFF,
+ AB8500_CODEC_CR0_POWERUP_ON
+} t_ab8500_codec_cr0_powerup;
+
+/* CR0 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR0_ENAANA_OFF,
+ AB8500_CODEC_CR0_ENAANA_ON
+} t_ab8500_codec_cr0_enaana;
+
+
+/* CR1 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR1_SWRESET_DISABLED,
+ AB8500_CODEC_CR1_SWRESET_ENABLED
+} t_ab8500_codec_cr1_swreset;
+
+
+/* CR2 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR2_ENAD1_DISABLED,
+ AB8500_CODEC_CR2_ENAD1_ENABLED
+} t_ab8500_codec_cr2_enad1;
+
+/* CR2 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR2_ENAD2_DISABLED,
+ AB8500_CODEC_CR2_ENAD2_ENABLED
+} t_ab8500_codec_cr2_enad2;
+
+/* CR2 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR2_ENAD3_DISABLED,
+ AB8500_CODEC_CR2_ENAD3_ENABLED
+} t_ab8500_codec_cr2_enad3;
+
+/* CR2 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR2_ENAD4_DISABLED,
+ AB8500_CODEC_CR2_ENAD4_ENABLED
+} t_ab8500_codec_cr2_enad4;
+
+/* CR2 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR2_ENAD5_DISABLED,
+ AB8500_CODEC_CR2_ENAD5_ENABLED
+} t_ab8500_codec_cr2_enad5;
+
+/* CR2 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR2_ENAD6_DISABLED,
+ AB8500_CODEC_CR2_ENAD6_ENABLED
+} t_ab8500_codec_cr2_enad6;
+
+
+/* CR3 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR3_ENDA1_DISABLED,
+ AB8500_CODEC_CR3_ENDA1_ENABLED
+} t_ab8500_codec_cr3_enda1;
+
+/* CR3 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR3_ENDA2_DISABLED,
+ AB8500_CODEC_CR3_ENDA2_ENABLED
+} t_ab8500_codec_cr3_enda2;
+
+/* CR3 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR3_ENDA3_DISABLED,
+ AB8500_CODEC_CR3_ENDA3_ENABLED
+} t_ab8500_codec_cr3_enda3;
+
+/* CR3 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR3_ENDA4_DISABLED,
+ AB8500_CODEC_CR3_ENDA4_ENABLED
+} t_ab8500_codec_cr3_enda4;
+
+/* CR3 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR3_ENDA5_DISABLED,
+ AB8500_CODEC_CR3_ENDA5_ENABLED
+} t_ab8500_codec_cr3_enda5;
+
+/* CR3 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR3_ENDA6_DISABLED,
+ AB8500_CODEC_CR3_ENDA6_ENABLED
+} t_ab8500_codec_cr3_enda6;
+
+
+/* CR4 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR4_LOWPOWHS_NORMAL,
+ AB8500_CODEC_CR4_LOWPOWHS_LP
+} t_ab8500_codec_cr4_lowpowhs;
+
+/* CR4 - 6:5 */
+typedef enum
+{
+ AB8500_CODEC_CR4_LOWPOWDACHS_NORMAL,
+ AB8500_CODEC_CR4_LOWPOWDACHS_DRIVERS_LP,
+ AB8500_CODEC_CR4_LOWPOWDACHS_LP,
+ AB8500_CODEC_CR4_LOWPOWDACHS_BOTH_LP
+} t_ab8500_codec_cr4_lowpowdachs;
+
+/* CR4 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR4_LOWPOWEAR_NORMAL,
+ AB8500_CODEC_CR4_LOWPOWEAR_LP
+} t_ab8500_codec_cr4_lowpowear;
+
+/* CR4 - 3:2 */
+typedef enum
+{
+ AB8500_CODEC_CR4_EAR_SEL_CM_0_95V,
+ AB8500_CODEC_CR4_EAR_SEL_CM_1_1V,
+ AB8500_CODEC_CR4_EAR_SEL_CM_1_27V,
+ AB8500_CODEC_CR4_EAR_SEL_CM_1_58V
+} t_ab8500_codec_cr4_ear_sel_cm;
+
+/* CR4 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR4_HS_HP_DIS_FILTER_ENABLED,
+ AB8500_CODEC_CR4_HS_HP_DIS_FILTER_DISABLED
+} t_ab8500_codec_cr4_hs_hp_dis;
+
+/* CR4 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR4_EAR_HP_DIS_FILTER_ENABLED,
+ AB8500_CODEC_CR4_EAR_HP_DIS_FILTER_DISABLED
+} t_ab8500_codec_cr4_ear_hp_dis;
+
+
+/* CR5 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR5_ENMIC1_DISABLED,
+ AB8500_CODEC_CR5_ENMIC1_ENABLED
+} t_ab8500_codec_cr5_enmic1;
+
+/* CR5 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR5_ENMIC2_DISABLED,
+ AB8500_CODEC_CR5_ENMIC2_ENABLED
+} t_ab8500_codec_cr5_enmic2;
+
+/* CR5 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR5_ENLINL_DISABLED,
+ AB8500_CODEC_CR5_ENLINL_ENABLED
+} t_ab8500_codec_cr5_enlinl;
+
+/* CR5 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR5_ENLINR_DISABLED,
+ AB8500_CODEC_CR5_ENLINR_ENABLED
+} t_ab8500_codec_cr5_enlinr;
+
+/* CR5 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR5_MUTMIC1_DISABLED,
+ AB8500_CODEC_CR5_MUTMIC1_ENABLED
+} t_ab8500_codec_cr5_mutmic1;
+
+/* CR5 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR5_MUTMIC2_DISABLED,
+ AB8500_CODEC_CR5_MUTMIC2_ENABLED
+} t_ab8500_codec_cr5_mutmic2;
+
+/* CR5 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR5_MUTLINL_DISABLED,
+ AB8500_CODEC_CR5_MUTLINL_ENABLED
+} t_ab8500_codec_cr5_mutlinl;
+
+/* CR5 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR5_MUTLINR_DISABLED,
+ AB8500_CODEC_CR5_MUTLINR_ENABLED
+} t_ab8500_codec_cr5_mutlinr;
+
+
+/* CR6 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR6_ENDMIC1_DISABLED,
+ AB8500_CODEC_CR6_ENDMIC1_ENABLED
+} t_ab8500_codec_cr6_endmic1;
+
+/* CR6 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR6_ENDMIC2_DISABLED,
+ AB8500_CODEC_CR6_ENDMIC2_ENABLED
+} t_ab8500_codec_cr6_endmic2;
+
+/* CR6 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR6_ENDMIC3_DISABLED,
+ AB8500_CODEC_CR6_ENDMIC3_ENABLED
+} t_ab8500_codec_cr6_endmic3;
+
+/* CR6 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR6_ENDMIC4_DISABLED,
+ AB8500_CODEC_CR6_ENDMIC4_ENABLED
+} t_ab8500_codec_cr6_endmic4;
+
+/* CR6 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR6_ENDMIC5_DISABLED,
+ AB8500_CODEC_CR6_ENDMIC5_ENABLED
+} t_ab8500_codec_cr6_endmic5;
+
+/* CR6 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR6_ENDMIC6_DISABLED,
+ AB8500_CODEC_CR6_ENDMIC6_ENABLED
+} t_ab8500_codec_cr6_endmic6;
+
+
+/* CR7 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR7_MIC1SEL_MIC1A,
+ AB8500_CODEC_CR7_MIC1SEL_MIC1B
+} t_ab8500_codec_cr7_mic1sel;
+
+/* CR7 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR7_LINRSEL_MIC2,
+ AB8500_CODEC_CR7_LINRSEL_LINR
+} t_ab8500_codec_cr7_linrsel;
+
+/* CR7 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR7_ENDRVHSL_DISABLED,
+ AB8500_CODEC_CR7_ENDRVHSL_ENABLED
+} t_ab8500_codec_cr7_endrvhsl;
+
+/* CR7 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR7_ENDRVHSR_DISABLED,
+ AB8500_CODEC_CR7_ENDRVHSR_ENABLED
+} t_ab8500_codec_cr7_endrvhsr;
+
+/* CR7 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR7_ENADCMIC_DISABLED,
+ AB8500_CODEC_CR7_ENADCMIC_ENABLED
+} t_ab8500_codec_cr7_enadcmic;
+
+/* CR7 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR7_ENADCLINL_DISABLED,
+ AB8500_CODEC_CR7_ENADCLINL_ENABLED
+} t_ab8500_codec_cr7_enadclinl;
+
+/* CR7 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR7_ENADCLINR_DISABLED,
+ AB8500_CODEC_CR7_ENADCLINR_ENABLED
+} t_ab8500_codec_cr7_enadclinr;
+
+
+/* CR8 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR8_CP_DIS_PLDWN_ENABLED,
+ AB8500_CODEC_CR8_CP_DIS_PLDWN_DISABLED
+} t_ab8500_codec_cr8_cp_dis_pldwn;
+
+/* CR8 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR8_ENEAR_DISABLED,
+ AB8500_CODEC_CR8_ENEAR_ENABLED
+} t_ab8500_codec_cr8_enear;
+
+/* CR8 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR8_ENHSL_DISABLED,
+ AB8500_CODEC_CR8_ENHSL_ENABLED
+} t_ab8500_codec_cr8_enhsl;
+
+/* CR8 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR8_ENHSR_DISABLED,
+ AB8500_CODEC_CR8_ENHSR_ENABLED
+} t_ab8500_codec_cr8_enhsr;
+
+/* CR8 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR8_ENHFL_DISABLED,
+ AB8500_CODEC_CR8_ENHFL_ENABLED
+} t_ab8500_codec_cr8_enhfl;
+
+/* CR8 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR8_ENHFR_DISABLED,
+ AB8500_CODEC_CR8_ENHFR_ENABLED
+} t_ab8500_codec_cr8_enhfr;
+
+/* CR8 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR8_ENVIBL_DISABLED,
+ AB8500_CODEC_CR8_ENVIBL_ENABLED
+} t_ab8500_codec_cr8_envibl;
+
+/* CR8 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR8_ENVIBR_DISABLED,
+ AB8500_CODEC_CR8_ENVIBR_ENABLED
+} t_ab8500_codec_cr8_envibr;
+
+
+/* CR9 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR9_ENDACEAR_DISABLED,
+ AB8500_CODEC_CR9_ENDACEAR_ENABLED
+} t_ab8500_codec_cr9_endacear;
+
+/* CR9 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR9_ENDACHSL_DISABLED,
+ AB8500_CODEC_CR9_ENDACHSL_ENABLED
+} t_ab8500_codec_cr9_endachsl;
+
+/* CR9 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR9_ENDACHSR_DISABLED,
+ AB8500_CODEC_CR9_ENDACHSR_ENABLED
+} t_ab8500_codec_cr9_endachsr;
+
+/* CR9 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR9_ENDACHFL_DISABLED,
+ AB8500_CODEC_CR9_ENDACHFL_ENABLED
+} t_ab8500_codec_cr9_endachfl;
+
+/* CR9 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR9_ENDACHFR_DISABLED,
+ AB8500_CODEC_CR9_ENDACHFR_ENABLED
+} t_ab8500_codec_cr9_endachfr;
+
+/* CR9 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR9_ENDACVIBL_DISABLED,
+ AB8500_CODEC_CR9_ENDACVIBL_ENABLED
+} t_ab8500_codec_cr9_endacvibl;
+
+/* CR9 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR9_ENDACVIBR_DISABLED,
+ AB8500_CODEC_CR9_ENDACVIBR_ENABLED
+} t_ab8500_codec_cr9_endacvibr;
+
+
+/* CR10 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR10_MUTEEAR_DISABLED,
+ AB8500_CODEC_CR10_MUTEEAR_ENABLED
+} t_ab8500_codec_cr10_muteear;
+
+/* CR10 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR10_MUTEHSL_DISABLED,
+ AB8500_CODEC_CR10_MUTEHSL_ENABLED
+} t_ab8500_codec_cr10_mutehsl;
+
+/* CR10 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR10_MUTEHSR_DISABLED,
+ AB8500_CODEC_CR10_MUTEHSR_ENABLED
+} t_ab8500_codec_cr10_mutehsr;
+
+/* CR10 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR10_MUTEHFL_DISABLED,
+ AB8500_CODEC_CR10_MUTEHFL_ENABLED
+} t_ab8500_codec_cr10_mutehfl;
+
+/* CR10 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR10_MUTEHFR_DISABLED,
+ AB8500_CODEC_CR10_MUTEHFR_ENABLED
+} t_ab8500_codec_cr10_mutehfr;
+
+/* CR10 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR10_MUTEVIBL_DISABLED,
+ AB8500_CODEC_CR10_MUTEVIBL_ENABLED
+} t_ab8500_codec_cr10_mutevibl;
+
+/* CR10 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR10_MUTEVIBR_DISABLED,
+ AB8500_CODEC_CR10_MUTEVIBR_ENABLED
+} t_ab8500_codec_cr10_mutevibr;
+
+
+/* CR11 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR11_EARSHORTPWD_DISABLED,
+ AB8500_CODEC_CR11_EARSHORTPWD_ENABLED
+} t_ab8500_codec_cr11_earshortpwd;
+
+/* CR11 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR11_EARSHORTDIS_ENABLED,
+ AB8500_CODEC_CR11_EARSHORTDIS_DISABLED
+} t_ab8500_codec_cr11_earshortdis;
+
+/* CR11 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR11_HSLSHORTDIS_ENABLED,
+ AB8500_CODEC_CR11_HSLSHORTDIS_DISABLED
+} t_ab8500_codec_cr11_hslshortdis;
+
+/* CR11 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR11_HSRSHORTDIS_ENABLED,
+ AB8500_CODEC_CR11_HSRSHORTDIS_DISABLED
+} t_ab8500_codec_cr11_hsrshortdis;
+
+/* CR11 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR11_HFLSHORTDIS_ENABLED,
+ AB8500_CODEC_CR11_HFLSHORTDIS_DISABLED
+} t_ab8500_codec_cr11_hflshortdis;
+
+/* CR11 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR11_HFRSHORTDIS_ENABLED,
+ AB8500_CODEC_CR11_HFRSHORTDIS_DISABLED
+} t_ab8500_codec_cr11_hfrshortdis;
+
+/* CR11 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR11_VIBLSHORTDIS_ENABLED,
+ AB8500_CODEC_CR11_VIBLSHORTDIS_DISABLED
+} t_ab8500_codec_cr11_viblshortdis;
+
+/* CR11 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR11_VIBRSHORTDIS_ENABLED,
+ AB8500_CODEC_CR11_VIBRSHORTDIS_DISABLED
+} t_ab8500_codec_cr11_vibrshortdis;
+
+
+/* CR12 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR12_ENCPHS_DISABLED,
+ AB8500_CODEC_CR12_ENCPHS_ENABLED
+} t_ab8500_codec_cr12_encphs;
+
+/* CR12 - 6:4 */
+typedef enum
+{
+ AB8500_CODEC_CR12_HSAUTOTIME_6_6USEC,
+ AB8500_CODEC_CR12_HSAUTOTIME_13_3USEC,
+ AB8500_CODEC_CR12_HSAUTOTIME_26_6USEC,
+ AB8500_CODEC_CR12_HSAUTOTIME_53_2USEC,
+ AB8500_CODEC_CR12_HSAUTOTIME_106_4USEC,
+ AB8500_CODEC_CR12_HSAUTOTIME_212_8USEC,
+ AB8500_CODEC_CR12_HSAUTOTIME_425_6USEC,
+ AB8500_CODEC_CR12_HSAUTOTIME_851_2USEC,
+} t_ab8500_codec_cr12_hsautotime;
+
+/* CR12 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR12_HSAUTOENSEL_DISABLED,
+ AB8500_CODEC_CR12_HSAUTOENSEL_ENABLED
+} t_ab8500_codec_cr12_hsautoensel;
+
+/* CR12 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR12_HSAUTOEN_DISABLED,
+ AB8500_CODEC_CR12_HSAUTOEN_ENABLED
+} t_ab8500_codec_cr12_hsautoen;
+
+
+/* CR13 - 7:4 */
+typedef enum
+{
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_25,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_50,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_100,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_150,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_200,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_250,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_300,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_350,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_400,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_450,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_500,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_550,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_600,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_650,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_700,
+ AB8500_CODEC_CR13_ENVDET_HTHRESH_750
+} t_ab8500_codec_cr13_envdet_hthresh;
+
+/* CR13 - 3:0 */
+typedef enum
+{
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_25,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_50,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_100,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_150,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_200,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_250,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_300,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_350,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_400,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_450,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_500,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_550,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_600,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_650,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_700,
+ AB8500_CODEC_CR13_ENVDET_LTHRESH_750
+} t_ab8500_codec_cr13_envdet_lthresh;
+
+
+/* CR14 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR14_SMPSLVEN_HIGHVOLTAGE,
+ AB8500_CODEC_CR14_SMPSLVEN_LOWVOLTAGE
+} t_ab8500_codec_cr14_smpslven;
+
+/* CR14 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR14_ENVDETSMPSEN_DISABLED,
+ AB8500_CODEC_CR14_ENVDETSMPSEN_ENABLED
+} t_ab8500_codec_cr14_envdetsmpsen;
+
+/* CR14 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR14_CPLVEN_HIGHVOLTAGE,
+ AB8500_CODEC_CR14_CPLVEN_LOWVOLTAGE
+} t_ab8500_codec_cr14_cplven;
+
+/* CR14 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR14_ENVDETCPEN_DISABLED,
+ AB8500_CODEC_CR14_ENVDETCPEN_ENABLED
+} t_ab8500_codec_cr14_envdetcpen;
+
+/* CR14 - 3:0 */
+typedef enum
+{
+ AB8500_CODEC_CR14_ENVET_TIME_27USEC,
+ AB8500_CODEC_CR14_ENVET_TIME_53USEC,
+ AB8500_CODEC_CR14_ENVET_TIME_106USEC,
+ AB8500_CODEC_CR14_ENVET_TIME_212USEC,
+ AB8500_CODEC_CR14_ENVET_TIME_424USEC,
+ AB8500_CODEC_CR14_ENVET_TIME_848USEC,
+ AB8500_CODEC_CR14_ENVET_TIME_1MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_3MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_6MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_13MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_27MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_54MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_109MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_218MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_436MSEC,
+ AB8500_CODEC_CR14_ENVET_TIME_872MSEC,
+} t_ab8500_codec_cr14_envet_time;
+
+
+/* CR15 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR15_PWMTOVIBL_DA_PATH,
+ AB8500_CODEC_CR15_PWMTOVIBL_PWM
+} t_ab8500_codec_cr15_pwmtovibl;
+
+/* CR15 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR15_PWMTOVIBR_DA_PATH,
+ AB8500_CODEC_CR15_PWMTOVIBR_PWM
+} t_ab8500_codec_cr15_pwmtovibr;
+
+/* CR15 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR15_PWMLCTRL_PWMNPLGPOL,
+ AB8500_CODEC_CR15_PWMLCTRL_PWMNPLDUTYCYCLE
+} t_ab8500_codec_cr15_pwmlctrl;
+
+/* CR15 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR15_PWMRCTRL_PWMNPRGPOL,
+ AB8500_CODEC_CR15_PWMRCTRL_PWMNPRDUTYCYCLE
+} t_ab8500_codec_cr15_pwmrctrl;
+
+/* CR15 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR15_PWMNLCTRL_PWMNLGPOL,
+ AB8500_CODEC_CR15_PWMNLCTRL_PWMNLDUTYCYCLE
+} t_ab8500_codec_cr15_pwmnlctrl;
+
+/* CR15 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR15_PWMPLCTRL_PWMPLGPOL,
+ AB8500_CODEC_CR15_PWMPLCTRL_PWMPLDUTYCYCLE
+} t_ab8500_codec_cr15_pwmplctrl;
+
+/* CR15 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR15_PWMNRCTRL_PWMNRGPOL,
+ AB8500_CODEC_CR15_PWMNRCTRL_PWMNRDUTYCYCLE
+} t_ab8500_codec_cr15_pwmnrctrl;
+
+/* CR15 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR15_PWMPRCTRL_PWMPRGPOL,
+ AB8500_CODEC_CR15_PWMPRCTRL_PWMPRDUTYCYCLE
+} t_ab8500_codec_cr15_pwmprctrl;
+
+
+/* CR16 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR16_PWMNLPOL_GNDVIB,
+ AB8500_CODEC_CR16_PWMNLPOL_VINVIB
+} t_ab8500_codec_cr16_pwmnlpol;
+
+/* CR16 - 6:0 */
+typedef t_uint8 t_ab8500_codec_cr16_pwmnldutycycle;
+
+
+/* CR17 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR17_PWMPLPOL_GNDVIB,
+ AB8500_CODEC_CR17_PWMPLPOL_VINVIB
+} t_ab8500_codec_cr17_pwmplpol;
+
+/* CR17 - 6:0 */
+typedef t_uint8 t_ab8500_codec_cr17_pwmpldutycycle;
+
+
+/* CR18 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR18_PWMNRPOL_GNDVIB,
+ AB8500_CODEC_CR18_PWMNRPOL_VINVIB
+} t_ab8500_codec_cr18_pwmnrpol;
+
+/* CR18 - 6:0 */
+typedef t_uint8 t_ab8500_codec_cr18_pwmnrdutycycle;
+
+
+/* CR19 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR19_PWMPRPOL_GNDVIB,
+ AB8500_CODEC_CR19_PWMPRPOL_VINVIB
+} t_ab8500_codec_cr19_pwmprpol;
+
+/* CR19 - 6:0 */
+typedef t_uint8 t_ab8500_codec_cr19_pwmprdutycycle;
+
+
+/* CR20 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR20_EN_SE_MIC1_DIFFERENTIAL,
+ AB8500_CODEC_CR20_EN_SE_MIC1_SINGLE
+} t_ab8500_codec_cr20_en_se_mic1;
+
+/* CR20 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr20_mic1_gain;
+
+
+/* CR21 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR21_EN_SE_MIC2_DIFFERENTIAL,
+ AB8500_CODEC_CR21_EN_SE_MIC2_SINGLE
+} t_ab8500_codec_cr21_en_se_mic2;
+
+/* CR21 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr21_mic2_gain;
+
+
+/* CR22 - 7:5 */
+typedef t_uint8 t_ab8500_codec_cr22_hsl_gain;
+
+/* CR22 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr22_linl_gain;
+
+
+/* CR23 - 7:5 */
+typedef t_uint8 t_ab8500_codec_cr23_hsr_gain;
+
+/* CR23 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr23_linr_gain;
+
+
+/* CR24 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr24_lintohsl_gain;
+
+
+/* CR25 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr25_lintohsr_gain;
+
+
+/* CR26 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR26_AD1NH_FILTER_ENABLED,
+ AB8500_CODEC_CR26_AD1NH_FILTER_DISABLED
+} t_ab8500_codec_cr26_ad1nh;
+
+/* CR26 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR26_AD2NH_FILTER_ENABLED,
+ AB8500_CODEC_CR26_AD2NH_FILTER_DISABLED
+} t_ab8500_codec_cr26_ad2nh;
+
+/* CR26 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR26_AD3NH_FILTER_ENABLED,
+ AB8500_CODEC_CR26_AD3NH_FILTER_DISABLED
+} t_ab8500_codec_cr26_ad3nh;
+
+/* CR26 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR26_AD4NH_FILTER_ENABLED,
+ AB8500_CODEC_CR26_AD4NH_FILTER_DISABLED
+} t_ab8500_codec_cr26_ad4nh;
+
+/* CR26 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR26_AD1_VOICE_AUDIOFILTER,
+ AB8500_CODEC_CR26_AD1_VOICE_LOWLATENCYFILTER
+} t_ab8500_codec_cr26_ad1_voice;
+
+/* CR26 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR26_AD2_VOICE_AUDIOFILTER,
+ AB8500_CODEC_CR26_AD2_VOICE_LOWLATENCYFILTER
+} t_ab8500_codec_cr26_ad2_voice;
+
+/* CR26 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR26_AD3_VOICE_AUDIOFILTER,
+ AB8500_CODEC_CR26_AD3_VOICE_LOWLATENCYFILTER
+} t_ab8500_codec_cr26_ad3_voice;
+
+/* CR26 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR26_AD4_VOICE_AUDIOFILTER,
+ AB8500_CODEC_CR26_AD4_VOICE_LOWLATENCYFILTER
+} t_ab8500_codec_cr26_ad4_voice;
+
+
+/* CR27 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR27_EN_MASTGEN_DISABLED,
+ AB8500_CODEC_CR27_EN_MASTGEN_ENABLED
+} t_ab8500_codec_cr27_en_mastgen;
+
+/* CR27 - 6:5 */
+typedef enum
+{
+ AB8500_CODEC_CR27_IF1_BITCLK_OSR_32,
+ AB8500_CODEC_CR27_IF1_BITCLK_OSR_64,
+ AB8500_CODEC_CR27_IF1_BITCLK_OSR_128,
+ AB8500_CODEC_CR27_IF1_BITCLK_OSR_256
+} t_ab8500_codec_cr27_if1_bitclk_osr;
+
+/* CR27 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR27_ENFS_BITCLK1_DISABLED,
+ AB8500_CODEC_CR27_ENFS_BITCLK1_ENABLED
+} t_ab8500_codec_cr27_enfs_bitclk1;
+
+/* CR27 - 2:1 */
+typedef enum
+{
+ AB8500_CODEC_CR27_IF0_BITCLK_OSR_32,
+ AB8500_CODEC_CR27_IF0_BITCLK_OSR_64,
+ AB8500_CODEC_CR27_IF0_BITCLK_OSR_128,
+ AB8500_CODEC_CR27_IF0_BITCLK_OSR_256
+} t_ab8500_codec_cr27_if0_bitclk_osr;
+
+/* CR27 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR27_ENFS_BITCLK0_DISABLED,
+ AB8500_CODEC_CR27_ENFS_BITCLK0_ENABLED
+} t_ab8500_codec_cr27_enfs_bitclk0;
+
+
+/* CR28 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR28_FSYNC0P_RISING_EDGE,
+ AB8500_CODEC_CR28_FSYNC0P_FALLING_EDGE
+} t_ab8500_codec_cr28_fsync0p;
+
+/* CR28 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR28_BITCLK0P_RISING_EDGE,
+ AB8500_CODEC_CR28_BITCLK0P_FALLING_EDGE
+} t_ab8500_codec_cr28_bitclk0p;
+
+/* CR28 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR28_IF0DEL_NOT_DELAYED,
+ AB8500_CODEC_CR28_IF0DEL_DELAYED
+} t_ab8500_codec_cr28_if0del;
+
+/* CR28 - 3:2 */
+typedef enum
+{
+ AB8500_CODEC_CR28_IF0FORMAT_DISABLED,
+ AB8500_CODEC_CR28_IF0FORMAT_TDM,
+ AB8500_CODEC_CR28_IF0FORMAT_I2S_LEFTALIGNED
+} t_ab8500_codec_cr28_if0format;
+
+/* CR28 - 1:0 */
+typedef enum
+{
+ AB8500_CODEC_CR28_IF0WL_16BITS,
+ AB8500_CODEC_CR28_IF0WL_20BITS,
+ AB8500_CODEC_CR28_IF0WL_24BITS,
+ AB8500_CODEC_CR28_IF0WL_32BITS
+} t_ab8500_codec_cr28_if0wl;
+
+
+/* CR29 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR29_IF0DATOIF1AD_NOTSENT,
+ AB8500_CODEC_CR29_IF0DATOIF1AD_SENT
+} t_ab8500_codec_cr29_if0datoif1ad;
+
+/* CR29 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR29_IF0CKTOIF1CK_NOTSENT,
+ AB8500_CODEC_CR29_IF0CKTOIF1CK_SENT
+} t_ab8500_codec_cr29_if0cktoif1ck;
+
+/* CR29 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR29_IF1MASTER_FS1CK1_INPUT,
+ AB8500_CODEC_CR29_IF1MASTER_FS1CK1_OUTPUT
+} t_ab8500_codec_cr29_if1master;
+
+/* CR29 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR29_IF1DATOIF0AD_NOTSENT,
+ AB8500_CODEC_CR29_IF1DATOIF0AD_SENT
+} t_ab8500_codec_cr29_if1datoif0ad;
+
+/* CR29 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR29_IF1CKTOIF0CK_NOTSENT,
+ AB8500_CODEC_CR29_IF1CKTOIF0CK_SENT
+} t_ab8500_codec_cr29_if1cktoif0ck;
+
+/* CR29 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR29_IF0MASTER_FS0CK0_INPUT,
+ AB8500_CODEC_CR29_IF0MASTER_FS0CK0_OUTPUT
+} t_ab8500_codec_cr29_if0master;
+
+/* CR29 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR29_IF0BFIFOEN_NORMAL_MODE,
+ AB8500_CODEC_CR29_IF0BFIFOEN_BURST_MODE
+} t_ab8500_codec_cr29_if0bfifoen;
+
+
+/* CR30 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR30_FSYNC1P_RISING_EDGE,
+ AB8500_CODEC_CR30_FSYNC1P_FALLING_EDGE
+} t_ab8500_codec_cr30_fsync1p;
+
+/* CR30 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR30_BITCLK1P_RISING_EDGE,
+ AB8500_CODEC_CR30_BITCLK1P_FALLING_EDGE
+} t_ab8500_codec_cr30_bitclk1p;
+
+/* CR30 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR30_IF1DEL_NOT_DELAYED,
+ AB8500_CODEC_CR30_IF1DEL_DELAYED
+} t_ab8500_codec_cr30_if1del;
+
+/* CR30 - 3:2 */
+typedef enum
+{
+ AB8500_CODEC_CR30_IF1FORMAT_DISABLED,
+ AB8500_CODEC_CR30_IF1FORMAT_TDM,
+ AB8500_CODEC_CR30_IF1FORMAT_I2S_LEFTALIGNED
+} t_ab8500_codec_cr30_if1format;
+
+/* CR30 - 1:0 */
+typedef enum
+{
+ AB8500_CODEC_CR30_IF1WL_16BITS,
+ AB8500_CODEC_CR30_IF1WL_20BITS,
+ AB8500_CODEC_CR30_IF1WL_24BITS,
+ AB8500_CODEC_CR30_IF1WL_32BITS
+} t_ab8500_codec_cr30_if1wl;
+
+
+/* CR31:46 - 7:4 or 3:0 */
+/* In ab8500_codec.h */
+
+
+/* CR47:50 - 7/6/5/4/3/2/1/0 */
+typedef enum
+{
+ AB8500_CODEC_CR47_TO_CR50_HIZ_SL_LOW_IMPEDANCE,
+ AB8500_CODEC_CR47_TO_CR50_HIZ_SL_HIGH_IMPEDANCE,
+} t_ab8500_codec_cr47_to_cr50_hiz_sl;
+
+
+/* CR51 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR51_DA12_VOICE_AUDIOFILTER,
+ AB8500_CODEC_CR51_DA12_VOICE_LOWLATENCYFILTER
+} t_ab8500_codec_cr51_da12_voice;
+
+/* CR51 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR51_SLDAI1TOSLADO1_NOT_LOOPEDBACK,
+ AB8500_CODEC_CR51_SLDAI1TOSLADO1_LOOPEDBACK
+} t_ab8500_codec_cr51_sldai1toslado1;
+
+
+/* CR51:56 - 4:0 */
+/* In ab8500_codec.h */
+
+
+/* CR52 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR52_SLDAI2TOSLADO2_NOT_LOOPEDBACK,
+ AB8500_CODEC_CR52_SLDAI2TOSLADO2_LOOPEDBACK
+} t_ab8500_codec_cr52_sldai2toslado2;
+
+
+/* CR53 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR53_DA34_VOICE_AUDIOFILTER,
+ AB8500_CODEC_CR53_DA34_VOICE_LOWLATENCYFILTER
+} t_ab8500_codec_cr53_da34_voice;
+
+/* CR53 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR53_SLDAI3TOSLADO3_NOT_LOOPEDBACK,
+ AB8500_CODEC_CR53_SLDAI3TOSLADO3_LOOPEDBACK
+} t_ab8500_codec_cr53_sldai3toslado3;
+
+
+/* CR54 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR54_SLDAI4TOSLADO4_NOT_LOOPEDBACK,
+ AB8500_CODEC_CR54_SLDAI4TOSLADO4_LOOPEDBACK
+} t_ab8500_codec_cr54_sldai4toslado4;
+
+
+/* CR55 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR55_DA56_VOICE_AUDIOFILTER,
+ AB8500_CODEC_CR55_DA56_VOICE_LOWLATENCYFILTER
+} t_ab8500_codec_cr55_da56_voice;
+
+/* CR55 - 6:5 */
+typedef enum
+{
+ AB8500_CODEC_CR55_SLDAI5TOSLADO5_NOT_LOOPEDBACK,
+ AB8500_CODEC_CR55_SLDAI5TOSLADO5_DA_IN1_LOOPEDBACK,
+ AB8500_CODEC_CR55_SLDAI5TOSLADO5_DA_IN3_LOOPEDBACK,
+ AB8500_CODEC_CR55_SLDAI5TOSLADO5_DA_IN5_LOOPEDBACK
+} t_ab8500_codec_cr55_sldai5toslado5;
+
+
+/* CR56 - 6:5 */
+typedef enum
+{
+ AB8500_CODEC_CR56_SLDAI6TOSLADO7_NOT_LOOPEDBACK,
+ AB8500_CODEC_CR56_SLDAI6TOSLADO7_DA_IN2_LOOPEDBACK,
+ AB8500_CODEC_CR56_SLDAI6TOSLADO7_DA_IN4_LOOPEDBACK,
+ AB8500_CODEC_CR56_SLDAI6TOSLADO7_DA_IN6_LOOPEDBACK
+} t_ab8500_codec_cr56_sldai6toslado7;
+
+
+/* CR57 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR57_BFIFULL_MSK_MASKED,
+ AB8500_CODEC_CR57_BFIFULL_MSK_ENABLED
+} t_ab8500_codec_cr57_bfifull_msk;
+
+/* CR57 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR57_BFIEMPT_MSK_MASKED,
+ AB8500_CODEC_CR57_BFIEMPT_MSK_ENABLED
+} t_ab8500_codec_cr57_bfiempt_msk;
+
+/* CR57 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR57_DACHAN_MSK_MASKED,
+ AB8500_CODEC_CR57_DACHAN_MSK_ENABLED
+} t_ab8500_codec_cr57_dachan_msk;
+
+/* CR57 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR57_GAIN_MSK_MASKED,
+ AB8500_CODEC_CR57_GAIN_MSK_ENABLED
+} t_ab8500_codec_cr57_gain_msk;
+
+/* CR57 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR57_DSPAD_MSK_MASKED,
+ AB8500_CODEC_CR57_DSPAD_MSK_ENABLED
+} t_ab8500_codec_cr57_dspad_msk;
+
+/* CR57 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR57_DSPDA_MSK_MASKED,
+ AB8500_CODEC_CR57_DSPDA_MSK_ENABLED
+} t_ab8500_codec_cr57_dspda_msk;
+
+/* CR57 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR57_STFIR_MSK_MASKED,
+ AB8500_CODEC_CR57_STFIR_MSK_ENABLED
+} t_ab8500_codec_cr57_stfir_msk;
+
+
+/* CR58 - Read Only */
+/* CR58 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR58_BFIFULL_EV_NOT_FULL,
+ AB8500_CODEC_CR58_BFIFULL_EV_FULL
+} t_ab8500_codec_cr58_bfifull_ev;
+
+/* CR58 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR58_BFIEMPT_EV_NOT_EMPTY,
+ AB8500_CODEC_CR58_BFIEMPT_EV_EMPTY
+} t_ab8500_codec_cr58_bfiempt_ev;
+
+/* CR58 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR58_DACHAN_EV_NO_SATURATION,
+ AB8500_CODEC_CR58_DACHAN_EV_SATURATION
+} t_ab8500_codec_cr58_dachan_ev;
+
+/* CR58 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR58_GAIN_EV_NO_SATURATION,
+ AB8500_CODEC_CR58_GAIN_EV_SATURATION
+} t_ab8500_codec_cr58_gain_ev;
+
+/* CR58 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR58_DSPAD_EV_NO_SATURATION,
+ AB8500_CODEC_CR58_DSPAD_EV_SATURATION
+} t_ab8500_codec_cr58_dspad_ev;
+
+/* CR58 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR58_DSPDA_EV_NO_SATURATION,
+ AB8500_CODEC_CR58_DSPDA_EV_SATURATION
+} t_ab8500_codec_cr58_dspda_ev;
+
+/* CR58 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR58_STFIR_EV_NO_SATURATION,
+ AB8500_CODEC_CR58_STFIR_EV_SATURATION
+} t_ab8500_codec_cr58_stfir_ev;
+
+
+/* CR59 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR59_VSSREADY_MSK_MASKED,
+ AB8500_CODEC_CR59_VSSREADY_MSK_ENABLED
+} t_ab8500_codec_cr59_vssready_msk;
+
+/* CR59 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR59_SHRTVIBL_MSK_MASKED,
+ AB8500_CODEC_CR59_SHRTVIBL_MSK_ENABLED
+} t_ab8500_codec_cr59_shrtvibl_msk;
+
+/* CR59 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR59_SHRTVIBR_MSK_MASKED,
+ AB8500_CODEC_CR59_SHRTVIBR_MSK_ENABLED
+} t_ab8500_codec_cr59_shrtvibr_msk;
+
+/* CR59 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR59_SHRTHFL_MSK_MASKED,
+ AB8500_CODEC_CR59_SHRTHFL_MSK_ENABLED
+} t_ab8500_codec_cr59_shrthfl_msk;
+
+/* CR59 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR59_SHRTHFR_MSK_MASKED,
+ AB8500_CODEC_CR59_SHRTHFR_MSK_ENABLED
+} t_ab8500_codec_cr59_shrthfr_msk;
+
+/* CR59 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR59_SHRTHSL_MSK_MASKED,
+ AB8500_CODEC_CR59_SHRTHSL_MSK_ENABLED
+} t_ab8500_codec_cr59_shrthsl_msk;
+
+/* CR59 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR59_SHRTHSR_MSK_MASKED,
+ AB8500_CODEC_CR59_SHRTHSR_MSK_ENABLED
+} t_ab8500_codec_cr59_shrthsr_msk;
+
+/* CR59 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR59_SHRTEAR_MSK_MASKED,
+ AB8500_CODEC_CR59_SHRTEAR_MSK_ENABLED
+} t_ab8500_codec_cr59_shrtear_msk;
+
+
+/* CR60 - Read Only */
+/* CR60 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR60_VSSREADY_EV_NOT_READY,
+ AB8500_CODEC_CR60_VSSREADY_EV_READY
+} t_ab8500_codec_cr60_vssready_ev;
+
+/* CR60 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR60_SHRTVIBL_EV_NO_SHORTCIRCUIT,
+ AB8500_CODEC_CR60_SHRTVIBL_EV_SHORTCIRCUIT
+} t_ab8500_codec_cr60_shrtvibl_ev;
+
+/* CR60 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR60_SHRTVIBR_EV_NO_SHORTCIRCUIT,
+ AB8500_CODEC_CR60_SHRTVIBR_EV_SHORTCIRCUIT
+} t_ab8500_codec_cr60_shrtvibr_ev;
+
+/* CR60 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR60_SHRTHFL_EV_NO_SHORTCIRCUIT,
+ AB8500_CODEC_CR60_SHRTHFL_EV_SHORTCIRCUIT
+} t_ab8500_codec_cr60_shrthfl_ev;
+
+/* CR60 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR60_SHRTHFR_EV_NO_SHORTCIRCUIT,
+ AB8500_CODEC_CR60_SHRTHFR_EV_SHORTCIRCUIT
+} t_ab8500_codec_cr60_shrthfr_ev;
+
+/* CR60 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR60_SHRTHSL_EV_NO_SHORTCIRCUIT,
+ AB8500_CODEC_CR60_SHRTHSL_EV_SHORTCIRCUIT
+} t_ab8500_codec_cr60_shrthsl_ev;
+
+/* CR60 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR60_SHRTHSR_EV_NO_SHORTCIRCUIT,
+ AB8500_CODEC_CR60_SHRTHSR_EV_SHORTCIRCUIT
+} t_ab8500_codec_cr60_shrthsr_ev;
+
+/* CR60 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR60_SHRTEAR_EV_NO_SHORTCIRCUIT,
+ AB8500_CODEC_CR60_SHRTEAR_EV_SHORTCIRCUIT
+} t_ab8500_codec_cr60_shrtear_ev;
+
+
+/* CR61 - 6:2 - Read Only */
+typedef enum
+{
+ AB8500_CODEC_CR61_REVISION_1_0,
+ AB8500_CODEC_CR61_REVISION_TBD
+} t_ab8500_codec_cr61_revision;
+
+/* CR61 - 1:0 */
+typedef enum
+{
+ AB8500_CODEC_CR61_FADE_SPEED_1MS,
+ AB8500_CODEC_CR61_FADE_SPEED_4MS,
+ AB8500_CODEC_CR61_FADE_SPEED_8MS,
+ AB8500_CODEC_CR61_FADE_SPEED_16MS
+} t_ab8500_codec_cr61_fade_speed;
+
+
+/* CR62 - Read Only */
+/* CR62 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR62_DMIC1SINC3_SINC5_SELECTED,
+ AB8500_CODEC_CR62_DMIC1SINC3_SINC3_SELECTED
+} t_ab8500_codec_cr62_dmic1sinc3;
+
+/* CR62 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR62_DMIC2SINC3_SINC5_SELECTED,
+ AB8500_CODEC_CR62_DMIC2SINC3_SINC3_SELECTED
+} t_ab8500_codec_cr62_dmic2sinc3;
+
+/* CR62 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR62_DMIC3SINC3_SINC5_SELECTED,
+ AB8500_CODEC_CR62_DMIC3SINC3_SINC3_SELECTED
+} t_ab8500_codec_cr62_dmic3sinc3;
+
+/* CR62 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR62_DMIC4SINC3_SINC5_SELECTED,
+ AB8500_CODEC_CR62_DMIC4SINC3_SINC3_SELECTED
+} t_ab8500_codec_cr62_dmic4sinc3;
+
+/* CR62 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR62_DMIC5SINC3_SINC5_SELECTED,
+ AB8500_CODEC_CR62_DMIC5SINC3_SINC3_SELECTED
+} t_ab8500_codec_cr62_dmic5sinc3;
+
+/* CR62 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR62_DMIC6SINC3_SINC5_SELECTED,
+ AB8500_CODEC_CR62_DMIC6SINC3_SINC3_SELECTED
+} t_ab8500_codec_cr62_dmic6sinc3;
+
+
+/* CR63 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR63_DATOHSLEN_DISABLED,
+ AB8500_CODEC_CR63_DATOHSLEN_ENABLED
+} t_ab8500_codec_cr63_datohslen;
+
+/* CR63 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR63_DATOHSREN_DISABLED,
+ AB8500_CODEC_CR63_DATOHSREN_ENABLED
+} t_ab8500_codec_cr63_datohsren;
+
+/* CR63 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR63_AD1SEL_LINLADL_SELECTED,
+ AB8500_CODEC_CR63_AD1SEL_DMIC1_SELECTED
+} t_ab8500_codec_cr63_ad1sel;
+
+/* CR63 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR63_AD2SEL_LINRADR_SELECTED,
+ AB8500_CODEC_CR63_AD2SEL_DMIC2_SELECTED
+} t_ab8500_codec_cr63_ad2sel;
+
+/* CR63 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR63_AD3SEL_ADMO_SELECTED,
+ AB8500_CODEC_CR63_AD3SEL_DMIC3_SELECTED
+} t_ab8500_codec_cr63_ad3sel;
+
+/* CR63 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR63_AD5SEL_AMADR_SELECTED,
+ AB8500_CODEC_CR63_AD5SEL_DMIC5_SELECTED
+} t_ab8500_codec_cr63_ad5sel;
+
+/* CR63 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR63_AD6SEL_ADMO_SELECTED,
+ AB8500_CODEC_CR63_AD6SEL_DMIC6_SELECTED
+} t_ab8500_codec_cr63_ad6sel;
+
+/* CR63 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR63_ANCSEL_NOT_MIXED_IN_EAR,
+ AB8500_CODEC_CR63_ANCSEL_MIXED_IN_EAR
+} t_ab8500_codec_cr63_ancsel;
+
+
+/* CR64 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR64_DATOHFREN_NOT_MIXED_TO_HFR,
+ AB8500_CODEC_CR64_DATOHFREN_MIXED_TO_HFR
+} t_ab8500_codec_cr64_datohfren;
+
+/* CR64 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR64_DATOHFLEN_NOT_MIXED_TO_HFL,
+ AB8500_CODEC_CR64_DATOHFLEN_MIXED_TO_HFL
+} t_ab8500_codec_cr64_datohflen;
+
+/* CR64 - 5 */
+typedef enum
+{
+ AB8500_CODEC_CR64_HFRSEL_DA4_MIXED_TO_HFR,
+ AB8500_CODEC_CR64_HFRSEL_ANC_MIXED_TO_HFR
+} t_ab8500_codec_cr64_hfrsel;
+
+/* CR64 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR64_HFLSEL_DA3_MIXED_TO_HFL,
+ AB8500_CODEC_CR64_HFLSEL_ANC_MIXED_TO_HFL
+} t_ab8500_codec_cr64_hflsel;
+
+/* CR64 - 3:2 */
+typedef enum
+{
+ AB8500_CODEC_CR64_STFIR1SEL_AD_OUT1_SELECTED,
+ AB8500_CODEC_CR64_STFIR1SEL_AD_OUT3_SELECTED,
+ AB8500_CODEC_CR64_STFIR1SEL_DA_IN1_SELECTED
+} t_ab8500_codec_cr64_stfir1sel;
+
+/* CR64 - 1:0 */
+typedef enum
+{
+ AB8500_CODEC_CR64_STFIR2SEL_AD_OUT2_SELECTED,
+ AB8500_CODEC_CR64_STFIR2SEL_AD_OUT4_SELECTED,
+ AB8500_CODEC_CR64_STFIR2SEL_DA_IN2_SELECTED
+} t_ab8500_codec_cr64_stfir2sel;
+
+
+/* CR65 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR65_FADEDIS_AD1_ENABLED,
+ AB8500_CODEC_CR65_FADEDIS_AD1_DISABLED
+} t_ab8500_codec_cr65_fadedis_ad1;
+
+/* CR65 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr65_ad1gain;
+
+
+/* CR66 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR66_FADEDIS_AD2_ENABLED,
+ AB8500_CODEC_CR66_FADEDIS_AD2_DISABLED
+} t_ab8500_codec_cr66_fadedis_ad2;
+
+/* CR66 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr66_ad2gain;
+
+
+/* CR67 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR67_FADEDIS_AD3_ENABLED,
+ AB8500_CODEC_CR67_FADEDIS_AD3_DISABLED
+} t_ab8500_codec_cr67_fadedis_ad3;
+
+/* CR67 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr67_ad3gain;
+
+
+/* CR68 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR68_FADEDIS_AD4_ENABLED,
+ AB8500_CODEC_CR68_FADEDIS_AD4_DISABLED
+} t_ab8500_codec_cr68_fadedis_ad4;
+
+/* CR68 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr68_ad4gain;
+
+
+/* CR69 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR69_FADEDIS_AD5_ENABLED,
+ AB8500_CODEC_CR69_FADEDIS_AD5_DISABLED
+} t_ab8500_codec_cr69_fadedis_ad5;
+
+/* CR69 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr69_ad5gain;
+
+
+/* CR70 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR70_FADEDIS_AD6_ENABLED,
+ AB8500_CODEC_CR70_FADEDIS_AD6_DISABLED
+} t_ab8500_codec_cr70_fadedis_ad6;
+
+/* CR70 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr70_ad6gain;
+
+
+/* CR71 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR71_FADEDIS_DA1_ENABLED,
+ AB8500_CODEC_CR71_FADEDIS_DA1_DISABLED
+} t_ab8500_codec_cr71_fadedis_da1;
+
+/* CR71 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr71_da1gain;
+
+
+/* CR72 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR72_FADEDIS_DA2_ENABLED,
+ AB8500_CODEC_CR72_FADEDIS_DA2_DISABLED
+} t_ab8500_codec_cr72_fadedis_da2;
+
+/* CR72 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr72_da2gain;
+
+
+/* CR73 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR73_FADEDIS_DA3_ENABLED,
+ AB8500_CODEC_CR73_FADEDIS_DA3_DISABLED
+} t_ab8500_codec_cr73_fadedis_da3;
+
+/* CR73 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr73_da3gain;
+
+
+/* CR74 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR74_FADEDIS_DA4_ENABLED,
+ AB8500_CODEC_CR74_FADEDIS_DA4_DISABLED
+} t_ab8500_codec_cr74_fadedis_da4;
+
+/* CR74 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr74_da4gain;
+
+
+/* CR75 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR75_FADEDIS_DA5_ENABLED,
+ AB8500_CODEC_CR75_FADEDIS_DA5_DISABLED
+} t_ab8500_codec_cr75_fadedis_da5;
+
+/* CR75 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr75_da5gain;
+
+
+/* CR76 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR76_FADEDIS_DA6_ENABLED,
+ AB8500_CODEC_CR76_FADEDIS_DA6_DISABLED
+} t_ab8500_codec_cr76_fadedis_da6;
+
+/* CR76 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr76_da6gain;
+
+
+/* CR77 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR77_FADEDIS_AD1L_TO_HFL_ENABLED,
+ AB8500_CODEC_CR77_FADEDIS_AD1L_TO_HFL_DISABLED
+} t_ab8500_codec_cr77_fadedis_ad1l;
+
+/* CR77 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr77_ad1lbgain_to_hfl;
+
+
+/* CR78 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR78_FADEDIS_AD2L_TO_HFR_ENABLED,
+ AB8500_CODEC_CR78_FADEDIS_AD2L_TO_HFR_DISABLED
+} t_ab8500_codec_cr78_fadedis_ad2l;
+
+/* CR78 - 5:0 */
+typedef t_uint8 t_ab8500_codec_cr78_ad2lbgain_to_hfr;
+
+
+/* CR79 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR79_HSSINC1_SINC3_CHOOSEN,
+ AB8500_CODEC_CR79_HSSINC1_SINC1_CHOOSEN
+} t_ab8500_codec_cr79_hssinc1;
+
+/* CR79 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR79_FADEDIS_HSL_ENABLED,
+ AB8500_CODEC_CR79_FADEDIS_HSL_DISABLED
+} t_ab8500_codec_cr79_fadedis_hsl;
+
+/* CR79 - 3:0 */
+typedef t_uint8 t_ab8500_codec_cr79_hsldgain;
+
+
+/* CR80 - 4 */
+typedef enum
+{
+ AB8500_CODEC_CR80_FADEDIS_HSR_ENABLED,
+ AB8500_CODEC_CR80_FADEDIS_HSR_DISABLED
+} t_ab8500_codec_cr80_fadedis_hsr;
+
+/* CR80 - 3:0 */
+typedef t_uint8 t_ab8500_codec_cr80_hsrdgain;
+
+
+/* CR81 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr81_stfir1gain;
+
+
+/* CR82 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr82_stfir2gain;
+
+
+/* CR83 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR83_ENANC_DISABLED,
+ AB8500_CODEC_CR83_ENANC_ENABLED
+} t_ab8500_codec_cr83_enanc;
+
+/* CR83 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR83_ANCIIRINIT_NOT_STARTED,
+ AB8500_CODEC_CR83_ANCIIRINIT_STARTED
+} t_ab8500_codec_cr83_anciirinit;
+
+/* CR83 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR83_ANCFIRUPDATE_RESETTED,
+ AB8500_CODEC_CR83_ANCFIRUPDATE_NOT_RESETTED
+} t_ab8500_codec_cr83_ancfirupdate;
+
+
+/* CR84 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr84_ancinshift;
+
+
+/* CR85 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr85_ancfiroutshift;
+
+
+/* CR86 - 4:0 */
+typedef t_uint8 t_ab8500_codec_cr86_ancshiftout;
+
+
+/* CR87 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr87_ancfircoeff_msb;
+
+
+/* CR88 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr88_ancfircoeff_lsb;
+
+
+/* CR89 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr89_anciircoeff_msb;
+
+
+/* CR90 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr90_anciircoeff_lsb;
+
+
+/* CR91 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr91_ancwarpdel_msb;
+
+
+/* CR92 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr92_ancwarpdel_lsb;
+
+
+/* CR93 - Read Only */
+/* CR93 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr93_ancfirpeak_msb;
+
+
+/* CR94 - Read Only */
+/* CR94 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr94_ancfirpeak_lsb;
+
+
+/* CR95 - Read Only */
+/* CR95 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr95_anciirpeak_msb;
+
+
+/* CR96 - Read Only */
+/* CR96 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr96_anciirpeak_lsb;
+
+
+/* CR97 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR97_STFIR_SET_LAST_NOT_APPLIED,
+ AB8500_CODEC_CR97_STFIR_SET_LAST_APPLIED
+} t_ab8500_codec_cr97_stfir_set;
+
+/* CR97 - 6:0 */
+typedef t_uint8 t_ab8500_codec_cr97_stfir_addr;
+
+
+/* CR98 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr98_stfir_coeff_msb;
+
+
+/* CR99 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr99_stfir_coeff_lsb;
+
+
+/* CR100 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR100_ENSTFIRS_DISABLED,
+ AB8500_CODEC_CR100_ENSTFIRS_ENABLED
+} t_ab8500_codec_cr100_enstfirs;
+
+/* CR100 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR100_STFIRSTOIF1_AUD_IF0_DATA_RATE,
+ AB8500_CODEC_CR100_STFIRSTOIF1_AUD_IF1_DATA_RATE
+} t_ab8500_codec_cr100_stfirstoif1;
+
+/* CR100 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR100_STFIR_BUSY_READY,
+ AB8500_CODEC_CR100_STFIR_BUSY_NOT_READY
+} t_ab8500_codec_cr100_stfir_busy;
+
+
+/* CR101 - 7 */
+typedef enum
+{
+ AB8500_CODEC_CR101_PARLHF_INDEPENDENT,
+ AB8500_CODEC_CR101_PARLHF_BRIDGED
+} t_ab8500_codec_cr101_parlhf;
+
+/* CR101 - 6 */
+typedef enum
+{
+ AB8500_CODEC_CR101_PARLVIB_INDEPENDENT,
+ AB8500_CODEC_CR101_PARLVIB_BRIDGED
+} t_ab8500_codec_cr101_parlvib;
+
+/* CR101 - 3 */
+typedef enum
+{
+ AB8500_CODEC_CR101_CLASSD_VIBLSWAPEN_DISABLED,
+ AB8500_CODEC_CR101_CLASSD_VIBLSWAPEN_ENABLED
+} t_ab8500_codec_cr101_classd_viblswapen;
+
+/* CR101 - 2 */
+typedef enum
+{
+ AB8500_CODEC_CR101_CLASSD_VIBRSWAPEN_DISABLED,
+ AB8500_CODEC_CR101_CLASSD_VIBRSWAPEN_ENABLED
+} t_ab8500_codec_cr101_classd_vibrswapen;
+
+/* CR101 - 1 */
+typedef enum
+{
+ AB8500_CODEC_CR101_CLASSD_HFLSWAPEN_DISABLED,
+ AB8500_CODEC_CR101_CLASSD_HFLSWAPEN_ENABLED
+} t_ab8500_codec_cr101_classd_hflswapen;
+
+/* CR101 - 0 */
+typedef enum
+{
+ AB8500_CODEC_CR101_CLASSD_HFRSWAPEN_DISABLED,
+ AB8500_CODEC_CR101_CLASSD_HFRSWAPEN_ENABLED
+} t_ab8500_codec_cr101_classd_hfrswapen;
+
+
+/* CR102 - 7:4 */
+typedef enum
+{
+ AB8500_CODEC_CR102_CLASSD_FIRBYP_ALL_ENABLED = 0,
+ AB8500_CODEC_CR102_CLASSD_FIRBYP_HFL_BYPASSED = 1,
+ AB8500_CODEC_CR102_CLASSD_FIRBYP_HFR_BYPASSED = 2,
+ AB8500_CODEC_CR102_CLASSD_FIRBYP_VIBL_BYPASSED = 4,
+ AB8500_CODEC_CR102_CLASSD_FIRBYP_VIBR_BYPASSED = 8
+} t_ab8500_codec_cr102_classd_firbyp;
+
+/* CR102 - 3:0 */
+typedef enum
+{
+ AB8500_CODEC_CR102_CLASSD_HIGHVOLEN_DISABLED = 0,
+ AB8500_CODEC_CR102_CLASSD_HIGHVOLEN_HFL_HIGHVOL = 1,
+ AB8500_CODEC_CR102_CLASSD_HIGHVOLEN_HFR_HIGHVOL = 2,
+ AB8500_CODEC_CR102_CLASSD_HIGHVOLEN_VIBL_HIGHVOL = 4,
+ AB8500_CODEC_CR102_CLASSD_HIGHVOLEN_VIBR_HIGHVOL = 8
+} t_ab8500_codec_cr102_classd_highvolen;
+
+
+/* CR103 - 7:4 */
+typedef t_uint8 t_ab8500_codec_cr103_classd_ditherhpgain;
+
+/* CR103 - 3:0 */
+typedef t_uint8 t_ab8500_codec_cr103_classd_ditherwgain;
+
+
+/* CR104 - 5:0 */
+/* In ab8500_codec.h */
+
+
+/* CR105 - 7:0 */
+/* In ab8500_codec.h */
+
+
+/* CR106 - 6:4 */
+/* In ab8500_codec.h */
+
+
+/* CR106 - 2 */
+/* In ab8500_codec.h */
+
+
+/* CR106 - 1 */
+/* In ab8500_codec.h */
+
+
+/* CR106 - 0 */
+/* In ab8500_codec.h */
+
+
+/* CR107 - 7:0 */
+/* In ab8500_codec.h */
+
+
+/* CR108 - 7:0 */
+/* In ab8500_codec.h */
+
+
+/* CR109 - Read Only */
+/* CR109 - 7:0 */
+typedef t_uint8 t_ab8500_codec_cr109_bfifosamples;
+
+
+
+/*configuration structure for AB8500 Codec*/
+typedef struct
+{
+ /* CR0 */
+ t_ab8500_codec_cr0_powerup cr0_powerup;
+ t_ab8500_codec_cr0_enaana cr0_enaana;
+
+ /* CR1 */
+ t_ab8500_codec_cr1_swreset cr1_swreset;
+
+ /* CR2 */
+ t_ab8500_codec_cr2_enad1 cr2_enad1;
+ t_ab8500_codec_cr2_enad2 cr2_enad2;
+ t_ab8500_codec_cr2_enad3 cr2_enad3;
+ t_ab8500_codec_cr2_enad4 cr2_enad4;
+ t_ab8500_codec_cr2_enad5 cr2_enad5;
+ t_ab8500_codec_cr2_enad6 cr2_enad6;
+
+ /* CR3 */
+ t_ab8500_codec_cr3_enda1 cr3_enda1;
+ t_ab8500_codec_cr3_enda2 cr3_enda2;
+ t_ab8500_codec_cr3_enda3 cr3_enda3;
+ t_ab8500_codec_cr3_enda4 cr3_enda4;
+ t_ab8500_codec_cr3_enda5 cr3_enda5;
+ t_ab8500_codec_cr3_enda6 cr3_enda6;
+
+ /* CR4 */
+ t_ab8500_codec_cr4_lowpowhs cr4_lowpowhs;
+ t_ab8500_codec_cr4_lowpowdachs cr4_lowpowdachs;
+ t_ab8500_codec_cr4_lowpowear cr4_lowpowear;
+ t_ab8500_codec_cr4_ear_sel_cm cr4_ear_sel_cm;
+ t_ab8500_codec_cr4_hs_hp_dis cr4_hs_hp_dis;
+ t_ab8500_codec_cr4_ear_hp_dis cr4_ear_hp_dis;
+
+ /* CR5 */
+ t_ab8500_codec_cr5_enmic1 cr5_enmic1;
+ t_ab8500_codec_cr5_enmic2 cr5_enmic2;
+ t_ab8500_codec_cr5_enlinl cr5_enlinl;
+ t_ab8500_codec_cr5_enlinr cr5_enlinr;
+ t_ab8500_codec_cr5_mutmic1 cr5_mutmic1;
+ t_ab8500_codec_cr5_mutmic2 cr5_mutmic2;
+ t_ab8500_codec_cr5_mutlinl cr5_mutlinl;
+ t_ab8500_codec_cr5_mutlinr cr5_mutlinr;
+
+ /* CR6 */
+ t_ab8500_codec_cr6_endmic1 cr6_endmic1;
+ t_ab8500_codec_cr6_endmic2 cr6_endmic2;
+ t_ab8500_codec_cr6_endmic3 cr6_endmic3;
+ t_ab8500_codec_cr6_endmic4 cr6_endmic4;
+ t_ab8500_codec_cr6_endmic5 cr6_endmic5;
+ t_ab8500_codec_cr6_endmic6 cr6_endmic6;
+
+ /* CR7 */
+ t_ab8500_codec_cr7_mic1sel cr7_mic1sel;
+ t_ab8500_codec_cr7_linrsel cr7_linrsel;
+ t_ab8500_codec_cr7_endrvhsl cr7_endrvhsl;
+ t_ab8500_codec_cr7_endrvhsr cr7_endrvhsr;
+ t_ab8500_codec_cr7_enadcmic cr7_enadcmic;
+ t_ab8500_codec_cr7_enadclinl cr7_enadclinl;
+ t_ab8500_codec_cr7_enadclinr cr7_enadclinr;
+
+ /* CR8 */
+ t_ab8500_codec_cr8_cp_dis_pldwn cr8_cp_dis_pldwn;
+ t_ab8500_codec_cr8_enear cr8_enear;
+ t_ab8500_codec_cr8_enhsl cr8_enhsl;
+ t_ab8500_codec_cr8_enhsr cr8_enhsr;
+ t_ab8500_codec_cr8_enhfl cr8_enhfl;
+ t_ab8500_codec_cr8_enhfr cr8_enhfr;
+ t_ab8500_codec_cr8_envibl cr8_envibl;
+ t_ab8500_codec_cr8_envibr cr8_envibr;
+
+ /* CR9 */
+ t_ab8500_codec_cr9_endacear cr9_endacear;
+ t_ab8500_codec_cr9_endachsl cr9_endachsl;
+ t_ab8500_codec_cr9_endachsr cr9_endachsr;
+ t_ab8500_codec_cr9_endachfl cr9_endachfl;
+ t_ab8500_codec_cr9_endachfr cr9_endachfr;
+ t_ab8500_codec_cr9_endacvibl cr9_endacvibl;
+ t_ab8500_codec_cr9_endacvibr cr9_endacvibr;
+
+ /* CR10 */
+ t_ab8500_codec_cr10_muteear cr10_muteear;
+ t_ab8500_codec_cr10_mutehsl cr10_mutehsl;
+ t_ab8500_codec_cr10_mutehsr cr10_mutehsr;
+ t_ab8500_codec_cr10_mutehfl cr10_mutehfl;
+ t_ab8500_codec_cr10_mutehfr cr10_mutehfr;
+ t_ab8500_codec_cr10_mutevibl cr10_mutevibl;
+ t_ab8500_codec_cr10_mutevibr cr10_mutevibr;
+
+ /* CR11 */
+ t_ab8500_codec_cr11_earshortpwd cr11_earshortpwd;
+ t_ab8500_codec_cr11_earshortdis cr11_earshortdis;
+ t_ab8500_codec_cr11_hslshortdis cr11_hslshortdis;
+ t_ab8500_codec_cr11_hsrshortdis cr11_hsrshortdis;
+ t_ab8500_codec_cr11_hflshortdis cr11_hflshortdis;
+ t_ab8500_codec_cr11_hfrshortdis cr11_hfrshortdis;
+ t_ab8500_codec_cr11_viblshortdis cr11_viblshortdis;
+ t_ab8500_codec_cr11_vibrshortdis cr11_vibrshortdis;
+
+ /* CR12 */
+ t_ab8500_codec_cr12_encphs cr12_encphs;
+ t_ab8500_codec_cr12_hsautotime cr12_hsautotime;
+ t_ab8500_codec_cr12_hsautoensel cr12_hsautoensel;
+ t_ab8500_codec_cr12_hsautoen cr12_hsautoen;
+
+ /* CR13 */
+ t_ab8500_codec_cr13_envdet_hthresh cr13_envdet_hthresh;
+ t_ab8500_codec_cr13_envdet_lthresh cr13_envdet_lthresh;
+
+ /* CR14 */
+ t_ab8500_codec_cr14_smpslven cr14_smpslven;
+ t_ab8500_codec_cr14_envdetsmpsen cr14_envdetsmpsen;
+ t_ab8500_codec_cr14_cplven cr14_cplven;
+ t_ab8500_codec_cr14_envdetcpen cr14_envdetcpen;
+ t_ab8500_codec_cr14_envet_time cr14_envet_time;
+
+
+ /* CR15 */
+ t_ab8500_codec_cr15_pwmtovibl cr15_pwmtovibl;
+ t_ab8500_codec_cr15_pwmtovibr cr15_pwmtovibr;
+ t_ab8500_codec_cr15_pwmlctrl cr15_pwmlctrl;
+ t_ab8500_codec_cr15_pwmrctrl cr15_pwmrctrl;
+ t_ab8500_codec_cr15_pwmnlctrl cr15_pwmnlctrl;
+ t_ab8500_codec_cr15_pwmplctrl cr15_pwmplctrl;
+ t_ab8500_codec_cr15_pwmnrctrl cr15_pwmnrctrl;
+ t_ab8500_codec_cr15_pwmprctrl cr15_pwmprctrl;
+
+
+ /* CR16 */
+ t_ab8500_codec_cr16_pwmnlpol cr16_pwmnlpol;
+ t_ab8500_codec_cr16_pwmnldutycycle cr16_pwmnldutycycle;
+
+
+ /* CR17 */
+ t_ab8500_codec_cr17_pwmplpol cr17_pwmplpol;
+ t_ab8500_codec_cr17_pwmpldutycycle cr17_pwmpldutycycle;
+
+
+ /* CR18 */
+ t_ab8500_codec_cr18_pwmnrpol cr18_pwmnrpol;
+ t_ab8500_codec_cr18_pwmnrdutycycle cr18_pwmnrdutycycle;
+
+
+ /* CR19 */
+ t_ab8500_codec_cr19_pwmprpol cr19_pwmprpol;
+ t_ab8500_codec_cr19_pwmprdutycycle cr19_pwmprdutycycle;
+
+
+ /* CR20 */
+ t_ab8500_codec_cr20_en_se_mic1 cr20_en_se_mic1;
+ t_ab8500_codec_cr20_mic1_gain cr20_mic1_gain;
+
+
+ /* CR21 */
+ t_ab8500_codec_cr21_en_se_mic2 cr21_en_se_mic2;
+ t_ab8500_codec_cr21_mic2_gain cr21_mic2_gain;
+
+
+ /* CR22 */
+ t_ab8500_codec_cr22_hsl_gain cr22_hsl_gain;
+ t_ab8500_codec_cr22_linl_gain cr22_linl_gain;
+
+
+ /* CR23 */
+ t_ab8500_codec_cr23_hsr_gain cr23_hsr_gain;
+ t_ab8500_codec_cr23_linr_gain cr23_linr_gain;
+
+
+ /* CR24 */
+ t_ab8500_codec_cr24_lintohsl_gain cr24_lintohsl_gain;
+
+
+ /* CR25 */
+ t_ab8500_codec_cr25_lintohsr_gain cr25_lintohsr_gain;
+
+
+ /* CR26 */
+ t_ab8500_codec_cr26_ad1nh cr26_ad1nh;
+ t_ab8500_codec_cr26_ad2nh cr26_ad2nh;
+ t_ab8500_codec_cr26_ad3nh cr26_ad3nh;
+ t_ab8500_codec_cr26_ad4nh cr26_ad4nh;
+ t_ab8500_codec_cr26_ad1_voice cr26_ad1_voice;
+ t_ab8500_codec_cr26_ad2_voice cr26_ad2_voice;
+ t_ab8500_codec_cr26_ad3_voice cr26_ad3_voice;
+ t_ab8500_codec_cr26_ad4_voice cr26_ad4_voice;
+
+
+ /* CR27 */
+ t_ab8500_codec_cr27_en_mastgen cr27_en_mastgen;
+ t_ab8500_codec_cr27_if1_bitclk_osr cr27_if1_bitclk_osr;
+ t_ab8500_codec_cr27_enfs_bitclk1 cr27_enfs_bitclk1;
+ t_ab8500_codec_cr27_if0_bitclk_osr cr27_if0_bitclk_osr;
+ t_ab8500_codec_cr27_enfs_bitclk0 cr27_enfs_bitclk0;
+
+ /* CR28 */
+ t_ab8500_codec_cr28_fsync0p cr28_fsync0p;
+ t_ab8500_codec_cr28_bitclk0p cr28_bitclk0p;
+ t_ab8500_codec_cr28_if0del cr28_if0del;
+ t_ab8500_codec_cr28_if0format cr28_if0format;
+ t_ab8500_codec_cr28_if0wl cr28_if0wl;
+
+
+ /* CR29 */
+ t_ab8500_codec_cr29_if0datoif1ad cr29_if0datoif1ad;
+ t_ab8500_codec_cr29_if0cktoif1ck cr29_if0cktoif1ck;
+ t_ab8500_codec_cr29_if1master cr29_if1master;
+ t_ab8500_codec_cr29_if1datoif0ad cr29_if1datoif0ad;
+ t_ab8500_codec_cr29_if1cktoif0ck cr29_if1cktoif0ck;
+ t_ab8500_codec_cr29_if0master cr29_if0master;
+ t_ab8500_codec_cr29_if0bfifoen cr29_if0bfifoen;
+
+
+ /* CR30 */
+ t_ab8500_codec_cr30_fsync1p cr30_fsync1p;
+ t_ab8500_codec_cr30_bitclk1p cr30_bitclk1p;
+ t_ab8500_codec_cr30_if1del cr30_if1del;
+ t_ab8500_codec_cr30_if1format cr30_if1format;
+ t_ab8500_codec_cr30_if1wl cr30_if1wl;
+
+
+ /* CR31 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr31_adotoslot1;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr31_adotoslot0;
+
+
+ /* CR32 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr32_adotoslot3;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr32_adotoslot2;
+
+
+ /* CR33 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr33_adotoslot5;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr33_adotoslot4;
+
+
+ /* CR34 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr34_adotoslot7;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr34_adotoslot6;
+
+
+ /* CR35 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr35_adotoslot9;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr35_adotoslot8;
+
+
+ /* CR36 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr36_adotoslot11;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr36_adotoslot10;
+
+
+ /* CR37 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr37_adotoslot13;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr37_adotoslot12;
+
+
+ /* CR38 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr38_adotoslot15;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr38_adotoslot14;
+
+
+ /* CR39 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr39_adotoslot17;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr39_adotoslot16;
+
+
+ /* CR40 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr40_adotoslot19;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr40_adotoslot18;
+
+
+ /* CR41 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr41_adotoslot21;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr41_adotoslot20;
+
+
+ /* CR42 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr42_adotoslot23;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr42_adotoslot22;
+
+
+ /* CR43 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr43_adotoslot25;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr43_adotoslot24;
+
+
+ /* CR44 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr44_adotoslot27;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr44_adotoslot26;
+
+
+ /* CR45 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr45_adotoslot29;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr45_adotoslot28;
+
+
+ /* CR46 */
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr46_adotoslot31;
+ t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr46_adotoslot30;
+
+
+ /* CR47 */
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl7;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl6;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl5;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl4;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl3;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl2;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl1;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl0;
+
+
+ /* CR48 */
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl15;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl14;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl13;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl12;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl11;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl10;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl9;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl8;
+
+
+ /* CR49 */
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl23;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl22;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl21;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl20;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl19;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl18;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl17;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl16;
+
+
+ /* CR50 */
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl31;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl30;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl29;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl28;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl27;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl26;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl25;
+ t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl24;
+
+
+ /* CR51 */
+ t_ab8500_codec_cr51_da12_voice cr51_da12_voice;
+ t_ab8500_codec_cr51_sldai1toslado1 cr51_sldai1toslado1;
+ t_ab8500_codec_cr51_to_cr56_sltoda cr51_sltoda1;
+
+
+ /* CR52 */
+ t_ab8500_codec_cr52_sldai2toslado2 cr52_sldai2toslado2;
+ t_ab8500_codec_cr51_to_cr56_sltoda cr52_sltoda2;
+
+
+ /* CR53 */
+ t_ab8500_codec_cr53_da34_voice cr53_da34_voice;
+ t_ab8500_codec_cr53_sldai3toslado3 cr53_sldai3toslado3;
+ t_ab8500_codec_cr51_to_cr56_sltoda cr53_sltoda3;
+
+ /* CR54 */
+ t_ab8500_codec_cr54_sldai4toslado4 cr54_sldai4toslado4;
+ t_ab8500_codec_cr51_to_cr56_sltoda cr54_sltoda4;
+
+
+ /* CR55 */
+ t_ab8500_codec_cr55_da56_voice cr55_da56_voice;
+ t_ab8500_codec_cr55_sldai5toslado5 cr55_sldai5toslado5;
+ t_ab8500_codec_cr51_to_cr56_sltoda cr55_sltoda5;
+
+
+ /* CR56 */
+ t_ab8500_codec_cr56_sldai6toslado7 cr56_sldai6toslado7;
+ t_ab8500_codec_cr51_to_cr56_sltoda cr56_sltoda6;
+
+
+ /* CR57 */
+ t_ab8500_codec_cr57_bfifull_msk cr57_bfifull_msk;
+ t_ab8500_codec_cr57_bfiempt_msk cr57_bfiempt_msk;
+ t_ab8500_codec_cr57_dachan_msk cr57_dachan_msk;
+ t_ab8500_codec_cr57_gain_msk cr57_gain_msk;
+ t_ab8500_codec_cr57_dspad_msk cr57_dspad_msk;
+ t_ab8500_codec_cr57_dspda_msk cr57_dspda_msk;
+ t_ab8500_codec_cr57_stfir_msk cr57_stfir_msk;
+
+
+ /* CR58 */
+ t_ab8500_codec_cr58_bfifull_ev cr58_bfifull_ev;
+ t_ab8500_codec_cr58_bfiempt_ev cr58_bfiempt_ev;
+ t_ab8500_codec_cr58_dachan_ev cr58_dachan_ev;
+ t_ab8500_codec_cr58_gain_ev cr58_gain_ev;
+ t_ab8500_codec_cr58_dspad_ev cr58_dspad_ev;
+ t_ab8500_codec_cr58_dspda_ev cr58_dspda_ev;
+ t_ab8500_codec_cr58_stfir_ev cr58_stfir_ev;
+
+
+ /* CR59 */
+ t_ab8500_codec_cr59_vssready_msk cr59_vssready_msk;
+ t_ab8500_codec_cr59_shrtvibl_msk cr59_shrtvibl_msk;
+ t_ab8500_codec_cr59_shrtvibr_msk cr59_shrtvibr_msk;
+ t_ab8500_codec_cr59_shrthfl_msk cr59_shrthfl_msk;
+ t_ab8500_codec_cr59_shrthfr_msk cr59_shrthfr_msk;
+ t_ab8500_codec_cr59_shrthsl_msk cr59_shrthsl_msk;
+ t_ab8500_codec_cr59_shrthsr_msk cr59_shrthsr_msk;
+ t_ab8500_codec_cr59_shrtear_msk cr59_shrtear_msk;
+
+
+ /* CR60 */
+ t_ab8500_codec_cr60_vssready_ev cr60_vssready_ev;
+ t_ab8500_codec_cr60_shrtvibl_ev cr60_shrtvibl_ev;
+ t_ab8500_codec_cr60_shrtvibr_ev cr60_shrtvibr_ev;
+ t_ab8500_codec_cr60_shrthfl_ev cr60_shrthfl_ev;
+ t_ab8500_codec_cr60_shrthfr_ev cr60_shrthfr_ev;
+ t_ab8500_codec_cr60_shrthsl_ev cr60_shrthsl_ev;
+ t_ab8500_codec_cr60_shrthsr_ev cr60_shrthsr_ev;
+ t_ab8500_codec_cr60_shrtear_ev cr60_shrtear_ev;
+
+
+ /* CR61 */
+ t_ab8500_codec_cr61_revision cr61_revision;
+ t_ab8500_codec_cr61_fade_speed cr61_fade_speed;
+
+
+ /* CR62 */
+ t_ab8500_codec_cr62_dmic1sinc3 cr62_dmic1sinc3;
+ t_ab8500_codec_cr62_dmic2sinc3 cr62_dmic2sinc3;
+ t_ab8500_codec_cr62_dmic3sinc3 cr62_dmic3sinc3;
+ t_ab8500_codec_cr62_dmic4sinc3 cr62_dmic4sinc3;
+ t_ab8500_codec_cr62_dmic5sinc3 cr62_dmic5sinc3;
+ t_ab8500_codec_cr62_dmic6sinc3 cr62_dmic6sinc3;
+
+
+ /* CR63 */
+ t_ab8500_codec_cr63_datohslen cr63_datohslen;
+ t_ab8500_codec_cr63_datohsren cr63_datohsren;
+ t_ab8500_codec_cr63_ad1sel cr63_ad1sel;
+ t_ab8500_codec_cr63_ad2sel cr63_ad2sel;
+ t_ab8500_codec_cr63_ad3sel cr63_ad3sel;
+ t_ab8500_codec_cr63_ad5sel cr63_ad5sel;
+ t_ab8500_codec_cr63_ad6sel cr63_ad6sel;
+ t_ab8500_codec_cr63_ancsel cr63_ancsel;
+
+
+ /* CR64 */
+ t_ab8500_codec_cr64_datohfren cr64_datohfren;
+ t_ab8500_codec_cr64_datohflen cr64_datohflen;
+ t_ab8500_codec_cr64_hfrsel cr64_hfrsel;
+ t_ab8500_codec_cr64_hflsel cr64_hflsel;
+ t_ab8500_codec_cr64_stfir1sel cr64_stfir1sel;
+ t_ab8500_codec_cr64_stfir2sel cr64_stfir2sel;
+
+
+ /* CR65 */
+ t_ab8500_codec_cr65_fadedis_ad1 cr65_fadedis_ad1;
+ t_ab8500_codec_cr65_ad1gain cr65_ad1gain;
+
+
+ /* CR66 */
+ t_ab8500_codec_cr66_fadedis_ad2 cr66_fadedis_ad2;
+ t_ab8500_codec_cr66_ad2gain cr66_ad2gain;
+
+
+ /* CR67 */
+ t_ab8500_codec_cr67_fadedis_ad3 cr67_fadedis_ad3;
+ t_ab8500_codec_cr67_ad3gain cr67_ad3gain;
+
+
+ /* CR68 */
+ t_ab8500_codec_cr68_fadedis_ad4 cr68_fadedis_ad4;
+ t_ab8500_codec_cr68_ad4gain cr68_ad4gain;
+
+
+ /* CR69 */
+ t_ab8500_codec_cr69_fadedis_ad5 cr69_fadedis_ad5;
+ t_ab8500_codec_cr69_ad5gain cr69_ad5gain;
+
+
+ /* CR70 */
+ t_ab8500_codec_cr70_fadedis_ad6 cr70_fadedis_ad6;
+ t_ab8500_codec_cr70_ad6gain cr70_ad6gain;
+
+
+ /* CR71 */
+ t_ab8500_codec_cr71_fadedis_da1 cr71_fadedis_da1;
+ t_ab8500_codec_cr71_da1gain cr71_da1gain;
+
+
+ /* CR72 */
+ t_ab8500_codec_cr72_fadedis_da2 cr72_fadedis_da2;
+ t_ab8500_codec_cr72_da2gain cr72_da2gain;
+
+
+ /* CR73 */
+ t_ab8500_codec_cr73_fadedis_da3 cr73_fadedis_da3;
+ t_ab8500_codec_cr73_da3gain cr73_da3gain;
+
+
+ /* CR74 */
+ t_ab8500_codec_cr74_fadedis_da4 cr74_fadedis_da4;
+ t_ab8500_codec_cr74_da4gain cr74_da4gain;
+
+
+ /* CR75 */
+ t_ab8500_codec_cr75_fadedis_da5 cr75_fadedis_da5;
+ t_ab8500_codec_cr75_da5gain cr75_da5gain;
+
+
+ /* CR76 */
+ t_ab8500_codec_cr76_fadedis_da6 cr76_fadedis_da6;
+ t_ab8500_codec_cr76_da6gain cr76_da6gain;
+
+
+ /* CR77 */
+ t_ab8500_codec_cr77_fadedis_ad1l cr77_fadedis_ad1l;
+ t_ab8500_codec_cr77_ad1lbgain_to_hfl cr77_ad1lbgain_to_hfl;
+
+
+ /* CR78 */
+ t_ab8500_codec_cr78_fadedis_ad2l cr78_fadedis_ad2l;
+ t_ab8500_codec_cr78_ad2lbgain_to_hfr cr78_ad2lbgain_to_hfr;
+
+
+ /* CR79 */
+ t_ab8500_codec_cr79_hssinc1 cr79_hssinc1;
+ t_ab8500_codec_cr79_fadedis_hsl cr79_fadedis_hsl;
+ t_ab8500_codec_cr79_hsldgain cr79_hsldgain;
+
+
+ /* CR80 */
+ t_ab8500_codec_cr80_fadedis_hsr cr80_fadedis_hsr;
+ t_ab8500_codec_cr80_hsrdgain cr80_hsrdgain;
+
+
+ /* CR81 */
+ t_ab8500_codec_cr81_stfir1gain cr81_stfir1gain;
+
+
+ /* CR82 */
+ t_ab8500_codec_cr82_stfir2gain cr82_stfir2gain;
+
+
+ /* CR83 */
+ t_ab8500_codec_cr83_enanc cr83_enanc;
+ t_ab8500_codec_cr83_anciirinit cr83_anciirinit;
+ t_ab8500_codec_cr83_ancfirupdate cr83_ancfirupdate;
+
+
+ /* CR84 */
+ t_ab8500_codec_cr84_ancinshift cr84_ancinshift;
+
+
+ /* CR85 */
+ t_ab8500_codec_cr85_ancfiroutshift cr85_ancfiroutshift;
+
+
+ /* CR86 */
+ t_ab8500_codec_cr86_ancshiftout cr86_ancshiftout;
+
+
+ /* CR87 */
+ t_ab8500_codec_cr87_ancfircoeff_msb cr87_ancfircoeff_msb;
+
+
+ /* CR88 */
+ t_ab8500_codec_cr88_ancfircoeff_lsb cr88_ancfircoeff_lsb;
+
+
+ /* CR89 */
+ t_ab8500_codec_cr89_anciircoeff_msb cr89_anciircoeff_msb;
+
+
+ /* CR90 */
+ t_ab8500_codec_cr90_anciircoeff_lsb cr90_anciircoeff_lsb;
+
+
+ /* CR91 */
+ t_ab8500_codec_cr91_ancwarpdel_msb cr91_ancwarpdel_msb;
+
+
+ /* CR92 */
+ t_ab8500_codec_cr92_ancwarpdel_lsb cr92_ancwarpdel_lsb;
+
+
+ /* CR93 */
+ t_ab8500_codec_cr93_ancfirpeak_msb cr93_ancfirpeak_msb;
+
+
+ /* CR94 */
+ t_ab8500_codec_cr94_ancfirpeak_lsb cr94_ancfirpeak_lsb;
+
+
+ /* CR95 */
+ t_ab8500_codec_cr95_anciirpeak_msb cr95_anciirpeak_msb;
+
+
+ /* CR96 */
+ t_ab8500_codec_cr96_anciirpeak_lsb cr96_anciirpeak_lsb;
+
+
+ /* CR97 */
+ t_ab8500_codec_cr97_stfir_set cr97_stfir_set;
+ t_ab8500_codec_cr97_stfir_addr cr97_stfir_addr;
+
+
+ /* CR98 */
+ t_ab8500_codec_cr98_stfir_coeff_msb cr98_stfir_coeff_msb;
+
+
+ /* CR99 */
+ t_ab8500_codec_cr99_stfir_coeff_lsb cr99_stfir_coeff_lsb;
+
+
+ /* CR100 */
+ t_ab8500_codec_cr100_enstfirs cr100_enstfirs;
+ t_ab8500_codec_cr100_stfirstoif1 cr100_stfirstoif1;
+ t_ab8500_codec_cr100_stfir_busy cr100_stfir_busy;
+
+
+ /* CR101 */
+ t_ab8500_codec_cr101_parlhf cr101_parlhf;
+ t_ab8500_codec_cr101_parlvib cr101_parlvib;
+ t_ab8500_codec_cr101_classd_viblswapen cr101_classd_viblswapen;
+ t_ab8500_codec_cr101_classd_vibrswapen cr101_classd_vibrswapen;
+ t_ab8500_codec_cr101_classd_hflswapen cr101_classd_hflswapen;
+ t_ab8500_codec_cr101_classd_hfrswapen cr101_classd_hfrswapen;
+
+
+ /* CR102 */
+ t_ab8500_codec_cr102_classd_firbyp cr102_classd_firbyp;
+ t_ab8500_codec_cr102_classd_highvolen cr102_classd_highvolen;
+
+
+ /* CR103 */
+ t_ab8500_codec_cr103_classd_ditherhpgain cr103_classd_ditherhpgain;
+ t_ab8500_codec_cr103_classd_ditherwgain cr103_classd_ditherwgain;
+
+
+ /* CR104 */
+ t_ab8500_codec_cr104_bfifoint cr104_bfifoint;
+
+
+ /* CR105 */
+ t_ab8500_codec_cr105_bfifotx cr105_bfifotx;
+
+
+ /* CR106 */
+ t_ab8500_codec_cr106_bfifofsext cr106_bfifofsext;
+ t_ab8500_codec_cr106_bfifomsk cr106_bfifomsk;
+ t_ab8500_codec_cr106_bfifomstr cr106_bfifomstr;
+ t_ab8500_codec_cr106_bfifostrt cr106_bfifostrt;
+
+
+ /* CR107 */
+ t_ab8500_codec_cr107_bfifosampnr cr107_bfifosampnr;
+
+
+ /* CR108 */
+ t_ab8500_codec_cr108_bfifowakeup cr108_bfifowakeup;
+
+
+ /* CR109 */
+ t_ab8500_codec_cr109_bfifosamples cr109_bfifosamples;
+
+
+} t_ab8500_codec_configuration;
+
+
+typedef struct
+{
+ t_uint8 slave_address_of_ab8500_codec;
+ t_ab8500_codec_direction ab8500_codec_direction;
+ t_ab8500_codec_mode ab8500_codec_mode_in;
+ t_ab8500_codec_mode ab8500_codec_mode_out;
+ t_ab8500_codec_audio_interface audio_interface;
+ t_ab8500_codec_src ab8500_codec_src;
+ t_ab8500_codec_dest ab8500_codec_dest;
+ t_uint8 in_left_volume;
+ t_uint8 in_right_volume;
+ t_uint8 out_left_volume;
+ t_uint8 out_right_volume;
+
+ t_ab8500_codec_configuration ab8500_codec_configuration;
+} t_ab8500_codec_system_context;
+#endif /* _AB8500_CODECP_H_ */
+
+/* End of file AB8500_CODECP.h */
+
+
diff --git a/arch/arm/mach-ux500/include/mach/ab8500_gpadc.h b/arch/arm/mach-ux500/include/mach/ab8500_gpadc.h
new file mode 100644
index 00000000000..150ff10173e
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/ab8500_gpadc.h
@@ -0,0 +1,28 @@
+/*
+ * ab8500_gpadc.c - AB8500 GPADC Driver
+ *
+ * Copyright (C) 2010 ST-Ericsson
+ * Licensed under GPLv2.
+ *
+ * Author: Arun R Murthy <arun.murthy@stericsson.com>
+ */
+
+#ifndef _AB8500_GPADC_H
+#define _Ab8500_GPADC_H
+
+/* GPADC source: From datasheer(ADCSwSel[4:0] in GPADCCtrl2) */
+#define BAT_CTRL 0x01
+#define ACC_DETECT1 0x04
+#define ACC_DETECT2 0x05
+#define MAIN_BAT_V 0x08
+#define BK_BAT_V 0x0C
+#define VBUS_V 0x09
+#define MAIN_CHARGER_V 0x03
+#define MAIN_CHARGER_C 0x0A
+#define USB_CHARGER_C 0x0B
+#define DIE_TEMP 0x0D
+#define BTEMP_BALL 0x02
+
+int ab8500_gpadc_conversion(int input);
+
+#endif /* _AB8500_GPADC_H */
diff --git a/arch/arm/mach-ux500/include/mach/av8100.h b/arch/arm/mach-ux500/include/mach/av8100.h
new file mode 100755
index 00000000000..a4afebf3c8c
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/av8100.h
@@ -0,0 +1,531 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms:
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __AV8100_H
+#define __AV8100_H
+
+#ifdef _cplusplus
+extern "C" {
+#endif /* _cplusplus */
+
+typedef enum av8100_error
+{
+ AV8100_OK = 0x0,
+ AV8100_INVALID_COMMAND = 0x1,
+ AV8100_INVALID_INTERFACE = 0x2,
+ AV8100_INVALID_IOCTL = 0x3,
+ AV8100_COMMAND_FAIL = 0x4,
+ AV8100_FWDOWNLOAD_FAIL = 0x5,
+ AV8100_FAIL = 0xFF,
+}av8100_error;
+
+typedef enum interface
+{
+ I2C_INTERFACE = 0x0,
+ DSI_INTERFACE = 0x1,
+}interface;
+
+/** AV8100 - DSI dcs command set */
+typedef enum
+{
+ DCS_VSYNC_START = 0x1,
+ DCS_VSYNC_END = 0x11,
+ DCS_HSYNC_START = 0x21,
+ DCS_HSYNC_END = 0x31,
+ DCS_SHORT_WRITE = 0x15,
+ DCS_LONG_WRITE = 0x39,
+ DCS_RGB565_PACKED = 0xE,
+ DCS_RGB666_PACKED = 0x1E,
+ DCS_RGB666_UNPACKED = 0x2E,
+ DCS_RGB888_PACKED = 0x3E,
+ DCS_RAM_WRITE = 0x3C,
+ DCS_RAM_WRITE_CONTINUE = 0x2C,
+ DCS_FW_DOWNLOAD = 0xDB,
+ DCS_WRITE_UC = 0xDC,
+ DCS_READ_UC = 0xDB,
+ DCS_NEXT_FILED_TYPE = 0xDA,
+ DCS_EXEC_UC = 0xDD,
+}dsi_dcs_command_type;
+
+/** AV8100 Operating modes */
+typedef enum
+{
+ AV8100_OPMODE_SHUTDOWN = 0x1,
+ AV8100_OPMODE_STANDBY,
+ AV8100_OPMODE_SCAN,
+ AV8100_OPMODE_INIT,
+ AV8100_OPMODE_IDLE,
+ AV8100_OPMODE_VIDEO
+}av8100_operating_mode;
+
+/** AV8100 status */
+#define AV8100_PLUGIN_NONE 0x00
+#define AV8100_HDMI_PLUGIN 0x01
+#define AV8100_CVBS_PLUGIN 0x02
+
+/** AV8100 Command Type */
+typedef enum
+{
+ AV8100_COMMAND_VIDEO_INPUT_FORMAT = 0x1,
+ AV8100_COMMAND_AUDIO_INPUT_FORMAT = 0x2,
+ AV8100_COMMAND_VIDEO_OUTPUT_FORMAT = 0x3,
+ AV8100_COMMAND_VIDEO_SCALING_FORMAT,
+ AV8100_COMMAND_COLORSPACECONVERSION,
+ AV8100_COMMAND_CEC_MESSAGEWRITE,
+ AV8100_COMMAND_CEC_MESSAGEREAD_BACK,
+ AV8100_COMMAND_DENC,
+ AV8100_COMMAND_HDMI,
+ AV8100_COMMAND_HDCP_SENDKEY,
+ AV8100_COMMAND_HDCP_MANAGEMENT,
+ AV8100_COMMAND_INFOFRAMES,
+ AV8100_COMMAND_EDID_SECTIONREADBACK,
+ AV8100_COMMAND_PATTERNGENERATOR,
+
+}av8100_command_type;
+
+/** AV8100 Command Type */
+typedef enum
+{
+ AV8100_COMMAND_VIDEO_INPUT_FORMAT_SIZE = 0x17,
+ AV8100_COMMAND_AUDIO_INPUT_FORMAT_SIZE = 0x8,
+ AV8100_COMMAND_VIDEO_OUTPUT_FORMAT_SIZE = 0x18,
+ AV8100_COMMAND_VIDEO_SCALING_FORMAT_SIZE = 0x9,
+ AV8100_COMMAND_COLORSPACECONVERSION_SIZE = 0x21,
+ AV8100_COMMAND_CEC_MESSAGEWRITE_SIZE = 0x14,
+ AV8100_COMMAND_CEC_MESSAGEREAD_BACK_SIZE = 0x14,
+ AV8100_COMMAND_DENC_SIZE = 0x5,
+ AV8100_COMMAND_HDMI_SIZE = 0x4,
+ AV8100_COMMAND_HDCP_SENDKEY_SIZE = 0x9,
+ AV8100_COMMAND_HDCP_MANAGEMENT_SIZE = 0x4,
+ AV8100_COMMAND_INFOFRAMES_SIZE = 0x22,
+ AV8100_COMMAND_EDID_SECTIONREADBACK_SIZE = 0x81,
+ AV8100_COMMAND_PATTERNGENERATOR_SIZE = 0x4,
+}av8100_command_size;
+
+/** AV8100 structures register & command definitions */
+
+/** AV8100 Internal registers ~ Register 0x0 to 0xF */
+/** Internal registers for I2C operations */
+
+typedef enum
+{
+ STANDBY_REG = 0x0,
+ AV8100_5_VOLT_TIME_REG = 0x1,
+ STANDBY_INTERRUPT_MASK_REG = 0x2,
+ STANDBY_PENDING_INTERRUPT_REG = 0x3,
+ GENERAL_INTERRUPT_MASK_REG = 0x4,
+ GENERAL_INTERRUPT_REG = 0x5,
+ GENERAL_STATUS_REG = 0x6,
+ GPIO_CONFIGURATION_REG = 0x7,
+ GENERAL_CONTROL_REG = 0x8,
+ FIRMWARE_DOWNLOAD_ENTRY_REG = 0xF
+}internal_reg;
+
+struct av8100_registers_internal
+{
+ volatile char standby;
+ volatile char av8100_5_volt_time;
+ volatile char standby_interrupt_mask;
+ volatile char standby_pending_interrupt;
+ volatile char general_interrupt_mask;
+ volatile char general_interrupt;
+ volatile char general_status;
+ volatile char gpio_configuration;
+ volatile char general_control;
+ volatile char firmware_download_entry;
+};
+
+/** AV8100 Video Input Format Command */
+struct av8100_video_input_format_command
+{
+
+ volatile char Identifier;
+ volatile char Mode;
+ volatile char Pixel_format;
+ volatile char Htotal[2];
+ volatile char Hactive[2];
+ volatile char Vtotal[2];
+ volatile char Vactive[2];
+ volatile char Videomode;
+ volatile char Number_DSI;
+ volatile char Virtualchannelcommandmode;
+ volatile char Virtualchannelvideomode;
+ volatile char Linenumber[2];
+ volatile char Tearingeffect;
+ volatile char Master_Clock_frequency[4];
+};
+
+/** AV8100 Audio Input Format Command */
+struct av8100_audio_input_format_command
+{
+
+ volatile char Identifier;
+ volatile char I2SOrTDM;
+ volatile char NumberofI2SentriesFreq;
+ volatile char BitFormat;
+ volatile char LPCMOrCompress;
+ volatile char SlaveOrMaster;
+ volatile char Mute;
+
+};
+
+/** AV8100 Video Output Format Command */
+struct av8100_video_output_format_command
+{
+
+ volatile char Identifier;
+ volatile char Formatter;
+ volatile char VSYNCpolarity;
+ volatile char HSYNCpolarity;
+ volatile char Htotal[2];
+ volatile char Hactive[2];
+ volatile char Vtotal[2];
+ volatile char Vactive[2];
+ volatile char HSYNCstart[2];
+ volatile char HSYNClength[2];
+ volatile char VSYNCstart[2];
+ volatile char VSYNClength[2];
+ volatile char Pixelfrequency[4];
+};
+
+/** AV8100 Video Video Scaling Format Command */
+struct av8100_video_scaling_format_command
+{
+ volatile char Identifier;
+ volatile char Hstart[2];
+ volatile char Hstop[2];
+ volatile char Vstart[2];
+ volatile char Vstop[2];
+};
+
+/** AV8100 Video Colorspace Conversion Command */
+struct av8100_colorspace_conversion_command
+{
+ volatile char Identifier;
+ volatile char C0[2];
+ volatile char C1[2];
+ volatile char C2[2];
+ volatile char C3[2];
+ volatile char C4[2];
+ volatile char C5[2];
+ volatile char C6[2];
+ volatile char C7[2];
+ volatile char C8[21];
+ volatile char AOFFSET[2];
+ volatile char BOFFSET[2];
+ volatile char COFFSET[2];
+ volatile char AMINIMUM;
+ volatile char AMAXIMUM;
+ volatile char BMINIMUM;
+ volatile char BMAXIMUM;
+ volatile char CMINIMUM;
+ volatile char CMAXIMUM;
+};
+
+/** AV8100 Video CEC message */
+struct av8100_CEC_message
+{
+ volatile char Identifier;
+ volatile char PhysicaladdressAB;
+ volatile char PhysicaladdressCD;
+ volatile char Bufferlength;
+ volatile char BufferData[16];
+};
+
+/** AV8100 Video CEC message Readback Command */
+struct av8100_CEC_message_readback_command
+{
+ volatile char Identifier;
+};
+
+/** AV8100 Video DENC Command */
+struct av8100_DENC_command
+{
+ volatile char Identifier;
+ volatile char CVBSvideoformatoutputchoice ;
+ volatile char Standardselection;
+ volatile char ON_OFF;
+ volatile char Macrovision_ON_OFF;
+};
+
+/** AV8100 Video HDMI Command */
+struct av8100_HDMI_command
+{
+ volatile char Identifier;
+ volatile char OFF_ON_AVMUTE;
+ volatile char HDMI_DVI;
+ volatile char DVIcontrolbit;
+};
+
+/** AV8100 Video HDCP sendkey Command */
+struct av8100_HDCP_sendkey_command
+{
+ volatile char Identifier;
+ volatile char Keynumber;
+ volatile char Key[7];
+};
+
+/** AV8100 Video HDCP management Command */
+struct av8100_HDCP_management_command
+{
+ volatile char Identifier;
+ volatile char RequestHDCPauthentication;
+ volatile char Requestencryptedtransmission;
+ volatile char OESS_EESS;
+};
+
+/** AV8100 Video Infoframe Command */
+struct av8100_Infoframe_command
+{
+ volatile char Identifier;
+ volatile char Infoframetype;
+ volatile char Infoframedata[30];
+ volatile char InfoframeCRC;
+};
+
+/** AV8100 Video EDID section readback Command */
+struct av8100_EDIDsectionreadback_command
+{
+ volatile char Identifier;
+ volatile char EDIDaddress;
+ volatile char EDIDblocknumber;
+};
+
+/** AV8100 Video Pattern Generator Command */
+struct av8100_PatternGenerator_command
+{
+ volatile char Identifier;
+ volatile char Testtypeselection;
+ volatile char VideoPatterngeneratorselection;
+ volatile char AudioSound;
+};
+
+/** AV8100 Video Command return */
+struct av8100_command_return
+{
+ volatile char Identifier;
+ volatile char OK_FAIL;
+};
+
+/** AV8100 Video CEC messgae readback command */
+struct av8100_EDID_section_readback
+{
+ volatile char Identifier;
+ volatile char OK_FAIL;
+ volatile char EDID[128];
+};
+
+typedef enum{
+ AV8100_AUDIO_I2S_MODE,
+ AV8100_AUDIO_I2SDELAYED_MODE, /* I2S Mode by default*/
+ AV8100_AUDIO_TDM_MODE /* 8 Channels by default*/
+} av8100_audio_if_format;
+
+typedef enum{
+ AV8100_AUDIO_MUTE_DISABLE,
+ AV8100_AUDIO_MUTE_ENABLE
+} av8100_audio_mute;
+
+typedef enum{
+ AV8100_AUDIO_SLAVE,
+ AV8100_AUDIO_MASTER
+} av8100_audio_if_mode;
+
+typedef enum{
+ AV8100_AUDIO_LPCM_MODE,
+ AV8100_AUDIO_COMPRESS_MODE
+} av8100_audio_format;
+
+typedef enum{
+ AV8100_AUDIO_16BITS,
+ AV8100_AUDIO_20BITS,
+ AV8100_AUDIO_24BITS
+} av8100_audio_word_length;
+
+typedef enum{
+ AV8100_AUDIO_FREQ_32KHZ,
+ AV8100_AUDIO_FREQ_44_1KHZ,
+ AV8100_AUDIO_FREQ_48KHZ,
+ AV8100_AUDIO_FREQ_64KHZ,
+ AV8100_AUDIO_FREQ_88_2KHZ,
+ AV8100_AUDIO_FREQ_96KHZ,
+ AV8100_AUDIO_FREQ_128KHZ,
+ AV8100_AUDIO_FREQ_176_1KHZ,
+ AV8100_AUDIO_FREQ_192KHZ
+} av8100_sample_freq;
+
+
+typedef enum{
+ AV8100_PATTERN_AUDIO_OFF,
+ AV8100_PATTERN_AUDIO_ON,
+ AV8100_PATTERN_AUDIO_I2S_MEM
+} av8100_pattern_audio;
+
+typedef enum{
+ AV8100_PATTERN_OFF,
+ AV8100_PATTERN_GENERATOR,
+ AV8100_PRODUCTION_TESTING
+} av8100_pattern_type;
+
+typedef enum{
+ AV8100_NO_PATTERN,
+ AV8100_PATTERN_VGA,
+ AV8100_PATTERN_720P,
+ AV8100_PATTERN_1080P
+} av8100_pattern_format;
+
+typedef enum{
+ AV8100_HDMI_OFF,
+ AV8100_HDMI_ON,
+ AV8100_HDMI_AVMUTE
+} av8100_hdmi_mode;
+
+typedef enum{
+ AV8100_HDMI,
+ AV8100_DVI
+} av8100_hdmi_format;
+
+typedef enum{
+ AV8100_DVI_CTRL_CTL0,
+ AV8100_DVI_CTRL_CTL1,
+ AV8100_DVI_CTRL_CTL2
+} av8100_DVI_format;
+
+typedef enum{
+ AV8100_SYNC_POSITIVE,
+ AV8100_SYNC_NEGATIVE
+} av8100_video_sync_pol;
+
+typedef enum{
+
+ AV8100_INPUT_PIX_RGB565,
+ AV8100_INPUT_PIX_RGB666,
+ AV8100_INPUT_PIX_RGB666P,
+ AV8100_INPUT_PIX_RGB888,
+ AV8100_INPUT_PIX_YCBCR422
+} av8100_pixel_format;
+
+typedef enum{
+ AV8100_TE_OFF, /* NO TE*/
+ AV8100_TE_DSI_LANE, /* TE generated on DSI lane */
+ AV8100_TE_IT_LINE, /* TE generated on IT line (GPIO) */
+ AV8100_TE_DSI_IT /* TE generatedon both DSI lane & IT line*/
+} av8100_te_config;
+
+typedef enum{
+
+ AV8100_DATA_LANES_USED_0, /* 0 DSI data lane connected*/
+ AV8100_DATA_LANES_USED_1, /* 1 DSI data lane connected */
+ AV8100_DATA_LANES_USED_2, /* 2 DSI data lane connected */
+ AV8100_DATA_LANES_USED_3, /* 3 DSI data lane connected */
+ AV8100_DATA_LANES_USED_4 /* 4 DSI data lane connected */
+} av8100_dsi_nb_data_lane;
+
+typedef enum{
+
+ AV8100_VIDEO_INTERLACE,
+ AV8100_VIDEO_PROGRESSIVE
+} av8100_video_mode;
+
+typedef enum{
+
+ AV8100_HDMI_DSI_OFF,
+ AV8100_HDMI_DSI_COMMAND_MODE,
+ AV8100_HDMI_DSI_VIDEO_MODE
+} av8100_dsi_mode;
+
+/* AV8100 video modes */
+typedef enum{
+ AV8100_CUSTOM,
+ AV8100_CEA1_640X480P_59_94HZ,
+ AV8100_CEA2_3_720X480P_59_94HZ, // new
+ AV8100_CEA4_1280X720P_60HZ,
+ AV8100_CEA5_1920X1080I_60HZ,
+ AV8100_CEA6_7_NTSC_60HZ, //new
+ AV8100_CEA14_15_480p_60HZ, //new
+ AV8100_CEA16_1920X1080P_60HZ, //new
+ AV8100_CEA17_18_720X576P_50HZ, //new
+ AV8100_CEA19_1280X720P_50HZ,
+ AV8100_CEA20_1920X1080I_50HZ,
+ AV8100_CEA21_22_576I_PAL_50HZ, //new
+ AV8100_CEA29_30_576P_50HZ, //new
+ AV8100_CEA31_1920x1080P_50Hz, //new
+ AV8100_CEA32_1920X1080P_24HZ,
+ AV8100_CEA33_1920X1080P_25HZ,
+ AV8100_CEA34_1920X1080P_30HZ,
+ AV8100_CEA60_1280X720P_24HZ,
+ AV8100_CEA61_1280X720P_25HZ,
+ AV8100_CEA62_1280X720P_30HZ,
+ AV8100_VESA9_800X600P_60_32HZ,
+ AV8100_VESA14_848X480P_60HZ,
+ AV8100_VESA16_1024X768P_60HZ,
+ AV8100_VESA22_1280X768P_59_99HZ,
+ AV8100_VESA23_1280X768P_59_87HZ,
+ AV8100_VESA27_1280X800P_59_91HZ,
+ AV8100_VESA28_1280X800P_59_81HZ,
+ AV8100_VESA39_1360X768P_60_02HZ,
+ AV8100_VESA81_1366X768P_59_79HZ,
+ AV8100_VIDEO_OUTPUT_CEA_VESA_MAX
+} av8100_output_CEA_VESA;
+
+/** AV8100 internal register access structure*/
+struct av8100_register
+{
+ char value;
+ char offset;
+};
+
+/** AV8100 command configuration registers access structure*/
+struct av8100_command_register
+{
+ unsigned char cmd_id; /* input */
+ unsigned char buf_len; /* input, output */
+ unsigned char buf[128]; /* input, output */
+ unsigned char return_status; /* output */
+};
+
+/* IOCTL return status */
+#define HDMI_COMMAND_RETURN_STATUS_OK 0
+#define HDMI_COMMAND_RETURN_STATUS_FAIL 1
+
+#define HDMI_REQUEST_FOR_REVOCATION_LIST_INPUT 2
+#define HDMI_CEC_MESSAGE_READBACK_MAXSIZE 16
+
+/** AV8100 status structure*/
+struct av8100_status
+{
+ char av8100_state;
+ char av8100_plugin_status;
+};
+
+/** Maximum size of the structure need to passed to AV8100 */
+
+#define AV8100_IOC_MAGIC 0xcc
+
+/** IOCTL Operations for accessing information from AV8100 */
+
+#define IOC_AV8100_READ_REGISTER _IOWR(AV8100_IOC_MAGIC,1,struct av8100_register)
+#define IOC_AV8100_WRITE_REGISTER _IOWR(AV8100_IOC_MAGIC,2,struct av8100_register)
+#define IOC_AV8100_SEND_CONFIGURATION_COMMAND _IOWR(AV8100_IOC_MAGIC,3,struct av8100_command_register)
+//#define IOC_AV8100_READ_CONFIGURATION_COMMAND _IOWR(AV8100_IOC_MAGIC,4,struct av8100_command_register)
+#define IOC_AV8100_GET_STATUS _IOWR(AV8100_IOC_MAGIC,4,struct av8100_status)
+#define IOC_AV8100_ENABLE _IOWR(AV8100_IOC_MAGIC,5,struct av8100_status)
+#define IOC_AV8100_DISABLE _IOWR(AV8100_IOC_MAGIC,6,struct av8100_status)
+#define IOC_AV8100_SET_VIDEO_FORMAT _IOWR(AV8100_IOC_MAGIC,7,struct av8100_status)
+#define IOC_AV8100_HDMI_ON _IOWR(AV8100_IOC_MAGIC,8,struct av8100_status)
+#define IOC_AV8100_HDMI_OFF _IOWR(AV8100_IOC_MAGIC,9,struct av8100_status)
+
+#define AV8100_IOC_MAXNR (1)
+
+#ifdef _cplusplus
+}
+#endif /* _cplusplus */
+
+#endif /* !defined(__AV8100_H) */
diff --git a/arch/arm/mach-ux500/include/mach/av8100_fw.h b/arch/arm/mach-ux500/include/mach/av8100_fw.h
new file mode 100755
index 00000000000..94c913dddb5
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/av8100_fw.h
@@ -0,0 +1,1050 @@
+/*---------------------------------------------------------------------------*/
+/* © copyright STEricsson,2009. All rights reserved. For */
+/* information, STEricsson reserves the right to license */
+/* this software concurrently under separate license conditions. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it */
+/* under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, */
+/* or (at your option)any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */
+/* the GNU Lesser General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*---------------------------------------------------------------------------*/
+
+/* AV8100 Firmware version : V3.02 */
+#define fw_size 16384
+char ReceiveTab[fw_size];
+char TransmitTab[fw_size];
+char av8100_fw_buff[fw_size] = {
+0x80,0xfe,0xcb,0xfe,0xbc,0xc2,0x73,0xc4,0x73,0xc4,0xc9,0xc5,0x72,0xc3,0xce,0xc5,
+0x16,0xc7,0xd0,0xc8,0xe5,0xc8,0xf6,0xc8,0x08,0xc9,0x1b,0xc9,0x20,0xc9,0x25,0xc9,
+0x2a,0xc9,0x2f,0xc9,0x44,0xc9,0x7e,0xc9,0xfa,0xc9,0xb6,0xc2,0xb6,0xc2,0xb7,0xc2,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x81,0xea,0xad,0xec,0xad,
+0x38,0x20,0x1b,0x72,0x80,0x81,0x4d,0x51,0x4d,0x51,0x4d,0x51,0x4d,0x51,0x4d,0x51,
+0x4d,0x51,0xb4,0x20,0xf4,0x2a,0x5a,0x90,0x82,0xfe,0xcd,0x80,0x00,0xaf,0x72,0x93,
+0xa3,0x20,0x5f,0x90,0x80,0x80,0x97,0x90,0x8d,0x20,0x0f,0xab,0x01,0xa6,0x88,0x89,
+0x90,0x96,0xad,0x97,0x90,0x9a,0xad,0x8b,0x93,0x9e,0xad,0x97,0x90,0xa2,0xad,0x80,
+0xb7,0xa6,0xad,0x81,0xb7,0xaa,0xad,0x82,0xb7,0xae,0xad,0x26,0x31,0x20,0x08,0x72,
+0x82,0xb7,0x21,0xa6,0x81,0xb7,0xc2,0xa6,0x80,0xb7,0x01,0xa6,0xb4,0x20,0xf5,0x2a,
+0x5a,0x90,0x80,0x00,0xa7,0x72,0x93,0xcc,0xad,0x49,0x27,0x97,0x90,0x5d,0x90,0xd4,
+0xad,0x82,0xb7,0xd8,0xad,0x81,0xb7,0xdc,0xad,0x80,0xb7,0xe0,0xad,0xff,0xae,0x90,
+0x81,0x59,0x29,0xea,0x26,0x5a,0xfb,0x38,0x20,0x07,0x72,0x4d,0x38,0x20,0x1a,0x72,
+0x49,0x00,0x38,0x20,0x05,0x72,0xbc,0xff,0xcd,0x08,0xae,0xf3,0x20,0x79,0x24,0x49,
+0x44,0x24,0x49,0x23,0x24,0x49,0x0b,0xad,0x82,0xfe,0xcd,0x9e,0x82,0xfe,0xcd,0x9f,
+0x5b,0x82,0xfe,0xcd,0x80,0xb6,0x82,0xfe,0xcd,0x81,0xb6,0x82,0xfe,0xcd,0x82,0xb6,
+0x82,0xad,0x9f,0x90,0x86,0xad,0x85,0x90,0x84,0x42,0x8c,0x20,0x9f,0x90,0x01,0xab,
+0x0f,0xa6,0x2a,0x31,0x20,0x08,0x72,0xfb,0x38,0x20,0x07,0x72,0x4d,0x38,0x20,0x1a,
+0x72,0xbc,0xff,0xcd,0xfb,0x38,0x20,0x07,0x72,0x30,0x20,0x10,0x72,0x31,0x20,0x1e,
+0x72,0x30,0x20,0x1c,0x72,0x95,0x05,0xa0,0x9e,0x52,0xc0,0xcc,0x5f,0x90,0x5f,0x4f,
+0x07,0x38,0x20,0x05,0x72,0x0c,0x39,0x20,0x05,0x72,0x81,0x41,0x29,0x38,0x20,0x18,
+0x72,0xd5,0x26,0x5a,0xfb,0x38,0x20,0x07,0x72,0x9d,0x9d,0x4d,0x38,0x20,0x1a,0x72,
+0x4d,0xae,0xff,0xcd,0x4d,0xae,0xff,0xcd,0x38,0x20,0x1b,0x72,0x4d,0x4d,0x4d,0x4d,
+0x4d,0x38,0x20,0x19,0x72,0x04,0x25,0x49,0x38,0x20,0x18,0x72,0x08,0xae,0x34,0x20,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x81,0xa5,0xbe,0x84,0xa3,
+0xb7,0xa4,0xd6,0x92,0x5c,0xa2,0xb7,0xa4,0xd6,0x92,0x5c,0xa1,0xb7,0xa4,0xd6,0x92,
+0x01,0xae,0xa0,0xb7,0xa4,0xc6,0x92,0x88,0xa5,0xbf,0x81,0xa0,0xb7,0xa4,0xc2,0x92,
+0xa0,0xb6,0xa1,0xb7,0xa4,0xd2,0x92,0x5a,0xa1,0xb6,0xa2,0xb7,0xa4,0xd2,0x92,0x5a,
+0xa2,0xb6,0xa3,0xb7,0xa4,0xd0,0x92,0xa3,0xb6,0x03,0xae,0xa5,0xbf,0x81,0xa3,0xb7,
+0xa4,0xda,0x92,0x5c,0xa3,0xb6,0xa2,0xb7,0xa4,0xda,0x92,0x5c,0xa2,0xb6,0xa1,0xb7,
+0xa4,0xda,0x92,0x01,0xae,0xa1,0xb6,0xa0,0xb7,0xa4,0xca,0x92,0xa0,0xb6,0xa5,0xbf,
+0x81,0xa5,0xbe,0xe9,0x26,0x4a,0xa4,0x00,0x66,0x72,0x5c,0xa4,0x00,0x66,0x72,0x5c,
+0xa4,0x00,0x66,0x72,0x01,0xae,0xa4,0x00,0x34,0x72,0xa5,0xbf,0x1b,0x27,0x4d,0xb1,
+0xfa,0xcc,0xa0,0xfb,0xcd,0x81,0xa5,0xbe,0xe9,0x26,0x4a,0xa4,0x00,0x39,0x72,0xa4,
+0x00,0x69,0x72,0x5a,0xa4,0x00,0x69,0x72,0x5a,0xa4,0x00,0x68,0x72,0x03,0xae,0xa5,
+0xbf,0x1b,0x27,0x4d,0x81,0xa0,0xb7,0xa4,0xc9,0x92,0xa0,0xb6,0xa1,0xb7,0xa4,0xd9,
+0x92,0x5a,0xa1,0xb6,0xa2,0xb7,0xa4,0xd9,0x92,0x5a,0xa2,0xb6,0xa3,0xb7,0xa4,0xdb,
+0x92,0xa3,0xb6,0x03,0xae,0xa5,0xbf,0xb1,0xfa,0xcc,0x39,0xfb,0xcd,0x81,0x01,0xa6,
+0x02,0x20,0xff,0xa6,0x04,0x24,0x08,0x27,0xa4,0xd1,0x92,0xa3,0xb6,0xa5,0x3c,0x09,
+0x26,0xa4,0xd1,0x92,0xa2,0xb6,0xa5,0x3c,0x12,0x26,0xa4,0xd1,0x92,0xa1,0xb6,0xa5,
+0x3c,0x23,0x26,0xa4,0xd1,0x92,0xa0,0xb6,0xa5,0x3f,0x81,0xa0,0x3c,0x02,0x24,0xa1,
+0xb7,0xa1,0xb9,0x9f,0xa2,0xb7,0xa2,0xbb,0x42,0x93,0x0f,0x27,0x4d,0x84,0xf7,0xfa,
+0xcd,0xa8,0xb6,0x05,0x27,0xa7,0xbe,0xa3,0xb7,0xa2,0xbf,0x42,0x93,0xa8,0xb6,0xa1,
+0xb7,0xa0,0xbf,0x42,0xa7,0xb6,0x89,0xa8,0xb7,0x81,0xa0,0x3f,0xa1,0x3f,0xa2,0xbf,
+0xa3,0xb7,0x81,0xa5,0xbe,0x84,0xa4,0xd7,0x92,0xa3,0xb6,0x5c,0xa4,0xd7,0x92,0xa2,
+0xb6,0x5c,0xa4,0xd7,0x92,0xa1,0xb6,0x01,0xae,0xa4,0xc7,0x92,0xa0,0xb6,0x88,0xa5,
+0xbf,0x81,0xa5,0xbe,0xa4,0xd7,0x92,0xa3,0xb6,0x5c,0xa4,0xd7,0x92,0xa2,0xb6,0x5c,
+0xa4,0xd7,0x92,0xa1,0xb6,0x01,0xae,0xa4,0xc7,0x92,0xa0,0xb6,0xa5,0xbf,0x81,0x01,
+0xa6,0x02,0x27,0x03,0x6d,0x04,0x26,0x02,0x6d,0x08,0x26,0x01,0x6d,0x0e,0x26,0x7d,
+0x81,0x84,0xa3,0xb7,0x03,0xe6,0xa2,0xb7,0x02,0xe6,0xa1,0xb7,0x01,0xe6,0xa0,0xb7,
+0xf6,0x88,0x81,0x01,0xa6,0x02,0x27,0xa3,0x3d,0x04,0x26,0xa2,0x3d,0x08,0x26,0xa1,
+0x3d,0x0e,0x26,0xa0,0x3d,0x81,0xf5,0x26,0x4a,0xa0,0x39,0xa1,0x39,0xa2,0x39,0xa3,
+0x38,0x0b,0x27,0x4d,0x81,0xa0,0x3f,0xa1,0x3f,0x81,0xa0,0xb7,0xa1,0xb7,0xff,0xa6,
+0x07,0x2a,0xa2,0xbf,0xa3,0xb7,0x81,0x41,0xa8,0xbb,0x41,0x52,0x93,0x84,0xa8,0xb7,
+0xa8,0xbb,0x52,0x01,0x7b,0xa7,0xbe,0xa8,0xb7,0x52,0x9f,0x90,0x88,0x81,0xa5,0xbe,
+0xa3,0xb7,0xa4,0xd6,0x92,0x5c,0xa2,0xb7,0xa4,0xd6,0x92,0x5c,0xa1,0xb7,0xa4,0xd6,
+0x92,0x01,0xae,0xa0,0xb7,0xa4,0xc6,0x92,0xa5,0xbf,0x81,0xa0,0x3f,0xa2,0xb7,0xa1,
+0xbf,0x5c,0x01,0x24,0xa2,0xbb,0x42,0x93,0xa0,0xb6,0xa3,0xb7,0xa2,0xbf,0x42,0x93,
+0xa0,0xbf,0x81,0x39,0x01,0xc6,0x39,0x01,0xc7,0x60,0xa6,0x02,0x20,0xa0,0xa6,0x09,
+0x26,0x2f,0x01,0x5a,0x72,0x0f,0x20,0x2f,0x01,0x02,0x35,0x39,0x01,0xc0,0x35,0x0a,
+0x27,0x4d,0xa6,0xf7,0xcd,0x1a,0x27,0x30,0x01,0xc6,0x21,0x20,0xa0,0xa6,0x25,0x20,
+0xc0,0xa6,0x04,0x27,0x4d,0xa6,0xf7,0xcd,0x2f,0x01,0x02,0x35,0x33,0x20,0x82,0xa6,
+0x3a,0x26,0x68,0x01,0xca,0x69,0x01,0xc6,0x3f,0x20,0x81,0xa6,0x46,0x26,0x68,0x01,
+0xca,0x69,0x01,0xc6,0x4b,0x20,0x20,0xa6,0xf1,0x27,0x4d,0x4d,0xf7,0xcd,0x53,0x27,
+0x30,0x01,0xc6,0x5a,0x20,0x40,0xa6,0x0f,0x26,0x4d,0x4d,0xf7,0xcd,0x62,0x27,0x30,
+0x01,0xc6,0x69,0x20,0x80,0xa6,0x1e,0x27,0x31,0x01,0xc6,0x14,0x27,0x4d,0x4d,0xf7,
+0xcd,0x76,0x27,0x30,0x01,0xc6,0x2e,0x27,0x07,0x01,0xc4,0x4f,0x01,0x20,0x4c,0x03,
+0x26,0x68,0x01,0xca,0x69,0x01,0xc6,0xe7,0xf9,0xcc,0x21,0xa6,0x31,0xe1,0xcd,0x02,
+0xae,0x94,0xa6,0x0c,0x27,0x07,0x01,0xc6,0x50,0x20,0xf8,0x27,0x32,0x01,0xc6,0xea,
+0xf9,0xcc,0xf9,0x27,0x20,0xa0,0xc6,0xf9,0xcc,0x03,0x26,0x20,0xa0,0x5a,0x27,0x1e,
+0xa0,0xb4,0xf9,0xcc,0x03,0x26,0x4a,0xa8,0xf9,0xcc,0x03,0x26,0x4a,0x79,0x27,0x20,
+0xa0,0x6e,0x27,0x20,0xa0,0x63,0x27,0x1f,0xa0,0x42,0x27,0x4a,0x34,0x27,0x20,0xa0,
+0x31,0x27,0x4d,0x98,0xf9,0xcc,0x03,0x26,0x07,0x01,0xce,0x08,0x27,0x38,0x01,0xc6,
+0xe7,0xf9,0xcc,0x03,0x26,0x32,0x01,0xc6,0x08,0x27,0x38,0x01,0xc6,0x39,0x01,0x38,
+0x01,0x55,0x81,0x84,0x05,0x20,0x18,0x72,0x06,0x20,0xc7,0x01,0x6b,0x01,0xea,0x72,
+0xe0,0xa4,0x38,0x01,0xc6,0x01,0x6b,0x1f,0xa4,0x06,0x20,0xc6,0xf1,0xf5,0xcd,0x03,
+0x20,0x6e,0xf5,0xcd,0x08,0x20,0xa9,0xf4,0xcd,0x02,0xa6,0x0f,0x27,0x32,0x01,0xc6,
+0x14,0x26,0x01,0x7b,0x18,0x20,0x31,0xe1,0xcd,0x5f,0x32,0xa6,0x01,0x6b,0xa9,0xf4,
+0xcd,0x4c,0x26,0x27,0x32,0x01,0xce,0x2b,0x26,0x01,0x7b,0x0d,0x20,0x00,0xf7,0xcd,
+0x34,0x27,0x32,0x01,0xc6,0x39,0x26,0x01,0x6b,0x2a,0xf6,0xcd,0x40,0x27,0x32,0x01,
+0xc6,0x45,0x26,0x01,0x6b,0xa9,0xf4,0xcd,0x4c,0x27,0x32,0x01,0xce,0x51,0x26,0x01,
+0x6b,0x6e,0xf5,0xcd,0x58,0x27,0x32,0x01,0xc6,0x5d,0x20,0x6e,0xf5,0xcd,0x62,0x20,
+0x6e,0xf5,0xcd,0x67,0x26,0x07,0x01,0xc6,0x6c,0x20,0x6b,0x27,0x20,0xa0,0x6a,0x27,
+0x1e,0xa0,0x5e,0x27,0x4a,0x4a,0x27,0x4a,0x1f,0x27,0x20,0xa0,0x1e,0x27,0x20,0xa0,
+0x22,0x27,0x20,0xa0,0x1c,0x27,0x20,0xa0,0x38,0x01,0xc7,0xec,0xf8,0xcc,0x03,0x26,
+0x38,0x01,0xc1,0x39,0x01,0xc7,0xee,0xf8,0xcd,0x88,0x81,0xa4,0xb7,0x00,0xa9,0x41,
+0x06,0xab,0x81,0x84,0x8b,0x41,0x00,0xa9,0x41,0x08,0xab,0x5b,0x09,0x6b,0x01,0x6b,
+0x4f,0x01,0x20,0x01,0xa6,0x04,0x26,0x05,0xe1,0x72,0x4f,0x01,0xc6,0x0c,0x26,0x04,
+0xe1,0x72,0x0d,0x20,0x13,0x26,0x4f,0x01,0xc1,0x05,0x7b,0x09,0x26,0x4e,0x01,0xc6,
+0xca,0x26,0x06,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x02,0xab,0x5b,0xe6,0xfb,0xcd,
+0x3e,0xad,0x5b,0xaf,0xfa,0xcd,0x44,0xad,0x5b,0x39,0xf5,0xcd,0x84,0xba,0xdf,0xcd,
+0x74,0xae,0x08,0xa6,0x02,0x4b,0x02,0x6b,0x06,0x7b,0x03,0x6b,0x07,0x7b,0x04,0x6b,
+0x08,0x7b,0x05,0x6b,0x09,0x7b,0xaf,0xfa,0xcd,0x67,0xad,0x5b,0x39,0xf5,0xcd,0x01,
+0x6b,0x06,0x6b,0x07,0x6b,0x08,0x6b,0x09,0x6b,0x02,0x6b,0x03,0x6b,0x04,0x6b,0x05,
+0x6b,0x4f,0x8b,0x41,0x00,0xa2,0x41,0x09,0xa0,0x5b,0x81,0x85,0x85,0x85,0x85,0x85,
+0x4f,0x01,0x20,0x01,0xa6,0x04,0x26,0x14,0xa1,0x02,0x7b,0x0a,0x26,0x14,0xa1,0x03,
+0x7b,0xcc,0x25,0x05,0xa1,0x04,0x6b,0x4c,0x04,0x7b,0xe2,0x25,0x08,0xa1,0x05,0x6b,
+0x4c,0x05,0x7b,0x4e,0x01,0x54,0x72,0x02,0x6b,0x4c,0x02,0x7b,0x05,0x20,0x03,0x6b,
+0x4c,0x03,0x7b,0x07,0x4e,0x01,0x00,0x72,0x05,0x6b,0x4f,0x84,0xba,0xdf,0xcd,0x74,
+0xae,0x05,0x7b,0x01,0x4b,0x04,0x6b,0x03,0x6b,0x02,0x6b,0x01,0x6b,0x4f,0x88,0x88,
+0x88,0x88,0x88,0x81,0x85,0x4f,0x42,0xf5,0xcd,0x84,0x33,0x01,0x4e,0x01,0x55,0xba,
+0xdf,0xcd,0x74,0xae,0x04,0xa6,0x01,0x4b,0xcc,0x25,0x04,0xa1,0x01,0x6b,0x4c,0x01,
+0x7b,0x7b,0xfb,0xcd,0x34,0xae,0xa4,0x00,0x01,0x35,0x3a,0xfa,0xcd,0xfa,0x26,0x5a,
+0x90,0x59,0x48,0x06,0x27,0x58,0x90,0x58,0x90,0x58,0x90,0x01,0xe6,0x72,0x5f,0x4e,
+0x01,0xc6,0x84,0xba,0xdf,0xcd,0x74,0xae,0x02,0x7b,0x01,0x4b,0x01,0x6b,0x4f,0x88,
+0x81,0x81,0xfb,0xcd,0x08,0xa6,0xa4,0xb7,0x81,0x84,0x8b,0x41,0x00,0xa9,0x41,0x0f,
+0xab,0x5b,0x10,0x6b,0x4f,0x84,0x8f,0xe0,0xcd,0x74,0xae,0x14,0xa6,0x88,0x0e,0x6b,
+0x01,0x7b,0xe0,0x25,0x04,0xa1,0x10,0x6b,0x4c,0x10,0x7b,0x23,0xad,0x00,0xa9,0x41,
+0x0a,0xab,0x5b,0x84,0x8f,0xe0,0xcd,0x74,0xae,0x10,0xab,0x11,0x7b,0x88,0x0e,0x6b,
+0x0d,0x7b,0x10,0x6b,0x4f,0x01,0x6b,0x49,0x01,0xc6,0x0a,0x6b,0x42,0x01,0xc6,0x0b,
+0x6b,0x43,0x01,0xc6,0x0c,0x6b,0x44,0x01,0xc6,0x0d,0x6b,0x45,0x01,0xc6,0xe0,0x25,
+0x08,0xa1,0x10,0x6b,0x4c,0x10,0x7b,0x5f,0xad,0x00,0xa9,0x41,0x06,0xab,0x5b,0x84,
+0x8f,0xe0,0xcd,0x74,0xae,0x18,0xab,0x11,0x7b,0x88,0x0f,0x6b,0x09,0x7b,0x10,0x6b,
+0x04,0xa6,0xdf,0x25,0x04,0xa1,0x10,0x6b,0x4c,0x10,0x7b,0xf8,0xf6,0xcd,0x00,0xa9,
+0x41,0x02,0xab,0x5b,0x84,0x8f,0xe0,0xcd,0x74,0xae,0x18,0xab,0x11,0x7b,0x88,0x0f,
+0x6b,0x05,0x7b,0x10,0x6b,0x4f,0x06,0x6b,0x1c,0x48,0xc6,0x07,0x6b,0x1d,0x48,0xc6,
+0x08,0x6b,0x1e,0x48,0xc6,0x09,0x6b,0x1f,0x48,0xc6,0x02,0x6b,0x18,0x48,0xc6,0x03,
+0x6b,0x19,0x48,0xc6,0x04,0x6b,0x1a,0x48,0xc6,0x05,0x6b,0x1b,0x48,0xc6,0x8b,0x41,
+0x00,0xa2,0x41,0x10,0xa0,0x5b,0x81,0x84,0x84,0x84,0x84,0x9a,0xaf,0xfa,0xcd,0x04,
+0xae,0xa4,0x00,0x48,0x35,0xa3,0x14,0xa3,0x12,0xa3,0x10,0xe6,0xfb,0xcd,0xa4,0xb7,
+0x00,0xa9,0x41,0x01,0xab,0x5b,0x9b,0x01,0x6b,0x04,0x48,0xc6,0x02,0x6b,0x05,0x48,
+0xc6,0x03,0x6b,0x06,0x48,0xc6,0x04,0x6b,0x07,0x48,0xc6,0x88,0x88,0x88,0x88,0x81,
+0x84,0x84,0x84,0x84,0x9a,0xaf,0xfa,0xcd,0x04,0xae,0xa4,0x00,0x48,0x35,0xa0,0x3f,
+0xa1,0x3f,0xa2,0x3f,0xa3,0xb7,0x3f,0xa4,0xa3,0xb6,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,
+0x4f,0xa3,0xb7,0x03,0xaa,0x04,0x7b,0x9b,0x01,0x6b,0x04,0x48,0xc6,0x02,0x6b,0x05,
+0x48,0xc6,0x03,0x6b,0x06,0x48,0xc6,0x04,0x6b,0x07,0x48,0xc6,0x88,0x88,0x88,0x88,
+0x81,0x85,0x85,0x85,0x85,0x4f,0x9a,0xaf,0xfa,0xcd,0x04,0xae,0xa4,0x00,0x48,0x35,
+0xa0,0x3f,0xa1,0x3f,0xa2,0x3f,0xa3,0xb7,0x3f,0xa4,0xa3,0xb6,0xa0,0xb7,0xa1,0xb7,
+0xa2,0xb7,0x4f,0xa3,0xb7,0xfc,0xa4,0x04,0x7b,0x9b,0x01,0x6b,0x04,0x48,0xc6,0x02,
+0x6b,0x05,0x48,0xc6,0x03,0x6b,0x06,0x48,0xc6,0x04,0x6b,0x07,0x48,0xc6,0x88,0x88,
+0x88,0x88,0x81,0x9a,0xaf,0xfa,0xcd,0x14,0xae,0xa4,0x00,0x48,0x35,0xa0,0xb7,0xa1,
+0xb7,0xa2,0xb7,0x4f,0xa3,0x00,0x33,0x01,0x55,0x10,0x48,0x34,0x01,0x55,0x11,0x48,
+0x35,0x01,0x55,0x12,0x48,0x36,0x01,0x55,0x13,0x48,0x37,0x01,0x55,0x9b,0xe6,0xfb,
+0xcc,0x30,0xae,0xa4,0x00,0x48,0x35,0x81,0x85,0x85,0x85,0x85,0x85,0x85,0x85,0x85,
+0x01,0x7b,0x58,0xf4,0xcd,0x02,0x7b,0x01,0x6b,0x4c,0x05,0x26,0x02,0x6b,0x01,0xa6,
+0x02,0x27,0x01,0xa4,0x07,0x6b,0x54,0xf4,0xcd,0xf7,0x27,0x07,0x7b,0x07,0x6b,0x54,
+0xf4,0xcd,0x05,0x20,0x9a,0xaf,0xfa,0xcd,0x5f,0xa4,0x00,0x48,0x35,0xa0,0x3f,0xa1,
+0x3f,0xa2,0x3f,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x06,0x7b,0x9b,0x06,
+0x6b,0x83,0xaa,0x06,0x7b,0x04,0x20,0x03,0xaa,0x06,0x7b,0x0a,0x20,0x02,0xaa,0x06,
+0x7b,0x10,0x20,0x01,0xaa,0x06,0x7b,0x18,0x20,0x14,0x27,0x4a,0x11,0x27,0x4a,0x0e,
+0x27,0x4a,0x0b,0x27,0x08,0x7b,0x03,0x6b,0x00,0x48,0xc6,0x04,0x6b,0x01,0x48,0xc6,
+0x05,0x6b,0x02,0x48,0xc6,0x06,0x6b,0x03,0x48,0xc6,0x01,0x6b,0x07,0x6b,0x4f,0x88,
+0x88,0x88,0x88,0x88,0x88,0x88,0x88,0x81,0x84,0x84,0x84,0x84,0x84,0x9a,0xaf,0xfa,
+0xcd,0x0c,0xae,0xa4,0x00,0x48,0x35,0xa0,0x3f,0xa1,0x3f,0xa2,0x3f,0xa3,0xb7,0x03,
+0xa4,0xa3,0xb6,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x04,0x7b,0x9b,0x04,
+0x6b,0x02,0xaa,0x04,0x7b,0x04,0x20,0x01,0xaa,0x04,0x7b,0x06,0x27,0x05,0x7b,0x01,
+0x6b,0x0c,0x48,0xc6,0x02,0x6b,0x0d,0x48,0xc6,0x03,0x6b,0x0e,0x48,0xc6,0x04,0x6b,
+0x0f,0x48,0xc6,0x88,0x88,0x88,0x88,0x88,0x81,0x0f,0x48,0xc6,0x81,0x84,0x84,0x84,
+0x84,0x84,0x9a,0xaf,0xfa,0xcd,0x04,0xae,0xa4,0x00,0x48,0x35,0xa0,0x3f,0xa1,0x3f,
+0xa2,0x3f,0xa3,0xb7,0x3f,0xa4,0xa3,0xb6,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,
+0xb7,0x04,0x7b,0x9b,0x04,0x6b,0xfb,0xa4,0x04,0x7b,0x04,0x20,0x04,0xaa,0x04,0x7b,
+0x06,0x27,0x05,0x7b,0x01,0x6b,0x04,0x48,0xc6,0x02,0x6b,0x05,0x48,0xc6,0x03,0x6b,
+0x06,0x48,0xc6,0x04,0x6b,0x07,0x48,0xc6,0x88,0x88,0x88,0x88,0x88,0x81,0x84,0x84,
+0x84,0x84,0x9a,0xaf,0xfa,0xcd,0x04,0xae,0xa4,0x00,0x48,0x35,0xa0,0x3f,0xa1,0x3f,
+0xa2,0x3f,0xa3,0xb7,0x3f,0xa4,0xa3,0xb6,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,
+0xb7,0xfc,0xa4,0x04,0x7b,0x9b,0x01,0x6b,0x04,0x48,0xc6,0x02,0x6b,0x05,0x48,0xc6,
+0x03,0x6b,0x06,0x48,0xc6,0x04,0x6b,0x07,0x48,0xc6,0x88,0x88,0x88,0x88,0x81,0x84,
+0x84,0x84,0x84,0x9a,0xaf,0xfa,0xcd,0x04,0xae,0xa4,0x00,0x48,0x35,0xa0,0x3f,0xa1,
+0x3f,0xa2,0x3f,0xa3,0xb7,0x3f,0xa4,0xa3,0xb6,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,
+0xa3,0xb7,0x03,0xaa,0x04,0x7b,0x9b,0x01,0x6b,0x04,0x48,0xc6,0x02,0x6b,0x05,0x48,
+0xc6,0x03,0x6b,0x06,0x48,0xc6,0x04,0x6b,0x07,0x48,0xc6,0x88,0x88,0x88,0x88,0xfe,
+0xce,0x80,0x3d,0xe1,0xb7,0x80,0x3d,0xab,0x93,0x80,0x3d,0x25,0x6e,0x9f,0x3d,0x81,
+0x5a,0xc0,0xcd,0x11,0xb7,0x57,0xf2,0xcd,0xf1,0x20,0x2e,0xf1,0xcd,0x0a,0x20,0x09,
+0xf1,0xcd,0x65,0xc0,0xcc,0x11,0xb7,0xf4,0xef,0xcd,0x03,0x20,0xf2,0xef,0xcd,0x08,
+0x20,0x68,0xee,0xcd,0x0d,0x20,0xd8,0xed,0xcd,0x12,0x20,0x54,0xeb,0xcd,0x29,0x20,
+0xbf,0xea,0xcd,0x1c,0x20,0xe0,0xea,0xcd,0x21,0x20,0xe7,0xe9,0xcd,0x26,0x20,0x91,
+0xe9,0xcd,0x2b,0x20,0x61,0xe9,0xcd,0x30,0x20,0x1e,0xe9,0xcd,0x35,0x20,0x19,0xe8,
+0xcd,0x81,0x88,0xf1,0xf2,0xd6,0x88,0xf2,0xf2,0xd6,0x58,0x97,0x5c,0x24,0x0f,0xa1,
+0x4a,0x68,0xf3,0x63,0xf3,0x5e,0xf3,0x56,0xf3,0x51,0xf3,0x4c,0xf3,0x47,0xf3,0x42,
+0xf3,0x3d,0xf3,0x38,0xf3,0x33,0xf3,0x2e,0xf3,0x29,0xf3,0x24,0xf3,0x1f,0xf3,0x81,
+0xe6,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x81,0x85,0x85,0x85,0x85,0x01,
+0xa6,0x02,0x20,0x4f,0x12,0x00,0xc0,0x84,0x55,0x4b,0xe1,0xcd,0x0a,0xa6,0x9a,0x78,
+0x84,0xc7,0x01,0x7b,0x79,0x84,0xc7,0x02,0x7b,0x7a,0x84,0xc7,0x03,0x7b,0x7b,0x84,
+0xc7,0x04,0x7b,0xaf,0xfa,0xcd,0x78,0xae,0xa4,0x00,0x84,0x35,0xa0,0x18,0x34,0xad,
+0x5b,0x9b,0x01,0x6b,0x78,0x84,0xc6,0x02,0x6b,0x79,0x84,0xc6,0x03,0x6b,0x7a,0x84,
+0xc6,0x04,0x6b,0x7b,0x84,0xc6,0x9a,0xa0,0xe7,0xcd,0x01,0xa6,0xa0,0xe7,0xcd,0x4f,
+0x9b,0x50,0x26,0x5b,0xfa,0xcd,0xa1,0x3f,0xa2,0x3f,0xa3,0x3f,0x62,0xad,0x5b,0x01,
+0x6b,0xc0,0x84,0xc6,0x02,0x6b,0xc1,0x84,0xc6,0x03,0x6b,0xc2,0x84,0xc6,0x04,0x6b,
+0xc3,0x84,0xc6,0x9a,0xb4,0x84,0x00,0x35,0xb5,0x84,0x00,0x35,0xb6,0x84,0x00,0x35,
+0xb7,0x84,0x02,0x35,0x9b,0x88,0x88,0x88,0x88,0x81,0xaf,0xfa,0xcd,0xb4,0xae,0xa4,
+0x00,0x84,0x35,0x81,0xe6,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x81,0x85,
+0x85,0x85,0x85,0x85,0x05,0x7b,0x05,0x6b,0x01,0xa6,0x14,0x00,0xde,0x35,0x13,0x00,
+0xc0,0x35,0x12,0x00,0xad,0x35,0x11,0x00,0xde,0x35,0x65,0xc0,0xcd,0x15,0x27,0x4d,
+0xdd,0xe0,0xcd,0x1d,0x20,0x9a,0x33,0xad,0xa2,0x18,0x2c,0xad,0x5b,0x9b,0x01,0x6b,
+0xb4,0x84,0xc6,0x02,0x6b,0xb5,0x84,0xc6,0x03,0x6b,0xb6,0x84,0xc6,0x04,0x6b,0xb7,
+0x84,0xc6,0x4b,0xe1,0xcd,0xfa,0xa6,0x9a,0x18,0x84,0x00,0x35,0x19,0x84,0x03,0x35,
+0x1a,0x84,0x83,0x35,0x1b,0x84,0x00,0x35,0x14,0x45,0x00,0x35,0x15,0x45,0x00,0x35,
+0x16,0x45,0x00,0x35,0x17,0x45,0x02,0x35,0x75,0xad,0xa2,0x16,0xa3,0x12,0x70,0xad,
+0x5b,0x9b,0x01,0x6b,0xb4,0x84,0xc6,0x02,0x6b,0xb5,0x84,0xc6,0x03,0x6b,0xb6,0x84,
+0xc6,0x04,0x6b,0xb7,0x84,0xc6,0x7c,0x20,0x65,0x27,0x4a,0x05,0x27,0x4a,0x12,0xb6,
+0x36,0xf2,0xcc,0x03,0x27,0x02,0xa1,0x11,0xb6,0x3a,0xf2,0xcc,0x76,0x01,0xc7,0x4c,
+0x9a,0xaf,0xfa,0xcd,0x18,0xae,0xa4,0x00,0x84,0x35,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,
+0x4f,0xa3,0xb7,0x12,0xb6,0x9b,0x3a,0xf2,0xcc,0x03,0x27,0x03,0xa1,0x05,0x01,0xc6,
+0x78,0x01,0x5f,0x72,0x79,0x01,0xc7,0x02,0xa6,0x02,0x20,0x0a,0xa6,0x0d,0x20,0x05,
+0x6b,0x01,0xa6,0x7a,0x01,0x5f,0x72,0x05,0x01,0x5f,0x72,0x12,0x27,0x4a,0x11,0x27,
+0x4a,0x18,0x27,0x4a,0x7a,0x01,0xc7,0x7f,0xa4,0x12,0xb6,0x05,0x01,0x03,0x35,0x56,
+0x26,0x4a,0x11,0xb6,0x9a,0x18,0x84,0x00,0x35,0x19,0x84,0x00,0x35,0x1a,0x84,0x00,
+0x35,0x1b,0x84,0x00,0x35,0x9b,0x05,0x01,0x5f,0x72,0x05,0x6b,0x4f,0x88,0x88,0x88,
+0x88,0x88,0x81,0x4f,0x81,0x01,0xa6,0x14,0x00,0xde,0x35,0x13,0x00,0xc0,0x35,0x12,
+0x00,0xad,0x35,0x11,0x00,0xde,0x35,0x65,0xc0,0xcd,0x16,0x27,0x85,0x4d,0xba,0xdf,
+0xcd,0x11,0xbe,0x12,0xb6,0x80,0x4b,0x81,0x9a,0x92,0xfa,0xcd,0xa4,0xb7,0x46,0xa9,
+0x41,0x81,0xa4,0xb7,0x00,0xa9,0x41,0x08,0xab,0x81,0x84,0x8b,0x41,0x00,0xa9,0x41,
+0x0b,0xab,0x5b,0x0c,0x6b,0x4f,0x9a,0xaf,0xfa,0xcd,0x30,0xae,0xa4,0x00,0x42,0x35,
+0xa0,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x5b,0x3a,0xfa,0xcd,0xfa,0x26,
+0x5a,0x90,0x59,0x48,0x06,0x27,0x06,0xe6,0x72,0x5f,0x03,0xa6,0x9b,0x01,0x6b,0x30,
+0x42,0xc6,0x02,0x6b,0x31,0x42,0xc6,0x03,0x6b,0x32,0x42,0xc6,0x04,0x6b,0x33,0x42,
+0xc6,0x06,0x6b,0x04,0xab,0x06,0x7b,0xa0,0x24,0x07,0xe1,0x72,0x13,0xb6,0x07,0x6b,
+0x04,0xab,0x07,0x7b,0x63,0xad,0x04,0xab,0x5c,0x01,0x24,0x07,0xeb,0x72,0x52,0x08,
+0xae,0x06,0x7b,0xe6,0xfb,0xcd,0x6d,0xad,0x5b,0x9b,0xce,0x25,0x04,0xa1,0x0c,0x6b,
+0x4c,0x0c,0x7b,0xa4,0xc7,0x92,0x14,0xe6,0x90,0xa5,0xbf,0x05,0x6b,0x4c,0x9f,0x90,
+0x05,0xe6,0x72,0xa4,0x3c,0x02,0x24,0x97,0xa5,0xbb,0x0c,0xe0,0x72,0x03,0xa6,0xa5,
+0xbf,0xf7,0xf0,0xcd,0x5b,0x22,0x25,0x05,0xe1,0x72,0x13,0xb6,0x0c,0x6b,0x08,0x6b,
+0x09,0x6b,0x0a,0x6b,0x0b,0x6b,0x4f,0x57,0x20,0x05,0x6b,0x4f,0xff,0xf0,0xcd,0x00,
+0xab,0x52,0x08,0xae,0x06,0x7b,0xe6,0xfb,0xcd,0xf7,0xf0,0xcd,0x5b,0x9b,0x08,0x6b,
+0x4f,0x09,0x6b,0x13,0xb6,0x0a,0x6b,0x12,0xb6,0x0b,0x6b,0x11,0xb6,0x06,0x6b,0x10,
+0xa6,0x02,0x20,0x0c,0xa6,0x06,0x20,0x08,0xa6,0x0a,0x20,0x04,0xa6,0xeb,0xf0,0xcc,
+0x01,0xa6,0x09,0x27,0x4a,0x08,0x27,0x4a,0x17,0x27,0x4a,0x1c,0x27,0x4a,0x19,0x27,
+0x81,0xa0,0x11,0xb6,0x8b,0x41,0x00,0xa2,0x41,0x0c,0xa0,0x5b,0x81,0x4f,0x81,0xaf,
+0xfa,0xcd,0xb4,0xae,0xa4,0x00,0x84,0x35,0x81,0x10,0x4d,0x00,0x35,0x11,0x4d,0x00,
+0x35,0x12,0x4d,0x00,0x35,0x81,0xe6,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,
+0x81,0x85,0x85,0x85,0x85,0x4f,0x9a,0x31,0x01,0x5f,0x72,0x04,0x20,0x31,0x01,0x01,
+0x35,0x06,0x26,0x91,0xa1,0x11,0xb6,0x06,0x27,0x27,0xa1,0x11,0xb6,0x46,0x01,0x12,
+0x00,0x55,0x47,0x01,0x13,0x00,0x55,0x48,0x01,0x14,0x00,0x55,0x49,0x01,0x15,0x00,
+0x55,0x14,0x48,0x12,0x00,0x55,0x15,0x48,0x13,0x00,0x55,0x16,0x48,0x14,0x00,0x55,
+0x17,0x48,0x15,0x00,0x55,0x42,0x01,0x16,0x00,0x55,0x43,0x01,0x17,0x00,0x55,0x44,
+0x01,0x18,0x00,0x55,0x45,0x01,0x19,0x00,0x55,0x10,0x48,0x16,0x00,0x55,0x11,0x48,
+0x17,0x00,0x55,0x12,0x48,0x18,0x00,0x55,0x13,0x48,0x19,0x00,0x55,0x50,0x26,0x28,
+0xa1,0x11,0xb6,0x56,0x20,0x92,0xfa,0xcd,0xa4,0xb7,0x48,0xa9,0x41,0x44,0xab,0x52,
+0x08,0xae,0x11,0xb6,0x6e,0xfa,0xcd,0x12,0xae,0x92,0xfa,0xcd,0xa4,0xb7,0x48,0xa9,
+0x41,0x40,0xab,0x52,0x08,0xae,0x11,0xb6,0x6e,0xfa,0xcd,0x16,0xae,0x2a,0x24,0x28,
+0xa1,0x11,0xb6,0x11,0xb6,0xb3,0xef,0xcc,0xdb,0xef,0xcd,0x13,0x4d,0x02,0x35,0xdb,
+0xef,0xcd,0x13,0x4d,0x42,0x35,0x0c,0x4d,0x1e,0x00,0x55,0x0d,0x4d,0x1f,0x00,0x55,
+0x0e,0x4d,0x20,0x00,0x55,0x0f,0x4d,0x21,0x00,0x55,0x08,0x4d,0x1a,0x00,0x55,0x09,
+0x4d,0x1b,0x00,0x55,0x0a,0x4d,0x1c,0x00,0x55,0x0b,0x4d,0x1d,0x00,0x55,0x04,0x4d,
+0x16,0x00,0x55,0x05,0x4d,0x17,0x00,0x55,0x06,0x4d,0x18,0x00,0x55,0x07,0x4d,0x19,
+0x00,0x55,0x00,0x4d,0x12,0x00,0x55,0x01,0x4d,0x13,0x00,0x55,0x02,0x4d,0x14,0x00,
+0x55,0x03,0x4d,0x15,0x00,0x55,0xe8,0xef,0xcd,0xa1,0x1a,0xd0,0xef,0xcd,0x5b,0x6a,
+0x24,0x92,0xa1,0x11,0xb6,0x70,0x25,0x80,0xa1,0x11,0xb6,0xe8,0xef,0xcd,0xa3,0xb7,
+0x60,0xaa,0xa3,0xb6,0xd0,0xef,0xcd,0x5b,0x01,0x6b,0xb4,0x84,0xc6,0x02,0x6b,0xb5,
+0x84,0xc6,0x03,0x6b,0xb6,0x84,0xc6,0x04,0x6b,0xb7,0x84,0xc6,0xaf,0xfa,0xcd,0x04,
+0xae,0xa4,0x00,0x48,0x35,0xa3,0x18,0xd0,0xef,0xcd,0x5b,0x01,0x6b,0x04,0x48,0xc6,
+0x02,0x6b,0x05,0x48,0xc6,0x03,0x6b,0x06,0x48,0xc6,0x04,0x6b,0x07,0x48,0xc6,0x9b,
+0x30,0x01,0x01,0x35,0x88,0x88,0x88,0x88,0x81,0x48,0x42,0x00,0x35,0x49,0x42,0x00,
+0x35,0x4a,0x42,0x00,0x35,0x81,0x85,0x85,0x85,0x85,0x4f,0x9a,0xdf,0xe4,0xcd,0x07,
+0x01,0x01,0x35,0xd0,0xde,0xcd,0x03,0x27,0xc3,0x00,0xc6,0x16,0xad,0x4b,0x42,0x01,
+0x35,0x04,0x20,0x4b,0x42,0x05,0x35,0x06,0x26,0x02,0xa1,0x11,0xb6,0x71,0xe3,0xcd,
+0xaf,0xfa,0xcd,0xb4,0xae,0xa4,0x00,0x84,0x35,0xa2,0x16,0xe6,0xfb,0xcd,0xa4,0xb7,
+0x00,0xa9,0x41,0x01,0xab,0x5b,0x01,0x6b,0xb4,0x84,0xc6,0x02,0x6b,0xb5,0x84,0xc6,
+0x03,0x6b,0xb6,0x84,0xc6,0x04,0x6b,0xb7,0x84,0xc6,0xaf,0xd4,0xcd,0x51,0x20,0x5a,
+0xad,0x4b,0x42,0x01,0x35,0x04,0x20,0x4b,0x42,0x05,0x35,0x06,0x26,0x02,0xa1,0x11,
+0xb6,0x14,0x26,0x4a,0x07,0x01,0xc6,0x6b,0x20,0x0a,0xe4,0xcd,0x11,0xe3,0xcd,0x08,
+0x26,0x11,0x3d,0x9b,0x88,0x88,0x88,0x88,0x81,0xaf,0xfa,0xcd,0x78,0xae,0xa4,0x00,
+0x84,0x35,0x81,0x18,0x80,0x00,0x35,0x19,0x80,0x00,0x35,0x1a,0x80,0x00,0x35,0x81,
+0x08,0x80,0x00,0x35,0x09,0x80,0x00,0x35,0x0a,0x80,0x00,0x35,0x81,0xe6,0xfb,0xcd,
+0xa4,0xb7,0x00,0xa9,0x41,0x03,0xab,0x81,0x04,0x80,0x00,0x35,0x05,0x80,0x00,0x35,
+0x06,0x80,0x00,0x35,0x81,0x85,0x85,0x85,0x85,0x85,0x85,0x4f,0x9a,0x0a,0xe4,0xcd,
+0x06,0x01,0x5f,0x72,0xbc,0x84,0x00,0x35,0xbd,0x84,0x00,0x35,0xbe,0x84,0x18,0x35,
+0xbf,0x84,0x00,0x35,0x45,0xad,0x1b,0x80,0x80,0x35,0x14,0x80,0x00,0x35,0x15,0x80,
+0x00,0x35,0x16,0x80,0x00,0x35,0x17,0x80,0x00,0x35,0x4e,0xad,0x0b,0x80,0x00,0x35,
+0x3c,0xad,0x07,0x80,0x00,0x35,0x00,0x80,0x00,0x35,0x01,0x80,0x00,0x35,0x02,0x80,
+0x00,0x35,0x03,0x80,0x00,0x35,0xce,0xed,0xcd,0xa3,0xb7,0xf8,0xa4,0xa3,0xb6,0x68,
+0xad,0x5b,0x03,0x6b,0x78,0x84,0xc6,0x04,0x6b,0x79,0x84,0xc6,0x05,0x6b,0x7a,0x84,
+0xc6,0x06,0x6b,0x7b,0x84,0xc6,0x69,0x20,0xdf,0xe4,0xcd,0x06,0x01,0x01,0x35,0x88,
+0xd3,0xcd,0xbc,0x84,0x00,0x35,0xbd,0x84,0x00,0x35,0xbe,0x84,0x1b,0x35,0xbf,0x84,
+0x40,0x35,0x04,0x20,0xbf,0x84,0x41,0x35,0x06,0x26,0x14,0x3d,0xc1,0xed,0xcd,0x1b,
+0x80,0x81,0x35,0xaf,0xfa,0xcd,0x14,0xae,0xa4,0x00,0x80,0x35,0x3a,0xfa,0xcd,0x52,
+0x80,0xae,0xb4,0xed,0xcd,0x0b,0x80,0x20,0x35,0x04,0x20,0x0b,0x80,0x60,0x35,0x06,
+0x26,0x6a,0x01,0xc7,0x16,0xb6,0x6b,0x01,0x60,0x20,0x55,0x6c,0x01,0x61,0x20,0x55,
+0x6d,0x01,0x62,0x20,0x55,0x6e,0x01,0x63,0x20,0x55,0x68,0x20,0x21,0x35,0x64,0x20,
+0x6b,0x01,0x55,0x65,0x20,0x6c,0x01,0x55,0x66,0x20,0x6d,0x01,0x55,0x67,0x20,0x6e,
+0x01,0x55,0x9d,0x9d,0x68,0x20,0x27,0x35,0x68,0x20,0x52,0x35,0x64,0x20,0x00,0x35,
+0x65,0x20,0x0f,0x35,0x66,0x20,0x42,0x35,0x67,0x20,0x40,0x35,0x68,0x20,0x22,0x35,
+0x60,0x20,0x01,0x01,0x55,0x61,0x20,0x02,0x01,0x55,0x62,0x20,0x03,0x01,0x55,0x63,
+0x20,0x04,0x01,0x55,0x6b,0x01,0x75,0xf3,0x55,0x6c,0x01,0x76,0xf3,0x55,0x6d,0x01,
+0x77,0xf3,0x55,0x6e,0x01,0x78,0xf3,0x55,0x6f,0x01,0xc7,0x70,0x01,0x21,0x35,0x71,
+0x01,0xe6,0x35,0x72,0x01,0xf0,0x35,0x23,0x20,0x6b,0x01,0x79,0xf3,0x55,0x6c,0x01,
+0x7a,0xf3,0x55,0x6d,0x01,0x7b,0xf3,0x55,0x6e,0x01,0x7c,0xf3,0x55,0x6f,0x01,0xc7,
+0x70,0x01,0x21,0x35,0x71,0x01,0xf0,0x35,0x72,0x01,0x7c,0x35,0x48,0x20,0x6b,0x01,
+0x7d,0xf3,0x55,0x6c,0x01,0x7e,0xf3,0x55,0x6d,0x01,0x7f,0xf3,0x55,0x6e,0x01,0x80,
+0xf3,0x55,0x6f,0x01,0xc7,0x70,0x01,0x21,0x35,0x71,0x01,0xf6,0x35,0x72,0x01,0x94,
+0x35,0x6d,0x20,0x9c,0xed,0xcd,0x07,0x80,0xe0,0x35,0x6b,0x01,0x71,0xf3,0x55,0x6c,
+0x01,0x72,0xf3,0x55,0x6d,0x01,0x73,0xf3,0x55,0x6e,0x01,0x74,0xf3,0x55,0x6f,0x01,
+0x5f,0x72,0x70,0x01,0x2a,0x35,0x71,0x01,0x09,0x35,0x72,0x01,0x8b,0x35,0x77,0x27,
+0x4a,0x55,0x27,0x4a,0x33,0x27,0x4a,0x12,0xb6,0x9c,0xed,0xcd,0x07,0x80,0xc0,0x35,
+0xaf,0xfa,0xcd,0x5f,0xa4,0x00,0x80,0x35,0x3a,0xfa,0xcd,0x06,0xaa,0x41,0x01,0xea,
+0x72,0x41,0x02,0xea,0x72,0x5f,0x28,0xaa,0xc0,0xa4,0x52,0x40,0xae,0x12,0xb6,0x01,
+0xef,0x72,0x02,0x6b,0x52,0x10,0xae,0x15,0xb6,0xce,0xed,0xcd,0xa3,0x10,0xa3,0x12,
+0xa3,0x14,0xa9,0xed,0xcd,0x5b,0x03,0x6b,0x78,0x84,0xc6,0x04,0x6b,0x79,0x84,0xc6,
+0x05,0x6b,0x7a,0x84,0xc6,0x06,0x6b,0x7b,0x84,0xc6,0xaf,0xfa,0xcd,0xb4,0xae,0xa4,
+0x00,0x84,0x35,0xa2,0x16,0xa9,0xed,0xcd,0x5b,0x03,0x6b,0xb4,0x84,0xc6,0x04,0x6b,
+0xb5,0x84,0xc6,0x05,0x6b,0xb6,0x84,0xc6,0x06,0x6b,0xb7,0x84,0xc6,0x2a,0xed,0xcc,
+0x03,0x27,0x4a,0x13,0xb6,0x9b,0x88,0x88,0x88,0x88,0x88,0x88,0x81,0x85,0x4f,0x1c,
+0x01,0x5a,0x72,0x9a,0x0c,0x8c,0x00,0x35,0x0d,0x8c,0x00,0x35,0x0e,0x8c,0x00,0x35,
+0x0f,0x8c,0x01,0x35,0x04,0x20,0x0f,0x8c,0x03,0x35,0x06,0x26,0x4a,0x1c,0x01,0xc6,
+0xaf,0xfa,0xcd,0x10,0xae,0xa4,0x00,0x8c,0x35,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,
+0xa3,0x00,0x1d,0x01,0x55,0xaf,0xfa,0xcd,0x1c,0xae,0xa4,0x00,0x8c,0x35,0x3a,0xfa,
+0xcd,0x5f,0x0f,0xa4,0x4e,0x1d,0x01,0xc6,0x9b,0x06,0x20,0xc7,0xfa,0xa4,0x06,0x20,
+0xc6,0x52,0x27,0x1c,0x01,0xc6,0xef,0x25,0x1c,0x01,0xc1,0x01,0x6b,0x4c,0x9f,0x1d,
+0x01,0xd7,0x12,0xe6,0x01,0xee,0x72,0x0a,0x20,0x4f,0x1c,0x01,0xc7,0x11,0xb6,0x88,
+0x81,0x85,0x4f,0x09,0x01,0x5f,0x72,0xef,0x25,0x0a,0x01,0xc1,0x01,0x6b,0x4c,0x9f,
+0x12,0xe7,0x0b,0x01,0xd6,0x01,0xee,0x72,0x0a,0x20,0x4f,0x11,0x00,0x0a,0x01,0x55,
+0x88,0x81,0x4f,0x9a,0xa8,0x84,0x29,0x00,0x55,0xa9,0x84,0x2a,0x00,0x55,0xaa,0x84,
+0x2b,0x00,0x55,0xab,0x84,0x2c,0x00,0x55,0xaf,0xfa,0xcd,0x48,0xae,0xa4,0x00,0x84,
+0x35,0x3a,0xfa,0xcd,0x27,0xbe,0x28,0xb6,0xaf,0xfa,0xcd,0x44,0xae,0xa4,0x00,0x84,
+0x35,0x3a,0xfa,0xcd,0x25,0xbe,0x26,0xb6,0xaf,0xfa,0xcd,0x40,0xae,0xa4,0x00,0x84,
+0x35,0x3a,0xfa,0xcd,0x23,0xbe,0x24,0xb6,0xaf,0xfa,0xcd,0x3c,0xae,0xa4,0x00,0x84,
+0x35,0x3a,0xfa,0xcd,0x21,0xbe,0x22,0xb6,0xaf,0xfa,0xcd,0x38,0xae,0xa4,0x00,0x84,
+0x35,0x3a,0xfa,0xcd,0x1f,0xbe,0x20,0xb6,0xaf,0xfa,0xcd,0x34,0xae,0xa4,0x00,0x84,
+0x35,0x3a,0xfa,0xcd,0x1d,0xbe,0x1e,0xb6,0xaf,0xfa,0xcd,0x30,0xae,0xa4,0x00,0x84,
+0x35,0x3a,0xfa,0xcd,0x1b,0xbe,0x1c,0xb6,0xaf,0xfa,0xcd,0x2c,0xae,0xa4,0x00,0x84,
+0x35,0x3a,0xfa,0xcd,0x19,0xbe,0x1a,0xb6,0xaf,0xfa,0xcd,0x28,0xae,0xa4,0x00,0x84,
+0x35,0x3a,0xfa,0xcd,0x17,0xbe,0x18,0xb6,0xaf,0xfa,0xcd,0x24,0xae,0xa4,0x00,0x84,
+0x35,0x3a,0xfa,0xcd,0x15,0xbe,0x16,0xb6,0xaf,0xfa,0xcd,0x20,0xae,0xa4,0x00,0x84,
+0x35,0x3a,0xfa,0xcd,0x13,0xbe,0x14,0xb6,0xaf,0xfa,0xcd,0x1c,0xae,0xa4,0x00,0x84,
+0x35,0x3a,0xfa,0xcd,0x11,0xbe,0x12,0xb6,0x9b,0x81,0x4f,0x77,0x01,0x01,0x35,0xda,
+0x00,0xcf,0x1f,0xbe,0xdb,0x00,0xc7,0x20,0xb6,0xd8,0x00,0xcf,0x1d,0xbe,0xd9,0x00,
+0xc7,0x1e,0xb6,0xd6,0x00,0xcf,0x1b,0xbe,0xd7,0x00,0xc7,0x1c,0xb6,0xd4,0x00,0xcf,
+0x19,0xbe,0xd5,0x00,0xc7,0x1a,0xb6,0xd2,0x00,0xcf,0x17,0xbe,0xd3,0x00,0xc7,0x18,
+0xb6,0xd0,0x00,0xcf,0x15,0xbe,0xd1,0x00,0xc7,0x16,0xb6,0xce,0x00,0xcf,0x13,0xbe,
+0xcf,0x00,0xc7,0x14,0xb6,0xcc,0x00,0xcf,0x11,0xbe,0xcd,0x00,0xc7,0x12,0xb6,0x81,
+0x4f,0x9a,0xcb,0xcf,0xcd,0xe9,0xd0,0xcd,0x84,0x84,0x84,0x84,0x84,0x84,0x84,0x84,
+0x29,0xd5,0xcd,0x01,0x01,0x3b,0x02,0x01,0x3b,0x03,0x01,0x3b,0x04,0x01,0x3b,0xf3,
+0x00,0x3b,0xf4,0x00,0x3b,0xf5,0x00,0x3b,0xf6,0x00,0x3b,0x15,0xcd,0xcd,0x9b,0xc7,
+0x20,0x9a,0xd0,0xde,0xcd,0x9b,0xce,0x27,0x07,0x01,0xc6,0xc3,0x00,0x01,0x35,0x9a,
+0x99,0xda,0xcd,0x9b,0xf1,0x25,0x01,0xe1,0x72,0x02,0x6b,0x4c,0x02,0x7b,0x9a,0x47,
+0xdd,0xcd,0x9b,0x08,0x20,0x4f,0x01,0x6b,0x12,0xb6,0x02,0x20,0x04,0xa6,0x04,0x26,
+0x02,0xa1,0x11,0xb6,0x81,0x85,0x85,0x4f,0xc3,0x00,0x5f,0x72,0x08,0x27,0x17,0x3d,
+0x88,0x88,0x81,0x85,0x85,0x85,0x85,0x85,0x01,0x7b,0x76,0x01,0x01,0x35,0x9a,0xaf,
+0xfa,0xcd,0xb4,0xae,0xa4,0x00,0x84,0x35,0xa3,0x1f,0xe6,0xfb,0xcd,0xa4,0xb7,0x00,
+0xa9,0x41,0x02,0xab,0x5b,0xb4,0x84,0xc7,0x02,0x7b,0xb5,0x84,0xc7,0x03,0x7b,0xb6,
+0x84,0xc7,0x04,0x7b,0xb7,0x84,0xc7,0x05,0x7b,0x7b,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,
+0x41,0x02,0xab,0x5b,0xa3,0x1e,0xa0,0x3f,0xa1,0x3f,0xa2,0xb7,0x03,0xa4,0xa2,0xb6,
+0xa3,0x3f,0xd7,0xfa,0xcd,0x5f,0x90,0xa7,0x00,0x01,0x35,0x5f,0x12,0xb6,0x04,0x6b,
+0xfc,0xa4,0x04,0x7b,0x02,0x6b,0xb4,0x84,0xc6,0x03,0x6b,0xb5,0x84,0xc6,0x04,0x6b,
+0xb6,0x84,0xc6,0x05,0x6b,0xb7,0x84,0xc6,0x36,0xe2,0xcd,0x1c,0xbe,0x20,0xa6,0x9b,
+0x01,0x01,0x22,0x00,0x55,0x02,0x01,0x23,0x00,0x55,0x03,0x01,0x24,0x00,0x55,0x04,
+0x01,0x25,0x00,0x55,0x14,0x27,0x80,0xfa,0xcd,0x22,0xae,0x00,0x01,0xc7,0x12,0xb6,
+0xbf,0x00,0xc7,0x21,0xb6,0xc0,0x00,0xcf,0x1f,0xbe,0xc1,0x00,0xc7,0x20,0xb6,0xfa,
+0x00,0xcf,0x19,0xbe,0xfb,0x00,0xc7,0x1a,0xb6,0xfe,0x00,0xcf,0x17,0xbe,0xff,0x00,
+0xc7,0x18,0xb6,0xf8,0x00,0xcf,0x15,0xbe,0xf9,0x00,0xc7,0x16,0xb6,0xfc,0x00,0xcf,
+0x13,0xbe,0xfd,0x00,0xc7,0x14,0xb6,0x16,0xe9,0xcc,0x73,0x01,0xc7,0x4c,0x16,0xe9,
+0xcc,0x01,0x6b,0x01,0xa6,0x45,0x27,0x4a,0x11,0x27,0x4a,0x0d,0x27,0x4d,0xbf,0x00,
+0x5f,0x72,0xc1,0x00,0x5f,0x72,0xc0,0x00,0x5f,0x72,0x05,0x01,0xc7,0x11,0xb6,0x01,
+0x6b,0x4f,0x88,0x88,0x88,0x88,0x88,0x81,0x84,0x84,0x84,0x84,0x84,0xdd,0xe6,0xcd,
+0xaf,0x25,0x10,0xa1,0x04,0x6b,0x4c,0x04,0x7b,0xc2,0x25,0x08,0xa1,0x05,0x6b,0x4c,
+0x05,0x7b,0x25,0xe7,0xcd,0x03,0x27,0x5d,0x03,0x26,0x4d,0x41,0x01,0xe4,0x72,0x41,
+0x02,0xe4,0x72,0xfa,0x26,0x5a,0x90,0x59,0x48,0x06,0x27,0x05,0xe6,0x72,0x01,0xa6,
+0x01,0xef,0x72,0x02,0x6b,0x5f,0x03,0x7b,0x4a,0xe7,0xcd,0x03,0x20,0x9d,0xad,0x04,
+0x26,0x05,0x7b,0x08,0x26,0x04,0x7b,0x05,0x6b,0x4f,0x03,0x6b,0x11,0xe6,0x04,0xee,
+0x72,0x04,0x6b,0x4f,0xf5,0x25,0x10,0xa1,0x04,0x6b,0x4c,0x04,0x7b,0x97,0xad,0x04,
+0x6b,0x4f,0x25,0xe7,0xcd,0xdd,0xe6,0xcd,0x07,0xe7,0xcd,0x88,0x88,0x88,0x88,0x88,
+0x81,0xb3,0x84,0x00,0x35,0xb0,0x84,0x00,0x35,0xb1,0x84,0x00,0x35,0x81,0xb0,0x84,
+0x00,0x35,0xb1,0x84,0x00,0x35,0xb2,0x84,0x00,0x35,0x0d,0xad,0xb2,0x84,0x03,0x35,
+0x13,0xad,0xb2,0x84,0x02,0x35,0x19,0xad,0xb2,0x84,0x00,0x35,0xb3,0x84,0x00,0x35,
+0x81,0xb0,0x84,0x00,0x35,0xb1,0x84,0x00,0x35,0xb2,0x84,0x00,0x35,0xb3,0x84,0x00,
+0x35,0x81,0x01,0xad,0xb0,0x84,0x00,0x35,0xb1,0x84,0x00,0x35,0xb2,0x84,0x01,0x35,
+0xb3,0x84,0x00,0x35,0x13,0xad,0x81,0x64,0xa6,0xb0,0x84,0x00,0x35,0xb1,0x84,0x00,
+0x35,0x4b,0xe1,0xcc,0x03,0xad,0xb2,0x84,0x00,0x35,0xb3,0x84,0x00,0x35,0x4b,0xe1,
+0xcd,0x10,0xad,0xb2,0x84,0x04,0x35,0xb3,0x84,0x00,0x35,0x81,0xad,0x84,0x00,0x35,
+0xae,0x84,0x00,0x35,0xaf,0x84,0x00,0x35,0x81,0xac,0x84,0x00,0x35,0x05,0xad,0x81,
+0xac,0x84,0x80,0x35,0x0c,0xad,0x07,0x27,0x4d,0x4b,0xe1,0xcc,0x64,0xa6,0xb0,0x84,
+0x00,0x35,0xb1,0x84,0x00,0x35,0xb2,0x84,0x00,0x35,0xb3,0x84,0x00,0x35,0x4b,0xe1,
+0xcd,0x0a,0xa6,0xb0,0x84,0x00,0x35,0xb1,0x84,0x00,0x35,0xb2,0x84,0x10,0x35,0xb3,
+0x84,0x00,0x35,0x81,0x84,0x84,0x84,0x84,0x75,0x01,0x01,0x35,0xaf,0xfa,0xcd,0x5f,
+0xa4,0x00,0x84,0x35,0xa0,0x1a,0xe6,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,
+0x5b,0x01,0x6b,0x00,0x84,0xc6,0x02,0x6b,0x01,0x84,0xc6,0x03,0x6b,0x02,0x84,0xc6,
+0x04,0x6b,0x03,0x84,0xc6,0x88,0x88,0x88,0x88,0x81,0x84,0x84,0x84,0x84,0xaf,0xfa,
+0xcd,0x5f,0xa4,0x00,0x84,0x35,0xa0,0x1b,0xe6,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,
+0x01,0xab,0x5b,0x01,0x6b,0x00,0x84,0xc6,0x02,0x6b,0x01,0x84,0xc6,0x03,0x6b,0x02,
+0x84,0xc6,0x04,0x6b,0x03,0x84,0xc6,0x88,0x88,0x88,0x88,0x81,0xaf,0xfa,0xcd,0x78,
+0xae,0xa4,0x00,0x84,0x35,0x81,0xe6,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,
+0x81,0x84,0x84,0x84,0x84,0x10,0xad,0xa3,0x1d,0x09,0xad,0x5b,0x17,0xad,0xa3,0x1c,
+0x10,0xad,0x5b,0x01,0x6b,0x78,0x84,0xc6,0x02,0x6b,0x79,0x84,0xc6,0x03,0x6b,0x7a,
+0x84,0xc6,0x04,0x6b,0x7b,0x84,0xc6,0x88,0x88,0x88,0x88,0x81,0xce,0xfa,0xcd,0xc0,
+0x00,0xce,0xc1,0x00,0xc6,0x81,0x84,0x84,0x84,0x84,0xa0,0x84,0xc7,0x01,0x7b,0xa1,
+0x84,0xc7,0x02,0x7b,0xa2,0x84,0xc7,0x03,0x7b,0xa3,0x84,0xc7,0x04,0x7b,0x03,0x6b,
+0x80,0xaa,0x03,0x7b,0x04,0x6b,0x06,0xaa,0x04,0x7b,0x0c,0x20,0x7b,0xfb,0xcd,0xa4,
+0xb7,0x00,0xa9,0x41,0x01,0xab,0x5b,0xa2,0x1e,0x34,0xad,0x11,0x24,0x00,0xa2,0xc0,
+0x00,0xc6,0x06,0xa0,0xc1,0x00,0xc6,0x0c,0x27,0x06,0x01,0xc6,0x22,0x26,0x03,0xa1,
+0x04,0x27,0x02,0xa1,0xbf,0x00,0xc6,0x2d,0x26,0x4a,0x05,0x01,0xc6,0x03,0x6b,0x80,
+0xa4,0x03,0x7b,0x04,0x6b,0x4f,0x01,0x6b,0xa0,0x84,0xc6,0x02,0x6b,0xa1,0x84,0xc6,
+0x03,0x6b,0xa2,0x84,0xc6,0x04,0x6b,0xa3,0x84,0xc6,0x70,0x26,0x03,0xa1,0x04,0x27,
+0x02,0xa1,0xbf,0x00,0xc6,0x7b,0x26,0x4a,0x05,0x01,0xc6,0x11,0x27,0x4a,0x06,0x01,
+0xc6,0xaf,0xfa,0xcd,0x78,0xae,0xa4,0x00,0x84,0x35,0xa0,0x1c,0xe6,0xfb,0xcd,0xa4,
+0xb7,0x00,0xa9,0x41,0x01,0xab,0x5b,0x01,0x6b,0x78,0x84,0xc6,0x02,0x6b,0x79,0x84,
+0xc6,0x03,0x6b,0x7a,0x84,0xc6,0x04,0x6b,0x7b,0x84,0xc6,0x48,0x83,0x00,0x35,0x49,
+0x83,0x00,0x35,0x4a,0x83,0x00,0x35,0x4b,0x83,0x0f,0x35,0x10,0x26,0x4a,0x24,0x83,
+0x00,0x35,0x25,0x83,0x00,0x35,0x26,0x83,0x00,0x35,0x27,0x83,0x00,0x35,0x4d,0x27,
+0x05,0x01,0xc6,0xaf,0xfa,0xcd,0xa4,0xae,0xa4,0x00,0x84,0x35,0xa2,0x1e,0xa0,0x3f,
+0xa1,0x3f,0xa2,0x1f,0x2b,0xe6,0xcd,0x14,0x26,0x03,0xa1,0x04,0x27,0x01,0xa1,0xbf,
+0x00,0xc6,0x1f,0x26,0x4a,0x05,0x01,0xc6,0xaf,0xfa,0xcd,0xa0,0xae,0xa4,0x00,0x84,
+0x35,0xa0,0x1f,0xa2,0x3f,0xa3,0x3f,0x4c,0xfa,0xcd,0x10,0xa6,0xce,0xfa,0xcd,0x5c,
+0x01,0x24,0x02,0xab,0xed,0x00,0xce,0xee,0x00,0xc6,0x0b,0x20,0x78,0x01,0xce,0x79,
+0x01,0xc6,0x2a,0x26,0x4a,0x0b,0x27,0x02,0xa0,0x05,0x01,0xc6,0x7e,0x01,0x5f,0x72,
+0x9f,0xe5,0xcc,0x03,0x27,0x07,0x01,0xc6,0x08,0x27,0x06,0x01,0xc6,0x88,0x88,0x88,
+0x88,0x81,0x84,0x84,0x84,0x84,0xa0,0x84,0xc7,0x01,0x7b,0xa1,0x84,0xc7,0x02,0x7b,
+0xa2,0x84,0xc7,0x03,0x7b,0xa3,0x84,0xc7,0x04,0x7b,0x7b,0xfb,0xcd,0xa4,0xb7,0x00,
+0xa9,0x41,0x01,0xab,0x5b,0xa2,0x1e,0xce,0xfa,0xcd,0xc0,0x00,0xce,0xc1,0x00,0xc6,
+0x03,0x6b,0x80,0xa4,0x03,0x7b,0x04,0x6b,0x4f,0x1f,0x26,0x03,0xa1,0x04,0x27,0x02,
+0xa1,0xbf,0x00,0xc6,0x2a,0x26,0x4a,0x05,0x01,0xc6,0x03,0x6b,0x7f,0xa4,0x03,0x7b,
+0x01,0x6b,0xa0,0x84,0xc6,0x02,0x6b,0xa1,0x84,0xc6,0x03,0x6b,0xa2,0x84,0xc6,0x04,
+0x6b,0xa3,0x84,0xc6,0x5e,0x26,0x06,0x01,0xc6,0x63,0x20,0x24,0x83,0x00,0x35,0x25,
+0x83,0x00,0x35,0x26,0x83,0x02,0x35,0x27,0x83,0x00,0x35,0xa0,0x84,0x00,0x35,0xa1,
+0x84,0x00,0x35,0xa2,0x84,0x00,0x35,0xa3,0x84,0x00,0x35,0xa4,0x84,0x00,0x35,0xa5,
+0x84,0x00,0x35,0xa6,0x84,0x00,0x35,0xa7,0x84,0x00,0x35,0xaf,0xfa,0xcd,0x78,0xae,
+0xa4,0x00,0x84,0x35,0xa0,0x1d,0xe6,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,
+0x5b,0x01,0x6b,0x78,0x84,0xc6,0x02,0x6b,0x79,0x84,0xc6,0x03,0x6b,0x7a,0x84,0xc6,
+0x04,0x6b,0x7b,0x84,0xc6,0x7e,0x01,0xc7,0x5f,0x26,0x06,0x01,0xce,0x64,0x26,0x07,
+0x01,0xc6,0x88,0x88,0x88,0x88,0x81,0xe6,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,
+0xab,0x81,0x84,0x84,0x84,0x84,0x00,0x40,0xc7,0x01,0x7b,0x01,0x40,0xc7,0x02,0x7b,
+0x02,0x40,0xc7,0x03,0x7b,0x03,0x40,0xc7,0x04,0x7b,0xaf,0xfa,0xcd,0x5f,0xa4,0x00,
+0x40,0x35,0xa0,0x1e,0x23,0xad,0x5b,0x04,0x6b,0x02,0xaa,0x04,0x7b,0x06,0x26,0x12,
+0x3d,0x04,0x6b,0x40,0xaa,0x04,0x7b,0x06,0x26,0xf2,0x00,0xc6,0x04,0x6b,0x10,0xaa,
+0x04,0x7b,0x06,0x26,0xf1,0x00,0xc6,0x01,0x6b,0x02,0x6b,0x03,0x6b,0x4f,0x04,0x6b,
+0x01,0xa6,0xaf,0xfa,0xcd,0xb4,0xae,0xa4,0x00,0x84,0x35,0xa3,0x18,0xa2,0x18,0x5e,
+0xad,0x5b,0x01,0x6b,0xb4,0x84,0xc6,0x02,0x6b,0xb5,0x84,0xc6,0x03,0x6b,0xb6,0x84,
+0xc6,0x04,0x6b,0xb7,0x84,0xc6,0x4b,0xe1,0xcd,0xfa,0xa6,0x14,0x45,0x00,0x35,0x15,
+0x45,0x00,0x35,0x16,0x45,0x00,0x35,0x17,0x45,0x02,0x35,0x88,0x88,0x88,0x88,0x81,
+0x01,0x40,0x00,0x35,0x02,0x40,0x00,0x35,0x03,0x40,0x00,0x35,0x81,0x84,0x84,0x84,
+0x84,0x07,0x01,0x5f,0x72,0xaf,0xfa,0xcd,0xb4,0xae,0xa4,0x00,0x84,0x35,0xa2,0x19,
+0xe6,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x5b,0x01,0x6b,0xb4,0x84,0xc6,
+0x02,0x6b,0xb5,0x84,0xc6,0x03,0x6b,0xb6,0x84,0xc6,0x04,0x6b,0xb7,0x84,0xc6,0x14,
+0x45,0x00,0x35,0x15,0x45,0x00,0x35,0x16,0x45,0x00,0x35,0x17,0x45,0x01,0x35,0x00,
+0x40,0x00,0x35,0x47,0xad,0x00,0x40,0x80,0x35,0x4d,0xad,0x88,0x88,0x88,0x88,0x81,
+0x00,0x88,0x00,0x35,0x01,0x88,0x00,0x35,0x02,0x88,0x00,0x35,0x81,0xa2,0x14,0xa3,
+0x14,0xa0,0x3f,0xa1,0x3f,0xa2,0xb7,0x01,0xa4,0xa2,0xb6,0xa3,0xb7,0xf8,0xa4,0xa3,
+0xb6,0xee,0xf9,0xcd,0x08,0xae,0x90,0x5f,0x26,0xb6,0x81,0x84,0x84,0x21,0xad,0x03,
+0x88,0x01,0x35,0x08,0x88,0x00,0x35,0x09,0x88,0x30,0x35,0x0a,0x88,0x00,0x35,0x0b,
+0x88,0x00,0x35,0xaf,0xfa,0xcd,0x0c,0xae,0xa4,0x00,0x88,0x35,0xa3,0x1e,0xa0,0xb7,
+0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x07,0xa4,0x01,0x7b,0x18,0x88,0x00,0x35,0x19,
+0x88,0x00,0x35,0x1a,0x88,0xff,0x35,0x1b,0x88,0xff,0x35,0x14,0x88,0x00,0x35,0x15,
+0x88,0x00,0x35,0x16,0x88,0xff,0x35,0x17,0x88,0xff,0x35,0x10,0x88,0x00,0x35,0x11,
+0x88,0x5f,0x35,0x12,0x88,0xff,0x35,0x13,0x88,0xff,0x35,0x04,0xe3,0xcd,0x03,0x88,
+0x00,0x35,0xac,0x84,0x00,0x35,0xad,0x84,0x00,0x35,0xae,0x84,0x00,0x35,0xaf,0x84,
+0x20,0x35,0xaf,0xfa,0xcd,0x7c,0xae,0xa4,0x00,0x84,0x35,0xa0,0x14,0xa1,0x1a,0xa1,
+0x10,0xe6,0xe2,0xcd,0x09,0x20,0xa1,0x1a,0xa1,0x10,0xe6,0xe2,0xcd,0x12,0x20,0xa1,
+0x10,0xe6,0xe2,0xcd,0x19,0x20,0xe6,0xe2,0xcd,0x27,0x20,0x17,0x27,0x4a,0x11,0x27,
+0x4a,0x0d,0x27,0x4a,0x0b,0x27,0x4a,0x9f,0x89,0x88,0x81,0xac,0x84,0x00,0x35,0xad,
+0x84,0x00,0x35,0xae,0x84,0x00,0x35,0xaf,0x84,0x00,0x35,0x7c,0x84,0x00,0x35,0x7d,
+0x84,0x00,0x35,0x7e,0x84,0x00,0x35,0x7f,0x84,0x00,0x35,0x00,0x88,0x00,0x35,0x01,
+0x88,0x00,0x35,0x02,0x88,0x00,0x35,0x03,0x88,0x00,0x35,0x05,0x01,0x5f,0x72,0x73,
+0x01,0x5f,0x72,0x81,0xe6,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x03,0xab,0xaf,0xfa,
+0xcc,0x5f,0xa4,0x00,0x84,0x35,0xa0,0x00,0x30,0x35,0x0c,0xad,0x5b,0xaf,0xfa,0xcd,
+0x5f,0xa4,0x00,0x84,0x35,0xa0,0x1a,0xa0,0x3f,0x1b,0xad,0x5b,0x81,0xa0,0x3f,0xe6,
+0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x03,0xab,0xaf,0xfa,0xcc,0x5f,0xa4,0x00,0x84,
+0x35,0xa0,0x18,0x0a,0xad,0x5b,0xaf,0xfa,0xcd,0x5f,0xa4,0x00,0x84,0x35,0x15,0xad,
+0x5b,0x81,0x85,0x90,0x85,0x90,0x01,0xee,0x72,0x02,0x7b,0x05,0x20,0x05,0xee,0x72,
+0x06,0x7b,0x07,0x24,0x05,0xe2,0x72,0x9f,0x06,0xe0,0x72,0x89,0x88,0x81,0x85,0x90,
+0x85,0x90,0x05,0xee,0x72,0x06,0x7b,0x05,0x20,0x01,0xee,0x72,0x02,0x7b,0x07,0x24,
+0x05,0xe2,0x72,0x9f,0x06,0xe0,0x72,0x89,0x88,0x81,0x84,0x84,0xe9,0x26,0xa4,0xb6,
+0xed,0x26,0x5d,0x01,0x6b,0x00,0xa2,0xa4,0xb7,0x01,0x7b,0x02,0x6b,0x01,0xa0,0x97,
+0x02,0x7b,0x9d,0x01,0x20,0x01,0xef,0x72,0x02,0x6b,0x23,0xfa,0xcd,0x03,0xae,0x90,
+0xa7,0x3f,0x5f,0x88,0x88,0x81,0x41,0x20,0x40,0x35,0x48,0x20,0x5f,0x72,0x46,0x20,
+0x5f,0x72,0x45,0x20,0xd8,0x35,0x81,0x9a,0x68,0x01,0xcf,0x69,0x01,0xc7,0x9b,0xcd,
+0x20,0x4f,0xd3,0x25,0x02,0xa1,0x02,0x7b,0x11,0xe7,0x01,0x7b,0x02,0x6b,0x4c,0x9f,
+0x02,0xee,0x72,0x01,0x6b,0x53,0x20,0xc6,0x50,0x20,0x12,0x72,0x04,0x26,0x4a,0x50,
+0x20,0x15,0x72,0x04,0x26,0x02,0x7b,0xf3,0x26,0x4d,0x41,0xdf,0xcd,0x88,0xa6,0x81,
+0x85,0x85,0x01,0xa6,0x05,0x27,0x4d,0x9e,0xdf,0xcd,0x41,0xa6,0x08,0x26,0x4d,0x89,
+0xdf,0xcd,0x02,0x6b,0x4f,0xae,0x00,0x5f,0x72,0x50,0x20,0x20,0x35,0x52,0x20,0x07,
+0x35,0x88,0x88,0x81,0x4d,0x41,0xdf,0xcd,0x88,0xa6,0x50,0x20,0x20,0x35,0x53,0x20,
+0xc7,0xde,0x20,0x50,0x20,0x12,0x72,0xe2,0x26,0x08,0xad,0x05,0x7b,0x4b,0xe1,0xcd,
+0x05,0xa6,0xed,0x26,0x13,0xad,0x02,0x7b,0xf3,0x26,0x4d,0x41,0xdf,0xcd,0x88,0xa6,
+0x81,0x85,0x85,0x01,0xa6,0x05,0x27,0x4d,0x9e,0xdf,0xcd,0x01,0x7b,0x08,0x26,0x4d,
+0x89,0xdf,0xcd,0xae,0x00,0x5f,0x72,0x50,0x20,0x20,0x35,0x52,0x20,0x07,0x35,0x89,
+0x88,0x81,0x4d,0x41,0xdf,0xcd,0x88,0xa6,0xda,0xdf,0xcc,0x4f,0x4b,0xe1,0xcd,0x05,
+0xa6,0x9d,0x25,0x06,0xe1,0x72,0x01,0x7b,0x4e,0x01,0xd7,0x53,0x20,0xc6,0x01,0x6b,
+0x08,0x20,0x11,0xe7,0x53,0x20,0xc6,0x01,0x6b,0x09,0x25,0x4c,0x9f,0x01,0xee,0x72,
+0x09,0xa1,0x06,0x7b,0x50,0x20,0x22,0x35,0x04,0x26,0xa8,0xb1,0xa8,0xbf,0x90,0x0b,
+0x26,0xa7,0xb3,0xa7,0x3f,0x01,0xe6,0x72,0x4a,0x5a,0x01,0x26,0x4d,0x5f,0x06,0x7b,
+0x50,0x20,0x15,0x72,0x04,0x26,0xa8,0xb1,0xa8,0xbf,0x90,0x0b,0x26,0xa7,0xb3,0xa7,
+0x3f,0x01,0xe6,0x72,0x5a,0x01,0x24,0x02,0xa0,0x5f,0x1a,0x25,0x02,0xa1,0x06,0x7b,
+0xb8,0x26,0x6a,0xad,0x50,0x20,0x15,0x72,0x04,0x26,0x4a,0x06,0x7b,0xc5,0x26,0x4d,
+0x8e,0xad,0x01,0xaa,0x02,0x7b,0xce,0x26,0x4d,0x82,0xad,0x4b,0xe1,0xcd,0x05,0xa6,
+0xd8,0x26,0x88,0xe0,0xcd,0x50,0x20,0x20,0x35,0x53,0x20,0xc7,0x03,0x7b,0x02,0x20,
+0x52,0x80,0xae,0x03,0x7b,0x07,0x27,0x70,0xa1,0xf0,0xa4,0x02,0x7b,0xf5,0x26,0x88,
+0xe0,0xcd,0x81,0x85,0x85,0x85,0x01,0xa6,0x06,0x27,0x4d,0xc9,0xad,0x02,0x7b,0x07,
+0x26,0x4d,0xbb,0xad,0xae,0x00,0x5f,0x72,0x01,0x6b,0x4f,0x50,0x20,0x20,0x35,0x52,
+0x20,0x07,0x35,0x88,0x89,0x88,0x81,0x4f,0x50,0x20,0x24,0x35,0x4b,0xe1,0xcd,0x05,
+0xa6,0x81,0x01,0xa6,0x03,0x27,0x4d,0xb7,0xad,0x82,0xa6,0x50,0x20,0x21,0x35,0x53,
+0x20,0xc7,0x81,0x4f,0x4b,0xe1,0xcd,0x05,0xa6,0x81,0x01,0xa6,0x03,0x27,0x4d,0xcf,
+0xad,0x81,0xa6,0x50,0x20,0x29,0x35,0x81,0x85,0x4f,0xae,0x00,0x5f,0x72,0x81,0x85,
+0x01,0xa6,0xae,0x00,0x5f,0x72,0x50,0x20,0x22,0x35,0x0c,0xae,0x00,0x0d,0x72,0x05,
+0x26,0x01,0xe1,0x72,0x01,0xe4,0x72,0xfa,0x27,0xae,0x00,0xc6,0x8f,0x01,0x20,0x88,
+0x81,0x85,0x4f,0x81,0x85,0x01,0xa6,0x50,0x20,0x05,0x35,0x08,0x27,0x01,0xe1,0x72,
+0x01,0xe4,0x72,0x51,0x20,0xc6,0xfa,0x51,0x20,0x0f,0x72,0x9d,0x01,0x20,0x88,0x81,
+0x44,0x42,0x00,0x35,0x45,0x42,0x00,0x35,0x46,0x42,0x00,0x35,0x47,0x42,0x00,0x35,
+0x00,0x42,0x00,0x35,0x01,0x42,0x00,0x35,0x02,0x42,0x01,0x35,0x03,0x42,0x01,0x35,
+0x10,0x20,0x00,0x42,0x08,0x35,0x01,0x42,0x00,0x35,0x02,0x42,0x01,0x35,0x03,0x42,
+0x00,0x35,0x12,0x26,0x4a,0xc2,0x00,0xc6,0x20,0x40,0x00,0x35,0x21,0x40,0x00,0x35,
+0x22,0x40,0x00,0x35,0x23,0x40,0x01,0x35,0x04,0x44,0xc4,0x00,0x55,0x05,0x44,0xc5,
+0x00,0x55,0x06,0x44,0xc6,0x00,0x55,0x07,0x44,0xc7,0x00,0x55,0x00,0x44,0xc8,0x00,
+0x55,0x01,0x44,0xc9,0x00,0x55,0x02,0x44,0xca,0x00,0x55,0x03,0x44,0xcb,0x00,0x55,
+0x81,0x92,0xfa,0xcd,0xa0,0x3f,0xa1,0x3f,0xa2,0x3f,0x81,0x92,0xfa,0xcd,0xa4,0xb7,
+0x01,0xaa,0x41,0x81,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x81,0xa4,0xc6,
+0x92,0xa5,0xbf,0xa4,0xb7,0x81,0x1c,0xad,0xa3,0x3f,0xa4,0xb7,0x01,0xaa,0x81,0x84,
+0x84,0x84,0xdf,0x26,0x03,0xe1,0x72,0x12,0xad,0x02,0xaa,0x41,0x03,0xaa,0x01,0xee,
+0x72,0x02,0x7b,0x92,0xfa,0xcd,0xa4,0xb7,0x02,0xaa,0x01,0x7b,0x02,0xee,0x72,0x32,
+0xad,0x03,0x7b,0x10,0x20,0x03,0x6b,0x03,0xa6,0x02,0x20,0x83,0xa6,0x04,0x26,0x02,
+0xa1,0x11,0xb6,0x59,0xad,0xa3,0x00,0x3d,0x35,0x02,0xee,0x72,0xa4,0xb7,0x01,0x7b,
+0x66,0xad,0xa3,0x00,0x08,0x35,0xa4,0xb7,0x02,0xaa,0x41,0x24,0xaa,0x01,0xee,0x72,
+0x02,0x7b,0x54,0xad,0x41,0x1c,0xaa,0x01,0xee,0x72,0x02,0x7b,0x5e,0xad,0x41,0x18,
+0xaa,0x01,0xee,0x72,0x02,0x7b,0x68,0xad,0x41,0x14,0xaa,0x01,0xee,0x72,0x02,0x7b,
+0xdf,0x26,0x03,0xe1,0x72,0xab,0xde,0xcd,0x01,0xaa,0x41,0x13,0xaa,0x01,0xee,0x72,
+0x02,0x7b,0xbd,0xde,0xcd,0x10,0xaa,0x01,0xee,0x72,0x02,0x7b,0xb3,0xde,0xcd,0x03,
+0x7b,0x0f,0x20,0x03,0x6b,0xcf,0xa6,0x02,0x20,0x0f,0xa6,0x06,0x20,0x0c,0xa6,0x08,
+0x20,0x06,0x27,0x4a,0x05,0x27,0x14,0xb6,0xda,0x26,0x03,0xe1,0x72,0xab,0xde,0xcd,
+0x01,0xaa,0x41,0x0d,0xaa,0x01,0xee,0x72,0x02,0x7b,0xbd,0xde,0xcd,0x0c,0xaa,0x01,
+0xee,0x72,0x02,0x7b,0x4c,0xfa,0xcd,0x10,0xa6,0xb3,0xde,0xcd,0x03,0x7b,0x14,0x20,
+0x03,0x6b,0xfc,0xa6,0x02,0x20,0xf0,0xa6,0x06,0x20,0xcc,0xa6,0x0a,0x20,0xc0,0xa6,
+0x0e,0x20,0x0c,0xa6,0x12,0x20,0x0f,0xa6,0x04,0x20,0x16,0x27,0x4a,0x15,0x27,0x4a,
+0x14,0x27,0x4a,0x13,0x27,0x4a,0x12,0x27,0x4a,0x27,0x27,0x4a,0x14,0x27,0x13,0xb6,
+0xd1,0x26,0x03,0xe1,0x72,0xab,0xde,0xcd,0x01,0xaa,0x41,0x0b,0xaa,0x01,0xee,0x72,
+0x02,0x7b,0xbd,0xde,0xcd,0x08,0xaa,0x01,0xee,0x72,0x02,0x7b,0xa0,0xb7,0x03,0xaa,
+0xa0,0xb6,0xa1,0xb7,0xc3,0xaa,0xa0,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x03,0x7b,0x1d,
+0x20,0x03,0x6b,0x4f,0x01,0x20,0x0c,0xa6,0x04,0x27,0x15,0x3d,0xa2,0xde,0xcd,0x41,
+0x04,0xaa,0x01,0xee,0x72,0x02,0x7b,0xa2,0xde,0xcd,0x01,0x6b,0x02,0xef,0x72,0x50,
+0xaa,0x41,0x4f,0x58,0x58,0x97,0x88,0x88,0x88,0x81,0xe6,0xfb,0xcd,0xc8,0xae,0xa4,
+0x00,0x00,0x35,0x81,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x81,0x4d,0x5f,
+0x12,0xb6,0x81,0xa4,0xb7,0x00,0xa9,0x41,0x07,0xab,0x81,0xc8,0x00,0x00,0x35,0xc9,
+0x00,0x00,0x35,0xca,0x00,0x18,0x35,0x81,0xa0,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,
+0x01,0xab,0x81,0xa0,0xb7,0x03,0xa4,0xa0,0xb6,0xa1,0x3f,0xa2,0x3f,0xa3,0x3f,0x4c,
+0xfa,0xcd,0x18,0xa6,0x3a,0xfa,0xcd,0x4a,0x81,0x3c,0xad,0x18,0xa4,0x48,0x48,0x48,
+0x4a,0x12,0xb6,0xaf,0xfa,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x81,0x8b,0x41,
+0x00,0xa9,0x41,0x0a,0xab,0x5b,0xaf,0xfa,0xcd,0x0c,0xae,0xa4,0x00,0x84,0x35,0xa3,
+0x36,0xa2,0x36,0xa1,0x36,0xa0,0x34,0x74,0xad,0x0a,0x20,0xa0,0x39,0xa1,0x39,0xa2,
+0x39,0xa3,0x38,0x3d,0xdd,0xcd,0x0d,0x26,0x02,0xa1,0x11,0xb6,0x84,0x84,0x84,0x84,
+0x84,0xda,0xd6,0xcd,0x88,0x0b,0x7b,0x88,0x0b,0x7b,0x88,0x0b,0x7b,0x88,0x0b,0x7b,
+0x88,0x06,0x7b,0x06,0x6b,0x44,0x44,0x06,0x7b,0x5c,0xfb,0xcd,0x02,0xa6,0x26,0xdd,
+0xcd,0x5b,0x0f,0x26,0x02,0xa1,0x11,0xb6,0x06,0x6b,0x08,0xa6,0x07,0x6b,0x4f,0x08,
+0x6b,0xbb,0xa6,0x09,0x6b,0x80,0xa6,0x0a,0x6b,0xc8,0x00,0x00,0x35,0xc9,0x00,0x00,
+0x35,0xca,0x00,0x60,0x35,0xcb,0x00,0x00,0x35,0x18,0x20,0xac,0xa6,0x09,0x6b,0x44,
+0xa6,0x0a,0x6b,0xc8,0x00,0x00,0x35,0xc9,0x00,0x00,0x35,0xca,0x00,0x62,0x35,0xcb,
+0x00,0x00,0x35,0x39,0x20,0x10,0xa6,0x07,0x6b,0x4f,0x08,0x6b,0x5d,0xa6,0x09,0x6b,
+0xc0,0xa6,0x0a,0x6b,0xc8,0x00,0x00,0x35,0xc9,0x00,0x00,0x35,0xca,0x00,0x30,0x35,
+0xcb,0x00,0x00,0x35,0x18,0x20,0x56,0xa6,0x09,0x6b,0x22,0xa6,0x0a,0x6b,0xc8,0x00,
+0x00,0x35,0xc9,0x00,0x00,0x35,0xca,0x00,0x31,0x35,0xcb,0x00,0x00,0x35,0x74,0x20,
+0x20,0xa6,0x07,0x6b,0x4f,0x08,0x6b,0x2e,0xa6,0x09,0x6b,0xe0,0xa6,0x0a,0x6b,0x19,
+0xdd,0xcd,0xcb,0x00,0x00,0x35,0x86,0xdc,0xcc,0x20,0xa6,0x07,0x6b,0x4f,0x08,0x6b,
+0x2b,0xa6,0x09,0x6b,0x11,0xa6,0x0a,0x6b,0x19,0xdd,0xcd,0xcb,0x00,0x80,0x35,0x86,
+0xdc,0xcc,0x20,0xa6,0x07,0x6b,0x4f,0x08,0x6b,0x1f,0xa6,0x09,0x6b,0x40,0xa6,0x0a,
+0x6b,0xc8,0x00,0x00,0x35,0xc9,0x00,0x00,0x35,0xca,0x00,0x10,0x35,0xcb,0x00,0x00,
+0x35,0x86,0xdc,0xcc,0x20,0xa6,0x07,0x6b,0x4f,0x08,0x6b,0x2e,0xa6,0x09,0x6b,0xe0,
+0xa6,0x0a,0x6b,0x4f,0x19,0xdd,0xcd,0xcb,0x00,0x00,0x35,0x67,0xdc,0xcc,0x03,0x26,
+0x4a,0x4d,0xdc,0xcc,0x03,0x26,0x4a,0x2c,0xdc,0xcc,0x03,0x26,0x4a,0x12,0xdc,0xcc,
+0x03,0x26,0x4a,0x6d,0x27,0x4a,0x57,0x27,0x4a,0x38,0x27,0x13,0xb6,0xaf,0xfa,0xcd,
+0xa4,0xbf,0x84,0xae,0xa3,0x1a,0xe6,0xfb,0xcd,0x26,0xdd,0xcd,0x5b,0x7b,0xfb,0xcd,
+0x26,0xdd,0xcd,0x5b,0xa1,0x1c,0x0e,0xdd,0xcd,0x5b,0xe3,0xdc,0xcd,0x5b,0xf8,0xdc,
+0xcd,0x5a,0x01,0x26,0x2e,0xdd,0xcd,0x13,0x20,0xa3,0x10,0x0e,0xdd,0xcd,0x5b,0xe3,
+0xdc,0xcd,0x5b,0xf8,0xdc,0xcd,0x5a,0x01,0x26,0x2e,0xdd,0xcd,0x15,0x26,0x4a,0x11,
+0xb6,0x34,0x20,0x08,0x6b,0x40,0xaa,0x08,0x7b,0x0a,0x6b,0x02,0xaa,0x0a,0x7b,0x0e,
+0x26,0x02,0xa1,0x11,0xb6,0x41,0x20,0x0e,0xdd,0xcd,0x5b,0xe3,0xdc,0xcd,0x5b,0xf8,
+0xdc,0xcd,0x5a,0x01,0x26,0x2e,0xdd,0xcd,0x54,0x20,0xa3,0x10,0xa1,0x1c,0x0e,0xdd,
+0xcd,0x5b,0xe3,0xdc,0xcd,0x5b,0xf8,0xdc,0xcd,0x5a,0x01,0x26,0x2e,0xdd,0xcd,0x17,
+0x26,0x4a,0x11,0xb6,0x77,0x20,0x0a,0x6b,0x02,0xaa,0x0a,0x7b,0x08,0x26,0x02,0xa1,
+0x11,0xb6,0x0a,0x6b,0x04,0xaa,0x0a,0x7b,0x43,0x27,0x16,0x3d,0xaf,0xfa,0xcd,0x26,
+0xdd,0xcd,0x5b,0xa2,0x1e,0xa0,0x3f,0xa1,0xb7,0x3e,0xa4,0xa1,0xb6,0xa2,0x3f,0xa3,
+0x3f,0x4c,0xfa,0xcd,0x11,0xa6,0x33,0xdd,0xcd,0x05,0x7b,0xc2,0x00,0xc7,0x12,0xb6,
+0x02,0x20,0x04,0xa6,0x04,0x26,0x02,0xa1,0x11,0xb6,0x05,0x6b,0x18,0xa6,0x02,0x20,
+0x14,0xa6,0x06,0x20,0x10,0xa6,0x08,0x20,0x06,0x27,0x4a,0x05,0x27,0x14,0xb6,0x8b,
+0x41,0x00,0xa2,0x41,0x0a,0xa0,0x5b,0x00,0x00,0xba,0x42,0x00,0x00,0xb8,0x41,0x0a,
+0xd7,0x23,0x3c,0x00,0x00,0x80,0x3f,0x81,0xe6,0xfb,0xcd,0xb7,0xae,0xa4,0x00,0x00,
+0x35,0x81,0xa4,0xb7,0x00,0xa9,0x41,0x17,0xab,0x81,0xa4,0x00,0x80,0x35,0xa0,0xb7,
+0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x81,0x8b,0x41,0x00,0xa9,0x41,0x1c,0xab,0x5b,
+0x20,0x80,0x00,0x35,0x21,0x80,0x00,0x35,0x22,0x80,0x00,0x35,0x23,0x80,0x40,0x35,
+0xaf,0xfa,0xcd,0x30,0xae,0x1e,0xad,0x16,0x7b,0xaf,0xfa,0xcd,0x2c,0xae,0x27,0xad,
+0x15,0x7b,0xaf,0xfa,0xcd,0x28,0xae,0x30,0xad,0x14,0x7b,0x33,0xfb,0xcd,0xa4,0xb7,
+0x00,0xa9,0x41,0x13,0xab,0x5b,0xe6,0xfb,0xcd,0x6f,0xae,0xa4,0x00,0x01,0x35,0x13,
+0x6b,0x60,0x20,0xc6,0x14,0x6b,0x61,0x20,0xc6,0x15,0x6b,0x62,0x20,0xc6,0x16,0x6b,
+0x63,0x20,0xc6,0x68,0x20,0x26,0x35,0x68,0x20,0x21,0x35,0x68,0x20,0x52,0x35,0x64,
+0x20,0xc7,0x0d,0x7b,0x65,0x20,0xc7,0x0e,0x7b,0x66,0x20,0xc7,0x0f,0x7b,0x67,0x20,
+0xc7,0x10,0x7b,0x60,0x20,0x6b,0x01,0x55,0x61,0x20,0x6c,0x01,0x55,0x62,0x20,0x6d,
+0x01,0x55,0x63,0x20,0x6e,0x01,0x55,0xaf,0xfa,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x0d,
+0xab,0x5b,0xc3,0xfb,0xcd,0x77,0xda,0xcd,0x5b,0x7f,0xda,0xcd,0xf0,0x27,0x1b,0xea,
+0x72,0x1c,0x7b,0xf7,0x26,0x4a,0x6a,0x01,0xc6,0x60,0xda,0xcc,0x03,0x27,0x4a,0x06,
+0x01,0xc6,0x84,0x84,0x84,0x84,0xd4,0xe1,0xcd,0x88,0x1a,0x7b,0x88,0x1a,0x7b,0x88,
+0x1a,0x7b,0x88,0x1a,0x7b,0x0f,0x20,0xaf,0xe1,0xcd,0x88,0x1a,0x7b,0x88,0x1a,0x7b,
+0x88,0x1a,0x7b,0x88,0x1a,0x7b,0x11,0x27,0x7c,0x01,0xc6,0x7e,0x01,0x5f,0x72,0x04,
+0x20,0x33,0xfb,0xcd,0x77,0xda,0xcd,0x5b,0x7f,0xda,0xcd,0x0c,0x2b,0xff,0xa2,0x11,
+0x7b,0xfd,0xa0,0x12,0x7b,0x0a,0x2b,0x00,0xa2,0x11,0x7b,0x04,0xa0,0x12,0x6b,0x18,
+0x7b,0x11,0x6b,0x17,0x7b,0x17,0x6b,0x60,0x20,0xc6,0x18,0x6b,0x61,0x20,0xc6,0x19,
+0x6b,0x62,0x20,0xc6,0x1a,0x6b,0x63,0x20,0xc6,0x68,0x20,0x26,0x35,0x68,0x20,0x24,
+0x35,0x64,0x20,0xaf,0x00,0x55,0x65,0x20,0xb0,0x00,0x55,0x66,0x20,0xb1,0x00,0x55,
+0x67,0x20,0xb2,0x00,0x55,0x68,0x20,0x21,0x35,0x64,0x20,0xc7,0x05,0x7b,0x65,0x20,
+0xc7,0x06,0x7b,0x66,0x20,0xc7,0x07,0x7b,0x67,0x20,0xc7,0x08,0x7b,0x60,0x20,0xb3,
+0x00,0x55,0x61,0x20,0xb4,0x00,0x55,0x62,0x20,0xb5,0x00,0x55,0x63,0x20,0xb6,0x00,
+0x55,0xaf,0x00,0x60,0x20,0x55,0xb0,0x00,0x61,0x20,0x55,0xb1,0x00,0x62,0x20,0x55,
+0xb2,0x00,0x63,0x20,0x55,0x68,0x20,0x21,0x35,0x64,0x20,0xc7,0x01,0x7b,0x65,0x20,
+0xc7,0x02,0x7b,0x66,0x20,0xc7,0x03,0x7b,0x67,0x20,0xc7,0x04,0x7b,0xb3,0x00,0x64,
+0x20,0x55,0xb4,0x00,0x65,0x20,0x55,0xb5,0x00,0x66,0x20,0x55,0xb6,0x00,0x67,0x20,
+0x55,0x68,0x20,0x64,0x35,0x64,0x20,0xb3,0x00,0x55,0x65,0x20,0xb4,0x00,0x55,0x66,
+0x20,0xb5,0x00,0x55,0x67,0x20,0xb6,0x00,0x55,0x68,0x20,0x21,0x35,0x64,0x20,0xc7,
+0x09,0x7b,0x65,0x20,0xc7,0x0a,0x7b,0x66,0x20,0xc7,0x0b,0x7b,0x67,0x20,0xc7,0x0c,
+0x7b,0x68,0x20,0x22,0x35,0xaf,0xfa,0xcd,0x60,0xae,0xa4,0x00,0x20,0x35,0x3a,0xfa,
+0xcd,0x1b,0xee,0x72,0x1c,0x7b,0x85,0xd9,0xcc,0x03,0x26,0x1b,0xea,0x72,0x1c,0x7b,
+0xaf,0xfa,0xcd,0x77,0xda,0xcd,0x5b,0xa0,0x3f,0xe6,0xfb,0xcd,0x5f,0xa4,0x00,0x84,
+0x35,0xaf,0xfa,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x09,0xab,0x5b,0xe6,0xfb,0xcd,0x89,
+0xae,0xa4,0x00,0xda,0x35,0x06,0x20,0x8d,0xae,0xa4,0x00,0xda,0x35,0x08,0x26,0x4c,
+0x1b,0x01,0xc6,0x05,0x6b,0x91,0xda,0xc6,0x06,0x6b,0x92,0xda,0xc6,0x07,0x6b,0x93,
+0xda,0xc6,0x08,0x6b,0x94,0xda,0xc6,0x01,0x6b,0x95,0xda,0xc6,0x02,0x6b,0x96,0xda,
+0xc6,0x03,0x6b,0x97,0xda,0xc6,0x04,0x6b,0x98,0xda,0xc6,0x8b,0x41,0x00,0xa2,0x41,
+0x1a,0xa0,0x5b,0x89,0x88,0x81,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x81,
+0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x81,0x84,0x84,0x84,0x84,0xaf,0xfa,0xcd,0x10,
+0xae,0xa4,0x00,0x84,0x35,0xa1,0x1e,0xe6,0xfb,0xcd,0x13,0xad,0x5b,0x10,0x84,0xc7,
+0x01,0x7b,0x11,0x84,0xc7,0x02,0x7b,0x12,0x84,0xc7,0x03,0x7b,0x13,0x84,0xc7,0x04,
+0x7b,0x02,0x6b,0x7f,0xa4,0x02,0x7b,0xaf,0xfa,0xcd,0x33,0xad,0x5b,0xa0,0xfb,0xcd,
+0xa4,0xb7,0x00,0xa9,0x41,0x07,0xab,0x5b,0xa0,0xb7,0x03,0xa4,0xa0,0xb6,0xa1,0x3f,
+0xa2,0x3f,0xa3,0x3f,0xe6,0xfb,0xcd,0x50,0xad,0x5b,0x01,0x6b,0x10,0x84,0xc6,0x02,
+0x6b,0x11,0x84,0xc6,0x03,0x6b,0x12,0x84,0xc6,0x04,0x6b,0x13,0x84,0xc6,0x7b,0xfb,
+0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x07,0xab,0x5b,0x4c,0xfa,0xcd,0x14,0xa6,0x01,0xd8,
+0xcd,0x0b,0x6b,0x4c,0x01,0x20,0x06,0xa6,0x05,0x20,0x02,0xa6,0x09,0x20,0x04,0xa6,
+0x0d,0x20,0x07,0xa6,0x10,0x27,0x10,0xa0,0x10,0x27,0x08,0xa0,0x10,0x27,0x04,0xa0,
+0x10,0x27,0x02,0xa0,0x21,0x27,0x02,0xa0,0x0b,0x7b,0x07,0x6b,0x60,0x20,0xc6,0x08,
+0x6b,0x61,0x20,0xc6,0x09,0x6b,0x62,0x20,0xc6,0x0a,0x6b,0x63,0x20,0xc6,0x68,0x20,
+0x26,0x35,0x68,0x20,0x21,0x35,0x68,0x20,0x52,0x35,0x64,0x20,0x00,0x35,0x65,0x20,
+0x00,0x35,0x66,0x20,0x80,0x35,0x67,0x20,0x00,0x35,0x9d,0x9d,0x68,0x20,0x27,0x35,
+0x60,0x20,0xbb,0x00,0x55,0x61,0x20,0xbc,0x00,0x55,0x62,0x20,0xbd,0x00,0x55,0x63,
+0x20,0xbe,0x00,0x55,0x68,0x20,0x61,0x35,0x68,0x20,0x52,0x35,0xaf,0xfa,0xcd,0x64,
+0xae,0xa4,0x00,0x20,0x35,0x01,0xd8,0xcd,0x0b,0x7b,0x68,0x20,0x22,0x35,0x60,0x20,
+0xc7,0x07,0x7b,0x61,0x20,0xc7,0x08,0x7b,0x62,0x20,0xc7,0x09,0x7b,0x63,0x20,0xc7,
+0x0a,0x7b,0x88,0x88,0x88,0x88,0x81,0x64,0x20,0x00,0x35,0x65,0x20,0x00,0x35,0x66,
+0x20,0x00,0x35,0x81,0x84,0xaf,0xfa,0xcd,0x10,0xae,0xa4,0x00,0x84,0x35,0xa2,0xb7,
+0x55,0xaa,0xa2,0xb6,0xa3,0xb7,0x55,0xaa,0xa3,0xb6,0xa1,0xb7,0x55,0xaa,0xa1,0xb6,
+0x4c,0xfa,0xcd,0x18,0xa6,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x01,0x7b,
+0xaf,0xfa,0xcd,0x14,0xae,0xa4,0x00,0x84,0x35,0xa0,0xb7,0x3f,0xa4,0xa0,0xb6,0xa1,
+0x3f,0xa2,0x3f,0xa3,0x3f,0x4c,0xfa,0xcd,0x18,0xa6,0xe6,0xfb,0xcd,0xa4,0xb7,0x00,
+0xa9,0x41,0x04,0xab,0x5b,0x25,0x24,0x0f,0xa1,0x07,0x7b,0x4b,0xe1,0xcd,0x64,0xa6,
+0x84,0x84,0x84,0x84,0xaf,0xe1,0xcd,0xb7,0x00,0x3b,0xb8,0x00,0x3b,0xb9,0x00,0x3b,
+0xba,0x00,0x3b,0x0f,0x20,0xd4,0xe1,0xcd,0xb7,0x00,0x3b,0xb8,0x00,0x3b,0xb9,0x00,
+0x3b,0xba,0x00,0x3b,0x11,0x26,0x4a,0x05,0x01,0xc6,0x14,0x84,0x0f,0x35,0x15,0x84,
+0x00,0x35,0x16,0x84,0x00,0x35,0x17,0x84,0x00,0x35,0x04,0x6b,0x60,0x20,0xc6,0x05,
+0x6b,0x61,0x20,0xc6,0x06,0x6b,0x62,0x20,0xc6,0x07,0x6b,0x63,0x20,0xc6,0x68,0x20,
+0xc7,0x4a,0x9d,0x9d,0x68,0x20,0xc7,0x27,0xa6,0x68,0x20,0x52,0x35,0x64,0x20,0x05,
+0x35,0x65,0x20,0xf5,0x35,0x66,0x20,0xe1,0x35,0x67,0x20,0x00,0x35,0x60,0x20,0xbb,
+0x00,0x55,0x61,0x20,0xbc,0x00,0x55,0x62,0x20,0xbd,0x00,0x55,0x63,0x20,0xbe,0x00,
+0x55,0xb7,0x00,0x60,0x20,0x55,0xb8,0x00,0x61,0x20,0x55,0xb9,0x00,0x62,0x20,0x55,
+0xba,0x00,0x63,0x20,0x55,0x68,0x20,0x26,0x35,0x68,0x20,0x21,0x35,0x68,0x20,0x52,
+0x35,0x64,0x20,0x00,0x35,0x65,0x20,0x00,0x35,0x66,0x20,0x80,0x35,0x67,0x20,0x00,
+0x35,0x68,0x20,0x27,0x35,0xbb,0x00,0x60,0x20,0x55,0xbc,0x00,0x61,0x20,0x55,0xbd,
+0x00,0x62,0x20,0x55,0xbe,0x00,0x63,0x20,0x55,0x68,0x20,0x52,0x35,0x64,0x20,0xc7,
+0x04,0x7b,0x65,0x20,0xc7,0x05,0x7b,0x66,0x20,0xc7,0x06,0x7b,0x67,0x20,0xc7,0x07,
+0x7b,0x68,0x20,0xc7,0x4a,0x68,0x20,0xc7,0x22,0xa6,0x60,0x20,0xc7,0x08,0x7b,0x61,
+0x20,0xc7,0x09,0x7b,0x62,0x20,0xc7,0x0a,0x7b,0x63,0x20,0xc7,0x0b,0x7b,0x68,0x20,
+0x52,0x35,0x10,0x84,0x02,0x35,0x11,0x84,0x55,0x35,0x12,0x84,0x55,0x35,0x13,0x84,
+0x55,0x35,0x01,0x6b,0x02,0xa6,0xcd,0xd6,0xcd,0x67,0x20,0x28,0x35,0x09,0x20,0x01,
+0xa6,0xcd,0xd6,0xcd,0x67,0x20,0x14,0x35,0x0b,0x25,0x02,0xa2,0x08,0x7b,0xdd,0xa0,
+0x09,0x7b,0x1e,0x20,0x4f,0xcd,0xd6,0xcd,0x67,0x20,0x0a,0x35,0x0a,0x25,0x04,0xa2,
+0x08,0x7b,0xd9,0xa0,0x09,0x7b,0x88,0x81,0xe7,0x00,0xce,0xe8,0x00,0xc6,0xaf,0xfa,
+0xcd,0x81,0x84,0x84,0xaf,0xfa,0xcd,0x0c,0xae,0xa4,0x00,0x41,0x35,0xce,0xfa,0xcd,
+0x41,0xdf,0x00,0xc9,0x41,0xe0,0x00,0xcb,0x17,0xad,0x08,0xae,0xa4,0x00,0x41,0x35,
+0xce,0xfa,0xcd,0x5c,0x01,0x26,0x4c,0x26,0xad,0x04,0xae,0xa4,0x00,0x41,0x35,0xce,
+0xfa,0xcd,0x41,0xdd,0x00,0xc9,0x41,0xde,0x00,0xcb,0x41,0x01,0xe2,0x72,0x41,0x02,
+0xe0,0x72,0xe5,0x00,0xce,0xe6,0x00,0xc6,0xaf,0xfa,0xcd,0x5f,0xa4,0x00,0x41,0x35,
+0xce,0xfa,0xcd,0x5c,0x01,0x26,0x4c,0x41,0x01,0xe2,0x72,0x41,0x02,0xe0,0x72,0xe5,
+0x00,0xce,0xe6,0x00,0xc6,0x02,0x6b,0xea,0x00,0xc6,0x01,0x6b,0xe9,0x00,0xc6,0x88,
+0x88,0x81,0xed,0x00,0xce,0xee,0x00,0xc6,0xaf,0xfa,0xcd,0x81,0x41,0xe9,0x00,0xc9,
+0x41,0xea,0x00,0xcb,0x46,0x54,0xe1,0x00,0xce,0xe2,0x00,0xc6,0x81,0xe9,0x00,0xce,
+0xea,0x00,0xc6,0xaf,0xfa,0xcd,0x81,0x4c,0xfa,0xcd,0x10,0xa6,0xce,0xfa,0xcd,0x81,
+0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x81,0x84,0x84,0x84,0x84,0x84,0x84,0x7c,0x83,
+0x00,0x35,0x7d,0x83,0x00,0x35,0x7e,0x83,0x0f,0x35,0x7f,0x83,0xff,0x35,0xaf,0xfa,
+0xcd,0x6c,0xae,0xa4,0x00,0x83,0x35,0xa0,0xfb,0xcd,0x23,0xad,0x5b,0x2e,0xad,0x43,
+0xad,0xaf,0xfa,0xcd,0x2d,0xad,0x5b,0xce,0xfa,0xcd,0x4e,0xad,0x0d,0x20,0x48,0xad,
+0x39,0xad,0x5b,0xce,0xfa,0xcd,0xe9,0x00,0xce,0xea,0x00,0xc6,0x10,0x26,0x4a,0xdc,
+0x00,0xc6,0xaf,0xfa,0xcd,0x68,0xae,0xa4,0x00,0x83,0x35,0xa0,0xfb,0xcd,0x57,0xad,
+0x5b,0x62,0xad,0x6d,0xad,0x5e,0xad,0x5b,0xce,0xfa,0xcd,0x75,0xad,0x64,0xae,0xa4,
+0x00,0x83,0x35,0xa0,0xfb,0xcd,0x6f,0xad,0x5b,0x7a,0xad,0x41,0xef,0x00,0xc9,0x41,
+0xf0,0x00,0xcb,0x05,0xee,0x72,0x06,0x7b,0xaf,0xfa,0xcd,0x79,0xd4,0xcd,0x5b,0xce,
+0xfa,0xcd,0x05,0xee,0x72,0x06,0x7b,0xaf,0xfa,0xcd,0x60,0xae,0xa4,0x00,0x83,0x35,
+0xa0,0xfb,0xcd,0x79,0xd4,0xcd,0x5b,0x81,0xd4,0xcd,0x41,0xef,0x00,0xc9,0x41,0xf0,
+0x00,0xcb,0xa5,0xd4,0xcd,0x79,0xd4,0xcd,0x5b,0xce,0xfa,0xcd,0xa5,0xd4,0xcd,0x5c,
+0xae,0xa4,0x00,0x83,0x35,0xce,0xfa,0xcd,0x46,0x54,0xe1,0x00,0xce,0xe2,0x00,0xc6,
+0x05,0xef,0x72,0x06,0x6b,0x4a,0x5a,0x01,0x26,0x4d,0xed,0x00,0xce,0xee,0x00,0xc6,
+0x10,0x20,0x06,0x6b,0xee,0x00,0xc6,0x05,0x6b,0xed,0x00,0xc6,0x0c,0x26,0x4a,0xdc,
+0x00,0xc6,0x88,0x88,0x88,0x88,0x88,0x88,0x81,0xed,0x00,0xce,0xee,0x00,0xc6,0xaf,
+0xfa,0xcd,0x81,0x4d,0x41,0xdf,0x00,0xc9,0x41,0xe0,0x00,0xcb,0x81,0x02,0xa0,0x41,
+0xdd,0x00,0xc9,0x41,0xde,0x00,0xcb,0x81,0x41,0xe9,0x00,0xc9,0x41,0xea,0x00,0xcb,
+0x46,0x54,0xe1,0x00,0xce,0xe2,0x00,0xc6,0x81,0xe5,0x00,0xce,0xe6,0x00,0xc6,0xaf,
+0xfa,0xcd,0x81,0xe9,0x00,0xce,0xea,0x00,0xc6,0xaf,0xfa,0xcd,0x81,0x4c,0xfa,0xcd,
+0x10,0xa6,0xce,0xfa,0xcd,0x81,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x81,0x8b,0x41,
+0x00,0xa9,0x41,0x0e,0xab,0x5b,0x98,0x83,0x00,0x35,0x99,0x83,0x00,0x35,0x9a,0x83,
+0x00,0x35,0x9b,0x83,0x18,0x35,0xaf,0xfa,0xcd,0x3c,0xae,0xa4,0x00,0x83,0x35,0xa0,
+0xfb,0xcd,0x25,0xad,0x5b,0x30,0xad,0x4f,0xad,0xaf,0xfa,0xcd,0x2f,0xad,0x5b,0xce,
+0xfa,0xcd,0x5a,0xad,0x0d,0x20,0x4a,0xad,0x3b,0xad,0x5b,0xce,0xfa,0xcd,0xe9,0x00,
+0xce,0xea,0x00,0xc6,0x10,0x26,0x4a,0xdc,0x00,0xc6,0xaf,0xfa,0xcd,0x38,0xae,0xa4,
+0x00,0x83,0x35,0xa0,0xfb,0xcd,0x59,0xad,0x5b,0x64,0xad,0x6f,0xad,0x60,0xad,0x5b,
+0xce,0xfa,0xcd,0x77,0xad,0x34,0xae,0xa4,0x00,0x83,0x35,0xa0,0xfb,0xcd,0x71,0xad,
+0x5b,0x7c,0xad,0x41,0xef,0x00,0xc9,0x41,0xf0,0x00,0xcb,0x07,0xee,0x72,0x08,0x7b,
+0xaf,0xfa,0xcd,0x33,0xd3,0xcd,0x5b,0xce,0xfa,0xcd,0x07,0xee,0x72,0x08,0x7b,0xaf,
+0xfa,0xcd,0x30,0xae,0xa4,0x00,0x83,0x35,0xa0,0xfb,0xcd,0x33,0xd3,0xcd,0x5b,0x3b,
+0xd3,0xcd,0x41,0xef,0x00,0xc9,0x41,0xf0,0x00,0xcb,0x7e,0xd3,0xcd,0x33,0xd3,0xcd,
+0x5b,0xce,0xfa,0xcd,0x7e,0xd3,0xcd,0x2c,0xae,0xa4,0x00,0x83,0x35,0xa0,0xfb,0xcd,
+0x33,0xd3,0xcd,0x5b,0x3b,0xd3,0xcd,0x41,0xeb,0x00,0xc9,0x41,0xec,0x00,0xcb,0x44,
+0xd3,0xcd,0x33,0xd3,0xcd,0x5b,0xce,0xfa,0xcd,0x44,0xd3,0xcd,0x10,0xae,0xa4,0x00,
+0x83,0x35,0xa0,0xfb,0xcd,0x33,0xd3,0xcd,0x5b,0x3b,0xd3,0xcd,0x4a,0x5a,0x01,0x26,
+0x74,0xd3,0xcd,0x0d,0xee,0x72,0x0e,0x7b,0xaf,0xfa,0xcd,0x33,0xd3,0xcd,0x5b,0xce,
+0xfa,0xcd,0x5a,0x01,0x24,0x69,0xd3,0xcd,0x4e,0xd3,0xcd,0x0c,0xae,0xa4,0x00,0x83,
+0x35,0xa0,0xfb,0xcd,0x33,0xd3,0xcd,0x5b,0x3b,0xd3,0xcd,0x0d,0xee,0x72,0x0e,0x7b,
+0xaf,0xfa,0xcd,0x33,0xd3,0xcd,0x5b,0xce,0xfa,0xcd,0x4a,0x5a,0x01,0x26,0x4d,0x4e,
+0xd3,0xcd,0x08,0xae,0xa4,0x00,0x83,0x35,0xa0,0xfb,0xcd,0x33,0xd3,0xcd,0x5b,0x3b,
+0xd3,0xcd,0x4a,0x5a,0x01,0x26,0x74,0xd3,0xcd,0x0d,0xee,0x72,0x0e,0x7b,0xaf,0xfa,
+0xcd,0x33,0xd3,0xcd,0x5b,0xce,0xfa,0xcd,0x5a,0x01,0x24,0x69,0xd3,0xcd,0x4e,0xd3,
+0xcd,0x04,0xae,0xa4,0x00,0x83,0x35,0xa0,0xfb,0xcd,0x33,0xd3,0xcd,0x5b,0x3b,0xd3,
+0xcd,0x0d,0xee,0x72,0x0e,0x7b,0xaf,0xfa,0xcd,0x33,0xd3,0xcd,0x5b,0xce,0xfa,0xcd,
+0x4a,0x5a,0x01,0x26,0x4d,0x4e,0xd3,0xcd,0x40,0xae,0xa4,0x00,0x83,0x35,0xa0,0x3f,
+0xa1,0x3f,0xa2,0xb7,0x0f,0xa4,0xa2,0xb6,0xce,0xfa,0xcd,0x05,0xee,0x72,0x06,0x7b,
+0xaf,0xfa,0xcd,0x28,0xae,0xa4,0x00,0x83,0x35,0xa0,0x3f,0xa1,0x3f,0xa2,0xb7,0x1f,
+0xa4,0xa2,0xb6,0xce,0xfa,0xcd,0xe1,0x00,0xce,0xe2,0x00,0xc6,0x78,0x84,0xc7,0x09,
+0x7b,0x79,0x84,0xc7,0x0a,0x7b,0x7a,0x84,0xc7,0x0b,0x7b,0x7b,0x84,0xc7,0x0c,0x7b,
+0x07,0xef,0x72,0x08,0x6b,0x4a,0x5a,0x01,0x26,0x4d,0xed,0x00,0xce,0xee,0x00,0xc6,
+0x06,0x6b,0xe4,0x00,0xc6,0x05,0x6b,0xe3,0x00,0xc6,0x0a,0x6b,0x05,0xaa,0x0a,0x7b,
+0x20,0x20,0x08,0x6b,0xee,0x00,0xc6,0x07,0x6b,0xed,0x00,0xc6,0x05,0xef,0x72,0x06,
+0x6b,0x59,0x48,0xe3,0x00,0xce,0xe4,0x00,0xc6,0x0a,0x6b,0x01,0xaa,0x0a,0x7b,0x1f,
+0x26,0x4a,0xdc,0x00,0xc6,0x09,0x6b,0x80,0xaa,0x09,0x7b,0x06,0x26,0x04,0xa1,0x00,
+0x01,0xc6,0x09,0x6b,0x20,0xa6,0x0a,0x6b,0x0b,0x6b,0x0c,0x6b,0x4f,0x0d,0x6b,0x0e,
+0xef,0x72,0xed,0x00,0xc9,0x41,0xee,0x00,0xcb,0xe7,0x00,0xce,0xe8,0x00,0xc6,0x8b,
+0x41,0x00,0xa2,0x41,0x0e,0xa0,0x5b,0x81,0x84,0x84,0x84,0x84,0x75,0x01,0x01,0x35,
+0xaf,0xfa,0xcd,0x78,0xae,0xa4,0x00,0x84,0x35,0xa0,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,
+0x41,0x01,0xab,0x5b,0xa0,0xb7,0x03,0xa4,0xa0,0xb6,0xa1,0xb7,0xc0,0xa4,0xa1,0xb6,
+0xa2,0x3f,0xa3,0x3f,0x4c,0xfa,0xcd,0x16,0xa6,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,
+0xa3,0x00,0xf7,0x00,0x55,0x01,0x6b,0xfc,0xa4,0x01,0x7b,0x02,0x6b,0x3f,0xa4,0x02,
+0x7b,0x01,0x6b,0x78,0x84,0xc6,0x02,0x6b,0x79,0x84,0xc6,0x03,0x6b,0x7a,0x84,0xc6,
+0x04,0x6b,0x7b,0x84,0xc6,0xaf,0xfa,0xcd,0x74,0xae,0xa4,0x00,0x84,0x35,0xce,0xfa,
+0xcd,0xda,0x00,0xce,0xdb,0x00,0xc6,0xaf,0xfa,0xcd,0x70,0xae,0xa4,0x00,0x84,0x35,
+0xce,0xfa,0xcd,0xd8,0x00,0xce,0xd9,0x00,0xc6,0xaf,0xfa,0xcd,0x6c,0xae,0xa4,0x00,
+0x84,0x35,0xce,0xfa,0xcd,0xd6,0x00,0xce,0xd7,0x00,0xc6,0xaf,0xfa,0xcd,0x68,0xae,
+0xa4,0x00,0x84,0x35,0xce,0xfa,0xcd,0xd4,0x00,0xce,0xd5,0x00,0xc6,0xaf,0xfa,0xcd,
+0x64,0xae,0xa4,0x00,0x84,0x35,0xce,0xfa,0xcd,0xd2,0x00,0xce,0xd3,0x00,0xc6,0x12,
+0x20,0x64,0x84,0x00,0x35,0x65,0x84,0x00,0x35,0x66,0x84,0x02,0x35,0x67,0x84,0xcb,
+0x35,0x12,0x25,0x02,0xa2,0xd2,0x00,0xc6,0xcb,0xa0,0xd3,0x00,0xc6,0x1e,0x26,0x02,
+0xa1,0x7a,0x01,0xc6,0x25,0x26,0x03,0xa1,0x05,0x01,0xc6,0xaf,0xfa,0xcd,0x60,0xae,
+0xa4,0x00,0x84,0x35,0xce,0xfa,0xcd,0xd0,0x00,0xce,0xd1,0x00,0xc6,0xaf,0xfa,0xcd,
+0x5c,0xae,0xa4,0x00,0x84,0x35,0xce,0xfa,0xcd,0xce,0x00,0xce,0xcf,0x00,0xc6,0xaf,
+0xfa,0xcd,0x58,0xae,0xa4,0x00,0x84,0x35,0xce,0xfa,0xcd,0xcc,0x00,0xce,0xcd,0x00,
+0xc6,0x88,0x88,0x88,0x88,0x81,0xa4,0xc6,0x92,0xa5,0xbf,0xa4,0xb7,0x81,0xa4,0xd6,
+0x92,0xa5,0x3f,0xa4,0xb7,0x81,0x84,0xda,0x00,0xcf,0xd2,0x00,0xce,0xdb,0x00,0xc7,
+0xd3,0x00,0xc6,0xd2,0x00,0xcf,0xd3,0x00,0xc7,0x4a,0x5a,0x01,0x26,0x4d,0x59,0x48,
+0xfa,0x00,0xce,0xfb,0x00,0xc6,0x0b,0x20,0x0e,0x26,0x4d,0xfa,0x00,0xce,0xfb,0x00,
+0xc6,0x0b,0x26,0x4a,0xdc,0x00,0xc6,0xd8,0x00,0xcf,0xd0,0x00,0xce,0xd9,0x00,0xc7,
+0xd1,0x00,0xc6,0xd1,0x00,0x5f,0x72,0xd0,0x00,0x5f,0x72,0xd6,0x00,0xcf,0xce,0x00,
+0xce,0xd7,0x00,0xc7,0xcf,0x00,0xc6,0xce,0x00,0xcf,0xcf,0x00,0xc7,0x4a,0x5a,0x01,
+0x26,0x4d,0xfa,0x26,0x5a,0x90,0x46,0x54,0x06,0x27,0xf7,0x00,0xce,0x90,0xf8,0x00,
+0xce,0xf9,0x00,0xc6,0xd4,0x00,0xcf,0xcc,0x00,0xce,0xd5,0x00,0xc7,0xcd,0x00,0xc6,
+0xcd,0x00,0x5f,0x72,0xcc,0x00,0x5f,0x72,0xe7,0x00,0x5f,0x72,0xe8,0x00,0x23,0x35,
+0x08,0x26,0x03,0xa1,0x7a,0x01,0xc6,0x0f,0x26,0x03,0xa1,0xfa,0x00,0xdf,0x00,0x55,
+0xfb,0x00,0xe0,0x00,0x55,0xfe,0x00,0xe3,0x00,0x55,0xff,0x00,0xe4,0x00,0x55,0xf8,
+0x00,0xdd,0x00,0x55,0xf9,0x00,0xde,0x00,0x55,0xfc,0x00,0xe1,0x00,0x55,0xfd,0x00,
+0xe2,0x00,0x55,0xae,0xcd,0xcc,0xc3,0xcf,0xcd,0xca,0xa9,0x41,0x20,0xab,0x52,0x1c,
+0xae,0x01,0x7b,0xaf,0xfa,0xcd,0xf3,0xae,0xa4,0x00,0x00,0x35,0x06,0xfa,0xcd,0xa4,
+0xb7,0xca,0xa9,0x41,0x1c,0xab,0x52,0x1c,0xae,0x01,0x7b,0xf2,0x00,0xc7,0xc3,0xcf,
+0xcd,0xca,0xa9,0x41,0x1b,0xab,0x52,0x1c,0xae,0x01,0x7b,0xf1,0x00,0xc7,0xc3,0xcf,
+0xcd,0xca,0xa9,0x41,0x1a,0xab,0x52,0x1c,0xae,0x01,0x7b,0xf0,0x00,0xc7,0xa4,0xd6,
+0x92,0xa5,0x3c,0xef,0x00,0xc7,0xbb,0xcf,0xcd,0xca,0xa9,0x41,0x18,0xab,0x52,0x1c,
+0xae,0x01,0x7b,0xed,0x00,0x5f,0x72,0xee,0x00,0x01,0x35,0xec,0x00,0xc7,0xa4,0xd6,
+0x92,0xa5,0x3c,0xeb,0x00,0xc7,0xbb,0xcf,0xcd,0xca,0xa9,0x41,0x14,0xab,0x52,0x1c,
+0xae,0x01,0x7b,0xea,0x00,0xc7,0xa4,0xd6,0x92,0xa5,0x3c,0xe9,0x00,0xc7,0xbb,0xcf,
+0xcd,0xca,0xa9,0x41,0x12,0xab,0x52,0x1c,0xae,0x01,0x7b,0xe8,0x00,0xc7,0xa4,0xd6,
+0x92,0xa5,0x3c,0xe7,0x00,0xc7,0xbb,0xcf,0xcd,0xca,0xa9,0x41,0x10,0xab,0x52,0x1c,
+0xae,0x01,0x7b,0xe6,0x00,0xc7,0xa4,0xd6,0x92,0xa5,0x3c,0xe5,0x00,0xc7,0xbb,0xcf,
+0xcd,0xca,0xa9,0x41,0x0e,0xab,0x52,0x1c,0xae,0x01,0x7b,0xe4,0x00,0xc7,0xa4,0xd6,
+0x92,0xa5,0x3c,0xe3,0x00,0xc7,0xbb,0xcf,0xcd,0xca,0xa9,0x41,0x0c,0xab,0x52,0x1c,
+0xae,0x01,0x7b,0xe2,0x00,0xc7,0xa4,0xd6,0x92,0xa5,0x3c,0xe1,0x00,0xc7,0xbb,0xcf,
+0xcd,0xca,0xa9,0x41,0x0a,0xab,0x52,0x1c,0xae,0x01,0x7b,0xe0,0x00,0xc7,0xa4,0xd6,
+0x92,0xa5,0x3c,0xdf,0x00,0xc7,0xbb,0xcf,0xcd,0xca,0xa9,0x41,0x08,0xab,0x52,0x1c,
+0xae,0x01,0x7b,0xde,0x00,0xc7,0xa4,0xd6,0x92,0xa5,0x3c,0xdd,0x00,0xc7,0xbb,0xcf,
+0xcd,0xca,0xa9,0x41,0x06,0xab,0x52,0x1c,0xae,0x01,0x7b,0xdc,0x00,0xc7,0xc3,0xcf,
+0xcd,0xca,0xa9,0x41,0x05,0xab,0x52,0x1c,0xae,0x01,0x7b,0xfd,0xce,0xcc,0x25,0xcf,
+0xcc,0x03,0x27,0x02,0xa1,0xfd,0xce,0xcc,0x03,0x26,0x03,0xa1,0x05,0x01,0xc6,0xf7,
+0x00,0xc7,0x29,0xb6,0xf3,0x00,0x2a,0x00,0x55,0xf4,0x00,0x2b,0x00,0x55,0xf5,0x00,
+0x2c,0x00,0x55,0xf6,0x00,0x2d,0x00,0x55,0xf1,0x00,0xc7,0x13,0xb6,0x13,0xb6,0xef,
+0x00,0xcf,0x22,0xbe,0xf0,0x00,0xc7,0x23,0xb6,0xed,0x00,0xcf,0x20,0xbe,0xee,0x00,
+0xc7,0x21,0xb6,0xeb,0x00,0xcf,0x1e,0xbe,0xec,0x00,0xc7,0x1f,0xb6,0xe9,0x00,0xcf,
+0x1c,0xbe,0xea,0x00,0xc7,0x1d,0xb6,0xe7,0x00,0xcf,0x26,0xbe,0xe8,0x00,0xc7,0x27,
+0xb6,0xe5,0x00,0xcf,0x24,0xbe,0xe6,0x00,0xc7,0x25,0xb6,0xe3,0x00,0xcf,0x18,0xbe,
+0xe4,0x00,0xc7,0x19,0xb6,0xe1,0x00,0xcf,0x14,0xbe,0xe2,0x00,0xc7,0x15,0xb6,0xdf,
+0x00,0xcf,0x1a,0xbe,0xe0,0x00,0xc7,0x1b,0xb6,0xdd,0x00,0xcf,0x16,0xbe,0xde,0x00,
+0xc7,0x17,0xb6,0xdc,0x00,0xc7,0x28,0xb6,0xc5,0xcd,0xcc,0x03,0x24,0x1d,0xa1,0x11,
+0xb6,0x09,0x27,0x11,0x3d,0x01,0x6b,0x4a,0x11,0xb6,0x88,0x00,0xf0,0x70,0x1c,0x05,
+0x01,0x01,0x03,0x00,0x03,0x00,0x8f,0x00,0x46,0x00,0x1b,0x00,0xaa,0x01,0x1e,0x03,
+0x00,0x07,0x00,0x03,0x50,0x05,0x01,0x00,0x60,0xa0,0x18,0x05,0x01,0x01,0x06,0x00,
+0x03,0x00,0x70,0x00,0x40,0x00,0x18,0x00,0xb0,0x01,0x1b,0x03,0x00,0x07,0x00,0x03,
+0x50,0x05,0x01,0x00,0xe0,0x1b,0xfa,0x04,0x01,0x00,0x06,0x00,0x03,0x00,0x80,0x00,
+0x48,0x00,0x1c,0x00,0x90,0x01,0x3f,0x03,0x90,0x06,0x20,0x03,0x00,0x05,0x01,0x00,
+0xc0,0x5f,0x3b,0x04,0x00,0x01,0x06,0x00,0x03,0x00,0x20,0x00,0x30,0x00,0x14,0x00,
+0xa0,0x00,0x37,0x03,0xa0,0x05,0x20,0x03,0x00,0x05,0x01,0x00,0xe0,0x12,0xbd,0x04,
+0x01,0x00,0x07,0x00,0x03,0x00,0x80,0x00,0x40,0x00,0x1b,0x00,0x80,0x01,0x1e,0x03,
+0x80,0x06,0x00,0x03,0x00,0x05,0x01,0x00,0x90,0x69,0x11,0x04,0x00,0x01,0x07,0x00,
+0x03,0x00,0x20,0x00,0x30,0x00,0x13,0x00,0xa0,0x00,0x16,0x03,0xa0,0x05,0x00,0x03,
+0x00,0x05,0x01,0x00,0x40,0xd2,0xdf,0x03,0x00,0x00,0x06,0x00,0x03,0x00,0x88,0x00,
+0x18,0x00,0x23,0x00,0x40,0x01,0x26,0x03,0x40,0x05,0x00,0x03,0x00,0x04,0x01,0x00,
+0xf0,0xfb,0x02,0x02,0x01,0x01,0x08,0x00,0x06,0x00,0x70,0x00,0x10,0x00,0x1f,0x00,
+0xf0,0x00,0x05,0x02,0x40,0x04,0xe0,0x01,0x50,0x03,0x01,0x00,0x00,0x5a,0x62,0x02,
+0x01,0x01,0x04,0x00,0x01,0x00,0x80,0x00,0x28,0x00,0x1b,0x00,0x00,0x01,0x74,0x02,
+0x20,0x04,0x58,0x02,0x20,0x03,0x01,0x00,0x10,0xf7,0x6c,0x04,0x01,0x01,0x05,0x00,
+0x01,0x00,0x28,0x00,0xe0,0x06,0x19,0x00,0xe4,0x07,0xee,0x02,0xe4,0x0c,0xd0,0x02,
+0x00,0x05,0x01,0x00,0x10,0xf7,0x6c,0x04,0x01,0x01,0x05,0x00,0x01,0x00,0x28,0x00,
+0x74,0x09,0x19,0x00,0x78,0x0a,0xee,0x02,0x78,0x0f,0xd0,0x02,0x00,0x05,0x01,0x00,
+0x40,0x5f,0x8a,0x03,0x01,0x01,0x05,0x00,0x01,0x00,0x28,0x00,0xe0,0x06,0x19,0x00,
+0xe4,0x07,0xee,0x02,0xe4,0x0c,0xd0,0x02,0x00,0x05,0x01,0x00,0x10,0xf7,0x6c,0x04,
+0x01,0x01,0x05,0x00,0x01,0x00,0x2c,0x00,0x58,0x00,0x29,0x00,0x18,0x01,0x65,0x04,
+0x98,0x08,0x38,0x04,0x80,0x07,0x01,0x00,0x10,0xf7,0x6c,0x04,0x01,0x01,0x05,0x00,
+0x01,0x00,0x2c,0x00,0x10,0x02,0x29,0x00,0xd0,0x02,0x65,0x04,0x50,0x0a,0x38,0x04,
+0x80,0x07,0x01,0x00,0x10,0xf7,0x6c,0x04,0x01,0x01,0x05,0x00,0x01,0x00,0x2c,0x00,
+0x7e,0x02,0x29,0x00,0x3e,0x03,0x65,0x04,0xbe,0x0a,0x38,0x04,0x80,0x07,0x01,0x00,
+0x20,0xee,0xd9,0x08,0x01,0x01,0x05,0x00,0x01,0x00,0x2c,0x00,0x10,0x02,0x29,0x00,
+0xd0,0x02,0x65,0x04,0x50,0x0a,0x38,0x04,0x80,0x07,0x01,0x00,0x80,0xf9,0x37,0x03,
+0x00,0x00,0x05,0x00,0x01,0x00,0x80,0x00,0x18,0x00,0x2c,0x00,0x20,0x01,0x71,0x02,
+0xc0,0x06,0x40,0x02,0xa0,0x05,0x01,0x01,0xc0,0xfc,0x9b,0x01,0x00,0x00,0x03,0x00,
+0x01,0x00,0x7e,0x00,0x18,0x00,0x16,0x00,0x20,0x01,0x71,0x02,0xc0,0x06,0x20,0x01,
+0xa0,0x05,0x00,0x00,0x10,0xf7,0x6c,0x04,0x01,0x01,0x05,0x00,0x01,0x00,0x2c,0x00,
+0x10,0x02,0x14,0x00,0xd0,0x02,0x65,0x04,0x50,0x0a,0x1c,0x02,0x80,0x07,0x00,0x00,
+0x10,0xf7,0x6c,0x04,0x01,0x01,0x05,0x00,0x01,0x00,0x28,0x00,0xb8,0x01,0x19,0x00,
+0xbc,0x02,0xee,0x02,0xbc,0x07,0xd0,0x02,0x00,0x05,0x01,0x00,0xc0,0xfc,0x9b,0x01,
+0x00,0x00,0x05,0x00,0x01,0x00,0x40,0x00,0x0c,0x00,0x2c,0x00,0x90,0x00,0x71,0x02,
+0x60,0x03,0x40,0x02,0xd0,0x02,0x01,0x00,0x20,0xee,0xd9,0x08,0x01,0x01,0x05,0x00,
+0x01,0x00,0x2c,0x00,0x58,0x00,0x29,0x00,0x18,0x01,0x65,0x04,0x98,0x08,0x38,0x04,
+0x80,0x07,0x01,0x00,0x80,0xf9,0x37,0x03,0x00,0x00,0x06,0x00,0x07,0x00,0x7c,0x00,
+0x20,0x00,0x24,0x00,0x14,0x01,0x0d,0x02,0xb4,0x06,0xe0,0x01,0xa0,0x05,0x01,0x01,
+0xc0,0xfc,0x9b,0x01,0x00,0x00,0x03,0x00,0x04,0x00,0x7c,0x00,0x26,0x00,0x12,0x00,
+0x14,0x01,0x0d,0x02,0xb4,0x06,0xf0,0x00,0xa0,0x05,0x00,0x00,0x10,0xf7,0x6c,0x04,
+0x01,0x01,0x05,0x00,0x01,0x00,0x2c,0x00,0x58,0x00,0x14,0x00,0x18,0x01,0x65,0x04,
+0x98,0x08,0x1c,0x02,0x80,0x07,0x00,0x00,0x10,0xf7,0x6c,0x04,0x01,0x01,0x05,0x00,
+0x01,0x00,0x28,0x00,0x6e,0x00,0x19,0x00,0x72,0x01,0xee,0x02,0x72,0x06,0xd0,0x02,
+0x00,0x05,0x01,0x00,0xc0,0xfc,0x9b,0x01,0x00,0x00,0x06,0x00,0x07,0x00,0x3e,0x00,
+0x10,0x00,0x24,0x00,0x8a,0x00,0x0d,0x02,0x5a,0x03,0xe0,0x01,0xd0,0x02,0x01,0x00,
+0x80,0x85,0x80,0x01,0x00,0x00,0x02,0x00,0x01,0x00,0x60,0x00,0x10,0x00,0x23,0x00,
+0xa0,0x00,0x0d,0x02,0x20,0x03,0xe0,0x01,0x80,0x02,0x01,0x80,0xae,0x00,0xc7,0x51,
+0x20,0xc6,0x50,0x20,0x11,0x72,0x80,0x85,0x90,0xa6,0x00,0x32,0xa5,0x00,0x32,0xa4,
+0x00,0x32,0xa9,0x00,0x32,0xa8,0x00,0x32,0xa7,0x00,0x32,0x84,0x84,0x84,0x84,0x69,
+0x01,0x5a,0x72,0x68,0x01,0x5a,0x72,0x04,0x26,0x69,0x01,0xc6,0x0d,0x27,0x68,0x01,
+0xca,0x69,0x01,0xc6,0x32,0x01,0x5f,0x72,0x04,0x20,0x32,0x01,0x01,0x35,0x06,0x27,
+0x10,0xa5,0x04,0x7b,0x01,0x6b,0x10,0x40,0xc6,0x02,0x6b,0x11,0x40,0xc6,0x03,0x6b,
+0x12,0x40,0xc6,0x04,0x6b,0x13,0x40,0xc6,0x3a,0xe1,0xcd,0x46,0x20,0xc7,0x46,0x20,
+0xc6,0x41,0x20,0x5f,0x72,0x0a,0x42,0x20,0x0d,0x72,0x88,0x88,0x88,0x88,0xa7,0x00,
+0x3b,0xa8,0x00,0x3b,0xa9,0x00,0x3b,0xa4,0x00,0x3b,0xa5,0x00,0x3b,0xa6,0x00,0x3b,
+0x89,0x90,0x80,0x85,0x90,0xa6,0x00,0x32,0xa5,0x00,0x32,0xa4,0x00,0x32,0xa9,0x00,
+0x32,0xa8,0x00,0x32,0xa7,0x00,0x32,0x00,0xc0,0xcd,0x15,0x20,0x10,0x72,0x07,0x27,
+0x09,0x2b,0x10,0xb6,0x12,0x20,0x01,0x35,0xa7,0x00,0x3b,0xa8,0x00,0x3b,0xa9,0x00,
+0x3b,0xa4,0x00,0x3b,0xa5,0x00,0x3b,0xa6,0x00,0x3b,0x89,0x90,0x80,0x0c,0x40,0x00,
+0x35,0x0d,0x40,0x00,0x35,0x0e,0x40,0x00,0x35,0x0f,0x40,0x04,0x35,0x11,0x20,0x80,
+0x35,0x80,0x11,0x20,0x40,0x35,0x80,0x11,0x20,0x20,0x35,0x80,0x11,0x20,0x10,0x35,
+0x80,0x11,0x20,0x08,0x35,0x80,0x17,0x20,0x14,0x72,0x80,0x17,0x20,0x15,0x72,0x05,
+0x17,0x20,0x05,0x72,0x11,0x20,0x04,0x35,0x80,0x75,0x01,0xc7,0x4a,0x05,0x20,0x1a,
+0x72,0x06,0x20,0x18,0x72,0x11,0x20,0xc7,0x02,0xa6,0x80,0x75,0x01,0xc7,0x05,0x20,
+0x1a,0x72,0x06,0x20,0x19,0x72,0x11,0x20,0xc7,0x01,0xa6,0x80,0x04,0x88,0x00,0x35,
+0x05,0x88,0x30,0x35,0x06,0x88,0x00,0x35,0x07,0x88,0x00,0x35,0x10,0x20,0x80,0x35,
+0x81,0xaf,0xfa,0xcd,0xbc,0xae,0xa4,0x00,0x84,0x35,0x81,0xa4,0xb7,0x00,0xa9,0x41,
+0x01,0xab,0x80,0x85,0x90,0xa6,0x00,0x32,0xa5,0x00,0x32,0xa4,0x00,0x32,0xa9,0x00,
+0x32,0xa8,0x00,0x32,0xa7,0x00,0x32,0xa3,0x00,0x32,0xa2,0x00,0x32,0xa1,0x00,0x32,
+0xa0,0x00,0x32,0x84,0x84,0x84,0x84,0x84,0x84,0xaf,0xfa,0xcd,0xa0,0xae,0xa4,0x00,
+0x84,0x35,0xa0,0xfb,0xcd,0x33,0xad,0x5b,0xa0,0x3f,0xa1,0x3f,0xa2,0x1f,0xce,0xfa,
+0xcd,0xaa,0x00,0xce,0xab,0x00,0xc6,0x03,0x6b,0x80,0xa4,0x03,0x7b,0x04,0x6b,0x4f,
+0x01,0x6b,0xa0,0x84,0xc6,0x02,0x6b,0xa1,0x84,0xc6,0x03,0x6b,0xa2,0x84,0xc6,0x04,
+0x6b,0xa3,0x84,0xc6,0x84,0x84,0xaa,0x00,0xcf,0xab,0x00,0xc7,0x93,0xe1,0xcd,0xc0,
+0x00,0xce,0xc1,0x00,0xc6,0xac,0x00,0x3b,0xad,0x00,0x3b,0x0f,0x20,0x77,0xe1,0xcd,
+0xc0,0x00,0xce,0xc1,0x00,0xc6,0xac,0x00,0x3b,0xad,0x00,0x3b,0x11,0x24,0x05,0xe2,
+0x72,0xac,0x00,0xc6,0x06,0xe0,0x72,0xad,0x00,0xc6,0x1f,0x24,0x05,0xe2,0x72,0xc0,
+0x00,0xc6,0x06,0xe0,0x72,0xc1,0x00,0xc6,0x1c,0x25,0xac,0x00,0xc2,0x05,0x7b,0xad,
+0x00,0xc0,0x06,0x7b,0x0c,0x24,0xc0,0x00,0xc2,0x05,0x7b,0xc1,0x00,0xc0,0x06,0x7b,
+0x5c,0x20,0xaa,0x00,0xcf,0xc0,0x00,0xce,0xab,0x00,0xc1,0x00,0x55,0x0d,0x26,0x06,
+0x01,0xc6,0x0d,0x20,0xac,0x00,0xce,0xab,0x00,0xc7,0xad,0x00,0xc6,0x0b,0x27,0x4a,
+0x05,0x01,0xc6,0x05,0x20,0x1d,0x72,0x05,0x20,0x1c,0x72,0x08,0x26,0x03,0xa1,0x04,
+0x27,0x02,0xa1,0xbf,0x00,0xc6,0x13,0x26,0xc0,0x00,0xc1,0x05,0x7b,0x1a,0x26,0xc1,
+0x00,0xc1,0x06,0x7b,0x21,0x26,0x4a,0x05,0x01,0xc6,0xac,0x00,0x5f,0x72,0xad,0x00,
+0xc7,0x06,0xa6,0xc6,0xc8,0xcd,0xa2,0xb7,0x18,0xaa,0xa2,0xb6,0xe6,0xfb,0xcd,0xbe,
+0xc8,0xcd,0x5b,0x12,0x20,0x0a,0xa6,0xc6,0xc8,0xcd,0xa2,0x18,0xe6,0xfb,0xcd,0xbe,
+0xc8,0xcd,0x5b,0x10,0x24,0x00,0xa2,0x05,0x7b,0x0a,0xa0,0x06,0x7b,0x1a,0x25,0x00,
+0xa2,0x05,0x7b,0x06,0xa0,0x06,0x7b,0x03,0x6b,0xc7,0xa4,0x03,0x7b,0x01,0x6b,0xbc,
+0x84,0xc6,0x02,0x6b,0xbd,0x84,0xc6,0x03,0x6b,0xbe,0x84,0xc6,0x04,0x6b,0xbf,0x84,
+0xc6,0x57,0x27,0x06,0x01,0xc6,0x06,0x6b,0xa7,0x83,0xc6,0x05,0x6b,0xa6,0x83,0xc6,
+0xab,0x00,0x5f,0x72,0xaa,0x00,0x5f,0x72,0xad,0x00,0x5f,0x72,0xac,0x00,0x5f,0x72,
+0x10,0x20,0x40,0x35,0x88,0x88,0x88,0x88,0x88,0x88,0xa0,0x00,0x3b,0xa1,0x00,0x3b,
+0xa2,0x00,0x3b,0xa3,0x00,0x3b,0xa7,0x00,0x3b,0xa8,0x00,0x3b,0xa9,0x00,0x3b,0xa4,
+0x00,0x3b,0xa5,0x00,0x3b,0xa6,0x00,0x3b,0x89,0x90,0x81,0x48,0x83,0x00,0x35,0x49,
+0x83,0x00,0x35,0x4a,0x83,0x00,0x35,0x4b,0x83,0x0f,0x35,0x80,0x85,0x90,0xa6,0x00,
+0x32,0xa5,0x00,0x32,0xa4,0x00,0x32,0xa9,0x00,0x32,0xa8,0x00,0x32,0xa7,0x00,0x32,
+0x84,0x84,0x84,0x84,0x76,0x01,0x5f,0x72,0xa7,0xe6,0xcd,0x20,0xad,0x05,0x26,0x4a,
+0x76,0x01,0xc6,0x0b,0x26,0x03,0xa1,0x05,0x01,0xc6,0x7c,0x01,0x5c,0x72,0x04,0x27,
+0x0f,0xa1,0x7c,0x01,0xc6,0x0b,0x20,0x75,0x01,0x01,0x35,0x11,0x26,0x7c,0x01,0x5a,
+0x72,0x17,0x27,0x7c,0x01,0xc6,0x11,0x26,0x03,0xea,0x72,0x04,0x7b,0x07,0x27,0x4c,
+0x03,0x7b,0x05,0x26,0x4c,0x04,0x7b,0x11,0x27,0x03,0x7b,0x04,0x26,0x4a,0x04,0x7b,
+0x0b,0xd8,0xcd,0x03,0xee,0x72,0x9f,0x03,0x6b,0x04,0xef,0x72,0x03,0xe2,0x72,0x41,
+0x04,0xe0,0x72,0x5f,0x01,0xa6,0x03,0x6b,0x01,0xe2,0x72,0x03,0x7b,0x04,0x6b,0x02,
+0xe0,0x72,0x04,0x7b,0x0e,0x24,0x03,0xe2,0x72,0x9f,0x04,0xe0,0x72,0x46,0x54,0x01,
+0xef,0x72,0x02,0x6b,0x46,0x54,0xe3,0x00,0xce,0xe4,0x00,0xc6,0x08,0x20,0xe3,0x00,
+0xce,0xe4,0x00,0xc6,0x08,0x26,0x4a,0xdc,0x00,0xc6,0xe3,0x26,0x03,0xe1,0x72,0xa6,
+0x83,0xc6,0xeb,0x26,0x04,0xe1,0x72,0xa7,0x83,0xc6,0x04,0x6b,0xa7,0x83,0xc6,0x03,
+0x6b,0xa6,0x83,0xc6,0xd6,0xc6,0xcc,0x84,0x84,0x84,0x84,0xb3,0x00,0x35,0x35,0xb4,
+0x00,0x86,0x35,0xb5,0x00,0x37,0x35,0xb6,0x00,0xbd,0x35,0x7c,0x01,0x0f,0x35,0x7e,
+0x01,0x01,0x35,0x05,0xc7,0xcd,0xaf,0xe1,0xcd,0xb7,0x00,0x3b,0xb8,0x00,0x3b,0xb9,
+0x00,0x3b,0xba,0x00,0x3b,0x31,0x26,0x7e,0x01,0xc6,0x75,0xe6,0xcd,0x03,0x27,0x7c,
+0x01,0xc6,0xec,0xc6,0xcc,0x03,0x26,0x02,0xa1,0x74,0x01,0xc6,0xd6,0xc6,0xcc,0x03,
+0x27,0x02,0xa1,0x05,0x01,0xc6,0x10,0x20,0x20,0x35,0x88,0x88,0x88,0x88,0xa7,0x00,
+0x3b,0xa8,0x00,0x3b,0xa9,0x00,0x3b,0xa4,0x00,0x3b,0xa5,0x00,0x3b,0xa6,0x00,0x3b,
+0x89,0x90,0x80,0x10,0x20,0x08,0x35,0x81,0xe6,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,
+0x02,0xab,0x80,0x85,0x90,0xa6,0x00,0x32,0xa5,0x00,0x32,0xa4,0x00,0x32,0xa9,0x00,
+0x32,0xa8,0x00,0x32,0xa7,0x00,0x32,0xa3,0x00,0x32,0xa2,0x00,0x32,0xa1,0x00,0x32,
+0xa0,0x00,0x32,0x84,0x84,0x84,0x84,0x84,0x35,0xe6,0xcd,0x75,0x01,0x5f,0x72,0x07,
+0x26,0x4a,0x75,0x01,0xc6,0x06,0x27,0x4a,0x05,0x01,0xc6,0xcb,0xcf,0xcd,0x77,0x01,
+0xc7,0x06,0x26,0x4a,0x77,0x01,0xc6,0xaf,0xfa,0xcd,0xa4,0xbf,0x84,0xae,0xa3,0x1a,
+0x4e,0xad,0x5b,0x09,0x20,0x04,0xae,0xa4,0x00,0x44,0x35,0xa0,0x3f,0x5b,0xad,0x5b,
+0x02,0x6b,0x08,0x84,0xc6,0x03,0x6b,0x09,0x84,0xc6,0x04,0x6b,0x0a,0x84,0xc6,0x05,
+0x6b,0x0b,0x84,0xc6,0xaf,0xfa,0xcd,0xa4,0xbf,0x84,0xae,0xa3,0x1b,0x7b,0xad,0x5b,
+0x2d,0x27,0x07,0x01,0xc6,0x32,0x27,0xc3,0x00,0xc6,0x02,0x6b,0x84,0x84,0xc6,0x03,
+0x6b,0x85,0x84,0xc6,0x04,0x6b,0x86,0x84,0xc6,0x05,0x6b,0x87,0x84,0xc6,0x1b,0x01,
+0x5c,0x72,0x04,0x27,0x4c,0x1b,0x01,0xc6,0x0a,0x20,0x1b,0x01,0x5f,0x72,0x06,0x27,
+0x7c,0x01,0xc6,0x7d,0x01,0x5c,0x72,0x04,0x24,0xff,0xa1,0x7d,0x01,0xc6,0x76,0x01,
+0x01,0x35,0xaf,0xfa,0xcd,0xa0,0xae,0xa4,0x00,0x84,0x35,0xa0,0x1f,0xbe,0xc5,0xcd,
+0x5b,0x02,0x6b,0xa0,0x84,0xc6,0x03,0x6b,0xa1,0x84,0xc6,0x04,0x6b,0xa2,0x84,0xc6,
+0x05,0x6b,0xa3,0x84,0xc6,0x84,0x84,0x84,0x84,0xaf,0xe1,0xcd,0xb7,0x00,0x3b,0xb8,
+0x00,0x3b,0xb9,0x00,0x3b,0xba,0x00,0x3b,0x7e,0x01,0x5f,0x72,0x41,0x25,0x04,0xa1,
+0x7d,0x01,0xc6,0x65,0x27,0x4a,0x05,0x01,0xc6,0xaf,0xfa,0xcd,0x9c,0xae,0xa4,0x00,
+0x83,0x35,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x01,0x6b,0x9f,0x83,0xc6,
+0x05,0x20,0x14,0x72,0x10,0x20,0x06,0x35,0x88,0x88,0x88,0x88,0x88,0xa0,0x00,0x3b,
+0xa1,0x00,0x3b,0xa2,0x00,0x3b,0xa3,0x00,0x3b,0xa7,0x00,0x3b,0xa8,0x00,0x3b,0xa9,
+0x00,0x3b,0xa4,0x00,0x3b,0xa5,0x00,0x3b,0xa6,0x00,0x3b,0x89,0x90,0x81,0xa4,0x00,
+0x8c,0x35,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x80,0x85,0x90,0xa6,0x00,
+0x32,0xa5,0x00,0x32,0xa4,0x00,0x32,0xa9,0x00,0x32,0xa8,0x00,0x32,0xa7,0x00,0x32,
+0xa3,0x00,0x32,0xa2,0x00,0x32,0xa1,0x00,0x32,0xa0,0x00,0x32,0x84,0xaf,0xfa,0xcd,
+0x0c,0xae,0x27,0xad,0xf0,0xa4,0x01,0x7b,0x1c,0x01,0x5f,0x72,0x05,0x20,0x16,0x72,
+0x06,0x20,0xc7,0x05,0xaa,0x06,0x20,0xc6,0x1b,0x27,0x04,0xa5,0x01,0x7b,0xaf,0xfa,
+0xcd,0x0c,0xae,0x48,0xad,0xf0,0xa4,0x05,0x20,0x16,0x72,0x06,0x20,0x14,0x72,0x11,
+0x20,0x1c,0x01,0x5a,0x72,0x60,0xc3,0xcd,0x02,0xa6,0x05,0x26,0x4a,0x05,0x20,0x4f,
+0x03,0x25,0x02,0xa1,0x1c,0x01,0xc6,0xaf,0xfa,0xcd,0x10,0xae,0x71,0xad,0x1d,0x01,
+0xd6,0x22,0x27,0x1c,0x01,0xce,0x59,0x27,0x0f,0xa5,0x01,0x7b,0xaf,0xfa,0xcd,0x0c,
+0xae,0x65,0xc4,0xcd,0x0f,0xa4,0x05,0x20,0x16,0x72,0x06,0x20,0x12,0x72,0x09,0x01,
+0x01,0x35,0x18,0x27,0x20,0xa5,0x01,0x7b,0x98,0xad,0x4f,0x05,0x27,0x80,0xa5,0x01,
+0x7b,0x0b,0x01,0xd7,0x17,0x8c,0xc6,0x0a,0x01,0x5c,0x72,0x0a,0x01,0xce,0x0f,0x27,
+0x80,0xa5,0x07,0x20,0x0a,0x01,0xcf,0x06,0x20,0x13,0x72,0x09,0x27,0x10,0xa5,0x20,
+0x26,0x09,0x01,0xce,0x01,0x6b,0x0f,0x8c,0xc6,0x10,0x20,0x10,0x35,0x88,0xa0,0x00,
+0x3b,0xa1,0x00,0x3b,0xa2,0x00,0x3b,0xa3,0x00,0x3b,0xa7,0x00,0x3b,0xa8,0x00,0x3b,
+0xa9,0x00,0x3b,0xa4,0x00,0x3b,0xa5,0x00,0x3b,0xa6,0x00,0x3b,0x89,0x90,0xaf,0xfa,
+0xcc,0x0c,0xae,0xa4,0x00,0x8c,0x35,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,
+0x80,0x85,0x90,0xa6,0x00,0x32,0xa5,0x00,0x32,0xa4,0x00,0x32,0xa9,0x00,0x32,0xa8,
+0x00,0x32,0xa7,0x00,0x32,0x84,0x84,0x84,0x84,0xa0,0x84,0xc7,0x01,0x7b,0xa1,0x84,
+0xc7,0x02,0x7b,0xa2,0x84,0xc7,0x03,0x7b,0xa3,0x84,0xc7,0x04,0x7b,0x76,0x01,0x01,
+0x35,0x01,0x6b,0x7f,0xa4,0x01,0x7b,0x0a,0x20,0x01,0x6b,0x80,0xaa,0x01,0x7b,0x12,
+0x27,0x02,0xa1,0x74,0x01,0xc6,0x0f,0x26,0x03,0xa1,0x04,0x27,0x02,0xa1,0x05,0x01,
+0xc6,0x1a,0x27,0x06,0x01,0xc6,0x05,0x26,0x07,0x01,0xc6,0x01,0x6b,0xa0,0x84,0xc6,
+0x02,0x6b,0xa1,0x84,0xc6,0x03,0x6b,0xa2,0x84,0xc6,0x04,0x6b,0xa3,0x84,0xc6,0x7d,
+0x01,0x5f,0x72,0x74,0x01,0xc7,0x03,0xa4,0x83,0x84,0xc6,0xfd,0xe1,0xcd,0x03,0x26,
+0x4a,0x73,0x01,0xc6,0x05,0x20,0x12,0x72,0x10,0x20,0x01,0x35,0x88,0x88,0x88,0x88,
+0xa7,0x00,0x3b,0xa8,0x00,0x3b,0xa9,0x00,0x3b,0xa4,0x00,0x3b,0xa5,0x00,0x3b,0xa6,
+0x00,0x3b,0x89,0x90,0x80,0x12,0x20,0x10,0x35,0x80,0xe6,0x20,0x8f,0xe9,0x26,0x01,
+0x7b,0x36,0xf8,0xcd,0x01,0x7b,0x0f,0xf3,0xcd,0x05,0x24,0x20,0xa1,0x0c,0x27,0x01,
+0x6b,0x28,0xc0,0xcd,0x79,0xc0,0xcd,0x88,0x81,0x84,0x06,0x20,0x08,0x35,0x9a,0x1a,
+0x20,0x10,0x72,0x15,0x20,0xc7,0xee,0xa4,0x15,0x20,0xc6,0x14,0x20,0xc7,0x7c,0xa4,
+0x14,0x20,0xc6,0x13,0x20,0xc7,0x08,0xa4,0x13,0x20,0xc6,0x3a,0xe1,0xcd,0x84,0x84,
+0x84,0x84,0x84,0x84,0x84,0x84,0x29,0xd5,0xcd,0x01,0x01,0x3b,0x02,0x01,0x3b,0x03,
+0x01,0x3b,0x04,0x01,0x3b,0x01,0x4b,0x80,0x4b,0x85,0x4b,0x80,0x4b,0xb0,0x84,0x00,
+0x35,0xb1,0x84,0x00,0x35,0xb2,0x84,0x00,0x35,0xb3,0x84,0x13,0x35,0xa4,0x84,0x00,
+0x35,0xa5,0x84,0x00,0x35,0xa6,0x84,0x00,0x35,0xa7,0x84,0x00,0x35,0xa0,0x84,0x00,
+0x35,0xa1,0x84,0x00,0x35,0xa2,0x84,0x00,0x35,0xa3,0x84,0x00,0x35,0x0c,0x8c,0x00,
+0x35,0x0d,0x8c,0x00,0x35,0x0e,0x8c,0x00,0x35,0x0f,0x8c,0x00,0x35,0x18,0x8c,0x00,
+0x35,0x19,0x8c,0x00,0x35,0x1a,0x8c,0x00,0x35,0x1b,0x8c,0x03,0x35,0x04,0x8c,0x00,
+0x35,0x05,0x8c,0x00,0x35,0x06,0x8c,0x00,0x35,0x07,0x8c,0x0a,0x35,0x00,0x8c,0x00,
+0x35,0x01,0x8c,0x00,0x35,0x02,0x8c,0x00,0x35,0x03,0x8c,0x00,0x35,0x1c,0x8c,0x00,
+0x35,0x1d,0x8c,0x00,0x35,0x1e,0x8c,0x00,0x35,0x1f,0x8c,0x04,0x35,0xfd,0xe1,0xcd,
+0x11,0xe3,0xcd,0x24,0x83,0x00,0x35,0x25,0x83,0x00,0x35,0x26,0x83,0x02,0x35,0x27,
+0x83,0x00,0x35,0x84,0x84,0x00,0x35,0x85,0x84,0x00,0x35,0x86,0x84,0x00,0x35,0x87,
+0x84,0x20,0x35,0xb4,0x84,0x00,0x35,0xb5,0x84,0x40,0x35,0xb6,0x84,0x00,0x35,0xb7,
+0x84,0x80,0x35,0x18,0x84,0x00,0x35,0x19,0x84,0x00,0x35,0x1a,0x84,0x00,0x35,0x1b,
+0x84,0x00,0x35,0x78,0x84,0x00,0x35,0x79,0x84,0x00,0x35,0x7a,0x84,0x00,0x35,0x7b,
+0x84,0x00,0x35,0x3f,0x20,0x01,0x35,0x3d,0x20,0xc7,0xff,0xa6,0x3c,0x20,0xc7,0x04,
+0xa6,0x3e,0x20,0xfe,0x35,0x01,0x01,0x02,0x35,0x02,0x01,0x49,0x35,0x03,0x01,0xf0,
+0x35,0x04,0x01,0xc7,0x0f,0x20,0x01,0x01,0x01,0x35,0x02,0x01,0x9b,0x35,0x03,0x01,
+0xfc,0x35,0x04,0x01,0xc0,0x35,0x0c,0x20,0x02,0x01,0x8c,0x35,0x03,0x01,0xba,0x35,
+0x04,0x01,0x80,0x35,0x1a,0x20,0x02,0x01,0x24,0x35,0x03,0x01,0xf8,0x35,0x04,0x01,
+0xc7,0x3c,0x20,0x01,0x01,0x5f,0x72,0x02,0x01,0x5f,0x72,0x03,0x01,0x5f,0x72,0x04,
+0x01,0x5f,0x72,0x3f,0x27,0x4a,0x30,0x27,0x4a,0x25,0x27,0x4a,0x1b,0x27,0x0f,0xa4,
+0x08,0x20,0xc6,0x7f,0x01,0xc7,0x0f,0xa4,0x4e,0x03,0x20,0xc6,0xf2,0x25,0x10,0xa1,
+0x01,0x6b,0x4c,0x58,0x01,0x4f,0x72,0x01,0xee,0x72,0x01,0x6b,0x4f,0xbf,0x00,0x5f,
+0x72,0xc1,0x00,0x5f,0x72,0xc0,0x00,0x5f,0x72,0x69,0x01,0x5f,0x72,0x68,0x01,0x5f,
+0x72,0x30,0x01,0x5f,0x72,0x38,0x01,0x5f,0x72,0x31,0x01,0x5f,0x72,0x32,0x01,0x5f,
+0x72,0x1b,0x01,0x5f,0x72,0x77,0x01,0x5f,0x72,0x7a,0x01,0x5f,0x72,0x06,0x01,0x5f,
+0x72,0x07,0x01,0x5f,0x72,0xae,0x00,0x5f,0x72,0x09,0x01,0x5f,0x72,0x1c,0x01,0x5f,
+0x72,0x0a,0x01,0x5f,0x72,0xc2,0x00,0x5f,0x72,0xc3,0x00,0x5f,0x72,0x05,0x01,0x5f,
+0x72,0x11,0x3f,0x10,0x3f,0x08,0x01,0x5f,0x72,0x56,0x01,0x5f,0x72,0x57,0x01,0x5f,
+0x72,0x7b,0x01,0x5f,0x72,0x7c,0x01,0xff,0x35,0x7e,0x01,0x5f,0x72,0x76,0x01,0x5f,
+0x72,0x9b,0x06,0x20,0x5f,0x72,0x88,0x81,0x84,0xe3,0xad,0xf4,0x25,0x40,0xa1,0x01,
+0x6b,0x4c,0x12,0x6f,0x01,0xee,0x72,0x01,0x6b,0x4f,0x88,0x81,0x05,0x20,0x10,0x72,
+0x15,0x20,0x11,0x72,0x10,0x1e,0x98,0xc2,0xcc,0x8b,0xff,0xa6,0x04,0xae,0x81,0x85,
+0x01,0x7b,0x9a,0x56,0x01,0xc7,0x0f,0xa4,0x56,0x01,0xc6,0x58,0x01,0x4f,0x72,0x56,
+0x01,0x5c,0x72,0x01,0x6b,0x58,0x01,0xd6,0x56,0x01,0xce,0x18,0x27,0x56,0x01,0xc1,
+0x57,0x01,0xc6,0x9b,0x01,0x6b,0x4f,0x88,0x81,0x84,0x9a,0x57,0x01,0xc7,0x0f,0xa4,
+0x57,0x01,0xc6,0x58,0x01,0xd7,0x57,0x01,0x5c,0x72,0x57,0x01,0xce,0x01,0x7b,0x14,
+0x27,0x01,0xe1,0x72,0x58,0x01,0xd6,0x97,0x0f,0xa4,0x4a,0x57,0x01,0xc6,0x9b,0x88,
+};
+
diff --git a/arch/arm/mach-ux500/include/mach/av8100_p.h b/arch/arm/mach-ux500/include/mach/av8100_p.h
new file mode 100755
index 00000000000..f3254cebbf9
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/av8100_p.h
@@ -0,0 +1,188 @@
+/*---------------------------------------------------------------------------*/
+/* © copyright STEricsson,2009. All rights reserved. For */
+/* information, STEricsson reserves the right to license */
+/* this software concurrently under separate license conditions. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it */
+/* under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, */
+/* or (at your option)any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */
+/* the GNU Lesser General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*---------------------------------------------------------------------------*/
+
+#include <mach/av8100.h>
+
+/* defines for av8100_ */
+#define av8100_command_offset 0x10
+#define AV8100_COMMAND_MAX_LENGTH 0x81
+#define GPIO_AV8100_RSTN 196
+#define GPIO_AV8100_INT 192
+#define AV8100_DRIVER_MINOR_NUMBER 240
+
+
+#define HDMI_HOTPLUG_INTERRUPT 0x1
+#define HDMI_HOTPLUG_INTERRUPT_MASK 0xFE
+#define CVBS_PLUG_INTERRUPT 0x2
+#define CVBS_PLUG_INTERRUPT_MASK 0xFD
+#define TE_INTERRUPT_MASK 0x40
+#define UNDER_OVER_FLOW_INTERRUPT_MASK 0x20
+
+#define REG_16_8_LSB(p) (unsigned char)(p & 0xFF)
+#define REG_16_8_MSB(p) (unsigned char)((p & 0xFF00)>>8)
+#define REG_32_8_MSB(p) (unsigned char)((p & 0xFF000000)>>24)
+#define REG_32_8_MMSB(p) (unsigned char)((p & 0x00FF0000)>>16)
+#define REG_32_8_MLSB(p) (unsigned char)((p & 0x0000FF00)>>8)
+#define REG_32_8_LSB(p) (unsigned char)(p & 0x000000FF)
+
+/**
+ * struct av8100_cea - CEA(consumer electronic access) standard structure
+ * @cea_id:
+ * @cea_nb:
+ * @vtotale:
+ **/
+
+ typedef struct {
+ char cea_id[40] ;
+ int cea_nb ;
+ int vtotale;
+ int vactive;
+ int vsbp ;
+ int vslen ;
+ int vsfp;
+ char vpol[5];
+ int htotale;
+ int hactive;
+ int hbp ;
+ int hslen ;
+ int hfp;
+ int frequence;
+ char hpol[5];
+ int reg_line_duration;
+ int blkoel_duration;
+ int uix4;
+ int pll_mult;
+ int pll_div;
+}av8100_cea;
+
+/**
+ * struct av8100_data - av8100_ internal structure
+ * @client: pointer to i2c client
+ * @work: work_struct scheduled during bottom half
+ * @sem: semaphore used for data protection
+ * @device_type: hdmi or cvbs
+ * @edid: extended display identification data
+ **/
+struct av8100_data{
+ struct i2c_client *client;
+ struct work_struct work;
+ struct semaphore sem;
+ char device_type;
+ char edid[127];
+};
+
+/**
+ * struct av8100_platform_data - av8100_ platform data
+ * @irq: irq num
+ **/
+struct av8100_platform_data {
+ unsigned gpio_base;
+ int irq;
+};
+/**
+ * struct av8100_video_input_format_cmd - video input format structure
+ * @dsi_input_mode:
+ * @input_pixel_format:
+ * @total_horizontal_pixel:
+ **/
+typedef struct {
+ av8100_dsi_mode dsi_input_mode;
+ av8100_pixel_format input_pixel_format;
+ unsigned short total_horizontal_pixel; /*number of total horizontal pixels in the frame*/
+ unsigned short total_horizontal_active_pixel; /*number of total horizontal active pixels in the frame*/
+ unsigned short total_vertical_lines; /*number of total vertical lines in the frame*/
+ unsigned short total_vertical_active_lines; /*number of total vertical active lines*/
+ av8100_video_mode video_mode;
+ av8100_dsi_nb_data_lane nb_data_lane;
+ unsigned char nb_virtual_ch_command_mode;
+ unsigned char nb_virtual_ch_video_mode;
+ unsigned short TE_line_nb; /* Tearing effect line number*/
+ av8100_te_config TE_config;
+ unsigned long master_clock_freq; /* Master clock frequency in HZ */
+} av8100_video_input_format_cmd;
+/**
+ * struct av8100_video_output_format_cmd - video output format structure
+ * @dsi_input_mode:
+ * @input_pixel_format:
+ * @total_horizontal_pixel:
+ **/
+typedef struct {
+ av8100_output_CEA_VESA video_output_cea_vesa;
+ av8100_video_sync_pol vsync_polarity;
+ av8100_video_sync_pol hsync_polarity;
+ unsigned short total_horizontal_pixel; /*number of total horizontal pixels in the frame*/
+ unsigned short total_horizontal_active_pixel; /*number of total horizontal active pixels in the frame*/
+ unsigned short total_vertical_in_half_lines; /*number of total vertical lines in the frame*/
+ unsigned short total_vertical_active_in_half_lines; /*number of total vertical active lines*/
+ unsigned short hsync_start_in_pixel;
+ unsigned short hsync_length_in_pixel;
+ unsigned short vsync_start_in_half_line;
+ unsigned short vsync_length_in_half_line;
+ unsigned long pixel_clock_freq_Hz;
+} av8100_video_output_format_cmd;
+/**
+ * struct av8100_pattern_generator_cmd - pattern generator format structure
+ * @pattern_type:
+ * @pattern_video_format:
+ * @pattern_audio_mode:
+ **/
+typedef struct {
+ av8100_pattern_type pattern_type;
+ av8100_pattern_format pattern_video_format;
+ av8100_pattern_audio pattern_audio_mode;
+} av8100_pattern_generator_cmd;
+/**
+ * struct av8100_audio_input_format_cmd - audio input format structure
+ * @audio_input_if_format:
+ * @i2s_input_nb:
+ * @sample_audio_freq:
+ **/
+typedef struct {
+ av8100_audio_if_format audio_input_if_format; /* mode of the MSP*/
+ unsigned char i2s_input_nb; /* 0, 1 2 3 4*/
+ av8100_sample_freq sample_audio_freq;
+ av8100_audio_word_length audio_word_lg;
+ av8100_audio_format audio_format;
+ av8100_audio_if_mode audio_if_mode;
+ av8100_audio_mute audio_mute;
+} av8100_audio_input_format_cmd;
+/**
+ * struct av8100_video_scaling_format_cmd - video scaling format structure
+ * @h_start_in_pixel:
+ * @h_stop_in_pixel:
+ * @v_start_in_line:
+ **/
+typedef struct {
+ unsigned short h_start_in_pixel;
+ unsigned short h_stop_in_pixel;
+ unsigned short v_start_in_line;
+ unsigned short v_stop_in_line;
+} av8100_video_scaling_format_cmd;
+/**
+ * struct av8100_hdmi_cmd - hdmi command structure
+ * @hdmi_mode:
+ * @hdmi_format:
+ * @dvi_format:
+ **/
+typedef struct {
+ av8100_hdmi_mode hdmi_mode;
+ av8100_hdmi_format hdmi_format;
+ av8100_DVI_format dvi_format; /* used only if HDMI_format = DVI*/
+} av8100_hdmi_cmd;
+/* STWav8100 Private functions */
diff --git a/arch/arm/mach-ux500/include/mach/bit_mask.h b/arch/arm/mach-ux500/include/mach/bit_mask.h
new file mode 100755
index 00000000000..9487dff5242
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/bit_mask.h
@@ -0,0 +1,110 @@
+/*---------------------------------------------------------------------------*/
+/* Copyright (C) STEricsson 2009. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it */
+/* under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, */
+/* or (at your option)any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */
+/* the GNU Lesser General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*---------------------------------------------------------------------------*/
+
+#ifndef _BITMASK_H_
+#define _BITMASK_H_
+
+/*-----------------------------------------------------------------------------
+ * Bit mask definition
+ *---------------------------------------------------------------------------*/
+#define TRUE 0x1
+#define FALSE 0x0
+#define MASK_NULL8 0x00
+#define MASK_NULL16 0x0000
+#define MASK_NULL32 0x00000000
+#define MASK_ALL8 0xFF
+#define MASK_ALL16 0xFFFF
+#define MASK_ALL32 0xFFFFFFFF
+
+#define MASK_BIT0 (1UL<<0)
+#define MASK_BIT1 (1UL<<1)
+#define MASK_BIT2 (1UL<<2)
+#define MASK_BIT3 (1UL<<3)
+#define MASK_BIT4 (1UL<<4)
+#define MASK_BIT5 (1UL<<5)
+#define MASK_BIT6 (1UL<<6)
+#define MASK_BIT7 (1UL<<7)
+#define MASK_BIT8 (1UL<<8)
+#define MASK_BIT9 (1UL<<9)
+#define MASK_BIT10 (1UL<<10)
+#define MASK_BIT11 (1UL<<11)
+#define MASK_BIT12 (1UL<<12)
+#define MASK_BIT13 (1UL<<13)
+#define MASK_BIT14 (1UL<<14)
+#define MASK_BIT15 (1UL<<15)
+#define MASK_BIT16 (1UL<<16)
+#define MASK_BIT17 (1UL<<17)
+#define MASK_BIT18 (1UL<<18)
+#define MASK_BIT19 (1UL<<19)
+#define MASK_BIT20 (1UL<<20)
+#define MASK_BIT21 (1UL<<21)
+#define MASK_BIT22 (1UL<<22)
+#define MASK_BIT23 (1UL<<23)
+#define MASK_BIT24 (1UL<<24)
+#define MASK_BIT25 (1UL<<25)
+#define MASK_BIT26 (1UL<<26)
+#define MASK_BIT27 (1UL<<27)
+#define MASK_BIT28 (1UL<<28)
+#define MASK_BIT29 (1UL<<29)
+#define MASK_BIT30 (1UL<<30)
+#define MASK_BIT31 (1UL<<31)
+
+/*-----------------------------------------------------------------------------
+ * quartet shift definition
+ *---------------------------------------------------------------------------*/
+#define MASK_QUARTET (0xFUL)
+#define SHIFT_QUARTET0 0
+#define SHIFT_QUARTET1 4
+#define SHIFT_QUARTET2 8
+#define SHIFT_QUARTET3 12
+#define SHIFT_QUARTET4 16
+#define SHIFT_QUARTET5 20
+#define SHIFT_QUARTET6 24
+#define SHIFT_QUARTET7 28
+#define MASK_QUARTET0 (MASK_QUARTET << SHIFT_QUARTET0)
+#define MASK_QUARTET1 (MASK_QUARTET << SHIFT_QUARTET1)
+#define MASK_QUARTET2 (MASK_QUARTET << SHIFT_QUARTET2)
+#define MASK_QUARTET3 (MASK_QUARTET << SHIFT_QUARTET3)
+#define MASK_QUARTET4 (MASK_QUARTET << SHIFT_QUARTET4)
+#define MASK_QUARTET5 (MASK_QUARTET << SHIFT_QUARTET5)
+#define MASK_QUARTET6 (MASK_QUARTET << SHIFT_QUARTET6)
+#define MASK_QUARTET7 (MASK_QUARTET << SHIFT_QUARTET7)
+
+/*-----------------------------------------------------------------------------
+ * Byte shift definition
+ *---------------------------------------------------------------------------*/
+#define MASK_BYTE (0xFFUL)
+#define SHIFT_BYTE0 0
+#define SHIFT_BYTE1 8
+#define SHIFT_BYTE2 16
+#define SHIFT_BYTE3 24
+#define MASK_BYTE0 (MASK_BYTE << SHIFT_BYTE0)
+#define MASK_BYTE1 (MASK_BYTE << SHIFT_BYTE1)
+#define MASK_BYTE2 (MASK_BYTE << SHIFT_BYTE2)
+#define MASK_BYTE3 (MASK_BYTE << SHIFT_BYTE3)
+
+/*-----------------------------------------------------------------------------
+ * Halfword shift definition
+ *---------------------------------------------------------------------------*/
+#define MASK_HALFWORD (0xFFFFUL)
+#define SHIFT_HALFWORD0 0
+#define SHIFT_HALFWORD1 16
+#define MASK_HALFWORD0 (MASK_HALFWORD << SHIFT_HALFWORD0)
+#define MASK_HALFWORD1 (MASK_HALFWORD << SHIFT_HALFWORD1)
+
+#endif
+
diff --git a/arch/arm/mach-ux500/include/mach/bits.h b/arch/arm/mach-ux500/include/mach/bits.h
new file mode 100755
index 00000000000..0f0e4edd1cc
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/bits.h
@@ -0,0 +1,64 @@
+/*----------------------------------------------------------------------------------*/
+/* copyright STMicroelectronics, 2007. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it under */
+/* the terms of the GNU General Public License as published by the Free */
+/* Software Foundation; either version 2.1 of the License, or (at your option) */
+/* any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but WITHOUT */
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS */
+/* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*----------------------------------------------------------------------------------*/
+
+
+
+/* DO NOT EDIT!! - this file automatically generated
+ * from .s file by awk -f s2h.awk
+ */
+/* Bit field definitions
+ * Copyright (C) ARM Limited 1998. All rights reserved.
+ */
+
+#ifndef __bits_h
+#define __bits_h 1
+
+#define BIT0 0x00000001
+#define BIT1 0x00000002
+#define BIT2 0x00000004
+#define BIT3 0x00000008
+#define BIT4 0x00000010
+#define BIT5 0x00000020
+#define BIT6 0x00000040
+#define BIT7 0x00000080
+#define BIT8 0x00000100
+#define BIT9 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+
+#endif
+
+/* END */
diff --git a/arch/arm/mach-ux500/include/mach/clkdev.h b/arch/arm/mach-ux500/include/mach/clkdev.h
new file mode 100755
index 00000000000..04b37a89801
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
new file mode 100644
index 00000000000..474f6d3d968
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_DB5500_REGS_H
+#define __MACH_DB5500_REGS_H
+
+#define U5500_PER1_BASE 0xA0020000
+#define U5500_PER2_BASE 0xA0010000
+#define U5500_PER3_BASE 0x80140000
+#define U5500_PER4_BASE 0x80150000
+#define U5500_PER5_BASE 0x80100000
+#define U5500_PER6_BASE 0x80120000
+
+#define U5500_GIC_DIST_BASE 0xA0411000
+#define U5500_GIC_CPU_BASE 0xA0410100
+#define U5500_DMA_BASE 0x90030000
+#define U5500_MCDE_BASE 0xA0400000
+#define U5500_MODEM_BASE 0xB0000000
+#define U5500_L2CC_BASE 0xA0412000
+#define U5500_SCU_BASE 0xA0410000
+#define U5500_DSI1_BASE 0xA0401000
+#define U5500_DSI2_BASE 0xA0402000
+#define U5500_SIA_BASE 0xA0100000
+#define U5500_SVA_BASE 0x80200000
+#define U5500_HSEM_BASE 0xA0000000
+#define U5500_NAND0_BASE 0x60000000
+#define U5500_NAND1_BASE 0x70000000
+#define U5500_TWD_BASE 0xa0410600
+#define U5500_B2R2_BASE 0xa0200000
+
+#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000)
+#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000)
+#define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000)
+#define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000)
+#define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000)
+#define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000)
+#define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000)
+#define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000)
+
+#define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000)
+#define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000)
+#define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000)
+
+#define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000)
+#define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000)
+#define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000)
+#define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000)
+
+#define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000)
+#define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000)
+#define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000)
+#define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000)
+#define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000)
+#define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000)
+#define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000)
+#define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000)
+#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000)
+#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000)
+#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000)
+
+#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000)
+#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000)
+#define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000)
+#define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000)
+#define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000)
+#define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000)
+#define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000)
+#define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000)
+#define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000)
+#define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000)
+#define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000)
+#define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000)
+#define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000)
+#define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000)
+#define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000)
+#define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000)
+#define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000)
+
+#define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000)
+#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000)
+#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000)
+#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000)
+#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5000)
+#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000)
+#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000)
+#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000)
+#define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000)
+#define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000)
+#define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000)
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
new file mode 100644
index 00000000000..e3d62b94ffc
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_DB8500_REGS_H
+#define __MACH_DB8500_REGS_H
+
+#define U8500_PER3_BASE 0x80000000
+#define U8500_STM_BASE 0x80100000
+#define U8500_STM_REG_BASE (U8500_STM_BASE+0xF000)
+#define U8500_PER2_BASE 0x80110000
+#define U8500_PER1_BASE 0x80120000
+#define U8500_B2R2_BASE 0x80130000
+#define U8500_HSEM_BASE 0x80140000
+#define U8500_PER4_BASE 0x80150000
+
+#define U8500_PER6_BASE 0xa03c0000
+#define U8500_PER5_BASE 0xa03e0000
+#define U8500_PER7_BASE_ED 0xa03d0000
+
+#define U8500_SVA_BASE 0xa0100000
+#define U8500_SIA_BASE 0xa0200000
+
+#define U8500_SGA_BASE 0xa0300000
+#define U8500_MCDE_BASE 0xa0350000
+#define U8500_DMA_BASE_ED 0xa0362000
+#define U8500_DMA_BASE 0x801C0000 /* v1 */
+
+#define U8500_SCU_BASE 0xa0410000
+#define U8500_GIC_CPU_BASE 0xa0410100
+#define U8500_TWD_BASE 0xa0410600
+#define U8500_GIC_DIST_BASE 0xa0411000
+#define U8500_L2CC_BASE 0xa0412000
+
+#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
+#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000)
+#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000)
+#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000)
+
+/* per7 base addressess */
+#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000)
+#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000)
+#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000)
+#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000)
+#define U8500_CLKRST7_BASE (U8500_PER7_BASE_ED + 0xf000)
+
+#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
+#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
+
+/* per6 base addressess */
+#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
+#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
+#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
+#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */
+#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */
+#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */
+#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
+#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
+#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
+
+/* per5 base addressess */
+#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
+#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
+
+/* per4 base addressess */
+#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000)
+#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000)
+#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000)
+#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000)
+#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000)
+#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
+#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
+#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000)
+
+/* per3 base addresses */
+#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
+#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
+#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
+#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
+#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
+#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
+#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
+#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
+#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
+
+/* per2 base addressess */
+#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
+#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
+#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
+#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
+#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
+#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
+#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
+#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
+#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
+#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
+#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
+#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
+
+/* per1 base addresses */
+#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
+#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
+#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
+#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
+#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
+#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
+#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000)
+#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000)
+#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
+
+#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
new file mode 100755
index 00000000000..9cec503ff01
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * Debugging macro include header
+ *
+ * Copyright (C) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <mach/hardware.h>
+
+ .macro addruart,rx
+ mrc p15, 0, \rx, c1, c0
+ tst \rx, #1 @MMU enabled?
+ ldreq \rx, =UX500_UART2_BASE @ no, physical address
+ ldrne \rx, =IO_ADDRESS(UX500_UART2_BASE) @ yes, virtual address
+ .endm
+
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ux500/include/mach/debug.h b/arch/arm/mach-ux500/include/mach/debug.h
new file mode 100755
index 00000000000..3567d7f5b38
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/debug.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2009 STMicroelectronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+#ifndef __INC_DBG_H
+#define __INC_DBG_H
+
+/* Store a submitter ID, unique for each HCL. */
+
+struct driver_debug_st {
+ int mtd;
+ int gpio;
+ int mmc;
+ int ssp;
+ int mtu;
+ int msp;
+ int spi;
+ int touch;
+ int dma;
+ int rtc;
+ int acodec;
+ int tourg;
+ int alsa;
+ int keypad;
+ int mcde;
+ int power;
+ int i2c;
+ int hsi;
+};
+
+#define stm_error(format, arg...) printk(KERN_ERR DRIVER_DEBUG_PFX ":ERROR " format "\n" , ## arg)
+#define stm_warn(format, arg...) printk(KERN_WARNING DRIVER_DEBUG_PFX ":WARNING " format "\n" , ## arg)
+#define stm_info(format, arg...) printk(KERN_INFO DRIVER_DEBUG_PFX ":INFO" format "\n" , ## arg)
+
+
+#define stm_dbg(debug, format, arg...) (!(DRIVER_DEBUG)) ? ({do {} while(0); }) : debug == 1 ? (printk(DRIVER_DBG DRIVER_DEBUG_PFX ": " format "\n" , ## arg)) : ({do {} while (0); })
+
+#define stm_dbg2(debug, format, arg...) (!(DRIVER_DEBUG)) ? ({do {} while(0); }) : debug == 2 ? (printk(DRIVER_DBG DRIVER_DEBUG_PFX ": " format "\n" , ## arg)) : ({do {} while (0); })
+
+#define stm_dbg3(debug, format, arg...) (!(DRIVER_DEBUG)) ? ({do {} while(0); }) : debug == 3 ? (printk(DRIVER_DBG DRIVER_DEBUG_PFX ": " format "\n" , ## arg)) : ({do {} while (0); })
+
+#define stm_dbg4(format, arg...) (DRIVER_DEBUG & 1) ? (printk(DRIVER_DBG DRIVER_DEBUG_PFX ": " format "\n" , ## arg)) : ({do {} while (0); })
+
+extern struct driver_debug_st DBG_ST;
+#endif
+
+/* __INC_DBG_H */
+
+/* End of file - debug.h */
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
new file mode 100644
index 00000000000..0ffc1a05c3d
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_DEVICES_H__
+#define __ASM_ARCH_DEVICES_H__
+
+struct platform_device;
+struct amba_device;
+
+void __init u8500_register_device(struct platform_device *dev, void *data);
+void __init u8500_register_amba_device(struct amba_device *dev, void *data);
+
+extern struct amba_device u5500_gpio0_device;
+extern struct amba_device u5500_gpio1_device;
+extern struct amba_device u5500_gpio2_device;
+extern struct amba_device u5500_gpio3_device;
+extern struct amba_device u5500_gpio4_device;
+
+extern struct amba_device u8500_gpio0_device;
+extern struct amba_device u8500_gpio1_device;
+extern struct amba_device u8500_gpio2_device;
+extern struct amba_device u8500_gpio3_device;
+
+extern struct platform_device u8500_msp0_device;
+extern struct platform_device u8500_msp1_device;
+extern struct platform_device u8500_msp2_device;
+extern struct amba_device u8500_msp2_spi_device;
+extern struct platform_device u8500_i2c0_device;
+extern struct platform_device ux500_i2c1_device;
+extern struct platform_device ux500_i2c2_device;
+extern struct platform_device ux500_i2c3_device;
+extern struct platform_device u8500_i2c4_device;
+extern struct platform_device u8500_mcde2_device;
+extern struct platform_device u8500_mcde3_device;
+extern struct platform_device u8500_mcde1_device;
+extern struct platform_device u8500_mcde0_device;
+extern struct platform_device u8500_hsit_device;
+extern struct platform_device u8500_hsir_device;
+extern struct platform_device u8500_shrm_device;
+extern struct platform_device ux500_b2r2_device;
+extern struct platform_device u8500_pmem_device;
+extern struct platform_device u8500_pmem_mio_device;
+extern struct platform_device u8500_pmem_hwb_device;
+extern struct amba_device ux500_rtc_device;
+extern struct platform_device ux500_dma_device;
+extern struct amba_device u8500_ssp0_device;
+extern struct amba_device u8500_ssp1_device;
+extern struct amba_device ux500_spi0_device;
+extern struct amba_device ux500_sdi4_device;
+extern struct amba_device ux500_sdi0_device;
+extern struct amba_device ux500_sdi1_device;
+extern struct amba_device ux500_sdi2_device;
+extern struct platform_device u8500_ab8500_device;
+extern struct platform_device ux500_musb_device;
+extern struct amba_device ux500_uart0_device;
+extern struct amba_device ux500_uart1_device;
+extern struct amba_device ux500_uart2_device;
+
+/*
+ * Do not use inside drivers. Check it in the board file and alter platform
+ * data.
+ */
+extern int platform_id;
+#define MOP500_PLATFORM_ID 0
+#define HREF_PLATFORM_ID 1
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/dma.h b/arch/arm/mach-ux500/include/mach/dma.h
new file mode 100755
index 00000000000..269dd4c8108
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/dma.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2009 ST-Ericsson.
+ * Copyright 2009 STMicroelectronics.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+#ifndef __INC_ASM_ARCH_DMA_H
+#define __INC_ASM_ARCH_DMA_H
+
+#define MAX_DMA_CHANNELS 32
+#ifndef __ASSEMBLY__
+#include <asm/scatterlist.h>
+
+typedef unsigned int dmach_t;
+typedef unsigned int dmamode_t;
+
+enum dma_flow_controller {
+ DMA_IS_FLOW_CNTLR,
+ PERIPH_IS_FLOW_CNTLR
+};
+enum {
+ DMA_FALSE,
+ DMA_TRUE
+};
+
+enum dma_xfer_dir {
+ MEM_TO_MEM,
+ MEM_TO_PERIPH,
+ PERIPH_TO_MEM,
+ PERIPH_TO_PERIPH
+};
+
+enum dma_endianess {
+ DMA_LITTLE_ENDIAN,
+ DMA_BIG_ENDIAN
+};
+enum dma_event {
+ XFER_COMPLETE,
+ XFER_ERROR
+};
+typedef void (*dma_callback_t)(void *data, enum dma_event event);
+
+#include <mach/dma_40-8500.h>
+
+/**
+ * struct stm_dma_pipe_info - Structure to be filled by client drivers.
+ *
+ * @reserve_channel: Whether you want to reserve the channel
+ * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
+ * @flow_cntlr: who is flow controller (Device or DMA)
+ * @phys_chan_id: physical channel ID on which this channel will execute
+ * @data: data of callback handler
+ * @callback: callback handler registered by client
+ * @channel_type: std/ext, basic/log/operational, priority, security
+ * @src_dev_type: Src device type
+ * @dst_dev_type: Dest device type
+ * @src_addr: Source address
+ * @dst_addr: Dest address
+ * @src_info: Parameters for Source half channel
+ * @dst_info: Parameters for Dest half channel
+ *
+ *
+ * This structure has to be filled by the client drivers, before requesting
+ * a DMA pipe. This information is used by the Driver to allocate or
+ * reserve an appropriate DMA channel for this client.
+ *
+ */
+struct stm_dma_pipe_info {
+ unsigned int reserve_channel;
+ enum dma_xfer_dir dir;
+ enum dma_flow_controller flow_cntlr;
+ enum dma_chan_id phys_chan_id;
+ void *data;
+ dma_callback_t callback;
+ unsigned int channel_type;
+ enum dma_src_dev_type src_dev_type;
+ enum dma_dest_dev_type dst_dev_type;
+ void *src_addr;
+ void *dst_addr;
+ struct dma_half_channel_info src_info;
+ struct dma_half_channel_info dst_info;
+};
+
+extern int stm_configure_dma_channel(int channel,
+ struct stm_dma_pipe_info *info);
+extern int stm_request_dma(int *channel, struct stm_dma_pipe_info *info);
+extern void stm_free_dma(int channel);
+extern int stm_set_callback_handler(int channel, void *callback_handler,
+ void *data);
+extern int stm_enable_dma(int channel);
+extern void stm_disable_dma(int channel);
+extern int stm_pause_dma(int channel);
+extern void stm_unpause_dma(int channel);
+extern void stm_set_dma_addr(int channel, void *src_addr , void *dst_addr);
+extern void stm_set_dma_count(int channel, int count);
+extern void stm_set_dma_sg(int channel, struct scatterlist *sg,
+ int nr_sg, int type);
+
+extern int stm_dma_residue(int channel);
+
+#endif /*__ASSEMBLY__*/
+#endif /* __INC_ASM_ARCH_DMA_H */
+/* End of file - dma.h */
+
diff --git a/arch/arm/mach-ux500/include/mach/dma_40-8500.h b/arch/arm/mach-ux500/include/mach/dma_40-8500.h
new file mode 100755
index 00000000000..7e0c15c7752
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/dma_40-8500.h
@@ -0,0 +1,788 @@
+/*----------------------------------------------------------------------------*/
+/* copyright STMicroelectronics, 2008. */
+/* */
+/* This program is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU General Public License as published by */
+/* the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, */
+/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS */
+/* FOR A PARTICULAR PURPOSE. See the GNU General Public License for */
+/* more details. */
+/* */
+/* You should have received a copy of the GNU General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*----------------------------------------------------------------------------*/
+
+#ifndef __INC_ARCH_ARM_SOC_DMA_H
+#define __INC_ARCH_ARM_SOC_DMA_H
+#include <linux/spinlock.h>
+
+/******************************************************************************/
+#define MEM_WRITE_BITS(reg, val, mask, sb) \
+ ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
+#define MEM_READ_BITS(reg, mask, sb) \
+ (((reg) & (mask)) >> (sb))
+
+#define REG_WR_BITS_1(reg, val, mask, sb) \
+ iowrite32(((val)<<(sb) | (~mask)), reg)
+#define REG_WR_BITS(reg, val, mask, sb) \
+ iowrite32(((ioread32(reg) & ~(mask)) | (((val)<<(sb)) & (mask))), reg)
+#define REG_RD_BITS(reg, mask, sb) (((ioread32(reg)) & (mask)) >> (sb))
+/******************************************************************************/
+#define FULL32_MASK 0xFFFFFFFF
+#define NO_SHIFT 0
+#define MAX_PHYSICAL_CHANNELS 32
+#define MAX_AVAIL_PHY_CHANNELS 8
+#define MAX_LOGICAL_CHANNELS 128
+#define NUM_CHANNELS (MAX_LOGICAL_CHANNELS + MAX_PHYSICAL_CHANNELS)
+/******************************************************************************/
+
+#define PHYSICAL_RESOURCE_TYPE_POS(i) (2*(i / 2))
+#define PHYSICAL_RESOURCE_TYPE_MASK(i) (0x3UL << PHYSICAL_RESOURCE_TYPE_POS(i))
+
+#define PHYSICAL_RESOURCE_CHANNEL_MODE_POS(i) (2*(i / 2))
+#define PHYSICAL_RESOURCE_CHANNEL_MODE_MASK(i) \
+ (0x3UL << PHYSICAL_RESOURCE_CHANNEL_MODE_POS(i))
+
+
+#define PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS(i) (2*(i / 2))
+#define PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_MASK(i) \
+ (0x3UL << PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS(i))
+
+#define PHYSICAL_RESOURCE_SECURE_MODE_POS(i) (2*(i / 2))
+#define PHYSICAL_RESOURCE_SECURE_MODE_MASK(i) \
+ (0x3UL << PHYSICAL_RESOURCE_SECURE_MODE_POS(i))
+
+#define ACT_PHY_RES_POS(i) (2*(i / 2))
+#define ACT_PHY_RES_MASK(i) (0x3UL << ACT_PHY_RES_POS(i))
+
+#define ACTIVATE_RESOURCE_MODE_POS(i) (2*(i / 2))
+#define ACTIVATE_RESOURCE_MODE_MASK(i) (0x3UL << ACTIVATE_RESOURCE_MODE_POS(i))
+
+/*****************************************************************************
+ Standard basic Channel configuration macros - start
+******************************************************************************/
+
+/* Standard channel parameters - basic mode */
+/* (Source and Destination config regs have */
+/* similar bit descriptions and hence same mask) */
+/*---------------------------------------------------------------------------*/
+#define SREG_CFG_PHY_MST_POS 15
+#define SREG_CFG_PHY_TIM_POS 14
+#define SREG_CFG_PHY_EIM_POS 13
+#define SREG_CFG_PHY_PEN_POS 12
+#define SREG_CFG_PHY_PSIZE_POS 10
+#define SREG_CFG_PHY_ESIZE_POS 8
+#define SREG_CFG_PHY_PRI_POS 7
+#define SREG_CFG_PHY_LBE_POS 6
+#define SREG_CFG_PHY_TM_POS 4
+#define SREG_CFG_PHY_EVTL_POS 0
+
+#define SREG_CFG_PHY_MST_MASK (0x1UL << SREG_CFG_PHY_MST_POS)
+#define SREG_CFG_PHY_TIM_MASK (0x1UL << SREG_CFG_PHY_TIM_POS)
+#define SREG_CFG_PHY_EIM_MASK (0x1UL << SREG_CFG_PHY_EIM_POS)
+#define SREG_CFG_PHY_PEN_MASK (0x1UL << SREG_CFG_PHY_PEN_POS)
+#define SREG_CFG_PHY_PSIZE_MASK (0x3UL << SREG_CFG_PHY_PSIZE_POS)
+#define SREG_CFG_PHY_ESIZE_MASK (0x3UL << SREG_CFG_PHY_ESIZE_POS)
+#define SREG_CFG_PHY_PRI_MASK (0x1UL << SREG_CFG_PHY_PRI_POS)
+#define SREG_CFG_PHY_LBE_MASK (0x1UL << SREG_CFG_PHY_LBE_POS)
+#define SREG_CFG_PHY_TM_MASK (0x3UL << SREG_CFG_PHY_TM_POS)
+#define SREG_CFG_PHY_EVTL_MASK (0xFUL << SREG_CFG_PHY_EVTL_POS)
+
+/* Standard channel parameters - basic mode (element register) */
+/*---------------------------------------------------------------------------*/
+#define SREG_ELEM_PHY_ECNT_POS 16
+#define SREG_ELEM_PHY_EIDX_POS 0
+
+#define SREG_ELEM_PHY_ECNT_MASK (0xFFFFUL << SREG_ELEM_PHY_ECNT_POS)
+#define SREG_ELEM_PHY_EIDX_MASK (0xFFFFUL << SREG_ELEM_PHY_EIDX_POS)
+
+/* Standard channel parameters - basic mode (Pointer register) */
+/*---------------------------------------------------------------------------*/
+#define SREG_PTR_PHYS_PTR_MASK (0xFFFFFFFFUL)
+
+/* Standard channel parameters - basic mode (Link register) */
+/*---------------------------------------------------------------------------*/
+#define SREG_LNK_PHY_TCP_POS 0
+#define SREG_LNK_PHY_LMP_POS 1
+#define SREG_LNK_PHY_PRE_POS 2
+/* Source destination link address. Contains the
+ * 29-bit byte word aligned address of the reload area.
+ */
+#define SREG_LNK_PHYS_LNK_MASK (0xFFFFFFF8UL)
+#define SREG_LNK_PHYS_TCP_MASK (0x1UL << SREG_LNK_PHY_TCP_POS)
+#define SREG_LNK_PHYS_LMP_MASK (0x1UL << SREG_LNK_PHY_LMP_POS)
+#define SREG_LNK_PHYS_PRE_MASK (0x1UL << SREG_LNK_PHY_PRE_POS)
+/******************************************************************************/
+/* Standard basic Channel configuration macros end */
+/******************************************************************************/
+
+/****************************************************************************/
+/* Standard basic Channel LOGICAL mode - start */
+/****************************************************************************/
+/*Configuration register */
+/*--------------------------------------------------------------------------*/
+
+#define SREG_CFG_LOG_MST_POS 15
+#define SREG_CFG_LOG_TIM_POS 14
+#define SREG_CFG_LOG_EIM_POS 13
+#define SREG_CFG_LOG_INCR_POS 12
+#define SREG_CFG_LOG_PSIZE_POS 10
+#define SREG_CFG_LOG_ESIZE_POS 8
+#define SREG_CFG_LOG_PRI_POS 7
+#define SREG_CFG_LOG_LBE_POS 6
+#define SREG_CFG_LOG_GIM_POS 5
+#define SREG_CFG_LOG_MFU_POS 4
+
+#define SREG_CFG_LOG_MST_MASK (0x1UL << SREG_CFG_LOG_MST_POS)
+#define SREG_CFG_LOG_TIM_MASK (0x1UL << SREG_CFG_LOG_TIM_POS)
+#define SREG_CFG_LOG_EIM_MASK (0x1UL << SREG_CFG_LOG_EIM_POS)
+#define SREG_CFG_LOG_INCR_MASK (0x1UL << SREG_CFG_LOG_INCR_POS)
+#define SREG_CFG_LOG_PSIZE_MASK (0x3UL << SREG_CFG_LOG_PSIZE_POS)
+#define SREG_CFG_LOG_ESIZE_MASK (0x3UL << SREG_CFG_LOG_ESIZE_POS)
+#define SREG_CFG_LOG_PRI_MASK (0x1UL << SREG_CFG_LOG_PRI_POS)
+#define SREG_CFG_LOG_LBE_MASK (0x1UL << SREG_CFG_LOG_LBE_POS)
+#define SREG_CFG_LOG_GIM_MASK (0x1UL << SREG_CFG_LOG_GIM_POS)
+#define SREG_CFG_LOG_MFU_MASK (0x1UL << SREG_CFG_LOG_MFU_POS)
+
+/*Element register*/
+
+#define SREG_ELEM_LOG_ECNT_POS 16
+#define SREG_ELEM_LOG_LIDX_POS 8
+#define SREG_ELEM_LOG_LOS_POS 1
+#define SREG_ELEM_LOG_TCP_POS 0
+
+#define SREG_ELEM_LOG_ECNT_MASK (0xFFFFUL << SREG_ELEM_LOG_ECNT_POS)
+#define SREG_ELEM_LOG_LIDX_MASK (0xFFUL << SREG_ELEM_LOG_LIDX_POS)
+#define SREG_ELEM_LOG_LOS_MASK (0x7FUL << SREG_ELEM_LOG_LOS_POS)
+#define SREG_ELEM_LOG_TCP_MASK (0x1UL << SREG_ELEM_LOG_TCP_POS)
+
+/*Pointer register */
+#define SREG_PTR_LOG_PTR_MASK (0xFFFFFFFFUL)
+
+/*Link registeri */
+#define DEACTIVATE_EVENTLINE 0x0
+#define ACTIVATE_EVENTLINE 0x1
+#define EVENTLINE_POS(i) (2*i)
+#define EVENTLINE_MASK(i) (0x3UL << EVENTLINE_POS(i))
+
+/* Standard basic Channel LOGICAL params in memory*/
+#define MEM_LCSP0_ECNT_POS 16
+#define MEM_LCSP0_SPTR_POS 0
+
+#define MEM_LCSP0_ECNT_MASK (0xFFFFUL << MEM_LCSP0_ECNT_POS)
+#define MEM_LCSP0_SPTR_MASK (0xFFFFUL << MEM_LCSP0_SPTR_POS)
+
+#define MEM_LCSP1_SPTR_POS 16
+
+#define MEM_LCSP1_SCFG_MST_POS 15
+#define MEM_LCSP1_SCFG_TIM_POS 14
+#define MEM_LCSP1_SCFG_EIM_POS 13
+#define MEM_LCSP1_SCFG_INCR_POS 12
+#define MEM_LCSP1_SCFG_PSIZE_POS 10
+#define MEM_LCSP1_SCFG_ESIZE_POS 8
+
+#define MEM_LCSP1_SLOS_POS 1
+#define MEM_LCSP1_STCP_POS 0
+
+#define MEM_LCSP1_SPTR_MASK (0xFFFFUL << MEM_LCSP1_SPTR_POS)
+
+#define MEM_LCSP1_SCFG_MST_MASK (0x1UL << MEM_LCSP1_SCFG_MST_POS)
+#define MEM_LCSP1_SCFG_TIM_MASK (0x1UL << MEM_LCSP1_SCFG_TIM_POS)
+#define MEM_LCSP1_SCFG_EIM_MASK (0x1UL << MEM_LCSP1_SCFG_EIM_POS)
+#define MEM_LCSP1_SCFG_INCR_MASK (0x1UL << MEM_LCSP1_SCFG_INCR_POS)
+#define MEM_LCSP1_SCFG_PSIZE_MASK (0x3UL << MEM_LCSP1_SCFG_PSIZE_POS)
+#define MEM_LCSP1_SCFG_ESIZE_MASK (0x3UL << MEM_LCSP1_SCFG_ESIZE_POS)
+
+#define MEM_LCSP1_SLOS_MASK (0x7FUL << MEM_LCSP1_SLOS_POS)
+#define MEM_LCSP1_STCP_MASK (0x1UL << MEM_LCSP1_STCP_POS)
+
+#define MEM_LCSP2_ECNT_POS 16
+#define MEM_LCSP2_DPTR_POS 0
+
+#define MEM_LCSP2_ECNT_MASK (0xFFFFUL << MEM_LCSP2_ECNT_POS)
+#define MEM_LCSP2_DPTR_MASK (0xFFFFUL << MEM_LCSP2_DPTR_POS)
+
+#define MEM_LCSP3_DPTR_POS 16
+
+#define MEM_LCSP3_DCFG_MST_POS 15
+#define MEM_LCSP3_DCFG_TIM_POS 14
+#define MEM_LCSP3_DCFG_EIM_POS 13
+#define MEM_LCSP3_DCFG_INCR_POS 12
+#define MEM_LCSP3_DCFG_PSIZE_POS 10
+#define MEM_LCSP3_DCFG_ESIZE_POS 8
+
+#define MEM_LCSP3_DLOS_POS 1
+#define MEM_LCSP3_DTCP_POS 0
+
+#define MEM_LCSP3_DPTR_MASK (0xFFFFUL << MEM_LCSP3_DPTR_POS)
+
+#define MEM_LCSP3_DCFG_MST_MASK (0x1UL << MEM_LCSP3_DCFG_MST_POS)
+#define MEM_LCSP3_DCFG_TIM_MASK (0x1UL << MEM_LCSP3_DCFG_TIM_POS)
+#define MEM_LCSP3_DCFG_EIM_MASK (0x1UL << MEM_LCSP3_DCFG_EIM_POS)
+#define MEM_LCSP3_DCFG_INCR_MASK (0x1UL << MEM_LCSP3_DCFG_INCR_POS)
+#define MEM_LCSP3_DCFG_PSIZE_MASK (0x3UL << MEM_LCSP3_DCFG_PSIZE_POS)
+#define MEM_LCSP3_DCFG_ESIZE_MASK (0x3UL << MEM_LCSP3_DCFG_ESIZE_POS)
+
+#define MEM_LCSP3_DLOS_MASK (0x7FUL << MEM_LCSP3_DLOS_POS)
+#define MEM_LCSP3_DTCP_MASK (0x1UL << MEM_LCSP3_DTCP_POS)
+#define DMA_INFINITE_XFER (0x80000000)
+#define CONFIG_USB_U8500_EVENT_LINES
+/******************************************************************************/
+
+/* Logical Standard Channel Parameters */
+
+struct std_log_memory_param {
+ u32 dmac_lcsp0;
+ u32 dmac_lcsp1;
+ u32 dmac_lcsp2;
+ u32 dmac_lcsp3;
+};
+
+struct std_src_log_memory_param {
+ u32 dmac_lcsp0;
+ u32 dmac_lcsp1;
+};
+
+struct std_dest_log_memory_param {
+ u32 dmac_lcsp2;
+ u32 dmac_lcsp3;
+};
+
+enum channel_command {
+ STOP_CHANNEL = 0x1,
+ RUN_CHANNEL = 0x2,
+ SUSPEND_REQ = 0x2,
+ SUSPENDED = 0x3
+};
+
+/* Standard Channel parameter register offsets */
+#define CHAN_REG_SSCFG 0x00
+#define CHAN_REG_SSELT 0x04
+#define CHAN_REG_SSPTR 0x08
+#define CHAN_REG_SSLNK 0x0C
+#define CHAN_REG_SDCFG 0x10
+#define CHAN_REG_SDELT 0x14
+#define CHAN_REG_SDPTR 0x18
+#define CHAN_REG_SDLNK 0x1C
+
+/* DMA Register Offsets */
+#define DREG_GCC 0x000
+#define DREG_PRTYP 0x004
+#define DREG_PRSME 0x008
+#define DREG_PRSMO 0x00C
+#define DREG_PRMSE 0x010
+#define DREG_PRMSO 0x014
+#define DREG_PRMOE 0x018
+#define DREG_PRMOO 0x01C
+#define DREG_LCPA 0x020
+#define DREG_LCLA 0x024
+#define DREG_SLCPA 0x028
+#define DREG_SLCLA 0x02C
+#define DREG_SSEG(j) (0x030 + j*4)
+#define DREG_SCEG(j) (0x040 + j*4)
+#define DREG_ACTIVE 0x050
+#define DREG_ACTIVO 0x054
+#define DREG_FSEB1 0x058
+#define DREG_FSEB2 0x05C
+#define DREG_PCMIS 0x060
+#define DREG_PCICR 0x064
+#define DREG_PCTIS 0x068
+#define DREG_PCEIS 0x06C
+#define DREG_SPCMIS 0x070
+#define DREG_SPCICR 0x074
+#define DREG_SPCTIS 0x078
+#define DREG_SPCEIS 0x07C
+#define DREG_LCMIS(j) (0x080 + j*4)
+#define DREG_LCICR(j) (0x090 + j*4)
+#define DREG_LCTIS(j) (0x0A0 + j*4)
+#define DREG_LCEIS(j) (0x0B0 + j*4)
+#define DREG_SLCMIS(j) (0x0C0 + j*4)
+#define DREG_SLCICR(j) (0x0D0 + j*4)
+#define DREG_SLCTIS(j) (0x0E0 + j*4)
+#define DREG_SLCEIS(j) (0x0F0 + j*4)
+#define DREG_STFU 0xFC8
+#define DREG_ICFG 0xFCC
+#define DREG_MPLUG(j) (0xFD0 + j*4)
+#define DREG_PERIPHID(j) (0xFE0 + j*4)
+#define DREG_CELLID(j) (0xFF0 + j*4)
+
+/*
+ * LLI related structures
+*/
+
+struct dma_lli_info {
+ u32 reg_cfg;
+ u32 reg_elt;
+ u32 reg_ptr;
+ u32 reg_lnk;
+};
+
+struct dma_logical_src_lli_info {
+ u32 dmac_lcsp0;
+ u32 dmac_lcsp1;
+};
+
+struct dma_logical_dest_lli_info {
+ u32 dmac_lcsp2;
+ u32 dmac_lcsp3;
+};
+
+/*****************************************************************************/
+enum dma_toggle_endianess {
+ DO_NOT_CHANGE_ENDIANESS,
+ CHANGE_ENDIANESS
+};
+
+enum dma_master_id {
+ DMA_MASTER_0,
+ DMA_MASTER_1
+};
+
+/******************************************************************/
+/*Description of bitfields of channel_type variable in info structure*/
+
+#define INFO_CH_TYPE_POS 0
+#define STANDARD_CHANNEL (0x1 << INFO_CH_TYPE_POS)
+#define EXTENDED_CHANNEL (0x2 << INFO_CH_TYPE_POS)
+
+#define INFO_PRIO_TYPE_POS 2
+#define HIGH_PRIORITY_CHANNEL (0x1 << INFO_PRIO_TYPE_POS)
+#define LOW_PRIORITY_CHANNEL (0x2 << INFO_PRIO_TYPE_POS)
+
+#define INFO_SEC_TYPE_POS 4
+#define SECURE_CHANNEL (0x1 << INFO_SEC_TYPE_POS)
+#define NON_SECURE_CHANNEL (0x2 << INFO_SEC_TYPE_POS)
+
+#define INFO_CH_MODE_TYPE_POS 6
+#define CHANNEL_IN_PHYSICAL_MODE (0x1 << INFO_CH_MODE_TYPE_POS)
+#define CHANNEL_IN_LOGICAL_MODE (0x2 << INFO_CH_MODE_TYPE_POS)
+#define CHANNEL_IN_OPERATION_MODE (0x3 << INFO_CH_MODE_TYPE_POS)
+
+#define INFO_CH_MODE_OPTION_POS 8
+#define PCHAN_BASIC_MODE (0x1 << INFO_CH_MODE_OPTION_POS)
+#define PCHAN_MODULO_MODE (0x2 << INFO_CH_MODE_OPTION_POS)
+#define PCHAN_DOUBLE_DEST_MODE (0x3 << INFO_CH_MODE_OPTION_POS)
+#define LCHAN_SRC_PHY_DEST_LOG (0x1 << INFO_CH_MODE_OPTION_POS)
+#define LCHAN_SRC_LOG_DEST_PHS (0x2 << INFO_CH_MODE_OPTION_POS)
+#define LCHAN_SRC_LOG_DEST_LOG (0x3 << INFO_CH_MODE_OPTION_POS)
+
+#define INFO_LINK_TYPE_POS 9
+#define LINK_PRE (0x0 << INFO_LINK_TYPE_POS)
+#define LINK_POST (0x1 << INFO_LINK_TYPE_POS)
+
+#define INFO_TIM_POS 10
+#define NO_TIM_FOR_LINK (0x0 << INFO_TIM_POS)
+#define TIM_FOR_LINK (0x1 << INFO_TIM_POS)
+
+/******************************************************************/
+
+enum dma_phys_res_type {
+ DMA_STANDARD = 0x1,
+ DMA_EXTENDED = 0x2
+};
+
+enum dma_chan_priority {
+ DMA_LOW_PRIORITY = 0x1,
+ DMA_HIGH_PRIORITY = 0x2
+};
+
+enum dma_chan_security {
+ DMA_SECURE_CHAN = 0x1,
+ DMA_NONSECURE_CHAN = 0x2
+};
+
+enum dma_channel_mode_option {
+ BASIC_MODE = 0x1,
+ MODULO_MODE = 0x2,
+ DOUBLE_DESTINATION_MODE = 0x3,
+
+ SRC_PHY_DEST_LOG = 0x1,
+ SRC_LOG_DEST_PHS = 0x2,
+ SRC_LOG_DEST_LOG = 0x3
+};
+
+enum dma_channel_mode {
+ DMA_CHAN_IN_PHYS_MODE = 0x1,
+ DMA_CHAN_IN_LOG_MODE = 0x2,
+ DMA_CHAN_IN_OPERATION_MODE = 0x3
+};
+
+enum dma_event_group {
+ DMA_EVENT_GROUP_0,
+ DMA_EVENT_GROUP_1,
+ DMA_EVENT_GROUP_2,
+ DMA_EVENT_GROUP_3,
+ DMA_NO_EVENT_GROUP
+};
+
+enum dma_half_chan {
+ DMA_SRC_HALF_CHANNEL,
+ DMA_DEST_HALF_CHANNEL
+};
+
+enum dma_addr_inc {
+ DMA_ADR_NOINC,
+ DMA_ADR_INC
+};
+
+enum dma_command {
+ DMA_STOP,
+ DMA_RUN,
+ DMA_SUSPEND_REQ,
+ DMA_SUSPENDED
+};
+
+enum dma_chan_status {
+ DMA_ONGOING_EXCHANGE,
+ DMA_SUSPENDED_EXCHANGE,
+ DMA_HALTED_EXCHANGE,
+ DMA_STATUS_UNKNOWN = -1
+};
+
+enum dma_chan_id {
+ DMA_CHAN_0,
+ DMA_CHAN_1,
+ DMA_CHAN_2,
+ DMA_CHAN_3,
+ DMA_CHAN_4,
+ DMA_CHAN_5,
+ DMA_CHAN_6,
+ DMA_CHAN_7,
+ DMA_CHAN_NOT_ALLOCATED = -1
+};
+
+enum dma_src_dev_type {
+ DMA_DEV_SPI0_RX = 0,
+ DMA_DEV_SD_MMC0_RX,
+ DMA_DEV_SD_MMC1_RX,
+ DMA_DEV_SD_MMC2_RX,
+ DMA_DEV_I2C1_RX,
+ DMA_DEV_I2C3_RX,
+ DMA_DEV_I2C2_RX,
+ DMA_DEV_SSP0_RX = 8,
+ DMA_DEV_SSP1_RX,
+ DMA_DEV_MCDE_RX,
+ DMA_DEV_UART2_RX,
+ DMA_DEV_UART1_RX,
+ DMA_DEV_UART0_RX,
+ DMA_DEV_MSP2_RX,
+ DMA_DEV_I2C0_RX, /*15*/
+#ifndef CONFIG_USB_U8500_EVENT_LINES
+ DMA_DEV_USB_OTG_IEP_8 ,
+ DMA_DEV_USB_OTG_IEP_1_9 ,
+ DMA_DEV_USB_OTG_IEP_2_10 ,
+ DMA_DEV_USB_OTG_IEP_3_11 ,
+#else
+ DMA_DEV_USB_OTG_IEP_7_15 ,
+ DMA_DEV_USB_OTG_IEP_6_14 ,
+ DMA_DEV_USB_OTG_IEP_5_13 ,
+ DMA_DEV_USB_OTG_IEP_4_12 ,
+#endif
+ DMA_DEV_SLIM0_CH0_RX_HSI_RX_CH0,
+ DMA_DEV_SLIM0_CH1_RX_HSI_RX_CH1,
+ DMA_DEV_SLIM0_CH2_RX_HSI_RX_CH2,
+ DMA_DEV_SLIM0_CH3_RX_HSI_RX_CH3,
+ DMA_DEV_SRC_SXA0_RX_TX,
+ DMA_DEV_SRC_SXA1_RX_TX,
+ DMA_DEV_SRC_SXA2_RX_TX,
+ DMA_DEV_SRC_SXA3_RX_TX,
+ DMA_DEV_SD_MM2_RX,
+ DMA_DEV_SD_MM0_RX,
+ DMA_DEV_MSP1_RX,
+ DMA_SLIM0_CH0_RX,
+ DMA_DEV_MSP0_RX = DMA_SLIM0_CH0_RX,
+ DMA_DEV_SD_MM1_RX,
+ DMA_DEV_SPI2_RX,
+ DMA_DEV_I2C3_RX2,
+ DMA_DEV_SPI1_RX,
+#ifndef CONFIG_USB_U8500_EVENT_LINES
+ DMA_DEV_USB_OTG_IEP_4_12 ,
+ DMA_DEV_USB_OTG_IEP_5_13 ,
+ DMA_DEV_USB_OTG_IEP_6_14 ,
+ DMA_DEV_USB_OTG_IEP_7_15 ,
+#else
+ DMA_DEV_USB_OTG_IEP_3_11 ,
+ DMA_DEV_USB_OTG_IEP_2_10 ,
+ DMA_DEV_USB_OTG_IEP_1_9 ,
+ DMA_DEV_USB_OTG_IEP_8 ,
+#endif
+ DMA_DEV_SPI3_RX,
+ DMA_DEV_SD_MM3_RX,
+ DMA_DEV_SD_MM4_RX,
+ DMA_DEV_SD_MM5_RX,
+ DMA_DEV_SRC_SXA4_RX_TX,
+ DMA_DEV_SRC_SXA5_RX_TX,
+ DMA_DEV_SRC_SXA6_RX_TX,
+ DMA_DEV_SRC_SXA7_RX_TX,
+ DMA_DEV_CAC1_RX,
+ DMA_DEV_MSHC_RX = 51,
+ DMA_DEV_SLIM1_CH0_RX_HSI_RX_CH4,
+ DMA_DEV_SLIM1_CH1_RX_HSI_RX_CH5,
+ DMA_DEV_SLIM1_CH2_RX_HSI_RX_CH6,
+ DMA_DEV_SLIM1_CH3_RX_HSI_RX_CH7,
+ DMA_DEV_CAC0_RX = 61,
+ DMA_DEV_SRC_MEMORY = 64,
+};
+
+enum dma_dest_dev_type {
+ DMA_DEV_SPI0_TX = 0,
+ DMA_DEV_SD_MMC0_TX,
+ DMA_DEV_SD_MMC1_TX,
+ DMA_DEV_SD_MMC2_TX,
+ DMA_DEV_I2C1_TX,
+ DMA_DEV_I2C3_TX,
+ DMA_DEV_I2C2_TX,
+ DMA_DEV_SSP0_TX = 8,
+ DMA_DEV_SSP1_TX,
+ DMA_DEV_UART2_TX = 11,
+ DMA_DEV_UART1_TX,
+ DMA_DEV_UART0_TX,
+ DMA_DEV_MSP2_TX,
+ DMA_DEV_I2C0_TX,
+#ifndef CONFIG_USB_U8500_EVENT_LINES
+ DMA_DEV_USB_OTG_OEP_8 ,
+ DMA_DEV_USB_OTG_OEP_1_9 ,
+ DMA_DEV_USB_OTG_OEP_2_10 ,
+ DMA_DEV_USB_OTG_OEP_3_11 ,
+#else
+ DMA_DEV_USB_OTG_OEP_7_15 ,
+ DMA_DEV_USB_OTG_OEP_6_14 ,
+ DMA_DEV_USB_OTG_OEP_5_13 ,
+ DMA_DEV_USB_OTG_OEP_4_12 ,
+#endif
+ DMA_DEV_SLIM0_CH0_TX_HSI_TX_CH0,
+ DMA_DEV_SLIM0_CH1_TX_HSI_TX_CH1,
+ DMA_DEV_SLIM0_CH2_TX_HSI_TX_CH2,
+ DMA_DEV_SLIM0_CH3_TX_HSI_TX_CH3,
+ DMA_DEV_DST_SXA0_RX_TX,
+ DMA_DEV_DST_SXA1_RX_TX,
+ DMA_DEV_DST_SXA2_RX_TX,
+ DMA_DEV_DST_SXA3_RX_TX,
+ DMA_DEV_SD_MM2_TX,
+ DMA_DEV_SD_MM0_TX,
+ DMA_DEV_MSP1_TX,
+ DMA_SLIM0_CH0_TX,
+ DMA_DEV_MSP0_TX = DMA_SLIM0_CH0_TX,
+ DMA_DEV_SD_MM1_TX,
+ DMA_DEV_SPI2_TX,
+ DMA_DEV_I2C3_TX2,
+ DMA_DEV_SPI1_TX,
+#ifndef CONFIG_USB_U8500_EVENT_LINES
+ DMA_DEV_USB_OTG_OEP_4_12 ,
+ DMA_DEV_USB_OTG_OEP_5_13 ,
+ DMA_DEV_USB_OTG_OEP_6_14 ,
+ DMA_DEV_USB_OTG_OEP_7_15 ,
+#else
+ DMA_DEV_USB_OTG_OEP_3_11 ,
+ DMA_DEV_USB_OTG_OEP_2_10 ,
+ DMA_DEV_USB_OTG_OEP_1_9 ,
+ DMA_DEV_USB_OTG_OEP_8 ,
+#endif
+ DMA_DEV_SPI3_TX,
+ DMA_DEV_SD_MM3_TX,
+ DMA_DEV_SD_MM4_TX,
+ DMA_DEV_SD_MM5_TX,
+ DMA_DEV_DST_SXA4_RX_TX,
+ DMA_DEV_DST_SXA5_RX_TX,
+ DMA_DEV_DST_SXA6_RX_TX,
+ DMA_DEV_DST_SXA7_RX_TX,
+ DMA_DEV_CAC1_TX,
+ DMA_DEV_CAC1_TX_HAC1_TX,
+ DMA_DEV_HAC1_TX,
+ DMA_DEV_MSHC_TX,
+ DMA_DEV_SLIM1_CH0_TX_HSI_TX_CH4,
+ DMA_DEV_SLIM1_CH1_TX_HSI_TX_CH5,
+ DMA_DEV_SLIM1_CH2_TX_HSI_TX_CH6,
+ DMA_DEV_SLIM1_CH3_TX_HSI_TX_CH7,
+ DMA_DEV_CAC0_TX = 61,
+ DMA_DEV_CAC0_TX_HAC0_TX,
+ DMA_DEV_HAC0_TX,
+ DMA_DEV_DEST_MEMORY = 64,
+};
+
+enum dma_half_chan_sync {
+ DMA_NO_SYNC,
+ DMA_PACKET_SYNC,
+ DMA_FRAME_SYNC,
+ DMA_BLOCK_SYNC
+};
+
+enum half_channel_type {
+ PHYSICAL_HALF_CHANNEL = 0x1,
+ LOGICAL_HALF_CHANNEL,
+};
+
+enum periph_data_width {
+ DMA_BYTE_WIDTH,
+ DMA_HALFWORD_WIDTH,
+ DMA_WORD_WIDTH,
+ DMA_DOUBLEWORD_WIDTH
+};
+
+enum dma_burst_size {
+ DMA_BURST_SIZE_1,
+ DMA_BURST_SIZE_4,
+ DMA_BURST_SIZE_8,
+ DMA_BURST_SIZE_16,
+ DMA_NO_BURST
+};
+
+enum dma_buffer_type {
+ SINGLE_BUFFERED,
+ DOUBLE_BUFFERED
+};
+
+enum dma_link_type {
+ POSTLINK,
+ PRELINK
+};
+
+struct dma_half_channel_info {
+ enum half_channel_type half_chan_type;
+ enum dma_endianess endianess;
+ enum periph_data_width data_width;
+ enum dma_burst_size burst_size;
+ enum dma_buffer_type buffer_type;
+ enum dma_event_group event_group;
+ enum dma_addr_inc addr_inc;
+ u32 event_line;
+};
+
+/**
+ * struct dma_channel_info - Data structure to
+ * manage state of a DMA channel.
+ *
+ * @device_id: Name of the device
+ * @pipe_id: Pipe Id allocated to the client driver.
+ * @channel_id: Channel Id allocated for the client,
+ * used internally by DMA Driver(when interrupt comes)
+ * (there are 128 Logical + 32 Physical). Max is 160 channels
+ * @active: Is the channel active at this point?
+ * 1 - active, 0- inactive
+ * @invalid: Has configuration been updated since we last updated
+ * the registers? invalid = 1 (need to update)
+ * @phys_chan_id:physical channel ID on which this channel will execute
+ * @src_addr: Src address for single DMA
+ * @dst_addr: Dest address for single DMA
+ * @xfer_len: Length of transfer expressed in Bytes
+ * @current_sg: Pointer to current SG element being used for xfer(only active
+ * if TIM_MASK is set)
+ * @lli_interrupt: 1 if interrupts generated for each LLI
+ * @sgcount_src: Number of SG items in source sg list
+ * @lli_block_id_src: Block id for LLI pool used for source half channel
+ * @sg_src: Head Pointer to SG list for source half channel
+ * @sgcount_dest: Number of SG items in Dest sg list
+ * @lli_block_id_dest: Block id for LLI pool used for Dest half channel
+ * @sg_dest: Head Pointer to SG list for Destination half channel
+ * @sg_block_id_src: Block id for SG pool used for SRC half channel
+ * @sg_block_id_dest: Block id for SG pool used for DEST half channel
+ * @link_type: Whether prelink or postlink
+ * @reserve_channel: whether channel is reserved.
+ * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
+ * @flow_cntlr: who is the flow controller DMA or Peripheral
+ * @data: Pointer to data of callback function
+ * @callback: Pointer to callback function
+ * @pr_type: Physical resource type : standard or extended
+ * @chan_mode: Mode of Physical resource
+ * For std channel: Physical,Logical,Operation
+ * @mode_option: Further options of mode selected above
+ * @priority: Priority for this channel
+ * @security: security for this channel
+ * @bytes_xfred: Number of Bytes xfered till now
+ * @ch_status:
+ * @src_dev_type: Device type of Source
+ * @dst_dev_type: Device type of Dest
+ * @src_info: Parameters describing source half channel
+ * @dst_info: Parameters describing dest half channel
+ * This is a private data structure of DMA driver used to maintain
+ * state information of a particular channel
+ */
+struct dma_channel_info {
+ const char *device_id;
+ u32 src_cfg;
+ u32 dst_cfg;
+ u32 dmac_lcsp3;
+ u32 dmac_lcsp1;
+ int pipe_id;
+ int channel_id;
+ int active;
+ int invalid;
+ enum dma_chan_id phys_chan_id;
+ void *src_addr;
+ void *dst_addr;
+ u32 xfer_len;
+ u32 src_xfer_elem;
+ u32 dst_xfer_elem;
+ struct scatterlist *current_sg;
+ /*For Scatter Gather DMA */
+ int lli_interrupt;
+ int sgcount_src;
+ int lli_block_id_src;
+ struct scatterlist *sg_src;
+ int sgcount_dest;
+ int lli_block_id_dest;
+ struct scatterlist *sg_dest;
+ int sg_block_id_src;
+ int sg_block_id_dest;
+
+ enum dma_link_type link_type;
+ unsigned int reserve_channel;
+ enum dma_xfer_dir dir;
+ enum dma_flow_controller flow_cntlr;
+
+ void *data;
+ dma_callback_t callback;
+
+ enum dma_phys_res_type pr_type;
+ enum dma_channel_mode chan_mode;
+ enum dma_channel_mode_option mode_option;
+ enum dma_chan_priority priority;
+ enum dma_chan_security security;
+
+ int bytes_xfred;
+ enum dma_chan_status ch_status;
+ enum dma_src_dev_type src_dev_type;
+ enum dma_dest_dev_type dst_dev_type;
+ struct dma_half_channel_info src_info;
+ struct dma_half_channel_info dst_info;
+ spinlock_t cfg_lock;
+};
+
+enum res_status {
+ RESOURCE_FREE,
+ RESOURCE_PHYSICAL,
+ RESOURCE_LOGICAL
+};
+
+struct phys_res_status {
+ int count;
+ enum res_status status;
+};
+
+struct phy_res_info {
+ enum res_status status;
+ u32 count;
+ u32 dirty;
+};
+
+#define NUM_LLI_PER_REQUEST 40
+#define NUM_SG_PER_REQUEST 40
+#define NUM_LOGICAL_CHANNEL_PER_PHY_RESOURCE 16
+#define NUM_LLI_PER_LOG_CHANNEL 8
+#define SIXTY_FOUR_KB (64 * 1024)
+
+#define MAX_NUM_OF_ELEM_IN_A_XFER (64*1024)
+/*Number of Fixed size LLI Blocks available for Physical channels */
+#define NUM_PCHAN_LLI_BLOCKS 32
+/*Number of Fixed size SG blocks */
+#define NUM_SG_BLOCKS 32
+/*Maximum Iterations taken before giving up suspending a channel */
+#define MAX_ITERATIONS 500
+
+extern struct driver_debug_st DBG_ST;
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/dsi.h b/arch/arm/mach-ux500/include/mach/dsi.h
new file mode 100755
index 00000000000..553ad998bb1
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/dsi.h
@@ -0,0 +1,777 @@
+/*---------------------------------------------------------------------------*/
+/* Copyright ST Ericsson 2009. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it */
+/* under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, */
+/* or (at your option)any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */
+/* the GNU Lesser General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*---------------------------------------------------------------------------*/
+
+#ifndef _DSI_H_
+#define _DSI_H_
+
+#ifdef _cplusplus
+extern "C" {
+#endif /* _cplusplus */
+#include <mach/mcde.h>
+#ifdef __KERNEL__
+
+#define DSI_DPHY_Z_CALIB_OUT_VALID 0x1
+/*******************************************************************************
+DSI Error Enums
+******************************************************************************/
+
+
+ typedef enum
+ {
+ DSI_OK = 0x1, /** No error.*/
+ DSI_NO_PENDING_EVENT_ERROR = 0x2,
+ DSI_NO_MORE_FILTER_PENDING_EVENT = 0x3,
+ DSI_NO_MORE_PENDING_EVENT = 0x4,
+ DSI_REMAINING_FILTER_PENDING_EVENTS = 0x5,
+ DSI_REMAINING_PENDING_EVENTS = 0x6,
+ DSI_INTERNAL_EVENT = 0x7,
+ DSI_INTERNAL_ERROR = 0x8,
+ DSI_NOT_CONFIGURED = 0x9,
+ DSI_REQUEST_PENDING = 0xA,
+ DSI_PLL_PROGRAM_ERROR = 0xB,
+ DSI_CLOCK_LANE_NOT_READY = 0xC,
+ DSI_DATA_LANE1_NOT_READY = 0xD,
+ DSI_DATA_LANE2_NOT_READY = 0xE,
+ DSI_REQUEST_NOT_APPLICABLE = 0x10,
+ DSI_INVALID_PARAMETER = 0x11,
+ DSI_UNSUPPORTED_FEATURE = 0x12,
+ DSI_UNSUPPORTED_HW = 0x13
+ }dsi_error;
+
+/********************************************************************************
+DSI Interrupt Type Enums
+********************************************************************************/
+#define DSI_NO_INTERRUPT 0x0
+
+typedef enum
+{
+ DSI_IRQ_TYPE_MCTL_MAIN = 0x01,
+ DSI_IRQ_TYPE_CMD_MODE = 0x02,
+ DSI_IRQ_TYPE_DIRECT_CMD_MODE = 0x03,
+ DSI_IRQ_TYPE_DIRECT_CMD_RD_MODE = 0x04,
+ DSI_IRQ_TYPE_VID_MODE = 0x05,
+ DSI_IRQ_TYPE_TG = 0x06,
+ DSI_IRQ_TYPE_DPHY_ERROR = 0x07,
+ DSI_IRQ_TYPE_DPHY_CLK_TRIM_RD = 0x08
+} dsi_irq_type;
+
+
+
+
+/*******************************************************************************
+ DSI Main Setting Registers Enums and structures
+******************************************************************************/
+
+ typedef enum
+ {
+ DSI_INT_MODE_DISABLE = 0x00,
+ DSI_INT_MODE_ENABLE = 0x01
+ }dsi_int_mode;
+
+ typedef enum
+ {
+ DSI_VSG_MODE_DISABLE = 0x00,
+ DSI_VSG_MODE_ENABLE = 0x01
+ }dsi_vsg_ctrl;
+
+ typedef enum
+ {
+ DSI_TVG_MODE_DISABLE = 0x00,
+ DSI_TVG_MODE_ENABLE = 0x01
+ }dsi_tvg_ctrl;
+
+ typedef enum
+ {
+ DSI_TBG_MODE_DISABLE = 0x00,
+ DSI_TBG_MODE_ENABLE = 0x01
+ }dsi_tbg_ctrl;
+
+ typedef enum
+ {
+ DSI_RD_MODE_DISABLE = 0x00,
+ DSI_RD_MODE_ENABLE = 0x01
+ }dsi_rd_ctrl;
+
+
+ typedef enum
+ {
+ DSI_SIGNAL_LOW = 0x0,
+ DSI_SIGNAL_HIGH = 0x1
+ }dsi_signal_state;
+
+ typedef enum
+ {
+ DSI_LINK0 = 0x00,
+ DSI_LINK1 = 0x01,
+ DSI_LINK2 = 0x02
+ }dsi_link;
+
+ typedef enum
+ {
+ DSI_COMMAND_MODE = 0x0,
+ DSI_VIDEO_MODE = 0x1,
+ DSI_INTERFACE_BOTH = 0x2,
+ DSI_INTERFACE_NONE = 0x3
+ }dsi_interface_mode;
+
+ typedef enum
+ {
+ DSI_INTERFACE_1 = 0x0,
+ DSI_INTERFACE_2 = 0x1
+ }dsi_interface;
+
+ typedef enum
+ {
+ DSI_DISABLE = 0x0,
+ DSI_ENABLE = 0x1
+ }dsi_link_state;
+
+ typedef enum
+ {
+ DSI_SIGNAL_RESET = 0x0,
+ DSI_SIGNAL_SET = 0x1
+ }dsi_stall_signal_state;
+
+ typedef enum
+ {
+ DSI_IF1_DISABLE = 0x0,
+ DSI_IF1_ENABLE = 0x1
+ }dsi_if1_state;
+
+ typedef enum
+ {
+ DSI_IF_DISABLE = 0x0,
+ DSI_IF_ENABLE = 0x1
+ }dsi_if_state;
+
+ typedef enum
+ {
+ DSI_PLL_IN_CLK_27 = 0x0,/** from TV PLL*/
+ DSI_PLL_IN_CLK_26 = 0x1 /** from system PLL*/
+ }dsi_pll_clk_in;
+
+ typedef enum
+ {
+ DSI_PLL_STOP = 0x0,
+ DSI_PLL_START = 0x1
+ }dsi_pll_mode;
+
+ typedef enum
+ {
+ DSI_BTA_DISABLE = 0x0,
+ DSI_BTA_ENABLE = 0x1
+ }dsi_bta_mode;
+
+ typedef enum
+ {
+ DSI_ECC_GEN_DISABLE = 0x0,
+ DSI_ECC_GEN_ENABLE = 0x1
+ }dsi_ecc_gen_mode;
+
+ typedef enum
+ {
+ DSI_CHECKSUM_GEN_DISABLE = 0x0,
+ DSI_CHECKSUM_GEN_ENABLE = 0x1
+ }dsi_checksum_gen_mode;
+
+ typedef enum
+ {
+ DSI_EOT_GEN_DISABLE = 0x0,
+ DSI_EOT_GEN_ENABLE = 0x1
+ }dsi_eot_gen_mode;
+
+ typedef enum
+ {
+ DSI_HOST_EOT_GEN_DISABLE = 0x0,
+ DSI_HOST_EOT_GEN_ENABLE = 0x1
+ }dsi_host_eot_gen_mode;
+
+ typedef enum
+ {
+ DSI_LANE_STOP = 0x0,
+ DSI_LANE_START = 0x1
+ }dsi_lane_state;
+ typedef enum
+ {
+ DSI_LANE_DISABLE = 0x0,
+ DSI_LANE_ENABLE = 0x1
+ }dsi_lane_mode;
+ typedef enum
+ {
+ DSI_CLK_CONTINIOUS_HS_DISABLE = 0x0,
+ DSI_CLK_CONTINIOUS_HS_ENABLE = 0x1
+ }dsi_clk_continious_hs_mode;
+ typedef enum
+ {
+ DSI_INTERNAL_PLL = 0x0,
+ DSI_SYSTEM_PLL = 0x1
+ }pll_out_sel; /** DPHY HS bit clock select*/
+ typedef enum
+ {
+ HS_INVERT_DISABLE = 0x0,
+ HS_INVERT_ENABLE = 0x1
+ }dsi_hs_invert_mode;
+ typedef enum
+ {
+ HS_SWAP_PIN_DISABLE = 0x0,
+ HS_SWAP_PIN_ENABLE = 0x1
+ }dsi_swap_pin_mode;
+ typedef enum
+ {
+ DSI_PLL_MASTER = 0x0,
+ DSI_PLL_SLAVE = 0x1
+ }dsi_pll_mode_sel;
+
+ typedef struct
+ {
+ u8 multiplier;
+ u8 division_ratio;
+ dsi_pll_clk_in pll_in_sel;
+ pll_out_sel pll_out_sel;
+ dsi_pll_mode_sel pll_master;
+ }dsi_pll_ctl;
+
+ typedef enum
+ {
+ DSI_REG_TE = 0x00,
+ DSI_IF_TE = 0x01
+ }dsi_te_sel;
+
+ typedef struct
+ {
+ dsi_te_sel te_sel;
+ dsi_interface interface;
+ }dsi_te_en;
+
+ typedef enum
+ {
+ DSI_TE_DISABLE = 0x0,
+ DSI_TE_ENABLE = 0x1
+ }dsi_te_ctrl;
+
+ typedef enum
+ {
+ DSI_CLK_LANE = 0x00,
+ DSI_DATA_LANE1 = 0x01,
+ DSI_DATA_LANE2 = 0x02
+ }dsi_lane;
+
+ typedef enum
+ {
+ DSI_DAT_LANE1 = 0x0,
+ DSI_DAT_LANE2 = 0x1
+ }dsi_data_lane;
+
+ typedef enum
+ {
+ DSI_CLK_LANE_START = 0x00,
+ DSI_CLK_LANE_IDLE = 0x01,
+ DSI_CLK_LANE_HS = 0x02,
+ DSI_CLK_LANE_ULPM = 0x03
+ }dsi_clk_lane_state;
+ typedef enum
+ {
+ DSI_CLK_LANE_LPM = 0x0,
+ DSI_CLK_LANE_HSM = 0x01
+ }dsi_interface_mode_type;
+ typedef enum
+ {
+ DSI_DATA_LANE_START = 0x000,
+ DSI_DATA_LANE_IDLE = 0x001,
+ DSI_DATA_LANE_WRITE = 0x002,
+ DSI_DATA_LANE_ULPM = 0x003,
+ DSI_DATA_LANE_READ = 0x004
+ }dsi_data_lane_state;
+
+ typedef struct
+ {
+ u8 clk_div;
+ u16 hs_tx_timeout;
+ u16 lp_rx_timeout;
+ }dsi_dphy_timeout;
+
+ typedef enum
+ {
+ DSI_PLL_LOCK = 0x01,
+ DSI_CLKLANE_READY = 0x02,
+ DSI_DAT1_READY = 0x04,
+ DSI_DAT2_READY = 0x08,
+ DSI_HSTX_TO_ERROR = 0x10,
+ DSI_LPRX_TO_ERROR = 0x20,
+ DSI_CRS_UNTERM_PCK = 0x40,
+ DSI_VRS_UNTERM_PCK = 0x80
+ }dsi_link_status;
+
+ typedef struct
+ {
+ u16 if_data;
+ dsi_signal_state if_valid;
+ dsi_signal_state if_start;
+ dsi_signal_state if_frame_sync;
+ }dsi_int_read;
+
+ typedef enum
+ {
+ DSI_ERR_SOT_HS_1 = 0x1,
+ DSI_ERR_SOT_HS_2 = 0x2,
+ DSI_ERR_SOTSYNC_1 = 0x4,
+ DSI_ERR_SOTSYNC_2 = 0x8,
+ DSI_ERR_EOTSYNC_1 = 0x10,
+ DSI_ERR_EOTSYNC_2 = 0x20,
+ DSI_ERR_ESC_1 = 0x40,
+ DSI_ERR_ESC_2 = 0x80,
+ DSI_ERR_SYNCESC_1 = 0x100,
+ DSI_ERR_SYNCESC_2 = 0x200,
+ DSI_ERR_CONTROL_1 = 0x400,
+ DSI_ERR_CONTROL_2 = 0x800,
+ DSI_ERR_CONT_LP0_1 = 0x1000,
+ DSI_ERR_CONT_LP0_2 = 0x2000,
+ DSI_ERR_CONT_LP1_1 = 0x4000,
+ DSI_ERR_CONT_LP1_2 = 0x8000,
+ }dsi_dphy_err;
+
+ typedef enum
+ {
+ DSI_VIRTUAL_CHANNEL_0 = 0x0,
+ DSI_VIRTUAL_CHANNEL_1 = 0x1,
+ DSI_VIRTUAL_CHANNEL_2 = 0x2,
+ DSI_VIRTUAL_CHANNEL_3 = 0x3
+ }dsi_virtual_ch;
+
+ typedef enum
+ {
+ DSI_ERR_NO_TE = 0x1,
+ DSI_ERR_TE_MISS = 0x2,
+ DSI_ERR_SDI1_UNDERRUN = 0x4,
+ DSI_ERR_SDI2_UNDERRUN = 0x8,
+ DSI_ERR_UNWANTED_RD = 0x10,
+ DSI_CSM_RUNNING = 0x20
+ }dsi_cmd_mode_sts;
+
+ typedef enum
+ {
+ DSI_COMMAND_DIRECT = 0x0,
+ DSI_COMMAND_GENERIC = 0x1
+ }dsi_cmd_type;
+
+ typedef struct
+ {
+ u16 rd_size;
+ dsi_virtual_ch rd_id;
+ dsi_cmd_type cmd_type;
+ }dsi_cmd_rd_property;
+
+ typedef enum
+ {
+ DSI_CMD_WRITE = 0x0,
+ DSI_CMD_READ = 0x1,
+ DSI_CMD_TE_REQUEST = 0x4,
+ DSI_CMD_TRIGGER_REQUEST = 0x5,
+ DSI_CMD_BTA_REQUEST = 0x6
+ }dsi_cmd_nat;
+
+ typedef enum
+ {
+ DSI_CMD_SHORT = 0x0,
+ DSI_CMD_LONG = 0x1
+ }dsi_cmd_packet;
+
+ typedef struct
+ {
+ u8 rddat0;
+ u8 rddat1;
+ u8 rddat2;
+ u8 rddat3;
+ }dsi_cmd_rddat;
+
+ typedef struct
+ {
+ dsi_cmd_nat cmd_nature;
+ dsi_cmd_packet packet_type;
+ u8 cmd_header;
+ dsi_virtual_ch cmd_id;
+ u8 cmd_size;
+ dsi_link_state cmd_lp_enable;
+ u8 cmd_trigger_val;
+ }dsi_cmd_main_setting;
+
+ typedef enum
+ {
+ DSI_CMD_TRANSMISSION = 0x1,
+ DSI_WRITE_COMPLETED = 0x2,
+ DSI_TRIGGER_COMPLETED = 0x4,
+ DSI_READ_COMPLETED = 0x8,
+ DSI_ACKNOWLEDGE_RECEIVED = 0x10,
+ DSI_ACK_WITH_ERR_RECEIVED = 0x20,
+ DSI_TRIGGER_RECEIVED = 0x40,
+ DSI_TE_RECEIVED = 0x80,
+ DSI_BTA_COMPLETED = 0x100,
+ DSI_BTA_FINISHED = 0x200,
+ DSI_READ_COMPLETED_WITH_ERR = 0x400,
+ DSI_TRIGGER_VAL = 0x7800,
+ DSI_ACK_VAL = 0xFFFF0000
+ }dsi_direct_cmd_sts;
+
+ typedef enum
+ {
+ DSI_TE_256 = 0x00,
+ DSI_TE_512 = 0x01,
+ DSI_TE_1024 = 0x02,
+ DSI_TE_2048 = 0x03
+ }dsi_te_timeout;
+
+ typedef enum
+ {
+ DSI_ARB_MODE_FIXED = 0x0,
+ DSI_ARB_MODE_ROUNDROBIN = 0x1
+ }dsi_arb_mode;
+
+ typedef struct
+ {
+ dsi_arb_mode arb_mode;
+ dsi_interface arb_fixed_if;
+ }dsi_arb_ctl;
+
+ typedef enum
+ {
+ DSI_STARTON_VSYNC = 0x00,
+ DSI_STARTON_VFP = 0x01,
+ }dsi_start_mode;
+
+ typedef enum
+ {
+ DSI_STOPBEFORE_VSYNV = 0x0,
+ DSI_STOPAT_LINEEND = 0x1,
+ DSI_STOPAT_ACTIVELINEEND = 0x2,
+ }dsi_stop_mode;
+
+ typedef enum
+ {
+ DSI_NO_BURST_MODE = 0x0,
+ DSI_BURST_MODE = 0x1,
+ }dsi_burst_mode;
+
+ typedef enum
+ {
+ DSI_VID_MODE_16_PACKED = 0x0,
+ DSI_VID_MODE_18_PACKED = 0x1,
+ DSI_VID_MODE_16_LOOSELY = 0x2,
+ DSI_VID_MODE_18_LOOSELY = 0x3
+ }dsi_vid_pixel_mode;
+
+ typedef enum
+ {
+ DSI_SYNC_PULSE_NOTACTIVE = 0x0,
+ DSI_SYNC_PULSE_ACTIVE = 0x1
+ }dsi_sync_pulse_active;
+
+ typedef enum
+ {
+ DSI_SYNC_PULSE_HORIZONTAL_NOTACTIVE = 0x0,
+ DSI_SYNC_PULSE_HORIZONTAL_ACTIVE = 0x1
+ }dsi_sync_pulse_horizontal;
+
+ typedef enum
+ {
+ DSI_NULL_PACKET = 0x0,
+ DSI_BLANKING_PACKET = 0x1,
+ DSI_LP_MODE = 0x2,
+ }dsi_blanking_packet;
+
+ typedef enum
+ {
+ DSI_RECOVERY_HSYNC = 0x0,
+ DSI_RECOVERY_VSYNC = 0x1,
+ DSI_RECOVERY_STOP = 0x2,
+ DSI_RECOVERY_HSYNC_VSYNC = 0x3
+ }dsi_recovery_mode;
+
+ typedef struct
+ {
+ dsi_start_mode vid_start_mode;
+ dsi_stop_mode vid_stop_mode;
+ dsi_virtual_ch vid_id;
+ u8 header;
+ dsi_vid_pixel_mode vid_pixel_mode;
+ dsi_burst_mode vid_burst_mode;
+ dsi_sync_pulse_active sync_pulse_active;
+ dsi_sync_pulse_horizontal sync_pulse_horizontal;
+ dsi_blanking_packet blkline_mode;
+ dsi_blanking_packet blkeol_mode;
+ dsi_recovery_mode recovery_mode;
+ }dsi_vid_main_ctl;
+
+ typedef struct
+ {
+ u16 vact_length;
+ u8 vfp_length;
+ u8 vbp_length;
+ u8 vsa_length;
+ }dsi_img_vertical_size;
+
+ typedef struct
+ {
+ u8 hsa_length;
+ u8 hbp_length;
+ u16 hfp_length;
+ u16 rgb_size;
+ }dsi_img_horizontal_size;
+
+ typedef struct
+ {
+ u16 line_val;
+ u8 line_pos;
+ u16 horizontal_val;
+ u8 horizontal_pos;
+ }dsi_img_position;
+
+ typedef enum
+ {
+ DSI_VSG_RUNNING = 0x1,
+ DSI_ERR_MISSING_DATA = 0x2,
+ DSI_ERR_MISSING_HSYNC = 0x4,
+ DSI_ERR_MISSING_VSYNC = 0x8,
+ DSI_ERR_SMALL_LENGTH = 0x10,
+ DSI_ERR_SMALL_HEIGHT = 0x20,
+ DSI_ERR_BURSTWRITE = 0x40,
+ DSI_ERR_LINEWRITE = 0x80,
+ DSI_ERR_LONGWRITE = 0x100,
+ DSI_ERR_VRS_WRONG_LENGTH = 0x200
+ }dsi_vid_mode_sts;
+
+ typedef enum
+ {
+ DSI_NULL_PACK = 0x0,
+ DSI_LP = 0x1,
+ }dsi_burst_lp;
+
+ typedef struct
+ {
+ dsi_burst_lp burst_lp;
+ u16 max_burst_limit;
+ u16 max_line_limit;
+ u16 exact_burst_limit;
+ }dsi_vca_setting;
+
+ typedef struct
+ {
+ u16 blkeol_pck;
+ u16 blkline_event_pck;
+ u16 blkline_pulse_pck;
+ u16 vert_balnking_duration;
+ u16 blkeol_duration;
+ }dsi_vid_blanking;
+
+ typedef struct
+ {
+ u8 col_red;
+ u8 col_green;
+ u8 col_blue;
+ u8 pad_val;
+ }dsi_vid_err_color;
+
+ typedef enum
+ {
+ DSI_TVG_MODE_UNIQUECOLOR = 0x0,
+ DSI_TVG_MODE_STRIPES = 0x1,
+ }dsi_tvg_mode;
+
+ typedef enum
+ {
+ DSI_TVG_STOP_FRAMEEND = 0x0,
+ DSI_TVG_STOP_LINEEND = 0x1,
+ DSI_TVG_STOP_IMMEDIATE = 0x2,
+ }dsi_tvg_stop_mode;
+
+
+
+ typedef struct
+ {
+ u8 tvg_stripe_size;
+ dsi_tvg_mode tvg_mode;
+ dsi_tvg_stop_mode stop_mode;
+ }dsi_tvg_control;
+
+ typedef struct
+ {
+ u16 tvg_nbline;
+ u16 tvg_line_size;
+ }dsi_tvg_img_size;
+
+ typedef struct
+ {
+ u8 col_red;
+ u8 col_green;
+ u8 col_blue;
+ }dsi_frame_color;
+
+ typedef enum
+ {
+ DSI_TVG_COLOR1 = 0x0,
+ DSI_TVG_COLOR2 = 0x1
+ }dsi_color_type;
+
+ typedef enum
+ {
+ DSI_TVG_STOPPED = 0x0,
+ DSI_TVG_RUNNING = 0x1
+ }dsi_tvg_state;
+
+ typedef enum
+ {
+ DSI_TVG_STOP = 0x0,
+ DSI_TVG_START = 0x1
+ }dsi_tvg_ctrl_state;
+
+ typedef enum
+ {
+ DSI_TBG_STOPPED = 0x0,
+ DSI_TBG_RUNNING = 0x1
+ }dsi_tbg_state;
+
+ typedef enum
+ {
+ DSI_SEND_1BYTE = 0x0,
+ DSI_SEND_2BYTE = 0x1,
+ DSI_SEND_BURST_STOP_COUNTER = 0x3,
+ DSI_SEND_BURST_STOP = 0x4
+ }dsi_tbg_mode;
+
+ typedef enum
+ {
+ DSI_ERR_FIXED = 0x1,
+ DSI_ERR_UNCORRECTABLE = 0x2,
+ DSI_ERR_CHECKSUM = 0x4,
+ DSI_ERR_UNDECODABLE = 0x8,
+ DSI_ERR_RECEIVE = 0x10,
+ DSI_ERR_OVERSIZE = 0x20,
+ DSI_ERR_WRONG_LENGTH = 0x40,
+ DSI_ERR_MISSING_EOT = 0x80,
+ DSI_ERR_EOT_WITH_ERR = 0x100
+ }dsi_direct_cmd_rd_sts_ctl;
+
+ typedef enum
+ {
+ DSI_TVG_STS = 0x1,
+ DSi_TBG_STS = 0x2
+ }dsi_tg_sts_ctl;
+
+typedef struct
+{
+ dsi_interface_mode dsi_if_mode;
+ dsi_interface dsiInterface;
+ dsi_if1_state dsi_if1_state;
+ dsi_link_state dsi_link_state;
+ dsi_int_mode dsi_int_mode;
+ dsi_interface_mode_type if_mode_type;
+}dsi_link_context;
+
+struct dsi_dphy_static_conf {
+ dsi_hs_invert_mode clocklanehsinvermode;
+ dsi_swap_pin_mode clocklaneswappinmode;
+ dsi_hs_invert_mode datalane1hsinvermode;
+ dsi_swap_pin_mode datalane1swappinmode;
+ dsi_hs_invert_mode datalane2hsinvermode;
+ dsi_swap_pin_mode datalane2swappinmode;
+ u8 ui_x4; /** unit interval time for clock lane*/
+};
+struct dsi_link_conf {
+ dsi_link_state dsiLinkState;
+ dsi_interface dsiInterface;
+ dsi_interface_mode dsiInterfaceMode;
+ dsi_interface_mode_type videoModeType; /** for LP/HS mode for vide mode */
+ dsi_interface_mode_type commandModeType;/** for LP/HS mode for command mode */
+ dsi_lane_mode clockLaneMode;
+ dsi_lane_mode dataLane1Mode;
+ dsi_lane_mode dataLane2Mode;
+ dsi_arb_mode arbMode;
+ dsi_te_ctrl if1TeCtrl;
+ dsi_te_ctrl if2TeCtrl;
+ dsi_te_ctrl regTeCtrl;
+ dsi_bta_mode btaMode;
+ dsi_rd_ctrl rdCtrl;
+ dsi_host_eot_gen_mode hostEotGenMode;
+ dsi_eot_gen_mode displayEotGenMode;
+ dsi_ecc_gen_mode dispEccGenMode;
+ dsi_checksum_gen_mode dispChecksumGenMode;
+ dsi_clk_continious_hs_mode clockContiniousMode;
+ u8 paddingValue;
+};
+#endif /** __KERNEL_ */
+
+u32 dsiconfdphy1(mcde_pll_ref_clk pll_sel, mcde_ch_id chid, dsi_link link);
+u32 dsidisplayinitLPcmdmode(mcde_ch_id chid, dsi_link link);
+
+dsi_error dsisetlinkstate(dsi_link link, dsi_link_state linkState, mcde_ch_id chid);
+u32 dsiLinkInit(struct dsi_link_conf *pdsiLinkConf, struct dsi_dphy_static_conf dphyStaticConf, mcde_ch_id chid, dsi_link link);
+int mcde_dsi_test_LP_directcommand_mode(struct fb_info *info,u32 key);
+int mcde_dsi_start(struct fb_info *info);
+int mcde_dsi_test_dsi_HS_directcommand_mode(struct fb_info *info,u32 key);
+
+int mcde_dsi_read_reg(struct fb_info *info, u32 reg, u32 *value);
+int mcde_dsi_write_reg(struct fb_info *info, u32 reg, u32 value);
+
+dsi_error dsisetPLLcontrol(dsi_link link, mcde_ch_id chid, dsi_pll_ctl pll_ctl);
+dsi_error dsisetPLLmode(dsi_link link, mcde_ch_id chid, dsi_pll_mode mode);
+dsi_error dsigetlinkstatus(dsi_link link, mcde_ch_id chid, u8 *p_status);
+dsi_error dsisetInterface(dsi_link link, mcde_ch_id chid, dsi_if_state state, dsi_interface interface);
+dsi_error dsisetInterface1mode(dsi_link link, dsi_interface_mode mode, mcde_ch_id chid);
+dsi_error dsisetInterfaceInLpm(dsi_link link, mcde_ch_id chid, dsi_interface_mode_type modType, dsi_interface interface);
+dsi_error dsisetTEtimeout(dsi_link link, mcde_ch_id chid, u32 te_timeout);
+dsi_error dsireadset(dsi_link link, dsi_rd_ctrl state, mcde_ch_id chid);
+dsi_error dsisetBTAmode(dsi_link link, dsi_bta_mode mode, mcde_ch_id chid);
+dsi_error dsisetdispEOTGenmode(dsi_link link, dsi_eot_gen_mode mode, mcde_ch_id chid);
+dsi_error dsisetdispHOSTEOTGenmode(dsi_link link, dsi_host_eot_gen_mode mode, mcde_ch_id chid);
+dsi_error dsisetdispCHKSUMGenmode(dsi_link link, dsi_checksum_gen_mode mode, mcde_ch_id chid);
+dsi_error dsisetdispECCGenmode(dsi_link link, dsi_ecc_gen_mode mode, mcde_ch_id chid);
+dsi_error dsisetCLKHSsendingmode(dsi_link link, dsi_clk_continious_hs_mode mode, mcde_ch_id chid);
+dsi_error dsisetpaddingval(dsi_link link, mcde_ch_id chid, u8 padding);
+dsi_error dsisetTE(dsi_link link, dsi_te_en tearing, dsi_te_ctrl state, mcde_ch_id chid);
+dsi_error dsisetlaneULPwaittime(dsi_link link, mcde_ch_id chid, dsi_lane lane, u16 timeout);
+
+dsi_error dsisetlanestate(dsi_link link, mcde_ch_id chid, dsi_lane_state mode, dsi_lane lane);
+dsi_error dsiset_hs_clock(dsi_link link, struct dsi_dphy_static_conf dphyStaticConf, mcde_ch_id chid);
+dsi_error dsisetDPHYtimeout(dsi_link link, mcde_ch_id chid, dsi_dphy_timeout timeout);
+void mcde_dsi_tpodisplay_init(struct fb_info *info);
+void mcde_dsi_taaldisplay_init(struct fb_info *info);
+
+/* following Apis are used by stw5810 driver for configuration */
+u32 dsisenddirectcommand(dsi_interface_mode_type mode_type, u32 cmd_head,u32 cmd_size,u32 cmd1,u32 cmd2,u32 cmd3,u32 cmd4, dsi_link link, mcde_ch_id chid);
+
+u32 dsiLPdcslongwrite(u32 VC_ID, u32 NoOfParam, u32 Param0, u32 Param1,u32 Param2, u32 Param3,
+ u32 Param4,u32 Param5,u32 Param6,u32 Param7,u32 Param8, u32 Param9,u32 Param10,u32 Param11,
+ u32 Param12,u32 Param13,u32 Param14, u32 Param15, mcde_ch_id chid, dsi_link link);
+
+u32 dsiLPdcsshortwrite1parm(u32 VC_ID, u32 Param0,u32 Param1, mcde_ch_id chid, dsi_link link);
+u32 dsiLPdcsshortwritenoparam(u32 VC_ID, u32 Param0, mcde_ch_id chid, dsi_link link);
+
+u32 dsiHSdcslongwrite(u32 VC_ID, u32 NoOfParam, u32 Param0, u32 Param1,u32 Param2, u32 Param3,
+ u32 Param4,u32 Param5,u32 Param6,u32 Param7,u32 Param8, u32 Param9,u32 Param10,u32 Param11,
+ u32 Param12,u32 Param13,u32 Param14, u32 Param15, mcde_ch_id chid, dsi_link link);
+
+u32 dsiHSdcsshortwrite1parm(u32 VC_ID, u32 Param0,u32 Param1, mcde_ch_id chid, dsi_link link);
+u32 dsiHSdcsshortwritenoparam(u32 VC_ID, u32 Param0, mcde_ch_id chid, dsi_link link);
+u32 dsireaddata(u8* byte0, u8* byte1, u8* byte2, u8* byte3, mcde_ch_id chid, dsi_link link);
+
+
+#ifdef _cplusplus
+}
+#endif /* _cplusplus */
+
+#endif /* !defined(_DSI_H_) */
+
+
diff --git a/arch/arm/mach-ux500/include/mach/dsi_reg.h b/arch/arm/mach-ux500/include/mach/dsi_reg.h
new file mode 100755
index 00000000000..a5fc8e39ff2
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/dsi_reg.h
@@ -0,0 +1,495 @@
+/*---------------------------------------------------------------------------*/
+/* Copyright (C) ST Ericsson 2009 */
+/* */
+/* This program is free software; you can redistribute it and/or modify it */
+/* under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, */
+/* or (at your option)any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */
+/* the GNU Lesser General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*---------------------------------------------------------------------------*/
+
+#ifndef _DSIREG_H_
+#define _DSIREG_H_
+
+#ifdef _cplusplus
+extern "C" {
+#endif /* _cplusplus */
+
+#include <linux/types.h>
+
+#define DSI_SET_BIT 0x1
+#define DSI_CLEAR_BIT 0x0
+#define DSI_SET_ALL_BIT 0xFFFFFFFF
+#define DSI_CLEAR_ALL_BIT 0x0
+#define DSI_MCTL_INTMODE_MASK MASK_BIT0
+#define DSI_MCTL_LINKEN_MASK MASK_BIT0
+#define DSI_MCTL_INTERFACE1_MODE_MASK MASK_BIT1
+#define DSI_MCTL_VID_EN_MASK MASK_BIT2
+#define DSI_MCTL_TVG_SEL_MASK MASK_BIT3
+#define DSI_MCTL_TBG_SEL_MASK MASK_BIT4
+#define DSI_MCTL_READEN_MASK MASK_BIT8
+#define DSI_MCTL_BTAEN_MASK MASK_BIT9
+#define DSI_MCTL_DISPECCGEN_MASK MASK_BIT10
+#define DSI_MCTL_DISPCHECKSUMGEN_MASK MASK_BIT11
+#define DSI_MCTL_HOSTEOTGEN_MASK MASK_BIT12
+#define DSI_MCTL_DISPEOTGEN_MASK MASK_BIT13
+#define DSI_PLL_MASTER_MASK MASK_BIT16
+#define DSI_PLL_OUT_SEL_MASK MASK_BIT11
+#define DSI_PLL_IN_SEL_MASK MASK_BIT10
+#define DSI_PLL_DIV_MASK (MASK_BIT7 | MASK_BIT8 | MASK_BIT9)
+#define DSI_PLL_MULT_MASK (MASK_BYTE0 & 0x7F)
+#define DSI_REG_TE_MASK MASK_BIT7
+#define DSI_IF1_TE_MASK MASK_BIT5
+#define DSI_IF2_TE_MASK MASK_BIT6
+#define DSI_LANE2_EN_MASK MASK_BIT0
+#define DSI_FORCE_STOP_MODE_MASK MASK_BIT1
+#define DSI_CLK_CONTINUOUS_MASK MASK_BIT2
+#define DSI_CLK_ULPM_EN_MASK MASK_BIT3
+#define DSI_DAT1_ULPM_EN_MASK MASK_BIT4
+#define DSI_DAT2_ULPM_EN_MASK MASK_BIT5
+#define DSI_WAIT_BURST_MASK (MASK_BIT6 | MASK_BIT7 | MASK_BIT8 | MASK_BIT9)
+#define DSI_CLKLANESTS_MASK (MASK_BIT0 | MASK_BIT1)
+#define DSI_DATALANE1STS_MASK (MASK_BIT2 | MASK_BIT3 | MASK_BIT4)
+#define DSI_DATALANE2STS_MASK (MASK_BIT5 | MASK_BIT6)
+#define DSI_CLK_DIV_MASK MASK_QUARTET0
+#define DSI_HSTX_TO_MASK (MASK_QUARTET1 | MASK_BYTE1 | MASK_BIT16 | MASK_BIT17)
+#define DSI_LPRX_TO_MASK (MASK_BYTE3 | MASK_QUARTET5 | MASK_BIT18 | MASK_BIT18)
+#define DSI_CLK_ULPOUT_MASK (MASK_BYTE0 | MASK_BIT8)
+#define DSI_DATA_ULPOUT_MASK (MASK_QUARTET3 | MASK_BIT9 | MASK_BIT10 | MASK_BIT11 | MASK_BIT16 | MASK_BIT17)
+#define DSI_PLL_START_MASK MASK_BIT0
+#define DSI_CKLANE_EN_MASK MASK_BIT3
+#define DSI_DAT1_EN_MASK MASK_BIT4
+#define DSI_DAT2_EN_MASK MASK_BIT5
+#define DSI_CLK_ULPM_MASK MASK_BIT6
+#define DSI_DAT1_ULPM_MASK MASK_BIT7
+#define DSI_DAT2_ULPM_MASK MASK_BIT8
+#define DSI_IF1_EN_MASK MASK_BIT9
+#define DSI_IF2_EN_MASK MASK_BIT10
+#define DSI_MAIN_STS_MASK MASK_BYTE0
+#define DSI_DPHY_ERROR_MASK MASK_HALFWORD0
+#define DSI_IF_DATA_MASK MASK_HALFWORD0
+#define DSI_IF_VALID_MASK MASK_BIT16
+#define DSI_IF_START_MASK MASK_BIT17
+#define DSI_IF_FRAME_SYNC_MASK MASK_BIT18
+#define DSI_IF_STALL_MASK MASK_BIT0
+#define DSI_INT_VAL_MASK MASK_BIT0
+#define DSI_DIRECT_CMD_RD_STS_MASK (MASK_BYTE0 | MASK_BIT8)
+#define DSI_CMD_MODE_STS_MASK (MASK_QUARTET0 | MASK_BIT4 | MASK_BIT5)
+#define DSI_RD_ID_MASK (MASK_BIT16 | MASK_BIT17 )
+#define DSI_RD_DCSNOTGENERIC_MASK MASK_BIT18
+#define DSI_CMD_NAT_MASK (MASK_BIT0 | MASK_BIT1 | MASK_BIT2)
+#define DSI_CMD_LONGNOTSHORT_MASK MASK_BIT3
+#define DSI_CMD_HEAD_MASK (MASK_QUARTET2 | MASK_BIT12 | MASK_BIT13)
+#define DSI_CMD_ID_MASK (MASK_BIT14 | MASK_BIT15)
+#define DSI_CMD_SIZE_MASK (MASK_QUARTET4 | MASK_BIT20)
+#define DSI_CMD_LP_EN_MASK (MASK_BIT21)
+#define DSI_TRIGGER_VAL_MASK MASK_QUARTET6
+#define DSI_TE_LOWERBIT_MASK MASK_BYTE2
+#define DSI_TE_UPPERBIT_MASK (MASK_BIT24 | MASK_BIT25)
+#define DSI_FIL_VAL_MASK MASK_BYTE1
+#define DSI_ARB_MODE_MASK MASK_BIT6
+#define DSI_ARB_PRI_MASK MASK_BIT7
+#define DSI_START_MODE_MASK (MASK_BIT0 | MASK_BIT1 )
+#define DSI_STOP_MODE_MASK (MASK_BIT2 | MASK_BIT3)
+#define DSI_VID_ID_MASK (MASK_BIT4 | MASK_BIT5)
+#define DSI_HEADER_MASK (MASK_BIT6 | MASK_BIT7 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10 | MASK_BIT11)
+#define DSI_PIXEL_MODE_MASK (MASK_BIT12 | MASK_BIT13)
+#define DSI_BURST_MODE_MASK (MASK_BIT14)
+#define DSI_SYNC_PULSE_ACTIVE_MASK (MASK_BIT15)
+#define DSI_SYNC_PULSE_HORIZONTAL_MASK (MASK_BIT16)
+#define DSI_BLKLINE_MASK (MASK_BIT17 | MASK_BIT18)
+#define DSI_BLKEOL_MASK (MASK_BIT19 | MASK_BIT20)
+#define DSI_RECOVERY_MODE_MASK (MASK_BIT21 | MASK_BIT22)
+#define DSI_VSA_LENGTH_MASK MASK_QUARTET0
+#define DSI_VBP_LENGTH_MASK MASK_QUARTET1
+#define DSI_VFP_LENGTH_MASK MASK_BYTE1
+#define DSI_VACT_LENGTH_MASK (MASK_BYTE2 | MASK_QUARTET6)
+#define DSI_HSA_LENGTH_MASK MASK_BYTE0
+#define DSI_HBP_LENGTH_MASK MASK_BYTE1
+#define DSI_HFP_LENGTH_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
+#define DSI_RGB_SIZE_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
+#define DSI_LINE_POS_MASK (MASK_BIT0 | MASK_BIT1)
+#define DSI_LINE_VAL_MASK (MASK_BIT2 | MASK_BIT3 | MASK_QUARTET1 | MASK_QUARTET2 | MASK_BIT12)
+#define DSI_HORI_POS_MASK (MASK_BIT0 | MASK_BIT1 |MASK_BIT2)
+#define DSI_HORI_VAL_MASK (MASK_BYTE1 | MASK_QUARTET1 | MASK_BIT3)
+#define DSI_VID_MODE_STS_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9)
+#define DSI_BURST_LP_MASK MASK_BIT16
+#define DSI_MAX_BURST_LIMIT_MASK MASK_HALFWORD0
+#define DSI_MAX_LINE_LIMIT_MASK MASK_HALFWORD1
+#define DSI_EXACT_BURST_LIMIT_MASK MASK_HALFWORD0
+#define DSI_BLKLINE_EVENT_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
+#define DSI_BLKEOL_PCK_MASK (MASK_BYTE2 | MASK_BIT15 | MASK_BIT14 | MASK_BIT13 | MASK_BIT24 | MASK_BIT25)
+#define DSI_BLKLINE_PULSE_PCK_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
+#define DSI_BLKEOL_DURATION_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
+#define DSI_VERT_BLANK_DURATION_MASK (MASK_BYTE2 | MASK_BIT15 | MASK_BIT14 | MASK_BIT13 | MASK_BIT24 | MASK_BIT25)
+#define DSI_COL_RED_MASK MASK_BYTE0
+#define DSI_COL_GREEN_MASK MASK_BYTE1
+#define DSI_COL_BLUE_MASK MASK_BYTE2
+#define DSI_PAD_VAL_MASK MASK_BYTE3
+#define DSI_TVG_STRIPE_MASK (MASK_BIT5 | MASK_BIT6 | MASK_BIT7)
+#define DSI_TVG_MODE_MASK (MASK_BIT3 | MASK_BIT4 )
+#define DSI_TVG_STOPMODE_MASK (MASK_BIT1 | MASK_BIT2 )
+#define DSI_TVG_RUN_MASK MASK_BIT0
+#define DSI_TVG_NBLINE_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
+#define DSI_TVG_LINE_SIZE_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
+#define DSI_CMD_MODE_STATUS_MASK (MASK_QUARTET0 | MASK_BIT4 | MASK_BIT5 )
+#define DSI_DIRECT_CMD_STS_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10 )
+#define DSI_DIRECT_CMD_RD_STATUS_MASK (MASK_BYTE0 | MASK_BIT8 )
+#define DSI_VID_MODE_STATUS_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 )
+#define DSI_TG_STS_MASK (MASK_BIT0 | MASK_BIT1)
+#define DSI_CLK_TRIM_RD_MASK MASK_BIT0
+#define DSI_IF1_LPM_EN_MASK MASK_BIT4
+#define DSI_IF2_LPM_EN_MASK MASK_BIT5
+#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT2 MASK_BIT5
+#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT2 MASK_BIT4
+#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT1 MASK_BIT3
+#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT1 MASK_BIT2
+#define DSIMCTL_DPHY_STATIC_HS_INVERT_CLK MASK_BIT1
+#define DSIMCTL_DPHY_STATIC_SWAP_PINS_CLK MASK_BIT0
+#define DSIMCTL_DPHY_STATIC_UI_X4 (MASK_BIT6 | MASK_BIT7 | MASK_QUARTET2)
+
+#define DSI_MCTL_INTERFACE1_MODE_SHIFT 1
+#define DSI_MCTL_VID_EN_SHIF 2
+#define DSI_MCTL_TVG_SEL_SHIFT 3
+#define DSI_MCTL_TBG_SEL_SHIFT 4
+#define DSI_MCTL_READEN_SHIFT 8
+#define DSI_MCTL_BTAEN_SHIFT 9
+#define DSI_MCTL_DISPECCGEN_SHIFT 10
+#define DSI_MCTL_DISPCHECKSUMGEN_SHIFT 11
+#define DSI_MCTL_HOSTEOTGEN_SHIFT 12
+#define DSI_MCTL_DISPEOTGEN_SHIFT 13
+#define DSI_PLL_MASTER_SHIFT 16
+#define DSI_PLL_OUT_SEL_SHIFT 11
+#define DSI_PLL_IN_SEL_SHIFT 10
+#define DSI_MCTL_VID_EN_SHIFT 2
+#define DSI_PLL_DIV_SHIFT 7
+#define DSI_REG_TE_SHIFT 7
+#define DSI_IF1_TE_SHIFT 5
+#define DSI_IF2_TE_SHIFT 6
+#define DSI_FORCE_STOP_MODE_SHIFT 1
+#define DSI_CLK_CONTINUOUS_SHIFT 2
+#define DSI_CLK_ULPM_EN_SHIFT 3
+#define DSI_DAT1_ULPM_EN_SHIFT 4
+#define DSI_DAT2_ULPM_EN_SHIFT 5
+#define DSI_WAIT_BURST_SHIFT 6
+#define DSI_DATALANE1STS_SHIFT 2
+#define DSI_DATALANE2STS_SHIFT 5
+#define DSI_HSTX_TO_SHIFT 4
+#define DSI_LPRX_TO_SHIFT 18
+#define DSI_DATA_ULPOUT_SHIFT 9
+#define DSI_CKLANE_EN_SHIFT 3
+#define DSI_DAT1_EN_SHIFT 4
+#define DSI_DAT2_EN_SHIFT 5
+#define DSI_CLK_ULPM_SHIFT 6
+#define DSI_DAT1_ULPM_SHIFT 7
+#define DSI_DAT2_ULPM_SHIFT 8
+#define DSI_IF1_EN_SHIFT 9
+#define DSI_IF2_EN_SHIFT 10
+#define DSI_IF_VALID_SHIFT 16
+#define DSI_IF_START_SHIFT 17
+#define DSI_IF_FRAME_SYNC_SHIFT 18
+#define DSI_RD_ID_SHIFT 16
+#define DSI_RD_DCSNOTGENERIC_SHIFT 18
+#define DSI_CMD_LONGNOTSHORT_SHIFT 3
+#define DSI_CMD_HEAD_SHIFT 8
+#define DSI_CMD_ID_SHIFT 14
+#define DSI_CMD_SIZE_SHIFT 16
+#define DSI_CMD_LP_EN_SHIFT 21
+#define DSI_TRIGGER_VAL_SHIFT 24
+#define DSI_TE_LOWERBIT_SHIFT 16
+#define DSI_TE_UPPERBIT_SHIFT 24
+#define DSI_FIL_VAL_SHIFT 8
+#define DSI_ARB_MODE_SHIFT 6
+#define DSI_ARB_PRI_SHIFT 7
+#define DSI_STOP_MODE_SHIFT 2
+#define DSI_VID_ID_SHIFT 4
+#define DSI_HEADER_SHIFT 6
+#define DSI_PIXEL_MODE_SHIFT 12
+#define DSI_BURST_MODE_SHIFT 14
+#define DSI_SYNC_PULSE_ACTIVE_SHIFT 15
+#define DSI_SYNC_PULSE_HORIZONTAL_SHIFT 16
+#define DSI_BLKLINE_SHIFT 17
+#define DSI_BLKEOL_SHIFT 19
+#define DSI_RECOVERY_MODE_SHIFT 21
+#define DSI_VBP_LENGTH_SHIFT 4
+#define DSI_VFP_LENGTH_SHIFT 8
+#define DSI_VACT_LENGTH_SHIFT 16
+#define DSI_HBP_LENGTH_SHIFT 8
+#define DSI_HFP_LENGTH_SHIFT 16
+#define DSI_LINE_VAL_SHIFT 2
+#define DSI_HORI_VAL_SHIFT 3
+#define DSI_BURST_LP_SHIFT 16
+#define DSI_MAX_LINE_LIMIT_SHIFT 16
+#define DSI_BLKEOL_PCK_SHIFT 13
+#define DSI_VERT_BLANK_DURATION_SHIFT 13
+#define DSI_COL_GREEN_SHIFT 8
+#define DSI_COL_BLUE_SHIFT 16
+#define DSI_PAD_VAL_SHIFT 24
+#define DSI_TVG_STRIPE_SHIFT 1
+#define DSI_TVG_MODE_SHIFT 3
+#define DSI_TVG_STOPMODE_SHIFT 5
+#define DSI_TVG_NBLINE_SHIFT 16
+#define DSIMCTL_DPHY_STATIC_SWAP_PINS_CLK_SHIFT 0
+#define DSIMCTL_DPHY_STATIC_HS_INVERT_CLK_SHIFT 1
+#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT1_SHIFT 2
+#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT1_SHIFT 3
+#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT2_SHIFT 4
+#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT2_SHIFT 5
+#define DSIMCTL_DPHY_STATIC_UI_X4_SHIFT 6
+#define DSI_IF1_LPM_EN_MASK_SHIFT 4
+#define DSI_IF2_LPM_EN_MASK_SHIFT 5
+
+#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK 0x80
+#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK_SHIFT 7
+
+#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK 0x40
+#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK_SHIFT 6
+
+#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR 0x20
+#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR_SHIFT 5
+
+#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR 0x10
+#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR_SHIFT 4
+
+#define DSI_MCTL_MAIN_STS_DAT2_READY 0x8
+#define DSI_MCTL_MAIN_STS_DAT2_READY_SHIFT 3
+
+#define DSI_MCTL_MAIN_STS_DAT1_READY 0x4
+#define DSI_MCTL_MAIN_STS_DAT1_READY_SHIFT 2
+
+#define DSI_MCTL_MAIN_STS_CLKLANE_READY 0x2
+#define DSI_MCTL_MAIN_STS_CLKLANE_READY_SHIFT 1
+
+#define DSI_MCTL_MAIN_STS_PLL_LOCK 0x1
+#define DSI_MCTL_MAIN_STS_PLL_LOCK_SHIFT 0
+/** Test mode conf */
+
+//**********************************************************************************************************************
+/** - DIRECT_CMD_WRDAT0 */
+//**********************************************************************************************************************
+
+#define DSIDIRECT_CMD_WRDAT0_WRDAT3 (0xFF000000)
+#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT3 (24)
+#define DSIDIRECT_CMD_WRDAT0_WRDAT2 (0xFF0000)
+#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT2 (16)
+#define DSIDIRECT_CMD_WRDAT0_WRDAT1 (0xFF00)
+#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT1 (8)
+#define DSIDIRECT_CMD_WRDAT0_WRDAT0 (0xFF)
+#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT0 (0)
+
+//**********************************************************************************************************************
+/** - DIRECT_CMD_WRDAT1 */
+//**********************************************************************************************************************
+
+#define DSIDIRECT_CMD_WRDAT1_WRDAT7 (0xFF000000)
+#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT7 (24)
+#define DSIDIRECT_CMD_WRDAT1_WRDAT6 (0xFF0000)
+#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT6 (16)
+#define DSIDIRECT_CMD_WRDAT1_WRDAT5 (0xFF00)
+#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT5 (8)
+#define DSIDIRECT_CMD_WRDAT1_WRDAT4 (0xFF)
+#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT4 (0)
+
+
+//**********************************************************************************************************************
+/** - DIRECT_CMD_WRDAT2 */
+//**********************************************************************************************************************
+
+#define DSIDIRECT_CMD_WRDAT2_WRDAT11 (0xFF000000)
+#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT11 (24)
+#define DSIDIRECT_CMD_WRDAT2_WRDAT10 (0xFF0000)
+#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT10 (16)
+#define DSIDIRECT_CMD_WRDAT2_WRDAT9 (0xFF00)
+#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT9 (8)
+#define DSIDIRECT_CMD_WRDAT2_WRDAT8 (0xFF)
+#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT8 (0)
+
+//**********************************************************************************************************************
+/** - DIRECT_CMD_WRDAT3 */
+//**********************************************************************************************************************
+
+#define DSIDIRECT_CMD_WRDAT3_WRDAT15 (0xFF000000)
+#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT15 (24)
+#define DSIDIRECT_CMD_WRDAT3_WRDAT14 (0xFF0000)
+#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT14 (16)
+#define DSIDIRECT_CMD_WRDAT3_WRDAT13 (0xFF00)
+#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT13 (8)
+#define DSIDIRECT_CMD_WRDAT3_WRDAT12 (0xFF)
+#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT12 (0)
+//**********************************************************************************************************************
+/** - DIRECT_CMD_READ */
+//**********************************************************************************************************************
+
+#define DSIDIRECT_CMD_RDAT3 (0xFF000000)
+#define Shift_DSIDIRECT_CMD_RDAT3 (24)
+#define DSIDIRECT_CMD_RDAT2 (0xFF0000)
+#define Shift_DSIDIRECT_CMD_RDAT2 (16)
+#define DSIDIRECT_CMD_RDAT1 (0xFF00)
+#define Shift_DSIDIRECT_CMD_RDAT1 (8)
+#define DSIDIRECT_CMD_RDAT0 (0xFF)
+#define Shift_DSIDIRECT_CMD_RDAT0 (0)
+
+/** TPO COMMAND HEADER */
+#define TPO_CMD_NONE 0x00
+#define TPO_CMD_SWRESET 0x01 /** SWRESET: Software Reset (01h) */
+#define TPO_CMD_SLPOUT 0x11 /** SLPOUT: Sleep Out (11h) */
+#define TPO_CMD_NORON 0x13 /** NORON: Normal Display Mode On (13h) */
+#define TPO_CMD_INVOFF 0x20 /** INVOFF: Display Inversion Off (20h) */
+#define TPO_CMD_INVON 0x21 /** INVOFF: Display Inversion Off (20h) */
+#define TPO_CMD_GAMMA_SET 0x26 /** Gamma set//reset GC0G2.2 */
+
+#define TPO_CMD_DISPOFF 0x28 /** DISPON: Display On (29h) */
+#define TPO_CMD_DISPON 0x29 /** DISPON: Display On (29h) */
+#define TPO_CMD_CASET 0x2A /** CASET :Columen address select */
+#define TPO_CMD_RASET 0x2B /** RASET :Row address select */
+#define TPO_CMD_RAMWR 0x2C /** RAMWR ram write */
+
+#define TPO_CMD_MADCTR 0x36 /** MADCTR: Memory Data Access Control (36h) */
+#define TPO_CMD_IDMOFF 0x38 /** IDMON: Idle Mode On (39h) */
+#define TPO_CMD_IDMON 0x39 /** IDMON: Idle Mode On (39h) */
+#define TPO_CMD_COLMOD 0x3A /** COLMOD: Interface Pixel Format (3Ah). */
+#define TPO_CMD_RAMWR_CONTINUE 0x3C /** Ram write continue */
+#define TPO_CMD_IFMODE 0xB0 /** IFMODE: Set Display Interface Mode (B0h) */
+#define TPO_CMD_DISSET6 0xB7 /** Display Function Setting 6 (B7h) */
+#define TPO_CMD_LPTS_FUNCTION_SET3 0xBC /** LPTS_FUNCTION_SET3 (0xBC) */
+#define TPO_CMD_DSLPOUT 0xCA /** deep sleepout 0xca */
+
+
+#define TPO_CMD_GAMCTRP1 0xE0 /** GAMCTRP1: Set Positive Gamma Correction Characteristics (E0h) */
+#define TPO_CMD_GAMCTRN1 0xE1 /** GAMCTRN1: Set Negative Gamma Correction Characteristics (E1h) */
+#define TPO_CMD_GAMCTRP2 0xE2 /** GAMCTRP2: Gamma (‘+’polarity) Correction Characteristics Setting (E2h) */
+#define TPO_CMD_GAMCTRN2 0xE3 /** GAMCTRN2: Gamma (‘-’polarity) Correction Characteristics Setting (E3h) */
+#define TPO_CMD_GAMCTRP3 0xE4 /** GAMCTRP3: Gamma (‘+’polarity) Correction Characteristics Setting (E4h) */
+#define TPO_CMD_GAMCTRN3 0xE5 /** GAMCTRN3: Gamma (‘-’polarity) Correction Characteristics Setting (E5h) */
+#define TPO_CMD_GAM_R_SEL 0xEA /** GAMMA SELECTION */
+
+
+
+#define VC_ID0 0
+#define VC_ID1 1
+
+
+
+
+struct dsi_link_registers
+{
+ /** Main control registers */
+ volatile u32 mctl_integration_mode;
+ volatile u32 mctl_main_data_ctl;
+ volatile u32 mctl_main_phy_ctl;
+ volatile u32 mctl_pll_ctl;
+ volatile u32 mctl_lane_sts;
+ volatile u32 mctl_dphy_timeout;
+ volatile u32 mctl_ulpout_time;
+ volatile u32 mctl_dphy_static;
+ volatile u32 mctl_main_en;
+ volatile u32 mctl_main_sts;
+ volatile u32 mctl_dphy_err;
+
+ volatile u32 reserved1;
+ /**
+ integration mode registers */
+ volatile u32 int_vid_rddata;
+ volatile u32 int_vid_gnt;
+ volatile u32 int_cmd_rddata;
+ volatile u32 int_cmd_gnt;
+ volatile u32 int_interrupt_ctl;
+ volatile u32 reserved2[3];
+ /**
+ Command mode registers */
+ volatile u32 cmd_mode_ctl;
+ volatile u32 cmd_mode_sts;
+ volatile u32 reserved3[2];
+ /**
+ Direct Command registers */
+ volatile u32 direct_cmd_send;
+ volatile u32 direct_cmd_main_settings;
+ volatile u32 direct_cmd_sts;
+ volatile u32 direct_cmd_rd_init;
+ volatile u32 direct_cmd_wrdat0;
+ volatile u32 direct_cmd_wrdat1;
+ volatile u32 direct_cmd_wrdat2;
+ volatile u32 direct_cmd_wrdat3;
+ volatile u32 direct_cmd_rddat;
+ volatile u32 direct_cmd_rd_property;
+ volatile u32 direct_cmd_rd_sts;
+ volatile u32 reserved4;
+ /**
+ Video mode registers */
+ volatile u32 vid_main_ctl;
+ volatile u32 vid_vsize;
+ volatile u32 vid_hsize1;
+ volatile u32 vid_hsize2;
+ volatile u32 vid_blksize1;
+ volatile u32 vid_blksize2;
+ volatile u32 vid_pck_time;
+ volatile u32 vid_dphy_time;
+ volatile u32 vid_err_color;
+ volatile u32 vid_vpos;
+ volatile u32 vid_hpos;
+ volatile u32 vid_mode_sts;
+ volatile u32 vid_vca_setting1;
+ volatile u32 vid_vca_setting2;
+ /**
+ Test Video Mode regsiter */
+ volatile u32 tvg_ctl;
+ volatile u32 tvg_img_size;
+ volatile u32 tvg_color1;
+ volatile u32 tvg_color2;
+ volatile u32 tvg_sts;
+ volatile u32 reserved5;
+ /**
+ Test Byte generator register */
+ volatile u32 tbg_ctl;
+ volatile u32 tbg_setting;
+ volatile u32 tbg_sts;
+ volatile u32 reserved6;
+ /**
+ Interrupt Enable and Edge detection register */
+ volatile u32 mctl_main_sts_ctl;
+ volatile u32 cmd_mode_sts_ctl;
+ volatile u32 direct_cmd_sts_ctl;
+ volatile u32 direct_cmd_rd_sts_ctl;
+ volatile u32 vid_mode_sts_ctl;
+ volatile u32 tg_sts_ctl;
+ volatile u32 mctl_dphy_err_ctl;
+ volatile u32 dphy_clk_trim_rd_ctl;
+ /**
+ Error/Interrupt Clear Register */
+ volatile u32 mctl_main_sts_clr;
+ volatile u32 cmd_mode_sts_clr;
+ volatile u32 direct_cmd_sts_clr;
+ volatile u32 direct_cmd_rd_sts_clr;
+ volatile u32 vid_mode_sts_clr;
+ volatile u32 tg_sts_clr;
+ volatile u32 mctl_dphy_err_clr;
+ volatile u32 dphy_clk_trim_rd_clr;
+ /**
+ Flag registers */
+ volatile u32 mctl_main_sts_flag;
+ volatile u32 cmd_mode_sts_flag;
+ volatile u32 direct_cmd_sts_flag;
+ volatile u32 direct_cmd_rd_sts_flag;
+ volatile u32 vid_mode_sts_flag;
+ volatile u32 tg_sts_flag;
+ volatile u32 mctl_dphy_err_flag;
+ volatile u32 dphy_clk_trim_rd_flag;
+ volatile u32 dhy_lanes_trim;
+};
+
+
+
+#ifdef _cplusplus
+}
+#endif /* _cplusplus */
+
+#endif /* !defined(_DSI_H_) */
+
+
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
new file mode 100755
index 00000000000..af3998021e2
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/entry-macro.S
@@ -0,0 +1,84 @@
+/*
+ * Low-level IRQ helper macros for U8500 platforms based
+ * heavily on realview platform
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <asm/hardware/gic.h>
+
+ .macro disable_fiq
+ .endm
+
+ .macro get_irqnr_preamble, base, tmp
+ ldr \base, =IO_ADDRESS(U8500_GIC_CPU_BASE)
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
+ /*
+ * The interrupt numbering scheme is defined in the
+ * interrupt controller spec. To wit:
+ *
+ * Interrupts 0-15 are IPI
+ * 16-28 are reserved
+ * 29-31 are local. We allow 30 to be used for the watchdog.
+ * 32-1020 are global
+ * 1021-1022 are reserved
+ * 1023 is "spurious" (no interrupt)
+ *
+ * For now, we ignore all local interrupts so only return an
+ * interrupt if it's between 30 and 1020. The test_for_ipi
+ * routine below will pick up on IPIs.
+ *
+ * A simple read from the controller will tell us the number
+ * of the highest priority enabled interrupt. We then just
+ * need to check whether it is in the
+ * valid range for an IRQ (30-1020 inclusive).
+ */
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+ /* bits 12-10 = src CPU, 9-0 = int # */
+ ldr \irqstat, [\base, #GIC_CPU_INTACK]
+
+ ldr \tmp, =1021
+
+ bic \irqnr, \irqstat, #0x1c00
+
+ cmp \irqnr, #29
+ cmpcc \irqnr, \irqnr
+ cmpne \irqnr, \tmp
+ cmpcs \irqnr, \irqnr
+
+ .endm
+
+ /* We assume that irqstat (the raw value of the IRQ acknowledge
+ * register) is preserved from the macro above.
+ * If there is an IPI, we immediately signal end of interrupt
+ * on the controller, since this requires the original
+ * irqstat value which we won't easily be able to recreate
+ * later.
+ */
+
+ .macro test_for_ipi, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ cmp \irqnr, #16
+ strcc \irqstat, [\base, #GIC_CPU_EOI]
+ cmpcs \irqnr, \irqnr
+ .endm
+
+ /* As above, this assumes that irqstat and base are
+ * preserved..
+ */
+
+ .macro test_for_ltirq, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ mov \tmp, #0
+ cmp \irqnr, #29
+ moveq \tmp, #1
+ streq \irqstat, [\base, #GIC_CPU_EOI]
+ cmp \tmp, #0
+ .endm
diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h
new file mode 100755
index 00000000000..b358f71b8cd
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/gpio.h
@@ -0,0 +1,190 @@
+/*----------------------------------------------------------------------------------*/
+/* copyright STMicroelectronics, 2007. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it under */
+/* the terms of the GNU General Public License as published by the Free */
+/* Software Foundation; either version 2.1 of the License, or (at your option) */
+/* any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but WITHOUT */
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS */
+/* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*----------------------------------------------------------------------------------*/
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H
+
+#ifndef __LINUX_GPIO_H
+#error "Do not include this file directly, include <linux/gpio.h> instead."
+#endif
+
+#define ARCH_NR_GPIOS 309 /* 292+17 for STMPE1601*/
+
+#include <mach/hardware.h>
+#include <asm-generic/gpio.h>
+#include <mach/irqs.h>
+
+/*
+ * Macro to decorate plain GPIO numbers
+ */
+#define GPIO(x) (x)
+#define stm_get_gpio_base(base, offset) base
+/*
+ * Macros to get IRQ number from GPIO pin and vice-versa
+ */
+#define GPIO_TO_IRQ(gpio) (gpio + MAX_CHIP_IRQ)
+#define IRQ_TO_GPIO(irq) (irq - MAX_CHIP_IRQ)
+
+/*
+ * Standard GPIOLIB APIs (additional APIs in include/asm-generic/gpio.h)
+ */
+static inline int gpio_to_irq(unsigned int gpio)
+{
+ if (gpio_is_valid(gpio))
+ return GPIO_TO_IRQ(gpio);
+ else
+ return -EINVAL;
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+ if (irq < NR_IRQS)
+ return IRQ_TO_GPIO(irq);
+ else
+ return -EINVAL;
+}
+
+static inline int gpio_get_value(unsigned int gpio)
+{
+ return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned int gpio, int value)
+{
+ __gpio_set_value(gpio, value);
+}
+
+/*
+ * Special values for gpio_set_value() to enable platform-specific
+ * GPIO configurations, in addition to named values for 0 and 1
+ */
+#define GPIO_LOW 0
+#define GPIO_HIGH 1
+#define GPIO_PULLUP_DIS 0xA
+#define GPIO_PULLUP_EN 0xB
+#define GPIO_ALTF_A 0xAFA /* Alternate function A */
+#define GPIO_ALTF_B 0xAFB /* Alternate function B */
+#define GPIO_ALTF_C 0xAFC /* Alternate function C */
+#define GPIO_RESET 0xAFD /* Input with pull-up/down */
+
+/*
+ * Alternate Function:
+ * refered in altfun_table to pointout particular altfun to be enabled
+ * when using GPIO_ALT_FUNCTION A/B/C enable/disable operation
+ */
+typedef enum {
+ GPIO_ALT_UART_0_MODEM,
+ GPIO_ALT_UART_0_NO_MODEM,
+ GPIO_ALT_UART_1,
+ GPIO_ALT_UART_2,
+ GPIO_ALT_I2C_0,
+ GPIO_ALT_I2C_1,
+ GPIO_ALT_I2C_2,
+ GPIO_ALT_I2C_3,
+ GPIO_ALT_I2C_4,
+ GPIO_ALT_MSP_0,
+ GPIO_ALT_MSP_1,
+ GPIO_ALT_MSP_2,
+ GPIO_ALT_MSP_3,
+ GPIO_ALT_SSP_0,
+ GPIO_ALT_SSP_1,
+ GPIO_ALT_MM_CARD,
+ GPIO_ALT_SD_CARD,
+ GPIO_ALT_DMA_0,
+ GPIO_ALT_DMA_1,
+ GPIO_ALT_HSIR,
+ GPIO_ALT_CCIR656_INPUT,
+ GPIO_ALT_CCIR656_OUTPUT,
+ GPIO_ALT_LCD_PANELA,
+ GPIO_ALT_LCD_PANELB_ED,
+ GPIO_ALT_LCD_PANELB,
+ GPIO_ALT_MDIF,
+ GPIO_ALT_SDRAM,
+ GPIO_ALT_HAMAC_AUDIO_DBG,
+ GPIO_ALT_HAMAC_VIDEO_DBG,
+ GPIO_ALT_CLOCK_RESET,
+ GPIO_ALT_TSP,
+ GPIO_ALT_IRDA,
+ GPIO_ALT_USB_MINIMUM,
+ GPIO_ALT_USB_I2C,
+ GPIO_ALT_OWM,
+ GPIO_ALT_PWL,
+ GPIO_ALT_FSMC,
+ GPIO_ALT_COMP_FLASH,
+ GPIO_ALT_SRAM_NOR_FLASH,
+ GPIO_ALT_FSMC_ADDLINE_0_TO_15,
+ GPIO_ALT_SCROLL_KEY,
+ GPIO_ALT_MSHC,
+ GPIO_ALT_HPI,
+ GPIO_ALT_USB_OTG,
+ GPIO_ALT_SDIO,
+ GPIO_ALT_HSMMC,
+ GPIO_ALT_FSMC_ADD_DATA_0_TO_25,
+ GPIO_ALT_HSIT,
+ GPIO_ALT_NOR,
+ GPIO_ALT_NAND,
+ GPIO_ALT_KEYPAD,
+ GPIO_ALT_VPIP,
+ GPIO_ALT_CAM,
+ GPIO_ALT_CCP1,
+ GPIO_ALT_EMMC,
+ GPIO_ALT_SDMMC,
+ GPIO_ALT_TRACE,
+ GPIO_ALT_MMIO_INIT_BOARD,
+ GPIO_ALT_MMIO_CAM_SET_I2C,
+ GPIO_ALT_MMIO_CAM_SET_EXT_CLK,
+ GPIO_ALT_SDMMC2,
+ GPIO_ALT_TP_SET_EXT_CLK,
+ GPIO_ALT_FUNMAX /* Add new alt func before this */
+
+
+} gpio_alt_function;
+
+/* GPIO pin data*/
+typedef enum {
+ GPIO_DATA_LOW, /* GPIO pin status is low. */
+ GPIO_DATA_HIGH /* GPIO pin status is high. */
+} gpio_data;
+
+struct gpio_altfun_data {
+ gpio_alt_function altfun;
+ int start;
+ int end;
+ int cont;
+ int type;
+ char dev_name[20];
+};
+
+struct clk;
+struct gpio_platform_data {
+ struct gpio_block_data *gpio_data;
+ int gpio_block_size;
+ struct gpio_altfun_data *altfun_table;
+ int altfun_table_size;
+ struct clk *clk; /* FIXME put this somewhere more appropriate */
+};
+
+struct gpio_block_data {
+ u32 block_base;
+ u32 block_size;
+ u32 base_offset;
+ int blocks_per_irq;
+ int irq;
+};
+
+extern int stm_gpio_altfuncenable(gpio_alt_function alt_func);
+extern int stm_gpio_altfuncdisable(gpio_alt_function alt_func);
+
+#endif /* __INC_GPIO_H */
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
new file mode 100755
index 00000000000..cd37b6bb1ee
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -0,0 +1,219 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson.
+ *
+ * U8500 hardware definitions
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#define IO_BASE 0xF0000000 /* VA of IO */
+#define IO_SIZE 0x1FF00000 /* VA Size for IO */
+#define IO_START 0x10100000 /* PA of IO */
+
+/*
+ * macro to get at IO space when running virtually
+ */
+#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + IO_BASE)
+
+#include <mach/db8500-regs.h>
+#include <mach/db5500-regs.h>
+
+#ifdef CONFIG_UX500_SOC_DB8500
+#define UX500(periph) U8500_##periph##_BASE
+#elif defined(CONFIG_UX500_SOC_DB5500)
+#define UX500(periph) U5500_##periph##_BASE
+#endif
+
+#define UX500_BACKUPRAM0_BASE UX500(BACKUPRAM0)
+#define UX500_BACKUPRAM1_BASE UX500(BACKUPRAM1)
+#define UX500_B2R2_BASE UX500(B2R2)
+
+#define UX500_CLKRST1_BASE UX500(CLKRST1)
+#define UX500_CLKRST2_BASE UX500(CLKRST2)
+#define UX500_CLKRST3_BASE UX500(CLKRST3)
+#define UX500_CLKRST5_BASE UX500(CLKRST5)
+#define UX500_CLKRST6_BASE UX500(CLKRST6)
+
+#define UX500_DMA_BASE UX500(DMA)
+#define UX500_FSMC_BASE UX500(FSMC)
+
+#define UX500_GIC_CPU_BASE UX500(GIC_CPU)
+#define UX500_GIC_DIST_BASE UX500(GIC_DIST)
+
+#define UX500_I2C1_BASE UX500(I2C1)
+#define UX500_I2C2_BASE UX500(I2C2)
+#define UX500_I2C3_BASE UX500(I2C3)
+
+#define UX500_L2CC_BASE UX500(L2CC)
+#define UX500_MCDE_BASE UX500(MCDE)
+#define UX500_MTU0_BASE UX500(MTU0)
+#define UX500_MTU1_BASE UX500(MTU1)
+#define UX500_PRCMU_BASE UX500(PRCMU)
+
+#define UX500_RNG_BASE UX500(RNG)
+#define UX500_RTC_BASE UX500(RTC)
+
+#define UX500_SCU_BASE UX500(SCU)
+
+#define UX500_SDI0_BASE UX500(SDI0)
+#define UX500_SDI1_BASE UX500(SDI1)
+#define UX500_SDI2_BASE UX500(SDI2)
+#define UX500_SDI3_BASE UX500(SDI3)
+#define UX500_SDI4_BASE UX500(SDI4)
+
+#define UX500_SPI0_BASE UX500(SPI0)
+#define UX500_SPI1_BASE UX500(SPI1)
+#define UX500_SPI2_BASE UX500(SPI2)
+#define UX500_SPI3_BASE UX500(SPI3)
+
+#define UX500_SIA_BASE UX500(SIA)
+#define UX500_SVA_BASE UX500(SVA)
+
+#define UX500_TWD_BASE UX500(TWD)
+
+#define UX500_UART0_BASE UX500(UART0)
+#define UX500_UART1_BASE UX500(UART1)
+#define UX500_UART2_BASE UX500(UART2)
+
+#define UX500_USBOTG_BASE UX500(USBOTG)
+
+#define U8500_ESRAM_BASE 0x40000000
+#define U8500_ESRAM_DMA_LCLA_OFFSET 0x80000
+#define U8500_ESRAM_DMA_LCPA_OFFSET 0x84000
+
+#define U8500_DMA_LCLA_BASE (U8500_ESRAM_BASE + U8500_ESRAM_DMA_LCLA_OFFSET)
+#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BASE + U8500_ESRAM_DMA_LCPA_OFFSET)
+
+/* SSP specific declaration */
+#define SSP_PER_ID 0x01080022
+#define SSP_PER_MASK 0x0fffffff
+
+/* SSP specific declaration */
+#define SPI_PER_ID 0x00080023
+#define SPI_PER_MASK 0x0fffffff
+
+/* MSP specific declaration */
+#define MSP_PER_ID 0x00280021
+#define MSP_PER_MASK 0x00ffffff
+
+/* DMA specific declaration */
+#define DMA_PER_ID 0x8A280080
+#define DMA_PER_MASK 0xffffffff
+
+#define GPIO_TOTAL_PINS 267
+#define GPIO_PER_ID 0x1f380060
+#define GPIO_PER_MASK 0xffffffff
+
+/* RTC specific declaration */
+#define RTC_PER_ID 0x00280031
+#define RTC_PER_MASK 0x00ffffff
+
+/*
+ * FIFO offsets for IPs
+ */
+#define I2C_TX_REG_OFFSET (0x10)
+#define I2C_RX_REG_OFFSET (0x18)
+#define UART_TX_RX_REG_OFFSET (0)
+#define MSP_TX_RX_REG_OFFSET (0)
+#define SSP_TX_RX_REG_OFFSET (0x8)
+#define SPI_TX_RX_REG_OFFSET (0x8)
+#define SD_MMC_TX_RX_REG_OFFSET (0x80)
+
+#define MSP_0_CONTROLLER 1
+#define MSP_1_CONTROLLER 2
+#define MSP_2_CONTROLLER 3
+
+#define SSP_0_CONTROLLER 4
+#define SSP_1_CONTROLLER 5
+
+#define SPI023_0_CONTROLLER 6
+#define SPI023_1_CONTROLLER 7
+#define SPI023_2_CONTROLLER 8
+#define SPI023_3_CONTROLLER 9
+
+/* MSP related board specific declaration************************/
+
+#define MSP_DATA_DELAY MSP_DELAY_0
+#define MSP_TX_CLOCK_EDGE MSP_FALLING_EDGE
+#define MSP_RX_CLOCK_EDGE MSP_FALLING_EDGE
+#define NUM_MSP_CONTROLLER 3
+
+/* I2C configuration
+ * * *
+ * * */
+#define I2C0_LP_OWNADDR 0x31
+#define I2C1_LP_OWNADDR 0x60
+#define I2C2_LP_OWNADDR 0x70
+#define I2C3_LP_OWNADDR 0x80
+#define I2C4_LP_OWNADDR 0x90
+
+/* SDMMC specific declarations */
+#define SDI_PER_ID 0x00480180
+#define SDI_PER_MASK 0x00ffffff
+/* B2R2 clock management register */
+#define PRCM_B2R2CLK_MGT_REG 0x80157078 /** B2R2 clock selection */
+
+#include <mach/mcde-base.h>
+
+#ifndef __ASSEMBLY__
+
+#include <asm/cputype.h>
+
+/* TODO: dynamic detection */
+static inline bool cpu_is_u8500(void)
+{
+#ifdef CONFIG_UX500_SOC_DB8500
+ return 1;
+#else
+ return 0;
+#endif
+}
+
+static inline bool cpu_is_u8500ed(void)
+{
+#ifdef CONFIG_MACH_U8500_SIMULATOR
+ /*
+ * SVP8500v1 unfortunately does not implement the changed MIDR register
+ * on v1, but instead maintains the old ED revision.
+ *
+ * So we hardcode this assuming that only SVP8500v1 is supported. If
+ * SVP8500ed is required, another Kconfig option will have to be added.
+ */
+ return 0;
+#else
+ return cpu_is_u8500() && ((read_cpuid_id() & 15) == 0);
+#endif
+}
+
+static inline bool cpu_is_u8500v1(void)
+{
+#ifdef CONFIG_MACH_U8500_SIMULATOR
+ /* See comment in cpu_is_u8500ed() */
+ return cpu_is_u8500();
+#else
+ return cpu_is_u8500() && ((read_cpuid_id() & 15) == 1);
+#endif
+}
+
+static inline bool cpu_is_u5500(void)
+{
+#ifdef CONFIG_UX500_SOC_DB5500
+ return 1;
+#else
+ return 0;
+#endif
+}
+
+/* Deprecated, don't use in new code. Just call cpu_is_u8500ed() directly. */
+static inline int u8500_is_earlydrop(void)
+{
+ return cpu_is_u8500ed();
+}
+
+#endif
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-ux500/include/mach/hcl_defs.h b/arch/arm/mach-ux500/include/mach/hcl_defs.h
new file mode 100755
index 00000000000..ce8ac33618f
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/hcl_defs.h
@@ -0,0 +1,252 @@
+/*
+ * Copyright (C) 2009 ST Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _HCL_DEFS_H
+#define _HCL_DEFS_H
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+//#include "platform_os.h"
+
+/*-----------------------------------------------------------------------------
+ * Type definition
+ *---------------------------------------------------------------------------*/
+typedef unsigned char t_uint8;
+typedef signed char t_sint8;
+typedef unsigned short t_uint16;
+typedef signed short t_sint16;
+typedef unsigned long t_uint32;
+typedef signed long t_sint32;
+
+typedef unsigned int t_bitfield;
+
+
+
+#if !defined(FALSE) && !defined(TRUE)
+typedef int t_bool;
+#define FALSE 0
+#define TRUE 1
+#endif
+
+/*
+ * Definition of the different kind of addresses manipulated into a system with MMU
+ * (handle physical AND logical addresses)
+ */
+
+
+typedef t_uint32 t_physical_address;
+typedef t_uint32 t_logical_address;
+
+
+
+/*
+ * Global frequency enumuration
+ * Added to avoid frequency conversion function which is required to convert one HCL
+ * frequency enumuration values to another HCL frequency enumuration values.
+ */
+
+/*typedef enum {
+ HCL_FREQ_NOT_SUPPORTED=-1,
+ HCL_FREQ_8KHZ ,
+ HCL_FREQ_11_25KHZ,
+ HCL_FREQ_12KHZ,
+ HCL_FREQ_16KHZ,
+ HCL_FREQ_22_05KHZ,
+ HCL_FREQ_22_5KHZ,
+ HCL_FREQ_24KHZ,
+ HCL_FREQ_32KHZ,
+ HCL_FREQ_44KHZ,
+ HCL_FREQ_44_1KHZ,
+ HCL_FREQ_48KHZ,
+ HCL_FREQ_64KHZ,
+ HCL_FREQ_88KHZ,
+ HCL_FREQ_88_2KHZ,
+ HCL_FREQ_96KHZ,
+ HCL_FREQ_128KHZ,
+ HCL_FREQ_176_4KHZ,
+ HCL_FREQ_192KHZ,
+
+ HCL_FREQ_1MHZ,
+ HCL_FREQ_2MHZ,
+ HCL_FREQ_3MHZ,
+ HCL_FREQ_4MHZ,
+ HCL_FREQ_5MHZ,
+ HCL_FREQ_6MHZ,
+ HCL_FREQ_8MHZ,
+ HCL_FREQ_11MHZ,
+ HCL_FREQ_12MHZ,
+ HCL_FREQ_16MHZ,
+ HCL_FREQ_22MHZ,
+ HCL_FREQ_24MHZ,
+ HCL_FREQ_48MHZ
+} t_frequency;
+
+*/
+
+typedef struct {
+ t_physical_address physical;
+ t_logical_address logical;
+} t_system_address;
+
+
+/*
+ * Define a type used to manipulate size of various buffers
+ */
+typedef t_uint32 t_size;
+
+typedef struct {
+ t_bitfield minor:8;
+ t_bitfield major:8;
+ t_bitfield version:16;
+} t_version;
+
+
+
+
+/*-----------------------------------------------------------------------------
+ * Keyword definition
+ *---------------------------------------------------------------------------*/
+#define PUBLIC /* Extern by default */
+#define PRIVATE static
+
+#ifndef NULL
+#define NULL (0)
+#endif /* ndef NULL */
+
+
+/*-----------------------------------------------------------------------------
+ * Bit setting or clearing
+ *---------------------------------------------------------------------------*/
+#define HCL_SET_BITS(reg,mask) ((reg) |= (mask))
+#define HCL_CLEAR_BITS(reg,mask) ((reg) &= ~(mask))
+#define HCL_READ_BITS(reg,mask) ((reg) & (mask))
+#define HCL_WRITE_BITS(reg,val,mask) ((reg) = (((reg) & ~(mask)) | ((val) & (mask))))
+#define HCL_READ_REG(reg) (reg)
+#define HCL_WRITE_REG(reg,val) ((reg) = (val))
+
+/*-----------------------------------------------------------------------------
+ * field offset extraction from a structure
+ *---------------------------------------------------------------------------*/
+#define HCL_BITFIELD_OFFSET(typeName, fieldName) (t_uint32)(&(((typeName *)0)->fieldName))
+
+/*-----------------------------------------------------------------------------
+ * Bit mask definition
+ *---------------------------------------------------------------------------*/
+#define MASK_NULL8 0x00
+#define MASK_NULL16 0x0000
+#define MASK_NULL32 0x00000000
+#define MASK_ALL8 0xFF
+#define MASK_ALL16 0xFFFF
+#define MASK_ALL32 0xFFFFFFFF
+
+#define MASK_BIT0 (1UL<<0)
+#define MASK_BIT1 (1UL<<1)
+#define MASK_BIT2 (1UL<<2)
+#define MASK_BIT3 (1UL<<3)
+#define MASK_BIT4 (1UL<<4)
+#define MASK_BIT5 (1UL<<5)
+#define MASK_BIT6 (1UL<<6)
+#define MASK_BIT7 (1UL<<7)
+#define MASK_BIT8 (1UL<<8)
+#define MASK_BIT9 (1UL<<9)
+#define MASK_BIT10 (1UL<<10)
+#define MASK_BIT11 (1UL<<11)
+#define MASK_BIT12 (1UL<<12)
+#define MASK_BIT13 (1UL<<13)
+#define MASK_BIT14 (1UL<<14)
+#define MASK_BIT15 (1UL<<15)
+#define MASK_BIT16 (1UL<<16)
+#define MASK_BIT17 (1UL<<17)
+#define MASK_BIT18 (1UL<<18)
+#define MASK_BIT19 (1UL<<19)
+#define MASK_BIT20 (1UL<<20)
+#define MASK_BIT21 (1UL<<21)
+#define MASK_BIT22 (1UL<<22)
+#define MASK_BIT23 (1UL<<23)
+#define MASK_BIT24 (1UL<<24)
+#define MASK_BIT25 (1UL<<25)
+#define MASK_BIT26 (1UL<<26)
+#define MASK_BIT27 (1UL<<27)
+#define MASK_BIT28 (1UL<<28)
+#define MASK_BIT29 (1UL<<29)
+#define MASK_BIT30 (1UL<<30)
+#define MASK_BIT31 (1UL<<31)
+
+/*-----------------------------------------------------------------------------
+ * quartet shift definition
+ *---------------------------------------------------------------------------*/
+#define MASK_QUARTET (0xFUL)
+#define SHIFT_QUARTET0 0
+#define SHIFT_QUARTET1 4
+#define SHIFT_QUARTET2 8
+#define SHIFT_QUARTET3 12
+#define SHIFT_QUARTET4 16
+#define SHIFT_QUARTET5 20
+#define SHIFT_QUARTET6 24
+#define SHIFT_QUARTET7 28
+#define MASK_QUARTET0 (MASK_QUARTET << SHIFT_QUARTET0)
+#define MASK_QUARTET1 (MASK_QUARTET << SHIFT_QUARTET1)
+#define MASK_QUARTET2 (MASK_QUARTET << SHIFT_QUARTET2)
+#define MASK_QUARTET3 (MASK_QUARTET << SHIFT_QUARTET3)
+#define MASK_QUARTET4 (MASK_QUARTET << SHIFT_QUARTET4)
+#define MASK_QUARTET5 (MASK_QUARTET << SHIFT_QUARTET5)
+#define MASK_QUARTET6 (MASK_QUARTET << SHIFT_QUARTET6)
+#define MASK_QUARTET7 (MASK_QUARTET << SHIFT_QUARTET7)
+
+/*-----------------------------------------------------------------------------
+ * Byte shift definition
+ *---------------------------------------------------------------------------*/
+#define MASK_BYTE (0xFFUL)
+#define SHIFT_BYTE0 0
+#define SHIFT_BYTE1 8
+#define SHIFT_BYTE2 16
+#define SHIFT_BYTE3 24
+#define MASK_BYTE0 (MASK_BYTE << SHIFT_BYTE0)
+#define MASK_BYTE1 (MASK_BYTE << SHIFT_BYTE1)
+#define MASK_BYTE2 (MASK_BYTE << SHIFT_BYTE2)
+#define MASK_BYTE3 (MASK_BYTE << SHIFT_BYTE3)
+
+/*-----------------------------------------------------------------------------
+ * Halfword shift definition
+ *---------------------------------------------------------------------------*/
+#define MASK_HALFWORD (0xFFFFUL)
+#define SHIFT_HALFWORD0 0
+#define SHIFT_HALFWORD1 16
+#define MASK_HALFWORD0 (MASK_HALFWORD << SHIFT_HALFWORD0)
+#define MASK_HALFWORD1 (MASK_HALFWORD << SHIFT_HALFWORD1)
+
+/*-----------------------------------------------------------------------------
+ * Global constants definition
+ *---------------------------------------------------------------------------*/
+ #define ONE_KB (1024)
+ #define ONE_MB (ONE_KB * ONE_KB)
+
+
+/*-----------------------------------------------------------------------------
+ * Address translation macros declaration
+ *---------------------------------------------------------------------------*/
+
+#define ARM_TO_AHB_ADDR(addr) (addr)
+#define AHB_TO_ARM_ADDR(addr) (addr)
+
+/* For input parameters - would not be changed by the API */
+#define IN
+/* For output parameters - would be changes by the API */
+#define OUT
+/* For input-output parameters - provides input to the API but would be changed by the API */
+#define INOUT
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HCL_DEFS_H */
+
+/* End of file hcl_defs.h */
+
+
diff --git a/arch/arm/mach-ux500/include/mach/hsi-stm.h b/arch/arm/mach-ux500/include/mach/hsi-stm.h
new file mode 100755
index 00000000000..3d1ac521ee1
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/hsi-stm.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2007 STMicroelectronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __HSI_STM_H__
+#define __HSI_STM_H__
+
+#define HSI_DRIVER_AUTHOR "STMicroelectronics"
+#define HSI_DRIVER_DESC "High-Speed Synchronous Serial Interface Driver"
+
+#define DRIVER_NAME "DRIVER HSI"
+/* enables/disables debug msgs */
+#define DRIVER_DEBUG 0
+/* msg header represents this module */
+#define DRIVER_DEBUG_PFX DRIVER_NAME
+#define DRIVER_DBG KERN_ERR
+
+#define HSI_DRIVER_NAME "hsi_driver"
+
+#define HSI_DEVICE_NAME "hsi_device"
+#define HSI_TX_PREFIX "hsi_tx:"
+#define HSI_RX_PREFIX "hsi_rx:"
+#define HSI_PREFIX "hsi:"
+/** HSIT register offsets */
+#define HSI_TX_ID 0x0
+#define HSI_TX_MODE 0x4
+#define HSI_TX_STATE 0x8
+#define HSI_TX_IOSTATE 0xC
+#define HSI_TX_BUFSTATE 0x10
+#define HSI_TX_DIVISOR 0x14
+#define HSI_TX_PARITY 0x18
+#define HSI_TX_BREAK 0x1C
+#define HSI_TX_CHANNELS 0x20
+#define HSI_TX_FLUSHBITS 0x24
+#define HSI_TX_PRIORITY 0x28
+#define HSI_TX_BURSTLEN 0x2C
+#define HSI_TX_PREAMBLE 0x30
+#define HSI_TX_DATASWAP 0x34
+#define HSI_TX_FRAMELENX 0x80
+#define HSI_TX_BUFFERX 0xC0
+#define HSI_TX_BASEX 0x100
+#define HSI_TX_SPANX 0x140
+#define HSI_TX_GAUGEX 0x180
+#define HSI_TX_WATERMARKX 0x1C0
+#define HSI_TX_DMAEN 0x200
+#define HSI_TX_WATERMARKIS 0x204
+#define HSI_TX_WATERMARKIM 0x208
+#define HSI_TX_WATERMARKIC 0x20C
+#define HSI_TX_WATERMARKID 0x210
+#define HSI_TX_PERIPHID0 0xFE0
+#define HSI_TX_PERIPHID1 0xFE4
+#define HSI_TX_PERIPHID2 0xFE8
+#define HSI_TX_PERIPHID3 0xFEC
+
+
+/** HSIT register offsets */
+#define HSI_RX_ID 0x0
+#define HSI_RX_MODE 0x4
+#define HSI_RX_STATE 0x8
+#define HSI_RX_BUFSTATE 0xC
+#define HSI_RX_THRESHOLD 0x10
+#define HSI_RX_PARITY 0x14
+#define HSI_RX_DETECTOR 0x18
+#define HSI_RX_EXCEP 0x1C
+#define HSI_RX_ACK 0x20
+#define HSI_RX_CHANNELS 0x24
+#define HSI_RX_REALTIME 0x28
+#define HSI_RX_OVERRUN 0x2C
+#define HSI_RX_OVERRUNACK 0x30
+#define HSI_RX_PREAMBLE 0x34
+#define HSI_RX_PIPEGAUGE 0x38
+#define HSI_RX_TIMEOUT 0x3C
+#define HSI_RX_BUFFERX 0x80
+#define HSI_RX_FRAMELENX 0xC0
+#define HSI_RX_BASEX 0x100
+#define HSI_RX_SPANX 0x140
+#define HSI_RX_GAUGEX 0x180
+#define HSI_RX_WATERMARKX 0x1C0
+#define HSI_RX_DMAEN 0x200
+#define HSI_RX_WATERMARKIS 0x204
+#define HSI_RX_WATERMARKIM 0x208
+#define HSI_RX_WATERMARKIC 0x20C
+#define HSI_RX_WATERMARKID 0x210
+#define HSI_RX_OVERRUNMIS 0x214
+#define HSI_RX_OVERRUNIM 0x218
+#define HSI_RX_EXCEPMIS 0x21C
+#define HSI_RX_EXCEPIM 0x220
+#define HSI_RX_PERIPHID0 0xFE0
+#define HSI_RX_PERIPHID1 0xFE4
+#define HSI_RX_PERIPHID2 0xFE8
+#define HSI_RX_PERIPHID3 0xFEC
+
+/*
+ * Masks used to enable or disable the reception of certain hardware events
+ * for the hsi_device_drivers
+ */
+#define HSI_EVENT_CLEAR 0x00
+#define HSI_EVENT_MASK 0xFF
+#define HSI_EVENT_BREAK_DETECTED_MASK 0x01
+#define HSI_EVENT_ERROR_MASK 0x02
+
+#define HSI_CH_OPEN 0x1
+
+#define ANY_HSI_CONTROLLER -1
+#define ANY_CHANNEL -1
+#define CHANNEL(channel) (1<<channel)
+
+
+#define HSI_MAX_FRAMELEN 32
+#define PLAT_HSI_MAX_CHANNELS 8
+
+struct base_span {
+ u8 base;
+ u8 span;
+};
+
+struct hsi_plat_data {
+ u8 dev_type;
+ u8 mode;
+ u8 parity;
+ u8 priority;
+ u8 channels;
+ u8 threshold;
+ u8 flushbits;
+ u8 dataswap;
+ u8 realtime;
+ u8 detector;
+ u8 framelen;
+ u8 watermark;
+ u8 currmode;
+ gpio_alt_function gpio_alt_func;
+ u32 divisor;
+ u32 burstlen;
+ u32 preamble;
+ u32 timeout;
+ struct base_span ch_base_span[PLAT_HSI_MAX_CHANNELS];
+ struct stm_dma_pipe_info hsi_dma_info[PLAT_HSI_MAX_CHANNELS];
+ struct hsi_controller *controller;
+};
+
+struct hsi_algorithm;
+extern struct hsi_algorithm hsi_algo;
+int hsi_read_interrupt_mode(struct hsi_channel *chnl);
+int hsi_write_interrupt_mode(struct hsi_channel *chnl);
+void hsi_cancel_write_interrupt_mode(struct hsi_channel *chnl);
+void hsi_cancel_read_interrupt_mode(struct hsi_channel *chnl);
+
+irqreturn_t hsi_tx_irq_handler(int irq, void *ctrlr);
+irqreturn_t hsi_rx_irq_handler(int irq, void *ctrlr);
+irqreturn_t hsi_rxexcep_irq_handler(int irq, void *ctrlr);
+
+void do_hsi_tx_tasklet(unsigned long ctrlr);
+void do_hsi_rx_tasklet(unsigned long ctrlr);
+void do_hsi_tx_dma_tasklet(unsigned long ctrlr);
+void do_hsi_rx_dma_tasklet(unsigned long ctrlr);
+void do_hsi_rxexcep_tasklet(unsigned long ctrlr);
+void hsi_u8_writer(struct hsi_channel *ch);
+void hsi_u8_reader(struct hsi_channel *ch);
+void hsi_u16_writer(struct hsi_channel *ch);
+void hsi_u16_reader(struct hsi_channel *ch);
+void hsi_u32_writer(struct hsi_channel *ch);
+void hsi_u32_reader(struct hsi_channel *ch);
+void hsi_dma_read_eot_handler(void *data);
+void hsi_dma_write_eot_handler(void *data);
+
+void hsi_cancel_write_dma_mode(struct hsi_channel *chnl);
+void hsi_cancel_read_dma_mode(struct hsi_channel *chnl);
+/*DMA Functions*/
+int hsi_read_dma_mode(struct hsi_channel *chnl);
+int hsi_write_dma_mode(struct hsi_channel *chnl);
+
+#endif /* __HSI_STM_H__ */
diff --git a/arch/arm/mach-ux500/include/mach/i2c-stm.h b/arch/arm/mach-ux500/include/mach/i2c-stm.h
new file mode 100755
index 00000000000..f211cfe9118
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/i2c-stm.h
@@ -0,0 +1,404 @@
+/*
+ * arch/arm/mach-stn8500/include/mach/i2c-stm.h
+ *
+ * Copyright (C) 2009 STMicroelectronics Pvt. Ltd.
+ *
+ * Author: Sachin Verma <sachin.verma@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef STM_I2C_HEADER
+#define STM_I2C_HEADER
+#include <linux/i2c.h>
+
+/*
+ * I2C Controller register offsets
+ */
+#define I2C_CR(r) (r + 0x000)
+#define I2C_SCR(r) (r + 0x004)
+#define I2C_HSMCR(r) (r + 0x008)
+#define I2C_MCR(r) (r + 0x00C)
+#define I2C_TFR(r) (r + 0x010)
+#define I2C_SR(r) (r + 0x014)
+#define I2C_RFR(r) (r + 0x018)
+#define I2C_TFTR(r) (r + 0x01C)
+#define I2C_RFTR(r) (r + 0x020)
+#define I2C_DMAR(r) (r + 0x024)
+#define I2C_BRCR(r) (r + 0x028)
+#define I2C_IMSCR(r) (r + 0x02C)
+#define I2C_RISR(r) (r + 0x030)
+#define I2C_MISR(r) (r + 0x034)
+#define I2C_ICR(r) (r + 0x038)
+#define I2C_THD_FST_STD(r) (r + 0x050)
+#define I2C_THU_FST_STD(r) (r + 0x058)
+
+
+/*
+ * I2C :: Controller Register
+ */
+#define I2C_CR_PE_POS 0
+#define I2C_CR_OM_POS 1
+#define I2C_CR_SAM_POS 3
+#define I2C_CR_SM_POS 4
+#define I2C_CR_SGCM_POS 6
+#define I2C_CR_FTX_POS 7
+#define I2C_CR_FRX_POS 8
+#define I2C_CR_DMA_TX_EN_POS 9
+#define I2C_CR_DMA_RX_EN_POS 10
+#define I2C_CR_DMA_SLE_POS 11
+#define I2C_CR_LM_POS 12
+#define I2C_CR_FON_POS 13
+#define I2C_CR_FS_POS 15
+
+#define I2C_CR_PE ((u32)(0x1UL << I2C_CR_PE_POS))
+#define I2C_CR_OM ((u32)(0x3UL << I2C_CR_OM_POS))
+#define I2C_CR_SAM ((u32)(0x1UL << I2C_CR_SAM_POS))
+#define I2C_CR_SM ((u32)(0x3UL << I2C_CR_SM_POS))
+#define I2C_CR_SGCM ((u32)(0x1UL << I2C_CR_SGCM_POS))
+#define I2C_CR_FTX ((u32)(0x1UL << I2C_CR_FTX_POS))
+#define I2C_CR_FRX ((u32)(0x1UL << I2C_CR_FRX_POS))
+#define I2C_CR_DMA_TX_EN ((u32)(0x1UL << I2C_CR_DMA_TX_EN_POS))
+#define I2C_CR_DMA_RX_EN ((u32)(0x1UL << I2C_CR_DMA_RX_EN_POS))
+#define I2C_CR_DMA_SLE ((u32)(0x1UL << I2C_CR_DMA_SLE_POS))
+#define I2C_CR_LM ((u32)(0x1UL << I2C_CR_LM_POS))
+#define I2C_CR_FON ((u32)(0x3UL << I2C_CR_FON_POS))
+#define I2C_CR_FS ((u32)(0x3UL << I2C_CR_FS_POS))
+
+/*
+ * I2C :: Slave Controller Register
+ */
+#define I2C_SCR_SLAVE_ADDR7BIT ((u32)(0x7FUL << 0))
+#define I2C_SCR_ESA10 ((u32)(0x7UL << 7))
+#define I2C_SCR_DATA_SETUP_TIME ((u32)(0xFFFFUL << 16))
+
+/*
+ * I2C :: Master Controller Register
+ */
+#define I2C_MCR_OP_POS 0
+#define I2C_MCR_A7_POS 1
+#define I2C_MCR_EA10_POS 8
+#define I2C_MCR_SB_POS 11
+#define I2C_MCR_AM_POS 12
+#define I2C_MCR_STOP_POS 14
+#define I2C_MCR_LENGTH_POS 15
+
+#define I2C_MCR_OP ((u32)(0x1UL << I2C_MCR_OP_POS))
+#define I2C_MCR_A7 ((u32)(0x7FUL << I2C_MCR_A7_POS))
+#define I2C_MCR_EA10 ((u32)(0x7UL << I2C_MCR_EA10_POS))
+#define I2C_MCR_SB ((u32)(0x1UL << I2C_MCR_SB_POS))
+#define I2C_MCR_AM ((u32)(0x3UL << I2C_MCR_AM_POS))
+#define I2C_MCR_STOP ((u32)(0x1UL << I2C_MCR_STOP_POS))
+#define I2C_MCR_LENGTH ((u32)(0x7FFUL << I2C_MCR_LENGTH_POS))
+
+/*
+ *Transmit FIFO Register
+ */
+#define I2C_TFR_TDATA ((u32)(0xFFUL << 0))
+
+/*
+ *Status Register
+ */
+#define I2C_SR_OP ((u32)(0x3UL << 0))
+#define I2C_SR_STATUS ((u32)(0x3UL << 2))
+#define I2C_SR_CAUSE ((u32)(0x7UL << 4))
+#define I2C_SR_TYPE ((u32)(0x3UL << 7))
+#define I2C_SR_LENGTH ((u32)(0x7FFUL << 9))
+
+/*
+ *Receive FIFO Register
+ */
+#define I2C_RFR_RDATA ((u32)(0xFFUL << 0))
+
+/*
+ *Transmit FIFO Threshhold register
+ */
+#define I2C_TFTR_THRESHOLD_TX ((u32)(0x3FFUL << 0))
+
+/*
+ *Receive FIFO Threshhold register
+ */
+#define I2C_RFTR_THRESHOLD_RX ((u32)(0x3FFUL << 0))
+
+/*
+ *BaudRate Control Register
+ */
+#define I2C_BRCR_BRCNT2 0x0000FFFF
+#define I2C_BRCR_BRCNT1 0xFFFF0000
+
+/*
+ *Interrupt bits in I2C_IMSCR, I2C_ICR, I2C_RIS
+ */
+#define I2C_IT_TXFE ((u32)(0x1UL << 0))
+#define I2C_IT_TXFNE ((u32)(0x1UL << 1))
+#define I2C_IT_TXFF ((u32)(0x1UL << 2))
+#define I2C_IT_TXFOVR ((u32)(0x1UL << 3))
+#define I2C_IT_RXFE ((u32)(0x1UL << 4))
+#define I2C_IT_RXFNF ((u32)(0x1UL << 5))
+#define I2C_IT_RXFF ((u32)(0x1UL << 6))
+#define I2C_IT_RFSR ((u32)(0x1UL << 16))
+#define I2C_IT_RFSE ((u32)(0x1UL << 17))
+#define I2C_IT_WTSR ((u32)(0x1UL << 18))
+#define I2C_IT_MTD ((u32)(0x1UL << 19))
+#define I2C_IT_STD ((u32)(0x1UL << 20))
+#define I2C_IT_MAL ((u32)(0x1UL << 24))
+#define I2C_IT_BERR ((u32)(0x1UL << 25))
+#define I2C_IT_MTDWS ((u32)(0x1UL << 28))
+
+
+#define I2C_IRQ_SRC_ALL 0x131F007F
+
+/**************************************************************/
+#define I2C_TEST_BIT(reg_name, val) (readl(reg_name) & (val))
+#define NUM_I2C_ADAPTERS 4
+
+
+#define MAX_I2C_FIFO_THRESHOLD 15
+
+
+typedef enum {
+ I2C_NO_OPERATION = 0xFF,
+ I2C_WRITE = 0x00,
+ I2C_READ = 0x01
+} i2c_operation_t;
+
+
+typedef enum {
+ I2C_DIGITAL_FILTERS_OFF,
+ I2C_DIGITAL_FILTERS_1_CLK_SPIKES,
+ I2C_DIGITAL_FILTERS_2_CLK_SPIKES,
+ I2C_DIGITAL_FILTERS_4_CLK_SPIKES
+} i2c_digital_filter_t;
+
+typedef enum {
+ I2C_DISABLED,
+ I2C_ENABLED
+} i2c_control_t;
+
+typedef enum {
+ I2C_FREQ_MODE_STANDARD, /* Standard mode. */
+ I2C_FREQ_MODE_FAST, /* Fast mode. */
+ I2C_FREQ_MODE_HIGH_SPEED
+} i2c_freq_mode_t;
+
+typedef enum {
+ I2C_BUS_SLAVE_MODE = 0, /* Slave Mode */
+ I2C_BUS_MASTER_MODE, /* Master Mode */
+ I2C_BUS_MASTER_SLAVE_MODE /* Dual Configuration Mode */
+} i2c_bus_control_mode_t;
+
+typedef enum {
+ I2C_NO_GENERAL_CALL_HANDLING,
+ I2C_SOFTWARE_GENERAL_CALL_HANDLING,
+ I2C_HARDWARE_GENERAL_CALL_HANDLING
+} i2c_general_call_handling_t;
+
+typedef enum {
+ I2C_TRANSFER_MODE_POLLING,
+ I2C_TRANSFER_MODE_INTERRUPT,
+ I2C_TRANSFER_MODE_DMA
+} i2c_transfer_mode_t;
+
+typedef enum {
+ I2C_7_BIT_ADDRESS = 0x1,
+ I2C_10_BIT_ADDRESS = 0x2
+} i2c_addr_t;
+
+typedef enum {
+ I2C_NO_INDEX, /* Current transfer is non-indexed */
+ I2C_BYTE_INDEX, /* Current transfer uses 8-bit index */
+ I2C_HALF_WORD_LITTLE_ENDIAN, /* Current transfer uses 16-bit index
+ in little endian mode */
+ I2C_HALF_WORD_BIG_ENDIAN, /* Current transfer uses 16-bit index
+ in big endian mode */
+ I2C_INVALID_INDEX = -1
+} i2c_index_format_t;
+
+typedef enum{
+ I2C_NOP,
+ I2C_ON_GOING,
+ I2C_OK,
+ I2C_ABORT
+} i2c_status_t;
+
+typedef enum {
+ I2C_NACK_ADDR,
+ I2C_NACK_DATA,
+ I2C_ACK_MCODE,
+ I2C_ARB_LOST,
+ I2C_BERR_START,
+ I2C_BERR_STOP,
+ I2C_OVFL
+} i2c_error_t;
+
+/**
+ * struct i2c_platform_data - Platform Data structure for I2C controller
+ * @gpio_alt_func: Gpio Alternate function used by this controller
+ * @name: Name of this I2C controller
+ * @own_addr: Own address of this I2C controller on the i2c bus
+ * @mode: Freq mode in which this controller will operate(std, fast, highspeed)
+ * @clk_freq: Frequenct at which SCL line is driven (e.g. 100 KHz)
+ * @slave_addressing_mode: seven or 10 bit addressing
+ * @digital_filter_control: Digital Filters to be applied
+ * @dma_sync_logic_control: Enabled/Disaled
+ * @start_byte_procedure: Enabled/Disabled
+ * @slave_data_setup_time: Data setup time for slave
+ * @bus_control_mode: Whether slave or master
+ * @i2c_loopback_mode: If true controller works in Loopback mode
+ * @xfer_mode: Polling/Interrupt/DMA mode
+ * @high_speed_master_code: Code for high speed master mode
+ * @i2c_tx_int_threshold: Interrupt Tx threshold
+ * @i2c_rx_int_threshold: Interrupt Rx Threshold
+ *
+ **/
+struct i2c_platform_data {
+ gpio_alt_function gpio_alt_func;
+ char name[48];
+ u32 own_addr;
+ i2c_freq_mode_t mode;
+ u32 clk_freq;
+ i2c_addr_t slave_addressing_mode;
+ i2c_digital_filter_t digital_filter_control;
+ i2c_control_t dma_sync_logic_control;
+ i2c_control_t start_byte_procedure;
+ u16 slave_data_setup_time;
+ i2c_bus_control_mode_t bus_control_mode;
+ i2c_control_t i2c_loopback_mode;
+ i2c_transfer_mode_t xfer_mode;
+ u8 high_speed_master_code;
+ u8 i2c_tx_int_threshold;
+ u8 i2c_rx_int_threshold;
+};
+
+
+/**
+ * struct i2c_controller_config - Configuration stored by controller
+ * @own_addr: Controllers own address on the I2C bus
+ * @clk_freq: Frequency at which SCL line is Driven
+ * @digital_filter_control: Digital filter control to be applied
+ * @dma_sync_logic_control: Enabled/Disabled
+ * @start_byte_procedure: Enabled/Disabled
+ * @slave_data_setup_time: Slave set up time
+ * @slave_addressing_mode: seven or 10 bit addressing
+ * @high_speed_master_code: Code for high speed master mode
+ * @mode: Standard/fast/Highspeed mode
+ * @bus_control_mode: Master/Slave/Dual
+ * @i2c_loopback_mode: Loopback mode
+ * @general_call_mode_handling:
+ * @xfer_mode: Polling/Interrupt/DMA mode
+ * @i2c_transmit_interrupt_threshold: Tx interrupt threshold
+ * @i2c_receive_interrupt_threshold: Rx interrupt threshold
+ * @transmit_burst_length:
+ * @receive_burst_length:
+ * @burst_length:
+ *
+ **/
+struct i2c_controller_config {
+ u16 own_addr;
+ u32 clk_freq;
+ i2c_digital_filter_t digital_filter_control;
+ i2c_control_t dma_sync_logic_control;
+ i2c_control_t start_byte_procedure;
+ u16 slave_data_setup_time;
+ i2c_addr_t slave_addressing_mode;
+ u8 high_speed_master_code;
+ i2c_freq_mode_t mode;
+ i2c_bus_control_mode_t bus_control_mode;
+ i2c_control_t i2c_loopback_mode;
+ i2c_general_call_handling_t general_call_mode_handling;
+ i2c_transfer_mode_t xfer_mode;
+ u8 i2c_transmit_interrupt_threshold;
+ u8 i2c_receive_interrupt_threshold;
+ u8 transmit_burst_length;
+ u8 receive_burst_length;
+ u16 burst_length;
+};
+
+
+/**
+ * struct client_data - Holds Data specific to a client we are dealing with
+ * @slave_address: Address of the Slave I2C Chip
+ * @register_index: Index at which we wish to read data on this I2C slave chip
+ * @index_format: 8bit/16bit(big/Little endian) index
+ * @count_data: The number of bytes to be transferred.
+ * @databuffer: Pointer to the data buffer. Used in Multi operation.
+ * @transfer_data: Number of bytes transferred till now
+ * @operation: Read/Write
+ *
+ *
+ **/
+struct client_data {
+ u16 slave_address;
+ u16 register_index;
+ i2c_index_format_t index_format;
+ u32 count_data;
+ u8 *databuffer;
+ u32 transfer_data;
+ i2c_operation_t operation;
+};
+
+/**
+ * struct i2c_driver_data - Private data structure for the I2C Controller driver
+ * @id: Bus Id of this I2C controller
+ * @adap: reference to the I2C adapter structure
+ * @irq: IRQ line for this Controller
+ * @regs: I/O regs Memory Area of this controller
+ * @event_wq:
+ * @config: Controller configuration
+ * @cli_data: Data of the client transfer we are about to perform
+ * @stop: Whether we need a stop condition or not
+ * @xfer_complete: used for timeout in interrupt xfer.
+ *
+ *
+ **/
+struct i2c_driver_data {
+ struct i2c_adapter adap;
+ int irq;
+ void __iomem *regs;
+ struct clk *clk;
+ struct i2c_controller_config cfg;
+ struct client_data cli_data;
+ int stop;
+ int result;
+ struct completion xfer_complete;
+};
+
+#define I2C_FIFO_FLUSH_COUNTER 5000000
+#define I2C_STATUS_UPDATE_COUNTER 5000000
+
+#define I2C_SET_BIT(reg_name, mask) (writel(readl(reg_name) | mask, (reg_name)))
+#define I2C_CLR_BIT(reg_name, mask) (writel(readl(reg_name) & ~(mask), \
+ (reg_name)))
+
+#define I2C_ALGO_STM 0x15000000
+#define I2C_HW_STM 0x01
+#define I2C_DRIVERID_STM 0xF000
+#define WRITE_FIELD(reg_name, mask, shift, value) \
+ (reg_name = ((reg_name & ~mask) | (value << shift)))
+
+#define GEN_MASK(val, mask, sb) ((u32)((((u32)val)<<(sb)) & (mask)))
+
+#define STM_SET_BITS(reg, mask) ((reg) |= (mask))
+#define STM_CLEAR_BITS(reg, mask) ((reg) &= ~(mask))
+
+#define I2C_WRITE 0
+#define I2C_READ 1
+
+#define I2C_MCR_LENGTH_STOP_OP 0x3FFC001
+#define I2C_WRITE_FIELD(reg_name, mask, shift, value) \
+ (writel((readl(reg_name) & ~mask) | (value << shift), \
+ reg_name))
+
+#define DEFAULT_BRCNT_REG (GEN_MASK((__u32)(STD_F_IN_HZ/(STD_SPEED_IN_HZ*2)), \
+ I2C_BRCR_BRCNT2, 0)| \
+ GEN_MASK(0, I2C_BRCR_BRCNT1, 16))
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/io.h b/arch/arm/mach-ux500/include/mach/io.h
new file mode 100755
index 00000000000..50553776b39
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/io.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/io.h
+ *
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Modifications:
+ * 06-12-1997 RMK Created.
+ * 07-04-1999 RMK Major cleanup
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a) __typesafe_io(a)
+#define __mem_pci(a) (a)
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
new file mode 100755
index 00000000000..363cd443c18
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2008 ST Microelectronics
+ * Copyright (C) 2009 ST-Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef ASM_ARCH_IRQS_H
+#define ASM_ARCH_IRQS_H
+
+#include <mach/hardware.h>
+
+#define IRQ_LOCALTIMER 29
+#define IRQ_LOCALWDOG 30
+
+
+#define IRQ_SPI_START 32
+
+/* Interrupt numbers generic for shared peripheral */
+#define IRQ_MTU0 (IRQ_SPI_START + 4)
+#define IRQ_SPI2 (IRQ_SPI_START + 6)
+#define IRQ_SPI0 (IRQ_SPI_START + 8)
+#define IRQ_UART0 (IRQ_SPI_START + 11)
+#define IRQ_I2C3 (IRQ_SPI_START + 12)
+#define IRQ_SSP0 (IRQ_SPI_START + 14)
+#define IRQ_MTU1 (IRQ_SPI_START + 17)
+#define IRQ_RTC_RTT (IRQ_SPI_START + 18)
+#define IRQ_UART1 (IRQ_SPI_START + 19)
+#define IRQ_I2C0 (IRQ_SPI_START + 21)
+#define IRQ_I2C1 (IRQ_SPI_START + 22)
+#define IRQ_USBOTG (IRQ_SPI_START + 23)
+#define IRQ_DMA (IRQ_SPI_START + 25)
+#define IRQ_UART2 (IRQ_SPI_START + 26)
+#define IRQ_HSIR_EXCEP (IRQ_SPI_START + 29)
+#define IRQ_MSP0 (IRQ_SPI_START + 31)
+#define IRQ_HSIR_CH0_OVRRUN (IRQ_SPI_START + 32)
+#define IRQ_HSIR_CH1_OVRRUN (IRQ_SPI_START + 33)
+#define IRQ_HSIR_CH2_OVRRUN (IRQ_SPI_START + 34)
+#define IRQ_HSIR_CH3_OVRRUN (IRQ_SPI_START + 35)
+#define STW4500_IRQ (IRQ_SPI_START + 40)
+#define IRQ_SDMMC2 (IRQ_SPI_START + 41)
+#define IRQ_SIA_IT0 (IRQ_SPI_START + 42)
+#define IRQ_SIA_IT1 (IRQ_SPI_START + 43)
+#define IRQ_SVA_IT0 (IRQ_SPI_START + 44)
+#define IRQ_SVA_IT1 (IRQ_SPI_START + 45)
+#define IRQ_PRCM_ACK_MBOX (IRQ_SPI_START + 47)
+#define IRQ_DISP (IRQ_SPI_START + 48)
+#define IRQ_SPI3 (IRQ_SPI_START + 49)
+#define IRQ_SDMMC1 (IRQ_SPI_START + 50)
+#define IRQ_I2C4 (IRQ_SPI_START + 51)
+#define IRQ_SSP1 (IRQ_SPI_START + 52)
+#define IRQ_I2C2 (IRQ_SPI_START + 55)
+#define IRQ_SDMMC3 (IRQ_SPI_START + 59)
+#define IRQ_SDMMC0 (IRQ_SPI_START + 60)
+#define IRQ_HWSEM (IRQ_SPI_START + 61)
+#define IRQ_MSP1 (IRQ_SPI_START + 62)
+#define IRQ_SPI1 (IRQ_SPI_START + 96)
+#define IRQ_MSP2 (IRQ_SPI_START + 98)
+#define IRQ_SDMMC4 (IRQ_SPI_START + 99)
+#define IRQ_SDMMC5 (IRQ_SPI_START + 100)
+#define IRQ_HSIRD0 (IRQ_SPI_START + 104)
+#define IRQ_HSIRD1 (IRQ_SPI_START + 105)
+#define IRQ_HSITD0 (IRQ_SPI_START + 106)
+#define IRQ_HSITD1 (IRQ_SPI_START + 107)
+#define IRQ_GPIO0 (IRQ_SPI_START + 119)
+#define IRQ_GPIO1 (IRQ_SPI_START + 120)
+#define IRQ_GPIO2 (IRQ_SPI_START + 121)
+#define IRQ_GPIO3 (IRQ_SPI_START + 122)
+#define IRQ_GPIO4 (IRQ_SPI_START + 123)
+#define IRQ_GPIO5 (IRQ_SPI_START + 124)
+#define IRQ_GPIO6 (IRQ_SPI_START + 125)
+#define IRQ_GPIO7 (IRQ_SPI_START + 126)
+#define IRQ_GPIO8 (IRQ_SPI_START + 127)
+#define IRQ_B2R2 (IRQ_SPI_START + 56)
+
+#define IRQ_CA_WAKE_REQ_ED (IRQ_SPI_START + 71)
+#define IRQ_AC_READ_NOTIFICATION_0_ED (IRQ_SPI_START + 66)
+#define IRQ_AC_READ_NOTIFICATION_1_ED (IRQ_SPI_START + 64)
+#define IRQ_CA_MSG_PEND_NOTIFICATION_0_ED (IRQ_SPI_START + 67)
+#define IRQ_CA_MSG_PEND_NOTIFICATION_1_ED (IRQ_SPI_START + 65)
+
+#define IRQ_CA_WAKE_REQ_V1 (IRQ_SPI_START + 83)
+#define IRQ_AC_READ_NOTIFICATION_0_V1 (IRQ_SPI_START + 78)
+#define IRQ_AC_READ_NOTIFICATION_1_V1 (IRQ_SPI_START + 76)
+#define IRQ_CA_MSG_PEND_NOTIFICATION_0_V1 (IRQ_SPI_START + 79)
+#define IRQ_CA_MSG_PEND_NOTIFICATION_1_V1 (IRQ_SPI_START + 77)
+
+#define GPIO_TOTAL_PINS 267
+
+#define MAX_CHIP_IRQ 161
+#define MAX_GPIO_IRQ (MAX_CHIP_IRQ + GPIO_TOTAL_PINS)
+
+#ifndef NR_IRQS
+#define NR_IRQS (MAX_GPIO_IRQ + 1)
+#endif
+
+/* Macros to get irqno for GPIO pin and vice-versa*/
+#define IRQNO_GPIO(x) (MAX_CHIP_IRQ + x)
+#define GPIO_PIN_FOR_IRQ(x) (x - MAX_CHIP_IRQ)
+
+/* Macros to get irqno for DMA channels and vice-versa*/
+#define IRQNO_FOR_DMACH(x) (MAX_GPIO_IRQ + x)
+#define DMACH_FOR_IRQNO(x) (x - MAX_GPIO_IRQ)
+
+
+#endif /*ASM_ARCH_IRQS_H*/
+
diff --git a/arch/arm/mach-ux500/include/mach/isa_ioctl.h b/arch/arm/mach-ux500/include/mach/isa_ioctl.h
new file mode 100755
index 00000000000..b05726f8c3c
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/isa_ioctl.h
@@ -0,0 +1,51 @@
+/*---------------------------------------------------------------------------*/
+/* Copyright ST Ericsson, 2009. */
+/* This program is free software; you can redistribute it and/or modify it */
+/* under the terms of the GNU General Public License as published by the */
+/* Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. */
+/* See the GNU General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*---------------------------------------------------------------------------*/
+#ifndef __MODEM_IPC_INCLUDED
+#define __MODEM_IPC_INCLUDED
+
+#define DLP_IOCTL_MAGIC_NUMBER 'M'
+#define COMMON_BUFFER_SIZE (1024*1024)
+
+/**
+DLP Message Structure for Userland
+*/
+struct t_dlp_message{
+ unsigned int offset;
+ unsigned int size;
+};
+
+/**
+mmap constants.
+*/
+enum t_dlp_mmap_params {
+ MMAP_DLQUEUE,
+ MMAP_ULQUEUE
+};
+
+/**
+DLP IOCTLs for Userland
+*/
+#define DLP_IOC_ALLOCATE_BUFFER \
+ _IOWR(DLP_IOCTL_MAGIC_NUMBER, 0, struct t_dlp_message *)
+#define DLP_IOC_DEALLOCATE_BUFFER \
+ _IOWR(DLP_IOCTL_MAGIC_NUMBER, 1, struct t_dlp_message *)
+#define DLP_IOC_GET_MESSAGE \
+ _IOWR(DLP_IOCTL_MAGIC_NUMBER, 2, struct t_dlp_message *)
+#define DLP_IOC_PUT_MESSAGE \
+ _IOWR(DLP_IOCTL_MAGIC_NUMBER, 3, struct t_dlp_message *)
+
+#endif /*__MODEM_IPC_INCLUDED*/
+
diff --git a/arch/arm/mach-ux500/include/mach/kpd.h b/arch/arm/mach-ux500/include/mach/kpd.h
new file mode 100755
index 00000000000..eae65ea7f94
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/kpd.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright STMicroelectronics, 2009.
+ * Copyright (C) 2009 ST-Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ */
+
+#ifndef __U8500_KPD_H
+#define __U8500_KPD_H
+
+#ifndef CONFIG_AUTOSCAN_ENABLED
+#define CONFIG_AUTOSCAN_ENABLED 1
+#endif
+#include <mach/hardware.h>
+
+#define MAX_KPROW 8
+#define MAX_KPCOL 8
+/*keypad related Constants*/
+#define KEYPAD_RELEASE_PERIOD 11 /*110 Msec, repeate key scan time */
+#define KEYPAD_SCAN_PERIOD 4 /*40Msec for new keypress */
+#define KEYPAD_STATE_DEFAULT 0
+#define KEYPAD_STATE_PRESSED 1
+#define KEYPAD_STATE_PRESSACK 2
+#define KEYPAD_STATE_RELEASED 3
+#define KEYPAD_STATE_RELEASEACK 2
+
+#define KPINTR_LKBIT 0 /*bit used for interrupt locking */
+
+struct keypad_t;
+/**
+ * struct keypad_device -
+ * platform data for keypad driver
+ * @init: pointer to keypad init function
+ * @exit: pointer to keypad deinitialisation function
+ * @autoscan_check: pointer to read autoscan status function, not used
+ * currently
+ * @autoscan_disable: pointer to autoscan feature disable function,
+ * not used currently
+ * @autoscan_results: pointer to read autoscan results function
+ * @autoscan_en: pointer to enable autoscan feature function, not used
+ * currently
+ * @irqen: pointer to enable irq function
+ * @irqdis: pointer to disable irq function
+ * @kcode_tbl: lookup table for keycodes
+ * @krow: mask for available rows, value is 0xFF
+ * @kcol: mask for available columns, value is 0xFF
+ * @irqdis_int: pointer to disable irq function, to be called from ISR
+ * @debounce_period: platform specific debounce time, can be fine tuned later
+ * @irqtype: type of interrupt
+ * @irq: irq no,
+ * @int_status: interrupt status
+ * @int_line_behaviour: dynamis interrupt line behaviour
+ */
+struct keypad_device {
+ int (*init)(struct keypad_t *kp);
+ int (*exit)(struct keypad_t *kp);
+ int (*autoscan_check)(void);
+ void (*autoscan_disable)(void);
+ int (*autoscan_results)(struct keypad_t *kp);
+ void (*autoscan_en)(void);
+ int (*irqen)(struct keypad_t *kp);
+ int (*irqdis)(struct keypad_t *kp); /* normal disable */
+ u8 *kcode_tbl;
+ u8 krow;
+ u8 kcol;
+ int (*irqdis_int)(struct keypad_t *kp);
+ /* func used wen disable in interrupt handler */
+ u8 debounce_period;
+ unsigned long irqtype;
+ u8 irq; /*IRQ no*/
+ u8 int_status;
+ u8 int_line_behaviour;
+ bool enable_wakeup;
+};
+
+/**
+ * struct keypad_t - keypad data structure used internally by keypad driver
+ * @irq: irq no
+ * @mode: 0 for interrupt mode, 1 for polling mode
+ * @key_state: array for saving keystates
+ * @lockbits: used for synchronisation in ISR
+ * @inp_dev: pointer to input device object
+ * @address_for_data: not used
+ * @kscan_work: work queue
+ * @board: keypad platform device
+ */
+struct keypad_t {
+ int irq;
+ int mode;
+ int key_state[MAX_KPROW][MAX_KPCOL];
+ unsigned long lockbits;
+ struct input_dev *inp_dev;
+ void *address_for_data;
+ struct delayed_work kscan_work;
+ struct keypad_device *board;
+};
+/**
+ * enum kp_int_status - enum for INTR status
+ * @KP_INT_DISABLED: interrupt disabled
+ * @KP_INT_ENABLED: interrupt enabled
+ */
+enum kp_int_status {
+ KP_INT_DISABLED = 0,
+ KP_INT_ENABLED,
+};
+/**
+ *enum kp_int_line_behaviour - enum for kp_int_line dynamic status
+ * @INT_LINE_NOTSET: IRQ not asserted
+ * @INT_LINE_SET: IRQ asserted
+ */
+enum kp_int_line_behaviour {
+ INT_LINE_NOTSET = 0,
+ INT_LINE_SET,
+};
+#endif /*__U8500_KPD_H*/
diff --git a/arch/arm/mach-ux500/include/mach/mcde-base.h b/arch/arm/mach-ux500/include/mach/mcde-base.h
new file mode 100644
index 00000000000..c785fcac2de
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/mcde-base.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/* MCDE specific declaration */
+#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
+
+#define U8500_MCDE_REGISTER_BANK_SIZE 0x20
+#define U8500_MCDE_BASE_SIZE 0x200
+
+#define U8500_MCDE_EXTSRC_BASE (U8500_MCDE_BASE + U8500_MCDE_BASE_SIZE)
+#define U8500_MCDE_EXTSRC_SIZE (U8500_MCDE_REGISTER_BANK_SIZE * 0x10)
+
+#define U8500_MCDE_OVERLAY_BASE (U8500_MCDE_BASE + 0x400)
+#define U8500_MCDE_OVERLAY_SIZE (0x20 * 0x10)
+
+#define U8500_MCDE_CHANNELA_CONFIG_BASE (U8500_MCDE_BASE + 0x600) /* MCDE channel config registers */
+#define U8500_MCDE_CHANNELB_CONFIG_BASE (U8500_MCDE_BASE + 0x600) /* MCDE channel config registers */
+#define U8500_MCDE_CHANNELC0_CONFIG_BASE (U8500_MCDE_BASE + 0x600) /* MCDE channel config registers */
+#define U8500_MCDE_CHANNELC1_CONFIG_BASE (U8500_MCDE_BASE + 0x600) /* MCDE channel config registers */
+#define U8500_MCDE_CHANNEL_CONFIG_SIZE (0x20 * 0x10)
+
+#define U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE (U8500_MCDE_BASE + 0x800) /* MCDE channel A specific registers */
+#define U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_SIZE 0x200
+
+#define U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE (U8500_MCDE_BASE + 0xA00) /* MCDE channel B specific registers */
+#define U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_SIZE 0x200
+
+#define U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_BASE (U8500_MCDE_BASE + 0xC00) /* MCDE channel C0/C1 speicific registers */
+#define U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_SIZE 0xCB
+
+#define U8500_MCDE_DSI_CHANNEL_BASE (U8500_MCDE_BASE + 0xE00) /* MCDE channelC0 config registers */
+#define U8500_MCDE_DSI_CHANNEL_SIZE 0x20
+#define U8500_MCDE_DSI_SIZE 0xF4
+#define U8500_MCDE_DSI_CLOCK_OFFSET 0xF0 /* MCDE DSI clock */
+#define U8500_DSI_LINK1_BASE 0xA0351000
+#define U8500_DSI_LINK_SIZE 0x1000
+#define U8500_DSI_LINK_COUNT 0x3
+#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
+#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
+
+#define PRCM_HDMICLK_MGT_REG 0x80157058 /** HDMI clock selection */
+#define PRCM_MCDECLK_MGT_REG 0x80157064 /** MCDE clock selection */
+#define PRCM_TVCLK_MGT_REG 0x8015707c /** MCDE clock selection */
+
+#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
+
+#define U8500_MCDE_REGISTER_SIZE 0x20
+#define U8500_MCDE_EXTSRC_BASE 0xA0350200
+#define U8500_MCDE_EXTSRC_SIZE (0x20 * 0x10)
+#define U8500_MCDE_OVL_BASE 0xA0350400
+#define U8500_MCDE_OVL_SIZE (0x20 * 0x10)
+#define U8500_MCDE_CHANNELA_CONFIG_BASE 0xA0350600 /* MCDE channelA config registers */
+#define U8500_MCDE_CHANNEL_CONFIG_SIZE (0x20 * 0x10)
+#define U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE 0xA0350800 /* MCDE channelA specific registers */
+#define U8500_MCDE_CHANNEL_SPECIFIC_REGISTER_SIZE 0x80
+#define U8500_MCDE_CHANNELB_CONFIG_BASE 0xA0350600 /* MCDE channelA config registers */
+#define U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE 0xA0350A00 /* MCDE channelA specific registers */
+#define U8500_MCDE_CHANNELC0_CONFIG_BASE 0xA0350600 /* MCDE channelC0 config registers */
+#define U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE 0xA0350C00 /* MCDE channelC specific registers */
+#define U8500_MCDE_CHANNELC1_CONFIG_BASE 0xA0350600 /* MCDE channelC1 config registers */
+#define U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE 0xA0350C00 /* MCDE channelC specific registers */
+#define U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_SIZE 0xA8
+#define U8500_MCDE_DSI_CHANNEL_BASE 0xA0350E00 /* MCDE channelC0 config registers */
+#define U8500_MCDE_DSI_CHANNEL_SIZE 0x20
+#define U8500_MCDE_DSI_SIZE 0xF4
+#define U8500_MCDE_DSI_CLOCK_OFFSET 0xF0 /* MCDE DSI clock */
+#define U8500_DSI_LINK1_BASE 0xA0351000
+#define U8500_DSI_LINK_SIZE 0x1000
+#define U8500_DSI_LINK_COUNT 0x3
+#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
+#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
+
+#define PRCM_HDMICLK_MGT_REG 0x80157058 /** HDMI clock selection */
+#define PRCM_MCDECLK_MGT_REG 0x80157064 /** MCDE clock selection */
+#define PRCM_TVCLK_MGT_REG 0x8015707c /** MCDE clock selection */
+
+#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
+
diff --git a/arch/arm/mach-ux500/include/mach/mcde.h b/arch/arm/mach-ux500/include/mach/mcde.h
new file mode 100755
index 00000000000..9da3eab3018
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/mcde.h
@@ -0,0 +1,1381 @@
+/*---------------------------------------------------------------------------*/
+/* Copyright (C) STEricssoni 2009. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it */
+/* under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, */
+/* or (at your option)any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */
+/* the GNU Lesser General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*---------------------------------------------------------------------------*/
+
+#ifndef _MCDE_H_
+#define _MCDE_H_
+#include <linux/gpio.h>
+#include <linux/fb.h>
+#include <mach/mcde_ioctls.h>
+
+#ifdef __KERNEL__
+
+/*******************************************************************************
+ MCDE Control Enums and structures
+ ******************************************************************************/
+/* typedef enum
+{
+ MCDE_CH_A_LSB = 0x00,
+ MCDE_CH_A_MID = 0x01,
+ MCDE_CH_A_MSB = 0x02,
+ MCDE_CH_B_LSB = 0x03,
+ MCDE_CH_B_MID = 0x04,
+ MCDE_CH_B_MSB = 0x05,
+ MCDE_CH_C_LSB = 0x06
+}mcde_out_mux_cfg;
+
+typedef enum
+{
+ MCDE_CH_NORMAL_MODE = 0x0,
+ MCDE_CH_MUX_MODE = 0x1
+}mcde_ch_ctrl;
+*/
+ typedef enum
+ {
+ MCDE_CH_FIFO_A_ENABLE = 0x0,
+ MCDE_CH_FIFO_B_ENABLE = 0x1
+ }mcde_ch_fifo_ab_mux_ctrl;
+
+ typedef enum
+ {
+ MCDE_CH_FIFO_0_ENABLE = 0x0,
+ MCDE_CH_FIFO_1_ENABLE = 0x1
+ }mcde_ch_fifo_01_mux_ctrl;
+
+ typedef enum
+ {
+ MCDE_INPUT_FIFO_DISABLE = 0x0,
+ MCDE_INPUT_FIFO_ENABLE = 0x1
+ }mcde_input_fifo_ctrl;
+
+ typedef enum
+ {
+ MCDE_DPI_DISABLE = 0x0,
+ MCDE_DPI_ENABLE = 0x1
+ }mcde_dpi_ctrl;
+
+ typedef enum
+ {
+ MCDE_DBI_DISABLE = 0x0,
+ MCDE_DBI_ENABLE = 0x1
+ }mcde_dbi_ctrl;
+
+ typedef enum
+ {
+ MCDE_DSIVID_DISABLE = 0x0,
+ MCDE_DSIVID_ENABLE = 0x1
+ }mcde_dsivid_ctrl;
+
+ typedef enum
+ {
+ MCDE_DSICMD_DISABLE = 0x0,
+ MCDE_DSICMD_ENABLE = 0x1
+ }mcde_dsicmd_ctrl;
+
+ typedef enum
+ {
+ MCDE_WTRMRK_LEVEL_0,
+ MCDE_WTRMRK_LEVEL_1,
+ MCDE_WTRMRK_LEVEL_2,
+ MCDE_WTRMRK_LEVEL_3,
+ MCDE_WTRMRK_LEVEL_4,
+ MCDE_WTRMRK_LEVEL_5,
+ MCDE_WTRMRK_LEVEL_6,
+ MCDE_WTRMRK_LEVEL_7
+ }mcde_fifo_wrtmrk_level;
+ typedef enum
+ {
+ MCDE_CH_AB_FRAMESYNC_DPI = 0x0,
+ MCDE_CH_AB_FRAMESYNC_DBI = 0x1
+ }mcde_ch_ab_framesync_cfg;
+
+typedef enum
+{
+ MCDE_DISABLE = 0x0,
+ MCDE_ENABLE = 0x1
+}mcde_state;
+
+typedef enum
+{
+ MCDE_CH_A_OUTPUT_FIFO_B = 0x0,
+ MCDE_CH_A_OUTPUT_FIFO_C1 = 0x1
+ }mcde_fifo_sel_bc1_cfg;
+
+ typedef enum
+ {
+ MCDE_CH_A_OUTPUT_FIFO_A = 0x0,
+ MCDE_CH_A_OUTPUT_FIFO_C0 = 0x1
+ }mcde_fifo_sel_ac0_cfg;
+
+ typedef enum
+ {
+ MCDE_CH_B_PULSE_PANEL7 = 0x0,
+ MCDE_CH_C0C1_PULSE_PANEL = 0x1
+ }mcde_sync_mux7_cfg;
+
+ typedef enum
+ {
+ MCDE_CH_A_PULSE_PANEL = 0x0,
+ MCDE_CH_B_PULSE_PANEL6 = 0x1
+ }mcde_sync_mux6_cfg;
+
+ typedef enum
+ {
+ MCDE_CH_B_CLK_PANEL5 = 0x0,
+ MCDE_CH_C_CHIP_SELECT5 = 0x1
+ }mcde_sync_mux5_cfg;
+
+ typedef enum
+ {
+ MCDE_CH_A_CLK_PANEL4 = 0x0,
+ MCDE_CH_B_CLK_PANEL4 = 0x1
+ }mcde_sync_mux4_cfg;
+/*
+typedef enum
+{
+ MCDE_CHIPSELECT_C0 = 0x0,
+ MCDE_CHIPSELECT_C1 = 0x1
+}mcde_sync_mux23_cfg;
+
+typedef enum
+{
+ MCDE_CH_A_OUT_ENABLE = 0x0,
+ MCDE_CH_C_OUT_ENABLE = 0x1
+}mcde_sync_mux1_cfg;
+*/
+ typedef enum
+ {
+ MCDE_CH_A_CLK_PANEL0 = 0x0,
+ MCDE_CH_C_CHIP_SELECT0 = 0x1
+ }mcde_sync_mux0_cfg;
+/*
+struct mcde_config
+{
+ mcde_out_mux_cfg data_msb1;
+ mcde_out_mux_cfg data_msb0;
+ mcde_out_mux_cfg data_mid;
+ mcde_out_mux_cfg data_lsb1;
+ mcde_out_mux_cfg data_lsb0;
+ mcde_fifo_wrtmrk_level fifo_wtrmrk_level;
+ mcde_ch_ab_framesync_cfg ch_b_frame_sync_ctrl;
+ mcde_ch_ab_framesync_cfg ch_a_frame_sync_ctrl;
+ mcde_fifo_sel_bc1_cfg ch_b_fifo_sel;
+ mcde_fifo_sel_ac0_cfg ch_a_fifo_sel;
+ mcde_sync_mux7_cfg panel_mcdeblp;
+ mcde_sync_mux6_cfg panel_mcdeealp;
+ mcde_sync_mux4_cfg panel_mcdebcp;
+ mcde_sync_mux4_cfg panel_mcdeacp4;
+ mcde_sync_mux23_cfg panel_mcdeaspl;
+ mcde_sync_mux23_cfg panel_mcdeaps;
+ mcde_sync_mux1_cfg panel_mcdealp;
+ mcde_sync_mux0_cfg panel_mcdeacp;
+};*/
+ struct mcde_control
+ {
+ mcde_ch_fifo_ab_mux_ctrl ch_fifo_ab_mux;
+ mcde_ch_fifo_01_mux_ctrl ch_fifo_01_mux;
+ mcde_input_fifo_ctrl input_fifo_enable;
+ mcde_dpi_ctrl dpi_a_enable;
+ mcde_dpi_ctrl dpi_b_enable;
+ mcde_dbi_ctrl dbi_c0_enable;
+ mcde_dbi_ctrl dbi_c1_enable;
+ mcde_dsivid_ctrl dsi_vid0_enable;
+ mcde_dsivid_ctrl dsi_vid1_enable;
+ mcde_dsivid_ctrl dsi_vid2_enable;
+ mcde_dsicmd_ctrl dsi_cmd0_enable;
+ mcde_dsicmd_ctrl dsi_cmd1_enable;
+ mcde_dsicmd_ctrl dsi_cmd2_enable;
+ };
+/*
+struct mcde_ch_mode_ctrl
+{
+ mcde_ch_ctrl sync_ctrl_chA;
+ mcde_ch_ctrl sync_ctrl_chB;
+ mcde_ch_ctrl flow_ctrl_chA;
+ mcde_ch_ctrl flow_ctrl_chB;
+};
+*/
+ struct mcde_irq_status
+ {
+ u32 irq_status;
+ u32 event_status;
+ u8 is_new;
+ } ;
+/*
+typedef enum
+{
+ MCDE_EVENT_MASTER_BUS_ERROR = 0x01,
+ MCDE_EVENT_END_OF_FRAME_TRANSFER = 0x02,
+ MCDE_EVENT_SYNCHRO_CAPTURE_TRIGGER = 0x04,
+ MCDE_EVENT_HORIZONTAL_SYNCHRO_CAPTURE = 0x08,
+ MCDE_EVENT_VERTICAL_SYNCHRO_CAPTURE = 0x10
+} mcde_event_id;
+*/
+/* Check *********************************/
+
+typedef enum
+{
+ MCDE_CH_A_LSB = 0x00,
+ MCDE_CH_A_MID = 0x01,
+ MCDE_CH_A_MSB = 0x02,
+ MCDE_CH_B_LSB = 0x03,
+ MCDE_CH_B_MID = 0x04,
+ MCDE_CH_B_MSB = 0x05,
+ MCDE_CH_C_LSB = 0x06
+}mcde_out_mux_ctrl;
+
+typedef enum
+{
+ MCDE_FIFO_FA = 0x0,
+ MCDE_FIFO_FB = 0x1,
+ MCDE_FIFO_F0 = 0x2,
+ MCDE_FIFO_F1 = 0x3
+}mcde_fifo;
+
+typedef enum
+{
+ MCDE_DPI_A = 0x0,
+ MCDE_DPI_B = 0x1,
+ MCDE_DBI_C0 = 0x2,
+ MCDE_DBI_C1 = 0x3,
+ MCDE_DSI_VID0 = 0x4,
+ MCDE_DSI_VID1 = 0x5,
+ MCDE_DSI_VID2 = 0x6,
+ MCDE_DSI_CMD0 = 0x7,
+ MCDE_DSI_CMD1 = 0x8,
+ MCDE_DSI_CMD2 = 0x9
+}mcde_fifo_output;
+
+struct mcde_fifo_ctrl
+{
+ mcde_fifo_output out_fifoa;
+ mcde_fifo_output out_fifob;
+ mcde_fifo_output out_fifo0;
+ mcde_fifo_output out_fifo1;
+};
+
+typedef enum
+{
+ MCDE_CH_NORMAL_MODE = 0x0,
+ MCDE_CH_MUX_MODE = 0x1
+}mcde_ch_ctrl;
+
+typedef enum
+{
+ MCDE_CHIPSELECT_C0 = 0x0,
+ MCDE_CHIPSELECT_C1 = 0x1
+}mcde_sync_mux_ctrl;
+
+typedef enum
+{
+ MCDE_CH_A_OUT_ENABLE = 0x0,
+ MCDE_CH_C_OUT_ENABLE = 0x1
+}mcde_sync_mux1_ctrl;
+
+typedef enum
+{
+ MCDE_CH_A_CLK_PANEL = 0x0,
+ MCDE_CH_C_CHIP_SELECT = 0x1
+}mcde_sync_mux0_ctrl;
+
+typedef enum
+{
+ MCDE_CDI_CH_A = 0x0,
+ MCDE_CDI_CH_B = 0x1
+}mcde_cdi_ctrl;
+
+typedef enum
+{
+ MCDE_CDI_DISABLE = 0x0,
+ MCDE_CDI_ENABLE = 0x1
+}mcde_cdi;
+/*
+typedef enum
+{
+ MCDE_DISABLE = 0x0,
+ MCDE_ENABLE = 0x1
+}mcde_state;
+
+typedef struct
+{
+ t_mcde_out_mux_ctrl data_msb1;
+ t_mcde_out_mux_ctrl data_msb0;
+ t_mcde_out_mux_ctrl data_mid;
+ t_mcde_out_mux_ctrl data_lsb1;
+ t_mcde_out_mux_ctrl data_lsb0;
+ u8 ififo_watermark;
+}mcde_control;
+*/
+typedef enum
+{
+ MCDE_OUTPUT_FIFO_B = 0x0,
+ MCDE_OUTPUT_FIFO_C1 = 0x1
+}mcde_swap_b_c1_ctrl;
+
+typedef enum
+{
+ MCDE_CONF_TVA_DPIC0_LCDB = 0x0,
+ MCDE_CONF_TVB_DPIC1_LCDA = 0x1,
+ MCDE_CONF_DPIC1_LCDA = 0x2,
+ MCDE_CONF_DPIC0_LCDB = 0x3,
+ MCDE_CONF_LCDA_LCDB = 0x4,
+ MCDE_CONF_DSI = 0x5
+}mcde_output_conf;
+
+typedef enum
+{
+ MCDE_OUTPUT_FIFO_A = 0x0,
+ MCDE_OUTPUT_FIFO_C0 = 0x1
+}mcde_swap_a_c0_ctrl;
+
+/*
+typedef struct
+{
+ u32 irq_status;
+ u32 event_status;
+ t_bool is_new;
+}mcde_irq_status;
+*/
+ typedef enum
+ {
+ MCDE_EVENT_MASTER_BUS_ERROR = 0x01,
+ MCDE_EVENT_END_OF_FRAME_TRANSFER = 0x02,
+ MCDE_EVENT_SYNCHRO_CAPTURE_TRIGGER = 0x04,
+ MCDE_EVENT_HORIZONTAL_SYNCHRO_CAPTURE = 0x08,
+ MCDE_EVENT_VERTICAL_SYNCHRO_CAPTURE = 0x10
+ } mcde_event_id;
+
+typedef struct
+{
+ u8 pllfreq_div;
+ u8 datachannels_num;
+ u8 delay_clk;
+ u8 delay_d2;
+ u8 delay_d1;
+ u8 delay_d0;
+}mcde_cdi_delay;
+/*******************************************************************************
+ External Source Enums and Structures
+ ******************************************************************************/
+
+ typedef enum
+ {
+ MCDE_EXT_SRC_0 = 0x0,
+ MCDE_EXT_SRC_1 = 0x1,
+ MCDE_EXT_SRC_2 = 0x2,
+ MCDE_EXT_SRC_3 = 0x3,
+ MCDE_EXT_SRC_4 = 0x4,
+ MCDE_EXT_SRC_5 = 0x5,
+ MCDE_EXT_SRC_6 = 0x6,
+ MCDE_EXT_SRC_7 = 0x7,
+ MCDE_EXT_SRC_8 = 0x8,
+ MCDE_EXT_SRC_9 = 0x9,
+ MCDE_EXT_SRC_10 = 0xA,
+ MCDE_EXT_SRC_11 = 0xB,
+ MCDE_EXT_SRC_12 = 0xC,
+ MCDE_EXT_SRC_13 = 0xD,
+ MCDE_EXT_SRC_14 = 0xE,
+ MCDE_EXT_SRC_15 = 0xF
+ }mcde_ext_src;
+
+
+ typedef enum
+ {
+ MCDE_U8500_PANEL_1BPP=1,
+ MCDE_U8500_PANEL_2BPP=2,
+ MCDE_U8500_PANEL_4BPP=4,
+ MCDE_U8500_PANEL_8BPP=8,
+ MCDE_U8500_PANEL_16BPP=16,
+ MCDE_U8500_PANEL_24BPP_PACKED=24,
+ MCDE_U8500_PANEL_24BPP=25,
+ MCDE_U8500_PANEL_32BPP=32,
+ MCDE_U8500_PANEL_YCBCR=11,
+ }mcde_fb_bpp;
+
+ typedef enum
+ {
+ MCDE_U8500_PANEL_16BPP_RGB=35,
+ MCDE_U8500_PANEL_16BPP_IRGB=36,
+ MCDE_U8500_PANEL_16BPP_ARGB=37,
+ MCDE_U8500_PANEL_12BPP=38,
+ }mcde_fb_16bpp_type;
+
+
+ typedef enum
+ {
+ MCDE_FS_FREQ_UNCHANGED = 0x0,
+ MCDE_FS_FREQ_DIV_2 = 0x1
+ }mcde_fs_div;
+
+ typedef enum
+ {
+ MCDE_FS_FREQ_DIV_ENABLE = 0x0,
+ MCDE_FS_FREQ_DIV_DISABLE = 0x1
+ }mcde_fs_ctrl;
+
+ typedef enum
+ {
+ MCDE_MULTI_CH_CTRL_ALL_OVR = 0x0,
+ MCDE_MULTI_CH_CTRL_PRIMARY_OVR = 0x1
+ }mcde_multi_ovr_ctrl;
+
+ typedef enum
+ {
+ MCDE_BUFFER_SEL_EXT = 0x0,
+ MCDE_BUFFER_AUTO_TOGGLE = 0x1,
+ MCDE_BUFFER_SOFTWARE_SELECT = 0x2,
+ MCDE_BUFFER_RESERVED
+ }mcde_buffer_sel_mode;
+
+ struct mcde_ext_src_ctrl
+ {
+ mcde_fs_div fs_div;
+ mcde_fs_ctrl fs_ctrl;
+ mcde_multi_ovr_ctrl ovr_ctrl;
+ mcde_buffer_sel_mode sel_mode;
+ };
+
+
+/*******************************************************************************
+ Overlay Enums and Structures
+ ******************************************************************************/
+
+
+/* typedef enum
+ {
+ MCDE_OVERLAY_0,
+ MCDE_OVERLAY_1,
+ MCDE_OVERLAY_2,
+ MCDE_OVERLAY_3,
+ MCDE_OVERLAY_4,
+ MCDE_OVERLAY_5,
+ MCDE_OVERLAY_6,
+ MCDE_OVERLAY_7
+ }mcde_overlay_id; */
+
+
+
+
+
+
+
+ /* typedef enum
+ {
+ MCDE_OVR_INTERLACE_DISABLE = 0x0,
+ MCDE_OVR_INTERLACE_ENABLE = 0x1
+ }mcde_ovr_interlace_ctrl;
+
+ typedef enum
+ {
+ MCDE_OVR_INTERLACE_TOPFIELD = 0x0,
+ MCDE_OVR_INTERLACE_BOTTOMFIELD = 0x1
+ }mcde_ovr_interlace_mode;*/
+
+ typedef enum
+ {
+ MCDE_CH_A = 0x0,
+ MCDE_CH_B = 0x1,
+ MCDE_CH_C0 = 0x2,
+ MCDE_CH_C1 = 0x3
+ }mcde_ch_id;
+
+ typedef enum
+ {
+ MCDE_FETCH_INPROGRESS = 0x0,
+ MCDE_FETCH_COMPLETE = 0x1
+ }mcde_ovr_fetch_status;
+
+ typedef enum
+ {
+ MCDE_OVR_READ_COMPLETE = 0x0,
+ MCDE_OVR_READ_INPROGRESS = 0x1
+ }mcde_ovr_read_status;
+
+ struct mcde_ovr_control
+ {
+ mcde_rotate_req rot_burst_req;
+ mcde_outsnd_req outstnd_req;
+ mcde_burst_req burst_req;
+ u8 priority;
+ mcde_color_key_ctrl color_key;
+ mcde_pal_ctrl pal_control;
+ mcde_col_conv_ctrl col_ctrl;
+ mcde_overlay_ctrl ovr_state;
+ mcde_ovr_alpha_enable alpha;
+ mcde_ovr_clip_enable clip;
+ };
+
+ struct mcde_ovr_config
+ {
+ u32 line_per_frame;
+ /* mcde_ovr_interlace_mode ovr_interlace;
+ mcde_ovr_interlace_ctrl ovr_intlace_ctrl;*/
+ mcde_ext_src src_id;
+ u16 ovr_ppl;
+ };
+
+ struct mcde_ovr_conf2
+ {
+ u8 alpha_value;
+ u8 pixoff;
+ mcde_ovr_opq_ctrl ovr_opaq;
+ mcde_blend_ctrl ovr_blend;
+ u32 watermark_level;
+ };
+ /*
+ struct mcde_ovr_blend_ctrl
+ {
+ u8 alpha_value;
+ mcde_ovr_opq_ctrl ovr_opaq;
+ mcde_blend_ctrl ovr_blend;
+ u8 ovr_zlevel;
+ u16 ovr_xpos;
+ u16 ovr_ypos;
+ };*/
+
+ struct mcde_ovr_comp
+ {
+ u8 ovr_zlevel;
+ u16 ovr_ypos;
+ mcde_ch_id ch_id;
+ u16 ovr_xpos;
+ };
+
+ struct mcde_ovr_clipincr
+ {
+ u32 lineincr;
+ u32 yclip;
+ u32 xclip;
+ };
+
+struct mcde_ovr_clip
+{
+ u32 ytlcoor;
+ u32 xtlcoor;
+ u32 ybrcoor;
+ u32 xbrcoor;
+};
+
+typedef struct
+{
+ u16 ovr_ypos;
+ u16 ovr_xpos;
+}mcde_ovr_xy;
+
+
+typedef enum
+{
+ MCDE_OVERLAY_NOT_BLOCKED = 0x0,
+ MCDE_OVERLAY_BLOCKED = 0x1
+}mcde_ovr_blocked_status;
+ struct mcde_ovr_status
+ {
+ mcde_ovr_blocked_status ovrb_status;
+ mcde_ovr_fetch_status ovr_status;
+ mcde_ovr_read_status ovr_read;
+ };
+
+ /*******************************************************************************
+ Channel Configuration Enums and Structures
+ ******************************************************************************/
+
+
+
+ /* struct
+ {
+ u16 InitDelay;
+ u16 PPDelay;
+ }mcde_ch_delay;*/
+
+ struct mcde_chsyncconf
+ {
+ u16 swint_vcnt;
+ mcde_frame_events swint_vevent;
+ u16 hwreq_vcnt;
+ mcde_frame_events hwreq_vevent;
+ };
+
+ struct mcde_chsyncmod
+ {
+ mcde_synchro_out_interface out_synch_interface;
+ mcde_synchro_source ch_synch_src;
+ mcde_sw_trigger sw_trig;
+
+ };
+
+
+
+ struct mcde_ch_priority
+ {
+ u8 ch_priority;
+ };
+
+typedef enum
+{
+ MCDE_CHNL_RUNNING_NORMALLY = 0x0,
+ MCDE_CHNL_ABORT_OCCURRED = 0x1
+}mcde_chnl_abort_state;
+
+typedef enum
+{
+ MCDE_CHNL_READ_ONGOING = 0x0,
+ MCDE_CHNL_READ_DONE = 0x1
+}mcde_chnl_read_status;
+
+typedef struct
+{
+ mcde_chnl_abort_state abort_state;
+ mcde_chnl_read_status read_state;
+}mcde_chnl_state;
+ /*******************************************************************************
+ Channel A/B Enums and Structures
+ ******************************************************************************/
+
+ typedef enum
+ {
+ MCDE_CLOCKWISE = 0x0,
+ MCDE_ANTICLOCKWISE = 0x1
+ }mcde_rot_dir;
+
+ typedef enum
+ {
+ MCDE_GAMMA_ENABLE = 0x0,
+ MCDE_GAMMA_DISABLE = 0x1
+ }mcde_gamma_ctrl;
+
+ typedef enum
+ {
+ MCDE_INPUT_YCrCb = 0x0,
+ MCDE_INPUT_RGB = 0x1
+ }mcde_flicker_format;
+
+ typedef enum
+ {
+ MCDE_ALPHA_INPUTSRC = 0x0,
+ MCDE_ALPHA_REGISTER = 0x1
+ }mcde_blend_control;
+
+ typedef enum
+ {
+ MCDE_FORCE_FILTER0 = 0x0,
+ MCDE_ADAPTIVE_FILTER = 0x1,
+ MCDE_TEST_MODE = 0x2
+ }mcde_flicker_filter_mode;
+
+
+ typedef enum
+ {
+ MCDE_ROTATION_DISABLE = 0x0,
+ MCDE_ROTATION_ENABLE = 0x1
+ }mcde_roten;
+
+ typedef enum
+ {
+ MCDE_CLR_ENHANCE_DISABLE = 0x0,
+ MCDE_CLR_ENHANCE_ENABLE = 0x1
+ }mcde_clr_enhance_ctrl;
+
+ typedef enum
+ {
+ MCDE_BLEND_DISABLE = 0x0,
+ MCDE_BLEND_ENABLE = 0x1
+ }mcde_blend_status;
+
+
+ typedef enum
+ {
+ MCDE_VERTICAL_ACTIVE_FRAME_DISABLE = 0x0,
+ MCDE_ALL_FRAME_ENABLE = 0x1
+ }mcde_va_enable;
+
+ typedef enum
+ {
+ MCDE_OUTPUT_NORMAL = 0x0,
+ MCDE_OUTPUT_TOGGLE = 0x1
+ }mcde_toggle_enable;
+
+ typedef enum
+ {
+ MCDE_SYNCHRO_HBP = 0x0,
+ MCDE_SYNCHRO_CLP = 0x1,
+ MCDE_SYNCHRO_HFP = 0x2,
+ MCDE_SYNCHRO_HSW = 0x3
+ }mcde_loadsel;
+
+ typedef enum
+ {
+ MCDE_DATA_RISING_EDGE = 0x0,
+ MCDE_DATA_FALLING_EDGE = 0x1
+ }mcde_data_lines;
+
+ struct mcde_chx_control0
+ {
+ mcde_rotate_req chx_read_request;
+ u8 alpha_blend;
+ mcde_rot_dir rot_dir;
+ mcde_gamma_ctrl gamma_ctrl;
+ mcde_flicker_format flicker_format;
+ mcde_flicker_filter_mode filter_mode;
+ mcde_blend_control blend_ctrl;
+ mcde_key_ctrl key_ctrl;
+ mcde_roten rot_enable;
+ mcde_dithering_control dither_ctrl;
+ mcde_clr_enhance_ctrl color_enhance;
+ mcde_antiflicker_ctrl anti_flicker;
+ mcde_blend_status blend;
+ };
+ struct mcde_chx_rgb_conv_coef
+ {
+ u16 Yr_red;
+ u16 Yr_green;
+ u16 Yr_blue;
+ u16 Cr_red;
+ u16 Cr_green;
+ u16 Cr_blue;
+ u16 Cb_red;
+ u16 Cb_green;
+ u16 Cb_blue;
+ u16 Off_red;
+ u16 Off_green;
+ u16 Off_blue;
+ };
+
+ struct mcde_chx_flickfilter_coef
+ {
+ u8 threshold_ctrl0;
+ u8 threshold_ctrl1;
+ u8 threshold_ctrl2;
+ u8 Coeff0_N3;
+ u8 Coeff0_N2;
+ u8 Coeff0_N1;
+ u8 Coeff1_N3;
+ u8 Coeff1_N2;
+ u8 Coeff1_N1;
+ u8 Coeff2_N3;
+ u8 Coeff2_N2;
+ u8 Coeff2_N1;
+ };
+
+ struct mcde_chx_tv_control
+ {
+ u16 num_lines;
+ mcde_tvmode tv_mode;
+ mcde_signal_level ifield;
+ mcde_display_mode sel_mode;
+ };
+
+ struct mcde_chx_tv_blanking_field
+ {
+ u16 blanking_start;
+ u16 blanking_end;
+ };
+
+struct mcde_chx_tv_blanking2_field
+ {
+ u16 blanking_start;
+ u16 blanking_end;
+ };
+
+
+ struct mcde_chx_tv_start_line
+ {
+ u16 field2_start_line;
+ u16 field1_start_line;
+ };
+
+ struct mcde_chx_tv_dvo_offset
+ {
+ u16 field2_window_offset;
+ u16 field1_window_offset;
+ };
+
+ struct mcde_chx_tv_swh_time
+ {
+ u16 tv_swh2;
+ u16 tv_swh1;
+ };
+
+ struct mcde_chx_tv_timing1
+ {
+ u16 src_window_width;
+ u16 destination_hor_offset;
+ };
+
+ struct mcde_chx_tv_lbalw_timing
+ {
+ u16 active_line_width;
+ u16 line_blanking_width;
+ };
+
+ struct mcde_chx_tv_background_time
+ {
+ u8 background_cr;
+ u8 background_cb;
+ u8 background_lu;
+ };
+
+struct mcde_chx_lcd_timing0
+ {
+ mcde_va_enable rev_va_enable;
+ mcde_toggle_enable rev_toggle_enable;
+ mcde_loadsel rev_sync_sel;
+ u8 rev_delay1;
+ u8 rev_delay0;
+ mcde_va_enable ps_va_enable;
+ mcde_toggle_enable ps_toggle_enable;
+ mcde_loadsel ps_sync_sel;
+ u8 ps_delay1;
+ u8 ps_delay0;
+ };
+
+ struct mcde_chx_lcd_timing1
+ {
+ mcde_signal_level io_enable;
+ mcde_data_lines ipc;
+ mcde_signal_level ihs;
+ mcde_signal_level ivs;
+ mcde_signal_level ivp;
+ mcde_signal_level iclspl;
+ mcde_signal_level iclrev;
+ mcde_signal_level iclsp;
+ mcde_va_enable mcde_spl;
+ mcde_toggle_enable spltgen;
+ mcde_loadsel spl_sync_sel;
+ u8 spl_delay1;
+ u8 spl_delay0;
+ };
+
+
+ struct mcde_chx_palette
+ {
+ u16 alphared;
+ u8 green;
+ u8 blue;
+ };
+
+ struct mcde_chx_gamma
+ {
+ u8 red;
+ u8 green;
+ u8 blue;
+ };
+ typedef enum
+ {
+ MCDE_ROTATE0 = 0x0,
+ MCDE_ROTATE1 = 0x1
+}mcde_rotate_num;
+
+
+ /*******************************************************************************
+ Channel C Enums
+ ******************************************************************************/
+
+ typedef enum
+ {
+ MCDE_SYNCHRO_NONE = 0x0,
+ MCDE_SYNCHRO_C0 = 0x1,
+ MCDE_SYNCHRO_C1 = 0x2,
+ MCDE_SYNCHRO_PINGPONG = 0x3
+ }mcde_sync_ctrl;
+
+ typedef enum
+ {
+ MCDE_SIG_INACTIVE_POL_LOW = 0x0,
+ MCDE_SIG_INACTIVE_POL_HIGH = 0x1
+ }mcde_sig_pol;
+
+ typedef enum
+ {
+ MCDE_CD_LOW = 0x0, /* CD low for data and high for command */
+ MCDE_CD_HIGH = 0x1 /* CD high for data and low for command */
+ }mcde_cd_polarity;
+
+ typedef enum
+ {
+ MCDE_RES_INACTIVE = 0x0,
+ MCDE_RES_ACTIVE = 0x1
+ }mcde_resen;
+
+ typedef enum
+ {
+ MCDE_CSEN_DEACTIVATED = 0x0,
+ MCDE_CSEN_ACTIVATED = 0x1
+ }mcde_cs_enable_rw;
+
+ typedef enum
+ {
+ MCDE_PCLK_TVCLK1 = 0x0,
+ MCDE_PCLK_72 = 0x1,
+ MCDE_PCLK_TVCLK2 = 0x2
+ }mcde_clk_sel;
+
+ typedef enum
+ {
+ MCDE_SELECT_OUTBAND = 0x0,
+ MCDE_SELECT_INBAND = 0x1,
+ }mcde_inband_select;
+
+ typedef enum
+ {
+ MCDE_BUS_SIZE_8 = 0x0,
+ MCDE_BUS_SIZE_16 = 0x1
+ }mcde_bus_size;
+
+ typedef enum
+ {
+ MCDE_SYNCHRO_CAPTURE_DISABLE = 0x0,
+ MCDE_SYNCHRO_CAPTURE_ENABLE = 0x1
+ }mcde_synchro_capture;
+
+ typedef enum
+ {
+ MCDE_VERTICAL_SYNCHRO_CAPTURE1 = 0x0,
+ MCDE_VERTICAL_SYNCHRO_CHANELA = 0x1,
+ }mcde_synchro_select;
+
+ typedef enum
+ {
+ MCDE_FIFO_WMLVL_4 = 0x0,
+ MCDE_FIFO_WMLVL_8 = 0x1
+ }mcde_fifo_wmlvl_sel;
+
+ typedef enum
+ {
+ MCDE_CHANEL_C_DISABLE = 0x0,
+ MCDE_CHANEL_C_ENABLE = 0x1
+ }mcde_chc_enable;
+
+ typedef enum
+ {
+ MCDE_POWER_DISABLE = 0x0,
+ MCDE_POWER_ENABLE = 0x1
+ }mcde_powen_select;
+
+ typedef enum
+ {
+ MCDE_FLOW_DISABLE = 0x0,
+ MCDE_FLOW_ENABLE = 0x1
+ }mcde_flow_select;
+
+ typedef enum
+ {
+ MCDE_DUPLX_DISABLE = 0x0,
+ MCDE_DUPLX_ENABLE = 0x1
+ }mcde_duplx_ctrl;
+
+ typedef enum
+ {
+ MCDE_DUPLX_MODE_NONE = 0x0,
+ MCDE_DUPLX_MODE_16_TO_32 = 0x1,
+ MCDE_DUPLX_MODE_24_TO_32_RS = 0x2,
+ MCDE_DUPLX_MODE_24_TO_32_LS = 0x3
+ }mcde_duplx_mode_select;
+
+ typedef enum
+ {
+ MCDE_TRANSFER_8_1 = 0x0,
+ MCDE_TRANSFER_8_2 = 0x1,
+ MCDE_TRANSFER_8_3 = 0x2,
+ MCDE_TRANSFER_16_1 = 0x4,
+ MCDE_TRANSFER_16_2 = 0x5
+ }mcde_bit_segmentation_select;
+
+ typedef enum
+ {
+ MCDE_TRANSACTION_COMMAND = 0x0,
+ MCDE_TRANSACTION_DATA = 0x1
+ }mcde_transaction_type;
+
+ typedef enum
+ {
+ MCDE_VSYNC_SELECT = 0x0,
+ MCDE_HSYNC_SELECT = 0x1
+ }mcde_vertical_sync_sel;
+
+ typedef enum
+ {
+ MCDE_VSYNC_ACTIVE_HIGH = 0x0,
+ MCDE_VSYNC_ACTIVE_LOW = 0x1,
+ }mcde_vertical_sync_polarity;
+
+ typedef enum
+ {
+ MCDE_STBCLK_DIV_1 = 0x0,
+ MCDE_STBCLK_DIV_2 = 0x1,
+ MCDE_STBCLK_DIV_4 = 0x2,
+ MCDE_STBCLK_DIV_8 = 0x3,
+ MCDE_STBCLK_DIV_16 = 0x4,
+ MCDE_STBCLK_DIV_32 = 0x5,
+ MCDE_STBCLK_DIV_64 = 0x6,
+ MCDE_STBCLK_DIV_128 = 0x7
+ }mcde_synchro_clk_div_factor;
+
+ typedef enum
+ {
+ MCDE_PANEL_INTEL_SERIES = 0x0,
+ MCDE_PANEL_MOTOROLA_SERIES = 0x1
+ }mcde_panel_protocol;
+
+ typedef enum
+ {
+ MCDE_PANEL_C0 = 0x0,
+ MCDE_PANEL_C1 = 0x1
+ }mcde_chc_panel;
+
+ typedef enum
+ {
+ MCDE_TXFIFO_WRITE_DATA = 0,
+ MCDE_TXFIFO_READ_DATA,
+ MCDE_TXFIFO_WRITE_COMMAND
+ } mcde_txfifo_request_type;
+
+
+ struct mcde_chc_ctrl
+ {
+ mcde_sync_ctrl sync;
+ mcde_resen resen;
+ mcde_synchro_select synsel;
+ mcde_clk_sel clksel;
+ };
+
+ struct mcde_chc_config
+ {
+ mcde_sig_pol res_pol;
+ mcde_sig_pol rd_pol;
+ mcde_sig_pol wr_pol;
+ mcde_cd_polarity cd_pol;
+ mcde_sig_pol cs_pol;
+ mcde_cs_enable_rw csen;
+ mcde_inband_select inband_mode;
+ mcde_bus_size bus_size;
+ mcde_synchro_capture syncen;
+ mcde_fifo_wmlvl_sel fifo_watermark;
+ mcde_chc_enable chcen;
+ };
+
+ struct mcde_pbc_config
+ {
+ mcde_duplx_ctrl duplex_ctrl;
+ mcde_duplx_mode_select duplex_mode;
+ mcde_bit_segmentation_select data_segment;
+ mcde_bit_segmentation_select cmd_segment;
+ };
+
+ struct mcde_pbc_mux
+ {
+ u32 imux0;
+ u32 imux1;
+ u32 imux2;
+ u32 imux3;
+ u32 imux4;
+ };
+
+ struct mcde_pbc_bitctrl
+ {
+ u32 bit_ctrl0;
+ u32 bit_ctrl1;
+ };
+
+ struct mcde_sync_conf
+ {
+ u8 debounce_length;
+ mcde_vertical_sync_sel sync_sel;
+ mcde_vertical_sync_polarity sync_pol;
+ mcde_synchro_clk_div_factor clk_div;
+ u16 vsp_max;
+ u16 vsp_min;
+ };
+
+ struct mcde_sync_trigger
+ {
+ u16 trigger_delay_cx;
+ u8 sync_delay_c1;
+ u8 sync_delay_c2;
+ };
+
+ struct mcde_cd_timing_activate
+ {
+ u8 cs_cd_deactivate;
+ u8 cs_cd_activate;
+ };
+
+ struct mcde_rw_timing
+ {
+ mcde_panel_protocol panel_type;
+ u8 readwrite_activate;
+ u8 readwrite_deactivate;
+ };
+
+ struct mcde_data_out_timing
+ {
+ u8 data_out_deactivate;
+ u8 data_out_activate;
+ };
+
+ /*********************************************************************
+ DSIX typedefs
+ *********************************************************************/
+ typedef enum
+ {
+ MCDE_DSI_CH_VID0 = 0x0,
+ MCDE_DSI_CH_CMD0 = 0x1,
+ MCDE_DSI_CH_VID1 = 0x2,
+ MCDE_DSI_CH_CMD1 = 0x3,
+ MCDE_DSI_CH_VID2 = 0x4,
+ MCDE_DSI_CH_CMD2 = 0x5
+ }mcde_dsi_channel;
+
+ typedef enum
+ {
+ MCDE_PLL_OUT_OFF = 0x0,
+ MCDE_PLL_OUT_1 = 0x1,
+ MCDE_PLL_OUT_2 = 0x2,
+ MCDE_PLL_OUT_4 = 0x3
+ }mcde_pll_div_sel;
+
+ typedef enum
+ {
+ MCDE_CLK27 = 0x0,
+ MCDE_TV1CLK = 0x1,
+ MCDE_HDMICLK = 0x2,
+ MCDE_TV2CLK = 0x3,
+ MCDE_MXTALI = 0x4
+ }mcde_pll_ref_clk;
+
+ typedef enum
+ {
+ MCDE_DSI_CLK27 = 0x0,
+ MCDE_DSI_MCDECLK = 0x1
+ }mcde_clk_divider;
+
+ typedef struct
+ {
+ mcde_pll_div_sel pllout_divsel2;
+ mcde_pll_div_sel pllout_divsel1;
+ mcde_pll_div_sel pllout_divsel0;
+ mcde_pll_ref_clk pll4in_sel;
+ mcde_clk_divider txescdiv_sel;
+ u32 txescdiv;
+ }mcde_dsi_clk_config;
+
+ typedef enum
+ {
+ MCDE_PACKING_RGB565 = 0x0,
+ MCDE_PACKING_RGB666 = 0x1,
+ MCDE_PACKING_RGB888_R = 0x2,
+ MCDE_PACKING_RGB888_B = 0x3,
+ MCDE_PACKING_HDTV = 0x4
+ }mcde_dsi_packing;
+
+ typedef enum
+ {
+ MCDE_DSI_OUT_GENERIC_CMD = 0x0,
+ MCDE_DSI_OUT_VIDEO_DCS = 0x1
+ }mcde_dsi_synchro;
+
+ typedef enum
+ {
+ MCDE_DSI_NO_SWAP = 0x0,
+ MCDE_DSI_SWAP = 0x1,
+ }mcde_dsi_swap;
+
+ typedef enum
+ {
+ MCDE_DSI_CMD_16 = 0x0,
+ MCDE_DSI_CMD_8 = 0x1
+ }mcde_dsi_cmd;
+
+ typedef enum
+ {
+ MCDE_DSI_CMD_MODE = 0x0,
+ MCDE_DSI_VID_MODE = 0x1,
+ }mcde_vid_mode;
+
+ typedef struct
+ {
+ mcde_dsi_packing packing;
+ mcde_dsi_synchro synchro;
+ mcde_dsi_swap byte_swap;
+ mcde_dsi_swap bit_swap;
+ mcde_dsi_cmd cmd8;
+ mcde_vid_mode vid_mode;
+ u8 blanking;
+ u32 words_per_frame;
+ u32 words_per_packet;
+ }mcde_dsi_conf;
+
+
+
+/*******************************************************************************
+MCDE Error Enums
+******************************************************************************/
+typedef enum
+{
+ MCDE_OK = 0x00, /* No error.*/
+ MCDE_NO_PENDING_EVENT_ERROR = 0x01,
+ MCDE_NO_MORE_FILTER_PENDING_EVENT = 0x02,
+ MCDE_NO_MORE_PENDING_EVENT = 0x03,
+ MCDE_REMAINING_FILTER_PENDING_EVENTS = 0x04,
+ MCDE_REMAINING_PENDING_EVENTS = 0x05,
+ MCDE_INTERNAL_EVENT = 0x06,
+ MCDE_INTERNAL_ERROR = 0x07,
+ MCDE_NOT_CONFIGURED = 0x08,
+ MCDE_REQUEST_PENDING = 0x09,
+ MCDE_REQUEST_NOT_APPLICABLE = 0x0A,
+ MCDE_INVALID_PARAMETER = 0x0B,
+ MCDE_UNSUPPORTED_FEATURE = 0x0C,
+ MCDE_UNSUPPORTED_HW = 0x0D
+}mcde_error;
+
+/*******************************************************************************
+MCDE driver specific structures
+******************************************************************************/
+
+typedef enum {
+ CHANNEL_A = 0x0,
+ CHANNEL_B = 0x1,
+ CHANNEL_C0 = 0x2,
+ CHANNEL_C1 = 0x3,
+}channel ;
+
+typedef enum {
+ RES_QVGA = 0x0,
+ RES_VGA = 0x1,
+ RES_WVGA = 0x2,
+}screenres;
+
+ typedef struct
+ {
+ u16 alphared;
+ u8 green;
+ u8 blue;
+ }mcde_palette;
+
+typedef struct
+{
+ u8 red;
+ u8 green;
+ u8 blue;
+}t_mcde_gamma;
+
+struct mcde_channel_data{
+ channel channelid;
+ u8 nopan;
+ u8 nowrap;
+ const char *restype;
+ mcde_bpp_ctrl inbpp;
+ mcde_out_bpp outbpp;
+ u8 bpp16_type;
+ u8 bgrinput;
+ gpio_alt_function gpio_alt_func;
+};
+// per channel structure
+struct mcde_ovlextsrc_conf{
+ u16 ovl_id; //bitmap of overlays used
+ u8 num_ovl;
+};
+
+struct clut_addrmap {
+ u32 clutaddr;
+ u32 clutdmaaddr;
+};
+
+
+#endif //__KERNEL__
+
+/* FUNCTION PROTOTYPE */
+void mcdefb_enable(struct fb_info *info);
+void mcdefb_disable(struct fb_info *info);
+int mcde_enable(struct fb_info *info);
+int mcde_disable(struct fb_info *info);
+int convertbpp(u8 bpp);
+int mcde_conf_channel_color_key(struct fb_info *info, struct mcde_channel_color_key chnannel_color_key);
+/*inline */unsigned long get_line_length(int x, int bpp);
+/* inline */unsigned long claim_mcde_lock(mcde_ch_id chid);
+/*inline*/ void release_mcde_lock(mcde_ch_id chid, unsigned long flags);
+int mcde_set_buffer(struct fb_info *info, u32 buffer_address, mcde_buffer_id buff_id);
+int mcde_conf_dithering_ctrl(struct mcde_dithering_ctrl_conf dithering_ctrl_conf, struct fb_info *info);
+bool mcde_get_hdmi_flag(void);
+void mcde_configure_hdmi_channel(void);
+void mcde_hdmi_display_init_command_mode(void);
+void mcde_hdmi_display_init_video_mode(void);
+void mcde_hdmi_test_directcommand_mode_highspeed(void);
+void mcde_send_hdmi_cmd_data(char* buf,int length, int dsicommand);
+void mcde_send_hdmi_cmd(char* buf,int length, int dsicommand);
+
+int mcde_extsrc_ovl_create(struct mcde_overlay_create *extsrc_ovl ,struct fb_info *info,u32 *pkey);
+int mcde_extsrc_ovl_remove(struct fb_info *info,u32 key);
+int mcde_alloc_source_buffer(struct mcde_sourcebuffer_alloc source_buff ,struct fb_info *info, u32 *pkey, u8 isUserRequest);
+int mcde_dealloc_source_buffer(struct fb_info *info, u32 srcbufferindex, u8 isUserRequest);
+int mcde_conf_extsource(struct mcde_ext_conf ext_src_config ,struct fb_info *info);
+int mcde_conf_overlay(struct mcde_conf_overlay ovrlayConfig ,struct fb_info *info);
+int mcde_conf_channel(struct mcde_ch_conf ch_config ,struct fb_info *info);
+int mcde_conf_lcd_timing(struct mcde_chnl_lcd_ctrl chnl_lcd_ctrl, struct fb_info *info);
+int mcde_conf_color_conversion_coeff(struct fb_info *info, mcde_colorconv_type color_conv_type);
+int mcde_conf_color_conversion(struct fb_info *info, struct mcde_conf_color_conv color_conv_ctrl);
+int mcde_conf_blend_ctrl(struct fb_info *info, struct mcde_blend_control blend_ctrl);
+int mcde_conf_rotation(struct fb_info *info, mcde_rot_dir rot_dir, mcde_roten rot_ctrl, u32 rot_addr0, u32 rot_addr1);
+int mcde_conf_chnlc(struct mcde_chc_config chnlc_config, struct mcde_chc_ctrl chnlc_control, struct fb_info *info);
+int mcde_conf_dsi_chnl(mcde_dsi_conf dsi_conf, mcde_dsi_clk_config clk_config, struct fb_info *info);
+int mcde_conf_scan_mode(mcde_scan_mode scan_mode, struct fb_info *info);
+
+mcde_error mcdesetextsrcconf(mcde_ch_id chid, mcde_ext_src src_id, struct mcde_ext_conf config);
+mcde_error mcdesetextsrcctrl(mcde_ch_id chid, mcde_ext_src src_id, struct mcde_ext_src_ctrl control);
+mcde_error mcdesetbufferaddr(mcde_ch_id chid, mcde_ext_src src_id, mcde_buffer_id buffer_id, u32 address);
+mcde_error mcdesetovrctrl(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_control ovr_cr);
+mcde_error mcdesetovrlayconf(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_config ovr_conf);
+mcde_error mcdesetovrconf2(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_conf2 ovr_conf2);
+mcde_error mcdesetovrljinc(mcde_ch_id chid, mcde_overlay_id overlay, u32 ovr_ljinc);
+mcde_error mcdesettopleftmargincrop(mcde_ch_id chid, mcde_overlay_id overlay, u32 ovr_topmargin, u16 ovr_leftmargin);
+mcde_error mcdesetovrcomp(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_comp ovr_comp);
+mcde_error mcdesetovrclip(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_clip ovr_clip);
+mcde_error mcdesetovrstate(mcde_ch_id chid, mcde_overlay_id overlay, mcde_overlay_ctrl state);
+mcde_error mcdesetovrpplandlpf(mcde_ch_id chid, mcde_overlay_id overlay, u16 ppl, u16 lpf);
+mcde_error mcdesetstate(mcde_ch_id chid, mcde_state state);
+mcde_error mcdesetchnlXconf(mcde_ch_id chid, u16 channelnum, struct mcde_chconfig config);
+mcde_error mcdesetswsync(mcde_ch_id chid, u16 channelnum, mcde_sw_trigger sw_trig);
+mcde_error mcdesetchnlbckgndcol(mcde_ch_id chid, u16 channelnum, struct mcde_ch_bckgrnd_col color);
+mcde_error mcdesetchnlsyncprio(mcde_ch_id chid, u16 channelnum, u32 priority);
+mcde_error mcdesetchnlXpowermode(mcde_ch_id chid, mcde_powen_select power);
+mcde_error mcdesetflowXctrl(mcde_ch_id chid, struct mcde_chx_control0 control);
+mcde_error mcdesetpanelctrl(mcde_ch_id chid, struct mcde_chx_control1 control);
+mcde_error mcdesetcolorkey(mcde_ch_id chid, struct mcde_chx_color_key key, mcde_colorkey_type type);
+mcde_error mcdesetcolorconvmatrix(mcde_ch_id chid, struct mcde_chx_rgb_conv_coef coef);
+mcde_error mcdesetflickerfiltercoef(mcde_ch_id chid, struct mcde_chx_flickfilter_coef coef);
+mcde_error mcdesetLCDtiming0ctrl(mcde_ch_id chid, struct mcde_chx_lcd_timing0 control);
+mcde_error mcdesetLCDtiming1ctrl(mcde_ch_id channel, struct mcde_chx_lcd_timing1 control);
+mcde_error mcdesetrotaddr(mcde_ch_id chid, u32 address, mcde_rotate_num rotnum);
+mcde_error mcdesetpalette(mcde_ch_id chid, mcde_palette palette);
+mcde_error mcdesetditherctrl(mcde_ch_id chid, struct mcde_chx_dither_ctrl control);
+mcde_error mcdesetditheroffset(mcde_ch_id chid, struct mcde_chx_dithering_offset offset);
+mcde_error mcdesetgammacoeff(mcde_ch_id chid, struct mcde_chx_gamma gamma);
+mcde_error mcdesetoutmuxconf(mcde_ch_id chid, mcde_out_bpp outbpp);
+mcde_error mcdesetchnlXpowermode(mcde_ch_id chid, mcde_powen_select power);
+mcde_error mcdesetchnlXflowmode(mcde_ch_id chid, mcde_flow_select flow);
+mcde_error mcdesetcflowXcolorkeyctrl(mcde_ch_id chid, mcde_key_ctrl key_ctrl);
+mcde_error mcdesetblendctrl(mcde_ch_id chid, struct mcde_blend_control blend_ctrl);
+mcde_error mcdesetrotation(mcde_ch_id chid, mcde_rot_dir rot_dir, mcde_roten rot_ctrl);
+mcde_error mcdesetcolorconvctrl(mcde_ch_id chid, mcde_overlay_id overlay, mcde_col_conv_ctrl col_ctrl);
+mcde_error mcderesetextsrcovrlay(mcde_ch_id chid);
+mcde_error mcdesetchnlsyncsrc(mcde_ch_id chid, u16 channelnum, struct mcde_chsyncmod sync_mod);
+mcde_error mcdesetchnlsyncevent(mcde_ch_id chid, struct mcde_ch_conf ch_config);
+mcde_error mcdesetchnlLCDctrlreg(mcde_ch_id chid, struct mcde_chnl_lcd_ctrl_reg lcd_ctrl_reg);
+mcde_error mcdesetchnlLCDhorizontaltiming(mcde_ch_id chid, struct mcde_chnl_lcd_horizontal_timing lcd_horizontal_timing);
+mcde_error mcdesetchnlLCDverticaltiming(mcde_ch_id chid, struct mcde_chnl_lcd_vertical_timing lcd_vertical_timing);
+mcde_error mcdesetditheringctrl(mcde_ch_id chid, mcde_dithering_ctrl dithering_control);
+mcde_error mcdesetscanmode(mcde_ch_id chid, mcde_scan_mode scan_mode);
+#endif
+
diff --git a/arch/arm/mach-ux500/include/mach/mcde_a0.h b/arch/arm/mach-ux500/include/mach/mcde_a0.h
new file mode 100755
index 00000000000..f848b6eaa90
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/mcde_a0.h
@@ -0,0 +1,866 @@
+#define WRITE_FIELD(reg, field, value) \
+ (reg = (reg & (~((field##_MASK) << (field##_SHIFT)))) | ((value & (field##_MASK)) << (field##_SHIFT)) )
+
+
+#define MCDE_CR (MCDE_BASE + 0x0)
+#define MCDE_CR_MCDEEN 0x80000000
+#define MCDE_CR_AUTOCLKG_EN 0x40000000
+#define MCDE_CR_FABMUX 0x00020000
+#define MCDE_CR_F01MUX 0x00010000
+#define MCDE_CR_IFIFOCTRLEN 0x00008000
+#define MCDE_CR_DPIA_EN 0x00000200
+#define MCDE_CR_DPIB_EN 0x00000100
+#define MCDE_CR_DPIC0_EN 0x00000080
+#define MCDE_CR_DPIC1_EN 0x00000040
+#define MCDE_CR_DSIVID0_EN 0x00000020
+#define MCDE_CR_DSIVID1_EN 0x00000010
+#define MCDE_CR_DSIVID2_EN 0x00000008
+#define MCDE_CR_DSICMD0_EN 0x00000004
+#define MCDE_CR_DSICMD1_EN 0x00000002
+#define MCDE_CR_DSICMD2_EN 0x00000001
+
+
+#define MCDE_CONF0 (MCDE_BASE + 0x4)
+#define MCDE_CONF0_OUTMUX4_SHIFT 28
+#define MCDE_CONF0_OUTMUX4_MASK 0x7
+#define MCDE_CONF0_OUTMUX3_SHIFT 25
+#define MCDE_CONF0_OUTMUX3_MASK 0x7
+#define MCDE_CONF0_OUTMUX2_SHIFT 22
+#define MCDE_CONF0_OUTMUX2_MASK 0x7
+#define MCDE_CONF0_OUTMUX1_SHIFT 19
+#define MCDE_CONF0_OUTMUX1_MASK 0x7
+#define MCDE_CONF0_OUTMUX0_SHIFT 16
+#define MCDE_CONF0_OUTMUX0_MASK 0x7
+#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT 12
+#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x7
+#define MCDE_CONF0_FSYNCTRLB 0x00000800
+#define MCDE_CONF0_FSYNCTRLA 0x00000400
+#define MCDE_CONF0_SWAP_B_C1 0x00000200
+#define MCDE_CONF0_SWAP_A_C0 0x00000100
+#define MCDE_CONF0_SYNCMUX7 0x00000080
+#define MCDE_CONF0_SYNCMUX6 0x00000040
+#define MCDE_CONF0_SYNCMUX5 0x00000020
+#define MCDE_CONF0_SYNCMUX4 0x00000010
+#define MCDE_CONF0_SYNCMUX3 0x00000008
+#define MCDE_CONF0_SYNCMUX2 0x00000004
+#define MCDE_CONF0_SYNCMUX1 0x00000002
+#define MCDE_CONF0_SYNCMUX0 0x00000001
+
+
+#define MCDE_SSP (MCDE_BASE + 0x8)
+#define MCDE_SSP_SSPEN 0x00010000
+#define MCDE_SSP_SSPCMD 0x00000100
+#define MCDE_SSP_SSPDATA_SHIFT 0
+#define MCDE_SSP_SSPDATA_MASK 0xFF
+
+
+#define MCDE_AIS (MCDE_BASE + 0x100)
+#define MCDE_AIS_DSI2AI 0x00000040
+#define MCDE_AIS_DSI1AI 0x00000020
+#define MCDE_AIS_DSI0AI 0x00000010
+#define MCDE_AIS_MCDEERRI 0x00000008
+#define MCDE_AIS_MCDECHNLI 0x00000004
+#define MCDE_AIS_MCDEOVLI 0x00000002
+#define MCDE_AIS_MCDEPPI 0x00000001
+
+
+#define MCDE_IMSCPP (MCDE_BASE + 0x104)
+#define MCDE_IMSCPP_ROTFDIM_SHIFT 6
+#define MCDE_IMSCPP_ROTFDIM_MASK 0x3
+#define MCDE_IMSCPP_VCMPC1IM 0x00000020
+#define MCDE_IMSCPP_VCMPC0IM 0x00000010
+#define MCDE_IMSCPP_VSCC1IM 0x00000008
+#define MCDE_IMSCPP_VSCC0IM 0x00000004
+#define MCDE_IMSCPP_VCMPBIM 0x00000002
+#define MCDE_IMSCPP_VCMPAIM 0x00000001
+
+
+#define MCDE_IMSCOVL (MCDE_BASE + 0x108)
+#define MCDE_IMSCOVL_OVLFDIM_SHIFT 16
+#define MCDE_IMSCOVL_OVLFDIM_MASK 0xFFFF
+#define MCDE_IMSCOVL_OVLRDIM_SHIFT 0
+#define MCDE_IMSCOVL_OVLRDIM_MASK 0xFFFF
+
+
+#define MCDE_IMSCCHNL (MCDE_BASE + 0x10C)
+#define MCDE_IMSCCHNL_CHNLAIM_SHIFT 16
+#define MCDE_IMSCCHNL_CHNLAIM_MASK 0xFFFF
+#define MCDE_IMSCCHNL_CHNLRDIM_SHIFT 0
+#define MCDE_IMSCCHNL_CHNLRDIM_MASK 0xFFFF
+
+
+#define MCDE_IMSCERR (MCDE_BASE + 0x110)
+#define MCDE_IMSCERR_OVLFERRIM_SHIFT 16
+#define MCDE_IMSCERR_OVLFERRIM_MASK 0xFFFF
+#define MCDE_IMSCERR_FUC1IM 0x00000100
+#define MCDE_IMSCERR_FUC0IM 0x00000080
+#define MCDE_IMSCERR_ROTBFEIM_SHIFT 5
+#define MCDE_IMSCERR_ROTBFEIM_MASK 0x3
+#define MCDE_IMSCERR_ROTAFEIM_SHIFT 3
+#define MCDE_IMSCERR_ROTAFEIM_MASK 0x3
+#define MCDE_IMSCERR_SCHBLCKDIM 0x00000004
+#define MCDE_IMSCERR_FUBIM 0x00000002
+#define MCDE_IMSCERR_FUAIM 0x00000001
+
+
+#define MCDE_RISPP (MCDE_BASE + 0x114)
+#define MCDE_RISPP_ROTFDRIS_SHIFT 6
+#define MCDE_RISPP_ROTFDRIS_MASK 0x3
+#define MCDE_RISPP_VCMPC1RIS 0x00000020
+#define MCDE_RISPP_VCMPC0RIS 0x00000010
+#define MCDE_RISPP_VSCC1RIS 0x00000008
+#define MCDE_RISPP_VSCC0RIS 0x00000004
+#define MCDE_RISPP_VCMPBRIS 0x00000002
+#define MCDE_RISPP_VCMPARIS 0x00000001
+
+
+#define MCDE_RISOVL (MCDE_BASE + 0x118)
+#define MCDE_RISOVL_OVLFDRIS_SHIFT 16
+#define MCDE_RISOVL_OVLFDRIS_MASK 0xFFFF
+#define MCDE_RISOVL_OVLRDRIS_SHIFT 0
+#define MCDE_RISOVL_OVLRDRIS_MASK 0xFFFF
+
+
+#define MCDE_RISCHNL (MCDE_BASE + 0x11C)
+#define MCDE_RISCHNL_CHNLARIS_SHIFT 16
+#define MCDE_RISCHNL_CHNLARIS_MASK 0xFFFF
+#define MCDE_RISCHNL_CHNLRDRIS_SHIFT 0
+#define MCDE_RISCHNL_CHNLRDRIS_MASK 0xFFFF
+
+
+#define MCDE_RISERR (MCDE_BASE + 0x120)
+#define MCDE_RISERR_OVLFERRIS_SHIFT 16
+#define MCDE_RISERR_OVLFERRIS_MASK 0xFFFF
+#define MCDE_RISERR_FUC1RIS 0x00000100
+#define MCDE_RISERR_FUC0RIS 0x00000080
+#define MCDE_RISERR_ROTBFERIS_SHIFT 5
+#define MCDE_RISERR_ROTBFERIS_MASK 0x3
+#define MCDE_RISERR_ROTAFERIS_SHIFT 3
+#define MCDE_RISERR_ROTAFERIS_MASK 0x3
+#define MCDE_RISERR_SCHBLCKDRIS 0x00000004
+#define MCDE_RISERR_FUBRIS 0x00000002
+#define MCDE_RISERR_FUARIS 0x00000001
+
+
+#define MCDE_MISPP (MCDE_BASE + 0x124)
+#define MCDE_MISPP_ROTFDMIS_SHIFT 6
+#define MCDE_MISPP_ROTFDMIS_MASK 0x3
+#define MCDE_MISPP_VCMPC1MIS 0x00000020
+#define MCDE_MISPP_VCMPC0MIS 0x00000010
+#define MCDE_MISPP_VSCC1MIS 0x00000008
+#define MCDE_MISPP_VSCC0MIS 0x00000004
+#define MCDE_MISPP_VCMPBMIS 0x00000002
+#define MCDE_MISPP_VCMPAMIS 0x00000001
+
+
+#define MCDE_MISOVL (MCDE_BASE + 0x128)
+#define MCDE_MISOVL_OVLFDMIS_SHIFT 16
+#define MCDE_MISOVL_OVLFDMIS_MASK 0xFFFF
+#define MCDE_MISOVL_OVLRDMIS_SHIFT 0
+#define MCDE_MISOVL_OVLRDMIS_MASK 0xFFFF
+
+
+#define MCDE_MISCHNL (MCDE_BASE + 0x12C)
+#define MCDE_MISCHNL_CHNLAMIS_SHIFT 16
+#define MCDE_MISCHNL_CHNLAMIS_MASK 0xFFFF
+#define MCDE_MISCHNL_CHNLRDMIS_SHIFT 0
+#define MCDE_MISCHNL_CHNLRDMIS_MASK 0xFFFF
+#define MCDE_MISCHNL_CHNL_A 0x00000001
+#define MCDE_MISCHNL_CHNL_B 0x00000002
+#define MCDE_MISCHNL_CHNL_C0 0x00000004
+#define MCDE_MISCHNL_CHNL_C1 0x00000008
+
+
+#define MCDE_MISERR (MCDE_BASE + 0x130)
+#define MCDE_MISERR_OVLFERMIS_SHIFT 16
+#define MCDE_MISERR_OVLFERMIS_MASK 0xFFFF
+#define MCDE_MISERR_FUC1MIS 0x00000100
+#define MCDE_MISERR_FUC0MIS 0x00000080
+#define MCDE_MISERR_ROTBFEMIS_SHIFT 5
+#define MCDE_MISERR_ROTBFEMIS_MASK 0x3
+#define MCDE_MISERR_ROTAFEMIS_SHIFT 3
+#define MCDE_MISERR_ROTAFEMIS_MASK 0x3
+#define MCDE_MISERR_SCHBLCKDMIS 0x00000004
+#define MCDE_MISERR_FUBMIS 0x00000002
+#define MCDE_MISERR_FUAMIS 0x00000001
+
+
+#define MCDE_SISPP (MCDE_BASE + 0x134)
+#define MCDE_SISOVL (MCDE_BASE + 0x138)
+#define MCDE_SISCHNL (MCDE_BASE + 0x13C)
+#define MCDE_SISERR (MCDE_BASE + 0x140)
+
+
+#define MCDE_PID (MCDE_BASE + 0x1FC)
+#define MCDE_PID_MAJOR_SHIFT 24
+#define MCDE_PID_MAJOR_MASK 0xFF
+#define MCDE_PID_MINOR_SHIFT 16
+#define MCDE_PID_MINOR_MASK 0xFF
+#define MCDE_PID_DEV_SHIFT 8
+#define MCDE_PID_DEV_MASK 0xFF
+#define MCDE_PID_METALFIX_SHIFT 0
+#define MCDE_PID_METALFIX_MASK 0xFF
+
+
+#define MCDE_EXTSRCA0 (MCDE_BASE + 0x200)
+#define MCDE_EXTSRCA1 (MCDE_BASE + 0x204)
+#define MCDE_EXTSRCA2 (MCDE_BASE + 0x2C8)
+
+
+#define MCDE_EXTSRCCONF (MCDE_BASE + 0x20C)
+#define MCDE_EXTSRCCONF_BEPO 0x00004000
+#define MCDE_EXTSRCCONF_BEBO 0x00002000
+#define MCDE_EXTSRCCONF_BGR 0x00001000
+#define MCDE_EXTSRCCONF_BPP_SHIFT 8
+#define MCDE_EXTSRCCONF_BPP_MASK 0xF
+#define MCDE_EXTSRCCONF_PRI_OVLID_SHIFT 4
+#define MCDE_EXTSRCCONF_PRI_OVLID_MASK 0xF
+#define MCDE_EXTSRCCONF_BUF_NB_SHIFT 2
+#define MCDE_EXTSRCCONF_BUF_NB_MASK 0x3
+#define MCDE_EXTSRCCONF_BUF_ID_SHIFT 0
+#define MCDE_EXTSRCCONF_BUF_ID_MASK 0x3
+
+
+#define MCDE_EXTSRCCR (MCDE_BASE + 0x210)
+#define MCDE_EXTSRCCR_FORCE_FS_DIV 0x00000008
+#define MCDE_EXTSRCCR_FS_DIV_DISABLE 0x00000004
+#define MCDE_EXTSRCCR_MULTIOVL_CTRL 0x00000002
+#define MCDE_EXTSRCCR_SEL_MOD_SHIFT 0
+#define MCDE_EXTSRCCR_SEL_MOD_MASK 0x3
+
+
+#define MCDE_OVLCR (MCDE_BASE + 0x400)
+#define MCDE_OVLCR_ROTBURSTSIZE_SHIFT 28
+#define MCDE_OVLCR_ROTBURSTSIZE_MASK 0xF
+#define MCDE_OVLCR_MAXOUTSTANDING_SHIFT 24
+#define MCDE_OVLCR_MAXOUTSTANDING_MASK 0xF
+#define MCDE_OVLCR_BURSTSIZE_SHIFT 20
+#define MCDE_OVLCR_BURSTSIZE_MASK 0xF
+#define MCDE_OVLCR_STBPRIO_SHIFT 16
+#define MCDE_OVLCR_STBPRIO_MASK 0xF
+#define MCDE_OVLCR_FETCH_ROPC_SHIFT 8
+#define MCDE_OVLCR_GETCH_ROPC_MASK 0xFF
+#define MCDE_OVLCR_OVLB 0x00000080
+#define MCDE_OVLCR_OVLR 0x00000040
+#define MCDE_OVLCR_OVLF 0x00000020
+#define MCDE_OVLCR_ALPHAPMEN 0x00000010
+#define MCDE_OVLCR_CKEYEN 0x00000008
+#define MCDE_OVLCR_COLCCTRL_SHIFT 1
+#define MCDE_OVLCR_COLCCTRL_MASK 0x3
+#define MCDE_OVLCR_OVLEN 0x00000001
+
+
+#define MCDE_OVLCONF (MCDE_BASE + 0x404)
+#define MCDE_OVLCONF_LPF_SHIFT 16
+#define MCDE_OVLCONF_LPF_MASK 0x7FF
+#define MCDE_OVLCONF_EXTSRC_ID_SHIFT 11
+#define MCDE_OVLCONF_EXTSRC_ID_MASK 0xF
+#define MCDE_OVLCONF_PPL_SHIFT 0
+#define MCDE_OVLCONF_PPL_MASK 0x7FF
+
+
+#define MCDE_OVLCONF2 (MCDE_BASE + 0x408)
+#define MCDE_OVLCONF2_PIXELFETCHWATERMARKLEVEL_SHIFT 16
+#define MCDE_OVLCONF2_PIXELFETCHWATERMARKLEVEL_MASK 0x1FFF
+#define MCDE_OVLCONF2_PIXOFF_SHIFT 10
+#define MCDE_OVLCONF2_PIXOFF_MASK 0x3F
+#define MCDE_OVLCONF2_OPQ 0x00000200
+#define MCDE_OVLCONF2_ALPHAVALUE_SHIFT 1
+#define MCDE_OVLCONF2_ALPHAVALUE_MASK 0xFF
+#define MCDE_OVLCONF2_BP 0x00000001
+
+
+#define MCDE_OVLLJINC (MCDE_BASE + 0x40C)
+
+
+#define MCDE_OVLCROP (MCDE_BASE + 0x410)
+#define MCDE_OVLCROP_LMRGN_SHIFT 22
+#define MCDE_OVLCROP_LMRGN_MASK 0x3FF
+#define MCDE_OVLCROP_TMRGN_SHIFT 0
+#define MCDE_OVLCROP_TMRGN_MASK 0x3FFFFF
+
+
+#define MCDE_OVLCOMP (MCDE_BASE + 0x414)
+#define MCDE_OVLCOMP_Z_SHIFT 27
+#define MCDE_OVLCOMP_Z_MASK 0xF
+#define MCDE_OVLCOMP_YPOS_SHIFT 16
+#define MCDE_OVLCOMP_YPOS_MASK 0x7FF
+#define MCDE_OVLCOMP_CH_ID_SHIFT 11
+#define MCDE_OVLCOMP_CH_ID_MASK 0xF
+#define MCDE_OVLCOMP_XPOS_SHIFT 0
+#define MCDE_OVLCOMP_XPOS_MASK 0x7FF
+
+
+#define MCDE_CHNLCONF (MCDE_BASE + 0x600)
+#define MCDE_CHNLCONF_LPF_SHIFT 16
+#define MCDE_CHNLCONF_LPF_MASK 0x7FF
+#define MCDE_CHNLCONF_PPL_SHIFT 0
+#define MCDE_CHNLCONF_PPL_MASK 0x7FF
+
+
+#define MCDE_CHNLSTAT (MCDE_BASE + 0x604)
+#define MCDE_CHNLSTAT_CHNLBLBCKGND_EN 0x00010000
+#define MCDE_CHNLSTAT_CHNLA 0x00000002
+#define MCDE_CHNLSTAT_CHNLRD 0x00000001
+
+
+#define MCDE_CHNLSYNCHMOD (MCDE_BASE + 0x608)
+#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_SHIFT 2
+#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_MASK 0x7
+#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_SHIFT 0
+#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_MASK 0x3
+
+
+#define MCDE_CHNLSYNCHSW (MCDE_BASE + 0x60C)
+#define MCDE_CHNLSYNCHSW_SW_TRIG 0x00000001
+
+
+#define MCDE_CHNLBCKGNDCOL (MCDE_BASE + 0x610)
+#define MCDE_CHNLBCKGNDCOL_R_SHIFT 16
+#define MCDE_CHNLBCKGNDCOL_R_MASK 0xFF
+#define MCDE_CHNLBCKGNDCOL_G_SHIFT 8
+#define MCDE_CHNLBCKGNDCOL_G_MASK 0xFF
+#define MCDE_CHNLBCKGNDCOL_B_SHIFT 0
+#define MCDE_CHNLBCKGNDCOL_B_MASK 0xFF
+
+
+#define MCDE_CHNLPRIO (MCDE_BASE + 0x614)
+#define MCDE_CHNLPRIO_CHNLPRIO_SHIFT 0
+#define MCDE_CHNLPRIO_CHNLPRIO_MASK 0xF
+
+
+#define MCDE_CR0 (MCDE_BASE + 0x800)
+#define MCDE_CR0_ROTBURSTSIZE_SHIFT 25
+#define MCDE_CR0_ROTBURSTSIZE_MASK 0x7F
+#define MCDE_CR0_ROTEN 0x01000000
+#define MCDE_CR0_ALPHABLEND_SHIFT 16
+#define MCDE_CR0_ALPHABLEND_MASK 0xFF
+#define MCDE_CR0_OLEDEN 0x00008000
+#define MCDE_CR0_PALMODE 0x00004000
+#define MCDE_CR0_FLICKFORMAT 0x00002000
+#define MCDE_CR0_FLICKMODE_SHIFT 11
+#define MCDE_CR0_FLICKMODE_MASK 0x3
+#define MCDE_CR0_BLENDCTRL 0x00000400
+#define MCDE_CR0_KEYCTRL_SHIFT 7
+#define MCDE_CR0_KEYCTRL_MASK 0x7
+#define MCDE_CR0_GAMEN 0x00000040
+#define MCDE_CR0_DITHEN 0x00000020
+#define MCDE_CR0_PALEN 0x00000010
+#define MCDE_CR0_AFLICKEN 0x00000008
+#define MCDE_CR0_BLENDEN 0x00000004
+#define MCDE_CR0_POWEREN 0x00000002
+#define MCDE_CR0_FLOEN 0x00000001
+
+
+#define MCDE_CR1 (MCDE_BASE + 0x804)
+#define MCDE_CR1_TEFFECTEN 0x80000000
+#define MCDE_CR1_CLKTYPE 0x40000000
+#define MCDE_CR1_BCD 0x20000000
+#define MCDE_CR1_OUTBPP_SHIFT 25
+#define MCDE_CR1_OUTBPP_MASK 0xF
+#define MCDE_CR1_CDWIN_SHIFT 13
+#define MCDE_CR1_CDWIN_MASK 0xF
+#define MCDE_CR1_CLKSEL_SHIFT 10
+#define MCDE_CR1_CLKSEL_MASK 0x7
+#define MCDE_CR1_PCD_SHIFT 0
+#define MCDE_CR1_PCD_MASK 0x3FF
+
+
+#define MCDE_COLKEY (MCDE_BASE + 0x808)
+#define MCDE_COLKEY_KEYA_SHIFT 24
+#define MCDE_COLKEY_KEYA_MASK 0xFF
+#define MCDE_COLKEY_KEYR_SHIFT 16
+#define MCDE_COLKEY_KEYR_MASK 0xFF
+#define MCDE_COLKEY_KEYG_SHIFT 8
+#define MCDE_COLKEY_KEYG_MASK 0xFF
+#define MCDE_COLKEY_KEYB_SHIFT 0
+#define MCDE_COLKEY_KEYB_MASK 0xFF
+
+
+#define MCDE_FCOLKEY (MCDE_BASE + 0x80C)
+#define MCDE_FCOLKEY_FKEYA_SHIFT 24
+#define MCDE_FCOLKEY_FKEYA_MASK 0xFF
+#define MCDE_FCOLKEY_FKEYR_SHIFT 16
+#define MCDE_FCOLKEY_FKEYR_MASK 0xFF
+#define MCDE_FCOLKEY_FKEYG_SHIFT 8
+#define MCDE_FCOLKEY_FKEYG_MASK 0xFF
+#define MCDE_FCOLKEY_FKEYB_SHIFT 0
+#define MCDE_FCOLKEY_FKEYB_MASK 0xFF
+
+
+#define MCDE_RGBCONV1 (MCDE_BASE + 0x810)
+#define MCDE_RGBCONV1_YR_RED_SHIFT 16
+#define MCDE_RGBCONV1_YR_RED_MASK 0x7FF
+#define MCDE_RGBCONV1_YR_GREEN_SHIFT 0
+#define MCDE_RGBCONV1_YR_GREEN_MASK 0x7FF
+
+
+#define MCDE_RGBCONV2 (MCDE_BASE + 0x814)
+#define MCDE_RGBCONV2_YR_BLUE_SHIFT 16
+#define MCDE_RGBCONV2_YR_BLUE_MASK 0x7FF
+#define MCDE_RGBCONV2_CR_RED_SHIFT 0
+#define MCDE_RGBCONV2_CR_RED_MASK 0x7FF
+
+
+#define MCDE_RGBCONV3 (MCDE_BASE + 0x818)
+#define MCDE_RGBCONV3_CR_GREEN_SHIFT 16
+#define MCDE_RGBCONV3_CR_GREEN_MASK 0x7FF
+#define MCDE_RGBCONV3_CR_BLUE_SHIFT 0
+#define MCDE_RGBCONV3_CR_BLUE_MASK 0x7FF
+
+
+#define MCDE_RGBCONV4 (MCDE_BASE + 0x81C)
+#define MCDE_RGBCONV4_CB_RED_SHIFT 16
+#define MCDE_RGBCONV4_CB_RED_MASK 0x7FF
+#define MCDE_RGBCONV4_CB_GREEN_SHIFT 0
+#define MCDE_RGBCONV4_CB_GREEN_MASK 0x7FF
+
+
+#define MCDE_RGBCONV5 (MCDE_BASE + 0x820)
+#define MCDE_RGBCONV5_CB_BLUE_SHIFT 16
+#define MCDE_RGBCONV5_CB_BLUE_MASK 0x7FF
+#define MCDE_RGBCONV5_OFF_RED_SHIFT 0
+#define MCDE_RGBCONV5_OFF_RED_MASK 0x7FF
+
+
+#define MCDE_RGBCONV6 (MCDE_BASE + 0x824)
+#define MCDE_RGBCONV6_OFF_GREEN_SHIFT 16
+#define MCDE_RGBCONV6_OFF_GREEN_MASK 0x7FF
+#define MCDE_RGBCONV6_OFF_BLUE_SHIFT 0
+#define MCDE_RGBCONV6_OFF_BLUE_MASK 0x7FF
+
+
+#define MCDE_FFCOEF0 (MCDE_BASE + 0x828)
+#define MCDE_FFCOEF0_TO_SHIFT 24
+#define MCDE_FFCOEF0_TO_MASK 0x0xF
+#define MCDE_FFCOEF0_COEFF0_N3_SHIFT 16
+#define MCDE_FFCOEF0_COEFF0_N3_MASK 0xFF
+#define MCDE_FFCOEF0_COEFF0_N2_SHIFT 8
+#define MCDE_FFCOEF0_COEFF0_N2_MASK 0xFF
+#define MCDE_FFCOEF0_COEFF0_N1_SHIFT 0
+#define MCDE_FFCOEF0_COEFF0_N1_MASK 0xFF
+
+
+#define MCDE_FFCOEF1 (MCDE_BASE + 0x82C)
+#define MCDE_FFCOEF1_T1_SHIFT 24
+#define MCDE_FFCOEF1_T1_MASK 0x0xF
+#define MCDE_FFCOEF1_COEFF1_N3_SHIFT 16
+#define MCDE_FFCOEF1_COEFF1_N3_MASK 0xFF
+#define MCDE_FFCOEF1_COEFF1_N2_SHIFT 8
+#define MCDE_FFCOEF1_COEFF1_N2_MASK 0xFF
+#define MCDE_FFCOEF1_COEFF1_N1_SHIFT 0
+#define MCDE_FFCOEF1_COEFF1_N1_MASK 0xFF
+
+
+#define MCDE_FFCOEF2 (MCDE_BASE + 0x830)
+#define MCDE_FFCOEF2_T2_SHIFT 24
+#define MCDE_FFCOEF2_T2_MASK 0x0xF
+#define MCDE_FFCOEF2_COEFF2_N3_SHIFT 16
+#define MCDE_FFCOEF2_COEFF2_N3_MASK 0xFF
+#define MCDE_FFCOEF2_COEFF2_N2_SHIFT 8
+#define MCDE_FFCOEF2_COEFF2_N2_MASK 0xFF
+#define MCDE_FFCOEF2_COEFF2_N1_SHIFT 0
+#define MCDE_FFCOEF2_COEFF2_N1_MASK 0xFF
+
+
+#define MCDE_TVCR (MCDE_BASE + 0x838)
+#define MCDE_TVCR_AVRGEN 0x00000100
+#define MCDE_TVCR_SDTVMODE_SHIFT 6
+#define MCDE_TVCR_SDTVMODE_MASK 0x3
+#define MCDE_TVCR_TVMODE_SHIFT 3
+#define MCDE_TVCR_TVMODE_MASK 0x7
+#define MCDE_TVCR_IFIELD 0x00000004
+#define MCDE_TVCR_INTEREN 0x00000002
+#define MCDE_TVCR_SEL_MOD 0x00000001
+
+
+#define MCDE_TVBL1 (MCDE_BASE + 0x83C)
+#define MCDE_TVBL1_BSL1_SHIFT 16
+#define MCDE_TVBL1_BSL1_MASK 0x7FF
+#define MCDE_TVBL1_BEL1_SHIFT 0
+#define MCDE_TVBL1_BEL1_MASK 0x7FF
+
+
+#define MCDE_TVISL (MCDE_BASE + 0x840)
+#define MCDE_TVISL_FSL2_SHIFT 16
+#define MCDE_TVISL_FSL2_MASK 0x7FF
+#define MCDE_TVISL_FSL1_SHIFT 0
+#define MCDE_TVISL_FSL1_MASK 0x7FF
+
+
+#define MCDE_TVDVO (MCDE_BASE + 0x844)
+#define MCDE_TVDVO_DVO2_SHIFT 16
+#define MCDE_TVDVO_DVO2_MASK 0x7FF
+#define MCDE_TVDVO_DVO1_SHIFT 0
+#define MCDE_TVDVO_DVO1_MASK 0x7FF
+
+
+#define MCDE_TVTIM1 (MCDE_BASE + 0x84C)
+#define MCDE_TVTIM1_DHO_SHIFT 0
+#define MCDE_TVTIM1_DHO_MASK 0x7FF
+
+
+#define MCDE_TVLBALW (MCDE_BASE + 0x850)
+#define MCDE_TVLBALW_ALW_SHIFT 16
+#define MCDE_TVLBALW_ALW_MASK 0x7FF
+#define MCDE_TVLBALW_LBW_SHIFT 0
+#define MCDE_TVLBALW_LBW_MASK 0x7FF
+
+
+#define MCDE_TVBL2 (MCDE_BASE + 0x854)
+#define MCDE_TVBL2_BSL2_SHIFT 16
+#define MCDE_TVBL2_BSL2_MASK 0x7FF
+#define MCDE_TVBL2_BEL2_SHIFT 0
+#define MCDE_TVBL2_BEL2_MASK 0x7FF
+
+
+#define MCDE_TVBLU (MCDE_BASE + 0x858)
+#define MCDE_TVBLU_TVBCR_SHIFT 16
+#define MCDE_TVBLU_TVBCR_MASK 0xFF
+#define MCDE_TVBLU_TVBCB_SHIFT 8
+#define MCDE_TVBLU_TVBCB_MASK 0xFF
+#define MCDE_TVBLU_TVBLU_SHIFT 0
+#define MCDE_TVBLU_TVBLU_MASK 0xFF
+
+
+#define MCDE_LDCTIM0 (MCDE_BASE + 0x85C)
+#define MCDE_LDCTIM0_REVVAEN 0x80000000
+#define MCDE_LDCTIM0_REVTGEN 0x40000000
+#define MCDE_LDCTIM0_REVLOADSEL_SHIFT 28
+#define MCDE_LDCTIM0_REVLOADSEL_MASK 0x3
+#define MCDE_LDCTIM0_REVDEL1_SHIFT 24
+#define MCDE_LDCTIM0_REVDEL1_MASK 0xF
+#define MCDE_LDCTIM0_REVDEL0_SHIFT 16
+#define MCDE_LDCTIM0_REVDEL0_MASK 0xFF
+#define MCDE_LDCTIM0_PSVAEN 0x00008000
+#define MCDE_LDCTIM0_PSTGEN 0x00004000
+#define MCDE_LDCTIM0_PSLOADSEL_SHIFT 12
+#define MCDE_LDCTIM0_PSLOADSEL_MASK 0x3
+#define MCDE_LDCTIM0_PSDEL1_SHIFT 8
+#define MCDE_LDCTIM0_PSDEL1_MASK 0xF
+#define MCDE_LDCTIM0_PSDEL0_SHIFT 0
+#define MCDE_LDCTIM0_PSDEL0_MASK 0xFF
+
+
+#define MCDE_LCDTIM1 (MCDE_BASE + 0x860)
+#define MCDE_LCDTIM1_IOE 0x00800000
+#define MCDE_LCDTIM1_IPC 0x00400000
+#define MCDE_LCDTIM1_IHS 0x00200000
+#define MCDE_LCDTIM1_IVS 0x00100000
+#define MCDE_LCDTIM1_IVP 0x00080000
+#define MCDE_LCDTIM1_ICLSPL 0x00040000
+#define MCDE_LCDTIM1_ICLREV 0x00020000
+#define MCDE_LCDTIM1_ICLSP 0x00010000
+#define MCDE_LCDTIM1_SPLVAEN 0x00008000
+#define MCDE_LCDTIM1_SPLTGEN 0x00004000
+#define MCDE_LCDTIM1_SPLLOADSEL_SHIFT 12
+#define MCDE_LCDTIM1_SPLLOADSEL_MASK 0x3
+#define MCDE_LCDTIM1_SPLDEL1_SHIFT 8
+#define MCDE_LCDTIM1_SPLDEL1_MASK 0xF
+#define MCDE_LCDTIM1_SPLDEL0_SHIFT 0
+#define MCDE_LCDTIM1_SPLDEL0_MASK 0xFF
+
+
+#define MCDE_DITCTRL (MCDE_BASE + 0x864)
+#define MCDE_DITCTRL_FOFFY_SHIFT 10
+#define MCDE_DITCTRL_FOFFY_MASK 0x1F
+#define MCDE_DITCTRL_FOFFX_SHIFT 5
+#define MCDE_DITCTRL_FOFFX_MASK 0x1F
+#define MCDE_DITCTRL_MASK 0x00000010
+#define MCDE_DITCTRL_MODE_SHIFT 2
+#define MCDE_DITCTRL_MODE_MASK 0x3
+#define MCDE_DITCTRL_COMP 0x00000002
+#define MCDE_DITCTRL_TEMP 0x00000001
+
+
+#define MCDE_DITOFF (MCDE_BASE + 0x868)
+#define MCDE_DITOFF_YB_SHIFT 24
+#define MCDE_DITOFF_YB_MASK 0x1F
+#define MCDE_DITOFF_XB_SHIFT 16
+#define MCDE_DITOFF_XB_MASK 0x1F
+#define MCDE_DITOFF_YG_SHIFT 8
+#define MCDE_DITOFF_YG_MASK 0x1F
+#define MCDE_DITOFF_XG_SHIFT 0
+#define MCDE_DITOFF_XG_MASK 0x1F
+
+
+#define MCDE_PAL0 (MCDE_BASE + 0x86C)
+#define MCDE_PAL0_GREEN_SHIFT 16
+#define MCDE_PAL0_GREEN_MASK 0xFFF
+#define MCDE_PAL0_BLUE_SHIFT 0
+#define MCDE_PAL0_BLUE_MASK 0xFFF
+
+
+#define MCDE_PAL1 (MCDE_BASE + 0x870)
+#define MCDE_PAL1_RED_SHIFT 0
+#define MCDE_PAL1_RED_MASK 0xFFF
+
+
+#define MCDE_ROTADD0 (MCDE_BASE + 0x874)
+//#define MCDE_ROTADD0_SHIFT 3
+//#define MCDE_ROTADD0_MASK
+#define MCDE_ROTADD1 (MCDE_BASE + 0x878)
+
+
+#define MCDE_ROTCONF (MCDE_BASE + 0x87C)
+#define MCDE_ROTCONF_RD_ROPC_SHIFT 24
+#define MCDE_ROTCONF_RD_ROPC_MASK 0xFF
+#define MCDE_ROTCONF_WR_ROPC_SHIFT 16
+#define MCDE_ROTCONF_WR_ROPC_MASK 0xFF
+#define MCDE_ROTCONF_STRIP_WIDTH_SHIFT 8
+#define MCDE_ROTCONF_STRIP_WIDTH_MASK 0xFF
+#define MCDE_ROTCONF_RD_MAXOUT_SHIFT 6
+#define MCDE_ROTCONF_RD_MAXOUT_MASK 0x3
+#define MCDE_ROTCONF_WR_MAXOUT_SHIFT 4
+#define MCDE_ROTCONF_WR_MAXOUT_MASK 0x3
+#define MCDE_ROTCONF_ROTDIR 0x00000008
+#define MCDE_ROTCONF_ROTBURSTSIZE_SHIFT 0
+#define MCDE_ROTCONF_ROTBURSTSIZE_MASK 0x7
+
+
+#define MCDE_SYNCHCONF (MCDE_BASE + 0x880)
+#define MCDE_SYNCHCONF_SWINTVCNT_SHIFT 18
+#define MCDE_SYNCHCONF_SWINTVCNT_MASK 0x3FFF
+#define MCDE_SYNCHCONF_SWINTVEVENT_SHIFT 16
+#define MCDE_SYNCHCONF_SWINTVEVENT_MASK 0x3
+#define MCDE_SYNCHCONF_HWREQVCNT_SHIFT 2
+#define MCDE_SYNCHCONF_HWREQVCNT_MASK 0x3FFF
+#define MCDE_SYNCHCONF_HWREQVEVENT_SHIFT 0
+#define MCDE_SYNCHCONF_HWREQVEVENT_MASK 0x3
+
+
+#define MCDE_GAM0 (MCDE_BASE + 0x888)
+#define MCDE_GAM0_BLUE_SHIFT 0
+#define MCDE_GAM0_BLUE_MASK 0x00FFFFFF
+
+
+#define MCDE_GAM1 (MCDE_BASE + 0x88C)
+#define MCDE_GAM1_GREEN_SHIFT 0
+#define MCDE_GAM1_GREEN_MASK 0x00FFFFFF
+
+
+#define MCDE_GAM2 (MCDE_BASE + 0x890)
+#define MCDE_GAM2_RED_SHIFT 0
+#define MCDE_GAM2_RED_MASK 0x00FFFFFF
+
+
+#define MCDE_OLEDCONV1 (MCDE_BASE + 0x894)
+#define MCDE_OLEDCONV1_ALPHA_GREEN_SHIFT 16
+#define MCDE_OLEDCONV1_ALPHA_GREEN_MASK 0x3FFF
+#define MCDE_OLEDCONV1_ALPHA_RED_SHIFT 0
+#define MCDE_OLEDCONV1_ALPHA_RED_MASK 0x3FFF
+
+
+#define MCDE_OLEDCONV2 (MCDE_BASE + 0x898)
+#define MCDE_OLEDCONV2_BETA_RED_SHIFT 16
+#define MCDE_OLEDCONV2_BETA_RED_MASK 0x3FFF
+#define MCDE_OLEDCONV2_ALPHA_BLUE_SHIFT 0
+#define MCDE_OLEDCONV2_ALPHA_BLUE_MASK 0x3FFF
+
+
+#define MCDE_OLEDCONV3 (MCDE_BASE + 0x89C)
+#define MCDE_OLEDCONV3_BETA_BLUE_SHIFT 16
+#define MCDE_OLEDCONV3_BETA_BLUE_MASK 0x3FFF
+#define MCDE_OLEDCONV3_BETA_GREEN_SHIFT 0
+#define MCDE_OLEDCONV3_BETA_GREEN_MASK 0x3FFF
+
+
+#define MCDE_OLEDCONV4 (MCDE_BASE + 0x8A0)
+#define MCDE_OLEDCONV4_GAMMA_GREEN_SHIFT 16
+#define MCDE_OLEDCONV4_GAMMA_GREEN_MASK 0x3FFF
+#define MCDE_OLEDCONV4_GAMMA_RED_SHIFT 0
+#define MCDE_OLEDCONV4_GAMMA_RED_MASK 0x3FFF
+
+
+#define MCDE_OLEDCONV5 (MCDE_BASE + 0x8A4)
+#define MCDE_OLEDCONV5_OFF_RED_SHIFT 16
+#define MCDE_OLEDCONV5_OFF_RED_MASK 0x3FFF
+#define MCDE_OLEDCONV5_GAMMA_BLUE_SHIFT 0
+#define MCDE_OLEDCONV5_GAMMA_BLUE_MASK 0x3FFF
+
+
+#define MCDE_OLEDCONV6 (MCDE_BASE + 0x8A8)
+#define MCDE_OLEDCONV6_OFF_BLUE_SHIFT 16
+#define MCDE_OLEDCONV6_OFF_BLUE_MASK 0x3FFF
+#define MCDE_OLEDCONV6_OFF_GREEN_SHIFT 0
+#define MCDE_OLEDCONV6_OFF_GREEN_MASK 0x3FFF
+
+
+#define MCDE_CRC (MCDE_BASE + 0xC00)
+#define MCDE_CRC_CLAMPC1EN 0x80000000
+#define MCDE_CRC_SYNCCTRL_SHIFT 29
+#define MCDE_CRC_SYNCCTRL_MASK 0x3
+#define MCDE_CRC_RES2POL 0x10000000
+#define MCDE_CRC_RES1POL 0x08000000
+#define MCDE_CRC_RD2POL 0x04000000
+#define MCDE_CRC_RD1POL 0x02000000
+#define MCDE_CRC_WR2POL 0x01000000
+#define MCDE_CRC_WR1POL 0x00800000
+#define MCDE_CRC_CD2POL 0x00400000
+#define MCDE_CRC_CD1POL 0x00200000
+#define MCDE_CRC_CS2POL 0x00100000
+#define MCDE_CRC_CS1POL 0x00080000
+#define MCDE_CRC_RESEN 0x00040000
+#define MCDE_CRC_CS2EN 0x00020000
+#define MCDE_CRC_CS1EN 0x00010000
+#define MCDE_CRC_YUVCONVC1EN 0x00008000
+#define MCDE_CRC_CLKSEL_SHIFT 13
+#define MCDE_CRC_CLKSEL_MASK 0x3
+#define MCDE_CRC_INBAND2 0x00001000
+#define MCDE_CRC_INBAND1 0x00000800
+#define MCDE_CRC_SIZE2 0x00000400
+#define MCDE_CRC_SIZE1 0x00000200
+#define MCDE_CRC_SYCEN1 0x00000100
+#define MCDE_CRC_SYCEN0 0x00000080
+#define MCDE_CRC_SYNCSEL 0x00000040
+#define MCDE_CRC_WMLVL2 0x00000020
+#define MCDE_CRC_WMLVL1 0x00000010
+#define MCDE_CRC_C2EN 0x00000008
+#define MCDE_CRC_C1EN 0x00000004
+#define MCDE_CRC_POWEREN 0x00000002
+#define MCDE_CRC_FLOEN 0x00000001
+
+
+#define MCDE_PBCCRC (MCDE_BASE + 0xC04)
+#define MCDE_PBCCRC_BPP_SHIFT 13
+#define MCDE_PBCCRC_BPP_MASK 0x7
+#define MCDE_PBCCRC_PDCTRL 0x00001000
+#define MCDE_PBCCRC_PDM_SHIFT 8
+#define MCDE_PBCCRC_PDM_MASK 0x3
+#define MCDE_PBCCRC_BSDM_SHIFT 4
+#define MCDE_PBCCRC_BSDM_MASK 0x7
+#define MCDE_PBCCRC_BSCM_SHIFT 0
+#define MCDE_PBCCRC_BSCM_MASK 0x7
+
+
+#define MCDE_PBCBMRC (MCDE_BASE + 0xC0C)
+#define MCDE_PBCBCRC (MCDE_BASE + 0xC34)
+
+
+#define MCDE_VSCRC (MCDE_BASE + 0xC5C)
+#define MCDE_VSCRC_VSDBL_SHIFT 29
+#define MCDE_VSCRC_VSDBL_MASK 0x7
+#define MCDE_VSCRC_VSSEL 0x10000000
+#define MCDE_VSCRC_VSPOL 0x08000000
+#define MCDE_VSCRC_VSPDIV_SHIFT 24
+#define MCDE_VSCRC_VSPDIV_MASK 0x7
+#define MCDE_VSCRC_VSPMAX_SHIFT 12
+#define MCDE_VSCRC_VSPMAX_MASK 0xFFF
+#define MCDE_VSCRC_VSPMIN_SHIFT 0
+#define MCDE_VSCRC_VSPMIN_MASK 0xFFF
+
+
+#define MCDE_SCTRC (MCDE_BASE + 0xC64)
+#define MCDE_SCTRC_TRDELC_SHIFT 16
+#define MCDE_SCTRC_TRDELC_MASK 0xFFF
+#define MCDE_SCTRC_SYNCDELC1_SHIFT 8
+#define MCDE_SCTRC_SYNCDELC1_MASK 0xFF
+#define MCDE_SCTRC_SYNCDELC0_SHIFT 0
+#define MCDE_SCTRC_SYNCDELC0_MASK 0xFF
+
+
+#define MCDE_SCSRC (MCDE_BASE + 0xC68)
+#define MCDE_SCSRC_VSTAC1 0x00000002
+#define MCDE_SCSRC_VSTAC0 0x00000001
+
+
+#define MCDE_BCNR (MCDE_BASE + 0xC6C)
+#define MCDE_BCNR_BCN_SHIFT 0
+#define MCDE_BCNR_BCN_MASK 0xFF
+
+
+#define MCDE_CSCDTR (MCDE_BASE + 0xC74)
+#define MCDE_CSCDTR_CSCDDEACT_SHIFT 8
+#define MCDE_CSCDTR_CSCDDEACT_MASK 0xFF
+#define MCDE_CSCDTR_CSCDACT_SHIFT 0
+#define MCDE_CSCDTR_CSCDACT_MASK 0xFF
+
+
+#define MCDE_RDWRTR (MCDE_BASE + 0xC7C)
+#define MCDE_RDWRTR_MOTINT 0x00010000
+#define MCDE_RDWRTR_RWDEACT_SHIFT 8
+#define MCDE_RDWRTR_RWDEACT_MASK 0xFF
+#define MCDE_RDWRTR_RWACT_SHIFT 0
+#define MCDE_RDWRTR_RWACT_MASK 0xFF
+
+
+#define MCDE_DOTR (MCDE_BASE + 0xC84)
+#define MCDE_DOTR_DODEACT_SHIFT 8
+#define MCDE_DOTR_DODEACT_MASK 0xFF
+#define MCDE_DOTR_DOACT_SHIFT 0
+#define MCDE_DOTR_DOACT_MASK 0xFF
+
+
+#define MCDE_WCMDC (MCDE_BASE + 0xC8C)
+#define MCDE_WDATADC (MCDE_BASE + 0xC94)
+
+
+#define MCDE_RDATADC (MCDE_BASE + 0xC9C)
+#define MCDE_RDATADC_STARTREAD 0x00010000
+#define MCDE_RDATADC_DATAREADFROMDISPLAYMODULE_SHIFT 0
+#define MCDE_RDATADC_DATAREADFROMDISPLAYMODULE_MASK 0xFF
+
+
+#define MCDE_STATC (MCDE_BASE + 0xCA4)
+#define MCDE_STATC_FIFOCMDFULL1 0x00000200
+#define MCDE_STATC_FIFOCMDEMPTY1 0x00000100
+#define MCDE_STATC_FIFOFULL1 0x00000080
+#define MCDE_STATC_FIFOEMPTY1 0x00000040
+#define MCDE_STATC_STATBUSY1 0x00000020
+#define MCDE_STATC_FIFOCMDFULL0 0x00000010
+#define MCDE_STATC_FIFOCMDEMPTY0 0x00000008
+#define MCDE_STATC_FIFOFULL0 0x00000004
+#define MCDE_STATC_FIFOEMPTY0 0x00000002
+#define MCDE_STATC_STATBUSY0 0x00000001
+
+
+#define MCDE_CTRLC (MCDE_BASE + 0xCA8)
+#define MCDE_CTRLC_FIFOWTRMRK_SHIFT 0
+#define MCDE_CTRLC_FIFOWTRMRK_MASK 0xFF
+
+
+#define MCDE_DSICONF0 (MCDE_BASE + 0xE00)
+#define MCDE_DSICONF0_PACKING_SHIFT 20
+#define MCDE_DSICONF0_PACKING_MASK 0x7
+#define MCDE_DSICONF0_DCSVID_NOTGEN 0x00040000
+#define MCDE_DSICONF0_BYTE_SWAP 0x00020000
+#define MCDE_DSICONF0_BIT_SWAP 0x00010000
+#define MCDE_DSICONF0_CMD8 0x00002000
+#define MCDE_DSICONF0_VID_MODE 0x00001000
+#define MCDE_DSICONF0_BLANKING_SHIFT 0
+#define MCDE_DSICONF0_BLANKING_MASK 0xFF
+
+
+#define MCDE_DSIFRAME (MCDE_BASE + 0xE04)
+
+#define MCDE_DSIPKT (MCDE_BASE + 0xE08)
+#define MCDE_DSIPKT_PACKET_SHIFT 0
+#define MCDE_DSIPKT_PACKET_MASK 0xFFFF
+
+
+#define MCDE_DSISYNC (MCDE_BASE + 0xE0C)
+#define MCDE_DSISYNC_SW_SHIFT 16
+#define MCDE_DSISYNC_SW_MASK 0xFFF
+#define MCDE_DSISYNC_DMA_SHIFT 0
+#define MCDE_DSISYNC_DMA_MASK 0xFFF
+
+
+#define MCDE_DSICMDW (MCDE_BASE + 0xE10)
+#define MCDE_DSICMDW_CMDW_START_SHIFT 16
+#define MCDE_DSICMDW_CMDW_START_MASK 0xFFFF
+#define MCDE_DSICMDW_CMDW_CONTINUE_SHIFT 0
+#define MCDE_DSICMDW_CMDW_CONTINUE_MASK 0xFFFF
+
+
+#define MCDE_DSIDELAY0 (MCDE_BASE + 0xE14)
+#define MCDE_DSIDELAY0_INTPKTDEL_SHIFT 0
+#define MCDE_DSIDELAY0_INTPKTDEL_MASK 0xFFFF
+
+
+#define MCDE_DSIDELAY1 (MCDE_BASE + 0xE18)
+#define MCDE_DSIDELAY1_FRAMESTARTDEL_SHIFT 16
+#define MCDE_DSIDELAY1_FRAMESTARTDEL_MASK 0xFF
+#define MCDE_DSIDELAY1_TEREQDEL_SHIFT 0
+#define MCDE_DSIDELAY1_TEREQDEL_MASK 0xFFF
+
+
diff --git a/arch/arm/mach-ux500/include/mach/mcde_common.h b/arch/arm/mach-ux500/include/mach/mcde_common.h
new file mode 100755
index 00000000000..fb992a6967b
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/mcde_common.h
@@ -0,0 +1,173 @@
+/*---------------------------------------------------------------------------*/
+/* Copyrighti (C) STEricsson 2009. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it */
+/* under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, */
+/* or (at your option)any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */
+/* the GNU Lesser General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*---------------------------------------------------------------------------*/
+
+#ifndef _MCDE_COMMON_H_
+#define _MCDE_COMMON_H_
+#include <linux/fb.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/bit_mask.h>
+#include <mach/mcde.h>
+#include <mach/mcde_reg.h>
+#include <mach/dsi.h>
+#include <mach/dsi_reg.h>
+
+#define MCDE_NAME "DRIVER MCDE"
+
+#define MCDE_DEFAULT_LOG_LEVEL 3
+#ifdef CONFIG_FB_NDK_MCDE
+extern int mcde_debug;
+module_param(mcde_debug, int, 0644);
+#endif
+#ifdef CONFIG_FB_NDK_MCDE
+MODULE_PARM_DESC(mcde_debug,"Debug level for messages");
+#define dbgprintk(num, format, args...) \
+ do { \
+ if(num >= mcde_debug ) \
+ printk("MCDE:"format, ##args); \
+ } while(0)
+#else
+#define dbgprintk(num, format, args...) \
+ do { \
+ printk("MCDE:"format, ##args); \
+ } while(0)
+#endif
+
+#define MCDE_DEBUG_INFO 1
+#define MCDE_ERROR_INFO 3
+
+/** Global data */
+
+#define MAX_LPF 1280
+#define MAX_PPL 1920
+#define NUM_MCDE_FLOWS 4
+#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
+#define NUM_OVERLAYS 6
+#define NUM_EXT_SRC 10
+#define NUM_MCDE_CHANNELS 4
+#else
+#define NUM_OVERLAYS 16
+#define NUM_EXT_SRC 16
+#define NUM_MCDE_CHANNELS 16
+#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
+#define NUM_FLOWS_A_B 2
+#define NUM_DSI_LINKS 3
+#define NUM_DSI_CHANNEL 6
+#define MCDE_MAX_FRAMEBUFF 16
+#define COLCONV_COEFF_OFF 6
+
+/** clcd events for double buffering */
+struct clcd_event_struct {
+ spinlock_t lock;
+ int event;
+ wait_queue_head_t wait;
+ unsigned int base;
+};
+
+/** bitmap of which overlays are in use (set) and unused (cleared) */
+//static u32 mcde_ovl_bmp;
+
+/** MCDE private struct - pointer available in fbinfo */
+struct mcdefb_info {
+ struct mcde_channel_data *chnl_info;
+ mcde_ch_id chid;
+ mcde_video_mode video_mode;
+ mcde_fifo_output fifoOutput;
+ mcde_output_conf output_conf;
+ mcde_dsi_clk_config clk_config;
+ mcde_ch_id dsi_formatter_plugged_channel[NUM_DSI_CHANNEL];
+ mcde_dsi_channel mcdeDsiChnl;
+ mcde_out_bpp outbpp;
+ int bpp16_type;
+ u8 bgrinput;
+ u8 isHwInitalized;
+ u16 palette_size;
+ u32 cmap[16];
+
+ mcde_ch_id pixel_pipeline;
+ u32 vcomp_irq;
+ u32 dsi_formatter;
+ u32 dsi_mode;
+
+ /** phy-virtual addresses allocated for framebuffer and overlays */
+ struct mcde_addrmap buffaddr[MCDE_MAX_FRAMEBUFF*2];
+ struct mcde_addrmap rotationbuffaddr0;
+ struct mcde_addrmap rotationbuffaddr1;
+
+ /** total number of overlays used in the system */
+ u8 tot_ovl_used;
+
+ /** bitmap of which overlays are in use (set) and unused (cleared) */
+ u16 mcde_cur_ovl_bmp;
+ u16 mcde_ovl_bmp_arr[MCDE_MAX_FRAMEBUFF];
+ spinlock_t mcde_spin_lock;
+
+ /** event for double buffering */
+ struct clcd_event_struct clcd_event;
+ u8 tvout;
+ u32 actual_bpp;
+#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
+ struct mcde_top_reg __iomem *regbase;
+#else
+ struct mcde_register_base __iomem * regbase;
+#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
+ struct mcde_ext_src_reg __iomem * extsrc_regbase[NUM_EXT_SRC];
+ struct mcde_ovl_reg __iomem * ovl_regbase[NUM_OVERLAYS];
+#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
+ struct mcde_chnl_conf_reg __iomem *ch_regbase1[NUM_MCDE_CHANNELS];
+ struct mcde_chAB_reg __iomem *ch_regbase2[NUM_FLOWS_A_B];
+ struct mcde_chC0C1_reg __iomem *ch_c_reg;
+#else
+ struct mcde_ch_synch_reg __iomem *ch_regbase1[NUM_MCDE_CHANNELS];
+ struct mcde_ch_reg __iomem *ch_regbase2[NUM_FLOWS_A_B];
+ struct mcde_chc_reg __iomem *ch_c_reg;
+#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
+ struct mcde_dsi_reg __iomem *mcde_dsi_channel_reg[NUM_DSI_CHANNEL];
+ volatile u32 __iomem *mcde_clkdsi;
+ struct dsi_link_registers __iomem *dsi_lnk_registers[NUM_DSI_LINKS];
+ volatile u32 __iomem *prcm_mcde_clk;
+ volatile u32 __iomem *prcm_hdmi_clk;
+ volatile u32 __iomem *prcm_tv_clk;
+ dsi_link dsi_lnk_no;
+ dsi_link_context dsi_lnk_context;
+ struct dsi_link_conf dsi_lnk_conf;
+
+ /* Added by QCSPWAN below for "pink display" */
+#ifdef CONFIG_DEBUG_FS
+ struct dentry *debugfs_dentry;
+ char debugfs_name[10];
+#endif
+ /* To serialize access from user space */
+ struct semaphore fb_sem;
+ /* End QCSPWAN */
+};
+
+
+//volatile mcde_system_context g_mcde_system_context;
+
+#define NUM_TOTAL_MODES ARRAY_SIZE(mcde_modedb)
+
+mcde_error mcdesetdsiclk(dsi_link link, mcde_ch_id chid, mcde_dsi_clk_config clk_config);
+mcde_error mcdesetfifoctrl(dsi_link link, mcde_ch_id chid, struct mcde_fifo_ctrl fifo_ctrl);
+mcde_error mcdesetoutputconf(dsi_link link, mcde_ch_id chid, mcde_output_conf output_conf);
+mcde_error mcdesetdsicommandword(dsi_link link,mcde_ch_id chid,mcde_dsi_channel dsichannel,u8 cmdbyte_lsb,u8 cmdbyte_msb);
+mcde_error mcdesetdsiconf(dsi_link link, mcde_ch_id chid, mcde_dsi_channel dsichannel, mcde_dsi_conf dsi_conf);
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/mcde_ioctls.h b/arch/arm/mach-ux500/include/mach/mcde_ioctls.h
new file mode 100755
index 00000000000..605b430c0d9
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/mcde_ioctls.h
@@ -0,0 +1,737 @@
+/*----------------------------------------------------------------------------------*/
+/* copyright STEricsson, 2009. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it under */
+/* the terms of the GNU General Public License as published by the Free */
+/* Software Foundation; either version 2.1 of the License, or (at your option) */
+/* any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but WITHOUT */
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS */
+/* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*----------------------------------------------------------------------------------*/
+
+#ifndef _MCDE_IOCTLS_H_
+#define _MCDE_IOCTLS_H_
+
+typedef enum
+{
+ COLOR_CONV_NONE = 0x0,
+ COLOR_CONV_YUV_RGB = 0x1,
+ COLOR_CONV_RGB_YUV = 0x2,
+ COLOR_CONV_YUV422_YUV444 = 0x3
+}mcde_colorconv_type;
+
+typedef enum
+{
+ MCDE_COL_CONV_DISABLE = 0x0,
+ MCDE_COL_CONV_NOT_SAT = 0x1,
+ MCDE_COL_CONV_SAT = 0x2,
+ MCDE_COL_CONV_RESERVED
+}mcde_col_conv_ctrl;
+
+struct mcde_ovr_blend_ctrl
+{
+ char alpha_value;
+ char ovr_opaq;
+ char ovr_blend;
+ char ovr_zlevel;
+ unsigned int ovr_xpos;
+ unsigned int ovr_ypos;
+};
+
+typedef enum
+{
+ MCDE_ROTATE_BURST_WORD_1 = 0x0,
+ MCDE_ROTATE_BURST_WORD_2 = 0x1,
+ MCDE_ROTATE_BURST_WORD_4 = 0x2,
+ MCDE_ROTATE_BURST_WORD_8 = 0x3,
+ MCDE_ROTATE_BURST_WORD_16 = 0x04,
+ MCDE_ROTATE_BURST_WORD_RESERVED
+ }mcde_rotate_req;
+
+typedef enum
+{
+ MCDE_OUTSTND_REQ_1 = 0x0,
+ MCDE_OUTSTND_REQ_2 = 0x1,
+ MCDE_OUTSTND_REQ_4 = 0x2,
+ MCDE_OUTSTND_REQ_8 = 0x3,
+ MCDE_OUTSTND_REQ_16 = 0x4,
+ MCDE_OUTSTND_REQ_RESERVED
+}mcde_outsnd_req;
+typedef enum
+{
+ MCDE_BURST_WORD_1 = 0x00,
+ MCDE_BURST_WORD_2 = 0x01,
+ MCDE_BURST_WORD_4 = 0x02,
+ MCDE_BURST_WORD_8 = 0x03,
+ MCDE_BURST_WORD_16 = 0x04,
+ MCDE_BURST_WORD_HW_1 = 0x8,
+ MCDE_BURST_WORD_HW_2 = 0x09,
+ MCDE_BURST_WORD_HW_4 = 0x0A,
+ MCDE_BURST_WORD_HW_8 = 0x0B,
+ MCDE_BURST_WORD_HW_16 = 0x0C
+}mcde_burst_req;
+typedef enum
+{
+ MCDE_COLOR_KEY_DISABLE = 0x0,
+ MCDE_COLOR_KEY_ENABLE = 0x01
+}mcde_color_key_ctrl;
+typedef enum
+{
+ MCDE_PAL_GAMA_DISABLE = 0x0,
+ MCDE_GAMA_ENABLE = 0x1,
+ MCDE_PAL_ENABLE = 0x2,
+ MCDE_PAL_GAMA_RESERVED
+}mcde_pal_ctrl;
+typedef enum
+{
+ MCDE_OVERLAY_DISABLE = 0x0,
+ MCDE_OVERLAY_ENABLE = 0x1
+}mcde_overlay_ctrl;
+typedef enum
+{
+ MCDE_PIXEL_ALPHA_SOURCE = 0x0,
+ MCDE_CONST_ALPHA_SOURCE = 0x1
+}mcde_blend_ctrl;
+typedef enum
+{
+ MCDE_OVR_OPAQUE_DISABLE = 0x0,
+ MCDE_OVR_OPAQUE_ENABLE = 0x1
+}mcde_ovr_opq_ctrl;
+typedef enum
+{
+ MCDE_OVR_PREMULTIPLIED_ALPHA_DISABLE = 0x0,
+ MCDE_OVR_PREMULTIPLIED_ALPHA_ENABLE = 0x1
+}mcde_ovr_alpha_enable;
+typedef enum
+{
+ MCDE_OVR_CLIP_DISABLE = 0x0,
+ MCDE_OVR_CLIP_ENABLE = 0x1
+}mcde_ovr_clip_enable;
+
+struct mcde_chconfig
+{
+ unsigned short lpf;
+ unsigned short ppl;
+};
+typedef enum
+{
+ MCDE_LCD_TV_0 = 0x0,
+ MCDE_LCD_TV_1 = 0x1,
+ MCDE_MDIF_IN_0 = 0x2,
+ MCDE_MDIF_IN_1 = 0x3,
+ MCDE_MDIF_OUT_0 = 0x4,
+ MCDE_MDIF_OUT_1 = 0x5
+}mcde_synchro_out_interface;
+typedef enum
+{
+ MCDE_SYNCHRO_OUTPUT_SOURCE = 0x0,
+ MCDE_SYNCHRO_AUTO = 0x1,
+ MCDE_SYNCHRO_SOFTWARE = 0x2,
+ MCDE_SYNCHRO_EXTERNAL_SOURCE = 0x3
+}mcde_synchro_source;
+typedef enum
+{
+ MCDE_NO_ACTION = 0x0,
+ MCDE_NEW_FRAME_SYNCHRO = 0x1
+}mcde_sw_trigger;
+typedef enum
+{
+ MCDE_VERTICAL_SYNCHRO = 0x00,
+ MCDE_BACK_PORCH = 0x01,
+ MCDE_ACTIVE_VIDEO = 0x02,
+ MCDE_FRONT_PORCH = 0x03
+}mcde_frame_events;
+struct mcde_ch_bckgrnd_col
+{
+ unsigned char red;
+ unsigned char green;
+ unsigned char blue;
+};
+typedef enum
+{
+ MCDE_TVCLK_EXTERNAL = 0x0,
+ MCDE_TVCLK_INTERNAL = 0x1
+}mcde_tv_clk;
+typedef enum
+{
+ MCDE_PCD_ENABLE = 0x0,
+ MCDE_PCD_BYPASS = 0x1
+}mcde_bcd_ctrl;
+typedef enum
+{
+ MCDE_BPP_1_TO_8 = 0x0,
+ MCDE_BPP_12 = 0x1,
+ MCDE_BPP_16 = 0x2,
+ MCDE_BPP_18 = 0x3,
+ MCDE_BPP_24 = 0x4
+}mcde_out_bpp;
+typedef enum
+{
+ MCDE_BUS_16_CONF1 = 0x0,
+ MCDE_BUS_16_CONF2 = 0x1,
+ MCDE_BUS_16_CONF3 = 0x2,
+ MCDE_BUS_18_CONF1 = 0x3,
+ MCDE_BUS_18_CONF2 = 0x4,
+ MCDE_BUS_24 = 0x5
+}mcde_lcd_bus;
+typedef enum
+{
+ MCDE_CLK_STBUS = 0x0,
+ MCDE_CLK_72 = 0x1,
+ MCDE_CLK_42 = 0x2,
+ MCDE_CLK_27 = 0x3,
+ MCDE_CLK_TVCLK1 = 0x4,
+ MCDE_CLK_TVCLK2 = 0x5
+}mcde_dpi2_clksel;
+
+struct mcde_chx_control1
+{
+ mcde_tv_clk tv_clk;
+ mcde_bcd_ctrl bcd_ctrl;
+ mcde_out_bpp out_bpp;
+ unsigned short clk_per_line;
+ mcde_lcd_bus lcd_bus;
+ mcde_dpi2_clksel dpi2_clk;
+ unsigned short pcd;
+};
+typedef enum
+{
+ MCDE_CLR_KEY_DISABLE = 0x0,
+ MCDE_ALPHA_RGB_KEY = 0x1,
+ MCDE_RGB_KEY = 0x2,
+ MCDE_FALPHA_FRGB_KEY = 0x4,
+ MCDE_FRGB_KEY = 0x5
+}mcde_key_ctrl;
+typedef enum
+{
+ MCDE_COLORKEY_NORMAL = 0x0,
+ MCDE_COLORKEY_FORCE= 0x1
+}mcde_colorkey_type;
+struct mcde_chx_color_key
+{
+ unsigned char alpha;
+ unsigned char red;
+ unsigned char green;
+ unsigned char blue;
+};
+typedef enum
+{
+ MCDE_SDTV_656P = 0x0,
+ MCDE_HDTV_480P = 0x1,
+ MCDE_HDTV_720P = 0x2,
+ MCDE_TV_NOTUSED = 0x3,
+}mcde_tvmode;
+typedef enum
+{
+ MCDE_ACTIVE_HIGH = 0x0,
+ MCDE_ACTIVE_LOW = 0x1
+}mcde_signal_level;
+typedef enum
+{
+ MCDE_MODE_LCD = 0x0,
+ MCDE_MODE_TV = 0x1
+}mcde_display_mode;
+typedef enum
+{
+ MCDE_SCAN_PROGRESSIVE_MODE = 0x0,
+ MCDE_SCAN_INTERLACED_MODE = 0x1,
+}mcde_scan_mode;
+
+typedef enum
+{
+ MCDE_TV_PAL = 0x0,
+ MCDE_TV_NTSC = 0x1,
+}mcde_tv_mode;
+
+struct mcde_chnl_lcd_ctrl_reg
+{
+ unsigned short num_lines;
+ unsigned short ppl;
+ mcde_tvmode tv_mode;
+ mcde_signal_level ifield;
+ mcde_scan_mode scan_mode;
+ mcde_display_mode sel_mode;
+};
+struct mcde_chnl_lcd_horizontal_timing
+{
+ unsigned short hbp;
+ unsigned short hfp;
+ unsigned short hsw;
+};
+struct mcde_chnl_lcd_vertical_timing
+{
+ unsigned short vbp;
+ unsigned short vfp;
+ unsigned short vsw;
+};
+
+typedef enum
+{
+ MCDE_ANTIFLICKER_DISABLE = 0x0,
+ MCDE_ANTIFLICKER_ENABLE = 0x1
+}mcde_antiflicker_ctrl;
+
+typedef enum
+{
+ MCDE_PIXEL_ORDER_LITTLE = 0x0,
+ MCDE_PIXEL_ORDER_BIG = 0x1
+}mcde_pixel_order_in_byte;
+
+typedef enum
+{
+ MCDE_BYTE_LITTLE = 0x0,
+ MCDE_BYTE_BIG = 0x1
+}mcde_byte_endianity;
+
+typedef enum
+{
+ MCDE_COL_RGB = 0x0,
+ MCDE_COL_BGR = 0x1
+}mcde_rgb_format_sel;
+
+typedef enum
+{
+ MCDE_PAL_1_BIT = 0x0,
+ MCDE_PAL_2_BIT = 0x1,
+ MCDE_PAL_4_BIT = 0x2,
+ MCDE_PAL_8_BIT = 0x3,
+ MCDE_RGB444_12_BIT = 0x4,
+ MCDE_ARGB_16_BIT = 0x5,
+ MCDE_IRGB1555_16_BIT = 0x6,
+ MCDE_RGB565_16_BIT = 0x7,
+ MCDE_RGB_PACKED_24_BIT = 0x8,
+ MCDE_RGB_UNPACKED_24_BIT = 0x9,
+ MCDE_ARGB_32_BIT =0xA,
+ MCDE_YCbCr_8_BIT = 0xB
+}mcde_bpp_ctrl;
+
+typedef enum
+{
+ MCDE_OVERLAY_0 = 0x0,
+ MCDE_OVERLAY_1 = 0x1,
+ MCDE_OVERLAY_2 = 0x2,
+ MCDE_OVERLAY_3 = 0x3,
+ MCDE_OVERLAY_4 = 0x4,
+ MCDE_OVERLAY_5 = 0x5,
+ MCDE_OVERLAY_6 = 0x6,
+ MCDE_OVERLAY_7 = 0x7
+}mcde_overlay_id;
+
+typedef enum
+{
+ MCDE_BUFFER_USED_NONE = 0x0,
+ MCDE_BUFFER_USED_1 = 0x1,
+ MCDE_BUFFER_USED_2 = 0x2,
+ MCDE_BUFFER_USED_3 = 0x3
+}mcde_num_buffer_used;
+
+typedef enum
+{
+ MCDE_BUFFER_ID_0 = 0x0,
+ MCDE_BUFFER_ID_1 = 0x1,
+ MCDE_BUFFER_ID_2 = 0x2,
+ MCDE_BUFFER_ID_RESERVED
+}mcde_buffer_id;
+
+typedef enum
+{
+ MCDE_MASK_DISABLE = 0x0,
+ MCDE_MASK_ENABLE = 0x1
+}mcde_masking_bit_ctrl;
+
+typedef enum
+{
+ MCDE_DITHERING_RESET = 0x0,
+ MCDE_DITHERING_ACTIVATE = 0x1
+}mcde_dithering_control;
+typedef enum
+{
+ MCDE_DITHERING_DISABLE = 0x0,
+ MCDE_DITHERING_ENABLE = 0x1
+}mcde_dithering_ctrl;
+struct mcde_chx_dither_ctrl
+{
+ unsigned char y_offset;
+ unsigned char x_offset;
+ mcde_masking_bit_ctrl masking_ctrl;
+ unsigned char mode;
+ mcde_dithering_ctrl comp_dithering;
+ mcde_dithering_ctrl temp_dithering;
+};
+struct mcde_chx_dithering_offset
+{
+ unsigned char y_offset_rb;
+ unsigned char x_offset_rb;
+ unsigned char y_offset_rg;
+ unsigned char x_offset_rg;
+};
+
+typedef enum{
+ VMODE_640_350_85_P,
+ VMODE_640_400_85_P,
+ VMODE_720_400_85_P,
+ VMODE_640_480_60_P,
+ VMODE_640_480_CRT_60_P,
+ VMODE_240_320_60_P,
+ VMODE_320_240_60_P,
+ VMODE_712_568_60_P,
+ VMODE_640_480_75_P,
+ VMODE_640_480_85_P,
+//#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
+ VMODE_480_864_60_P,
+//#endif
+ VMODE_864_480_60_P,
+ VMODE_800_600_56_P,
+ VMODE_800_600_60_P,
+ VMODE_800_600_72_P,
+ VMODE_800_600_75_P,
+ VMODE_800_600_85_P,
+ VMODE_1024_768_60_P,
+ VMODE_1024_768_70_P,
+ VMODE_1024_768_75_P,
+ VMODE_1024_768_85_P,
+ VMODE_1152_864_75_P,
+ VMODE_1280_960_60_P,
+ VMODE_1280_960_85_P,
+ VMODE_1280_1024_60_P,
+ VMODE_1280_1024_75_P,
+ VMODE_1280_1024_85_P,
+ VMODE_1600_1200_60_P,
+ VMODE_1600_1200_65_P,
+ VMODE_1600_1200_70_P,
+ VMODE_1600_1200_75_P,
+ VMODE_1600_1200_85_P,
+ VMODE_1792_1344_60_P,
+ VMODE_1792_1344_75_P,
+ VMODE_1856_1392_60_P,
+ VMODE_1856_1392_75_P,
+ VMODE_1920_1440_60_P,
+ VMODE_1920_1440_75_P,
+ VMODE_720_480_60_P,
+ VMODE_720_480_60_I,
+ VMODE_720_576_50_P,
+ VMODE_720_576_50_I,
+ VMODE_1280_720_50_P,
+ VMODE_1280_720_60_P,
+ VMODE_1920_1080_50_I,
+ VMODE_1920_1080_60_I,
+ VMODE_1920_1080_60_P,
+#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
+ VMODE_1920_1080_30_P,
+#endif
+}mcde_video_mode;
+/*****************************************************************************
+IOCTLs for access from user space
+*******************************************************************************/
+
+#define MCDE_IOC_MAGIC 'm'
+
+#define MCDE_IOCTL_OVERLAY_CREATE _IOWR(MCDE_IOC_MAGIC, 0x0,struct mcde_overlay_create)
+#define MCDE_IOCTL_OVERLAY_REMOVE _IOR(MCDE_IOC_MAGIC, 0x1,unsigned long)
+#define MCDE_IOCTL_COLOR_KEYING_ENABLE _IOWR(MCDE_IOC_MAGIC, 0x2,struct mcde_channel_color_key)
+#define MCDE_IOCTL_COLOR_KEYING_DISABLE _IOR(MCDE_IOC_MAGIC, 0x3,unsigned long)
+#define MCDE_IOCTL_COLOR_COVERSION_ENABLE _IOWR(MCDE_IOC_MAGIC, 0x4,struct mcde_conf_color_conv)
+#define MCDE_IOCTL_COLOR_COVERSION_DISABLE _IOR(MCDE_IOC_MAGIC, 0x5,unsigned long)
+#define MCDE_IOCTL_ROTATION_ENABLE _IOR(MCDE_IOC_MAGIC, 0x6,unsigned char)
+#define MCDE_IOCTL_ROTATION_DISABLE _IOR(MCDE_IOC_MAGIC, 0x7,unsigned char)
+#define MCDE_IOCTL_SET_VIDEOMODE _IOR(MCDE_IOC_MAGIC, 0x8, unsigned long)
+#define MCDE_IOCTL_ALLOC_FRAMEBUFFER _IOWR(MCDE_IOC_MAGIC, 0x9,struct mcde_sourcebuffer_alloc)
+#define MCDE_IOCTL_DEALLOC_FRAMEBUFFER _IOWR(MCDE_IOC_MAGIC, 0xA, unsigned long)
+#define MCDE_IOCTL_CONFIGURE_EXTSRC _IOR(MCDE_IOC_MAGIC, 0xB,struct mcde_ext_conf)
+#define MCDE_IOCTL_CONFIGURE_OVRLAY _IOR(MCDE_IOC_MAGIC, 0xC,struct mcde_conf_overlay)
+#define MCDE_IOCTL_CONFIGURE_CHANNEL _IOR(MCDE_IOC_MAGIC, 0xD,struct mcde_ch_conf)
+#define MCDE_IOCTL_CONFIGURE_PANEL _IOR(MCDE_IOC_MAGIC, 0xE,struct mcde_chnl_lcd_ctrl)
+#define MCDE_IOCTL_MCDE_ENABLE _IOR(MCDE_IOC_MAGIC, 0xF,unsigned long)
+#define MCDE_IOCTL_MCDE_DISABLE _IOR(MCDE_IOC_MAGIC, 0x10,unsigned long)
+#define MCDE_IOCTL_CHANNEL_BLEND_ENABLE _IOWR(MCDE_IOC_MAGIC,0x11,struct mcde_blend_control)
+#define MCDE_IOCTL_CHANNEL_BLEND_DISABLE _IOR(MCDE_IOC_MAGIC, 0x12,unsigned long)
+#define MCDE_IOCTL_CONFIGURE_DENC _IOR(MCDE_IOC_MAGIC, 0x13,unsigned long)
+#define MCDE_IOCTL_CONFIGURE_HDMI _IOR(MCDE_IOC_MAGIC, 0x14,unsigned long)
+#define MCDE_IOCTL_SET_SOURCE_BUFFER _IOR(MCDE_IOC_MAGIC, 0x15,struct mcde_source_buffer)
+#define MCDE_IOCTL_DITHERING_ENABLE _IOR(MCDE_IOC_MAGIC, 0x16,struct mcde_dithering_ctrl_conf)
+#define MCDE_IOCTL_DITHERING_DISABLE _IOR(MCDE_IOC_MAGIC, 0x16,unsigned long)
+#define MCDE_IOCTL_ANTIFLICKER_ENABLE _IOR(MCDE_IOC_MAGIC, 0x17,unsigned long)
+#define MCDE_IOCTL_ANTIFLICKER_DISABLE _IOR(MCDE_IOC_MAGIC, 0x18,unsigned long)
+#define MCDE_IOCTL_TEST_DSI_LPMODE _IOR(MCDE_IOC_MAGIC, 0x19,unsigned long)
+#define MCDE_IOCTL_TEST_DSI_HSMODE _IOR(MCDE_IOC_MAGIC, 0x1A,unsigned long)
+#define MCDE_IOCTL_SET_SCAN_MODE _IOWR(MCDE_IOC_MAGIC, 0x1B,unsigned long)
+#define MCDE_IOCTL_GET_SCAN_MODE _IOR(MCDE_IOC_MAGIC, 0x1C,unsigned long)
+
+#define MCDE_IOCTL_TV_PLUG_STATUS _IOR(MCDE_IOC_MAGIC, 0x1D,unsigned long)
+#define MCDE_IOCTL_TV_CHANGE_MODE _IOWR(MCDE_IOC_MAGIC, 0x1E,unsigned long)
+#define MCDE_IOCTL_TV_GET_MODE _IOR(MCDE_IOC_MAGIC, 0x1F,unsigned long)
+
+/**
+ * struct mcde_overlay_create - To create overlay
+ * @xorig: frame buffer x-offset
+ * @yorig: frame buffer y-offset
+ * @xwidth: frame buffer x-width
+ * @yheight - frame buffer y-height
+ * @bpp: input source bits per pixel
+ * @fg: if set then overlay goes to foreground,else remains in background
+ * @key: unique framebuffer key returned by driver
+ * @bgrinput: if set then implies BGR input
+ * @usedefault: if set then uses base overlay buffer
+ *
+ *
+ **/
+struct mcde_overlay_create {
+ unsigned long xorig;
+ unsigned long yorig;
+ unsigned long xwidth;
+ unsigned long yheight;
+ char bpp; /** input source bits per pixel */
+ char fg; /** if set then overlay goes to foreground,else remains in background */
+ unsigned long key; /** unique framebuffer key returned by driver */
+ unsigned long bgrinput; /** if set then implies BGR input */
+ char usedefault; // if set then uses base overlay buffer
+};
+/**
+ * struct mcde_addrmap - source frame buffer address map structure
+ * @cpuaddr: logical address of the framebuffer
+ * @dmaaddr: physical address of the framebuffer
+ * @bufflength: buffer length
+ *
+ *
+ **/
+struct mcde_addrmap {
+ unsigned long cpuaddr;
+ unsigned long dmaaddr;
+ unsigned long bufflength;
+};
+/**
+ * struct mcde_source_buffer - source frame buffer addresses structure
+ * @buff_addr: frame buffer addresses structure
+ * @buffid: buffer id
+ *
+ *
+ **/
+struct mcde_source_buffer
+{
+ struct mcde_addrmap buffaddr;
+ unsigned char buffid;
+};
+/**
+ * struct mcde_sourcebuffer_alloc - source frame buffer allocation structure
+ * @xwidth: frame buffer x-width
+ * @yheight: frame buffer y-height
+ * @bpp: input source bits per pixel
+ * @doubleBufferingEnabled: double buffer control
+ * @key: unique framebuffer key returned by driver
+ * @buff_addr: frame buffer addresses structure
+ *
+ *
+ **/
+struct mcde_sourcebuffer_alloc {
+ unsigned long xwidth;
+ unsigned long yheight;
+ char bpp; /** input source bits per pixel */
+ char doubleBufferingEnabled;
+ unsigned long key; /** unique framebuffer key returned by driver */
+ struct mcde_addrmap buff_addr;
+};
+
+/**
+ * struct mcde_dithering_ctrl_conf - Structure of overlay configuration
+ * @rot_burst_req: rotation burst request
+ * @outstnd_req: outstanding request
+ * @burst_req: burst request
+ * @priority: priority
+ * @color_key: color key control
+ * @pal_control: pal control
+ * @col_ctrl: color conversion control
+ * @convert_format: conversion format
+ * @ovr_state: overlay control
+ * @ovr_ypos: overlay y-position
+ * @ovr_xpos: overlay x-position
+ * @alpha: alpha control
+ * @alpha_value: alpha value
+ * @pixoff: pixel offset
+ * @ovr_opaq: overlay opaque control
+ * @ovr_blend: overlay blend control
+ * @watermark_level: watermark level
+ * @ovr_zlevel: foreground level
+ * @clip: clip control
+ * @ytlcoor: clip y-topleft coordinates
+ * @xtlcoor: clip x-topleft coordinates
+ * @ybrcoor: clip y-bottomright coordinates
+ * @xbrcoor: clip x-bottomright coordinates
+ * @xwidth: x-width
+ * @yheight: y-height
+ * @bpp: input bpp
+ *
+ *
+ **/
+struct mcde_conf_overlay {
+ mcde_rotate_req rot_burst_req;
+ mcde_outsnd_req outstnd_req;
+ mcde_burst_req burst_req;
+ unsigned char priority;
+ mcde_color_key_ctrl color_key;
+ mcde_pal_ctrl pal_control;
+ mcde_col_conv_ctrl col_ctrl;
+ mcde_colorconv_type convert_format;
+ mcde_overlay_ctrl ovr_state;
+
+ unsigned short ovr_ypos;
+ unsigned short ovr_xpos;
+
+ mcde_ovr_alpha_enable alpha;
+ unsigned char alpha_value;
+ unsigned char pixoff;
+ mcde_ovr_opq_ctrl ovr_opaq;
+ mcde_blend_ctrl ovr_blend;
+ unsigned long watermark_level;
+ unsigned char ovr_zlevel;
+
+ mcde_ovr_clip_enable clip;
+ unsigned long ytlcoor;
+ unsigned long xtlcoor;
+ unsigned long ybrcoor;
+ unsigned long xbrcoor;
+
+ unsigned long xwidth;
+ unsigned long yheight;
+ char bpp; /** input source bits per pixel */
+
+};
+/**
+ * struct mcde_blend_control - channel configuration structure
+ * @chconfig: channel config structure
+ * @out_synch_interface: out sync interface
+ * @ch_synch_src: channel sync source
+ * @sw_trig: software trigger param
+ * @swint_vcnt: int count param
+ * @swint_vevent: event count param
+ * @chbckgrndcolor: channel background color
+ * @ch_priority: channel priority
+ * @control1: channel control structure
+ *
+ *
+ **/
+struct mcde_ch_conf
+{
+ struct mcde_chconfig chconfig;
+ mcde_synchro_out_interface out_synch_interface;
+ mcde_synchro_source ch_synch_src;
+ mcde_sw_trigger sw_trig;
+ unsigned short swint_vcnt;
+ mcde_frame_events swint_vevent;
+ unsigned short hwreq_vcnt;
+ mcde_frame_events hwreq_vevent;
+ struct mcde_ch_bckgrnd_col chbckgrndcolor;
+ unsigned char ch_priority;
+ struct mcde_chx_control1 control1;
+};
+/**
+ * struct mcde_blend_control - color keying configuration structure
+ * @key_ctrl: color key control
+ * @color_key_type: color key type
+ * @color_key: channel color key structure
+ *
+ *
+ **/
+struct mcde_channel_color_key
+{
+ mcde_key_ctrl key_ctrl;
+ mcde_colorkey_type color_key_type;
+ struct mcde_chx_color_key color_key;
+};
+/**
+ * struct mcde_conf_color_conv - color conversion configuration structure
+ * @convert_format: convert format type
+ * @col_ctrl: color conversion control
+ *
+ *
+ **/
+struct mcde_conf_color_conv
+{
+ mcde_colorconv_type convert_format;
+ mcde_col_conv_ctrl col_ctrl;
+};
+/**
+ * struct mcde_blend_control - blend control configuration structure
+ * @blenden: blend enable
+ * @blend_ctrl: blend control
+ * @alpha_blend: alpha blend
+ * @ovr1_id: overlay1 ID
+ * @ovr2_id: overlay2 ID
+ * @ovr2_enable: overlay2 enable
+ * @ovr1_blend_ctrl: overlay1 blend control structure
+ * @ovr2_blend_ctrl: overlay2 blend control structure
+ *
+ *
+ **/
+struct mcde_blend_control
+{
+ char blenden;
+ char blend_ctrl;
+ char alpha_blend;
+ char ovr1_id;
+ char ovr2_id;
+ char ovr2_enable;
+ struct mcde_ovr_blend_ctrl ovr1_blend_ctrl;
+ struct mcde_ovr_blend_ctrl ovr2_blend_ctrl;
+
+};
+/**
+ * struct mcde_chnl_lcd_ctrl - LCD control structure
+ * @lcd_ctrl_reg: lcd control reg structure
+ * @lcd_horizontal_timing: lcd horizontal timing structure
+ * @lcd_vertical_timing: lcd vertical timing structure
+ *
+ *
+ **/
+struct mcde_chnl_lcd_ctrl
+{
+ struct mcde_chnl_lcd_ctrl_reg lcd_ctrl_reg;
+ struct mcde_chnl_lcd_horizontal_timing lcd_horizontal_timing;
+ struct mcde_chnl_lcd_vertical_timing lcd_vertical_timing;
+
+};
+/**
+ * struct mcde_ext_conf - External source configuration structure
+ * @ovr_pxlorder: overlay pixel order
+ * @endianity: byte endianity
+ * @rgb_format: format type
+ * @bpp: input bpp
+ * @provr_id: overlay id
+ * @buf_num: number of buffers used
+ * @buf_id: buffer id to be used
+ *
+ *
+ **/
+struct mcde_ext_conf
+{
+ mcde_pixel_order_in_byte ovr_pxlorder;
+ mcde_byte_endianity endianity;
+ mcde_rgb_format_sel rgb_format;
+ mcde_bpp_ctrl bpp;
+ mcde_overlay_id provr_id;
+ mcde_num_buffer_used buf_num;
+ mcde_buffer_id buf_id;
+};
+/**
+ * struct mcde_dithering_ctrl_conf - Structure of dithering configuration
+ * @dithering_ctrl: dithering control
+ * @input_bpp: input bpp
+ * @output_bpp: output bpp
+ * @mcde_chx_dither_ctrl: structure of dithering control
+ * @mcde_chx_dithering_offset: structure of the dithering offset
+ *
+ *
+ **/
+struct mcde_dithering_ctrl_conf
+{
+ mcde_dithering_ctrl dithering_ctrl;
+ mcde_bpp_ctrl input_bpp;
+ mcde_out_bpp output_bpp;
+ struct mcde_chx_dither_ctrl mcde_chx_dither_ctrl;
+ struct mcde_chx_dithering_offset mcde_chx_dithering_offset;
+};
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/mcde_reg.h b/arch/arm/mach-ux500/include/mach/mcde_reg.h
new file mode 100755
index 00000000000..45a1a935670
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/mcde_reg.h
@@ -0,0 +1,794 @@
+/*---------------------------------------------------------------------------*/
+/* Copyrighti (C) STEricsson 2009. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it */
+/* under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, */
+/* or (at your option)any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */
+/* the GNU Lesser General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*---------------------------------------------------------------------------*/
+
+#ifndef _MCDEREG_H_
+#define _MCDEREG_H_
+
+#include <linux/types.h>
+#include <mach/bit_mask.h>
+
+/*******************************************************************
+ MCDE Control Register Fields
+********************************************************************/
+#define MCDE_DISABLE 0x00000000
+#define MCDE_ENABLE 0x80000000
+#define MCDE_SET_BIT 0x1
+#define MCDE_CLEAR_BIT 0x0
+#define MCDE_CTRL_MCDEEN_MASK MASK_BIT31
+#define MCDE_CTRL_MCDEEN_SHIFT 31
+#define MCDE_CTRL_FABMUX_MASK MASK_BIT17
+#define MCDE_CTRL_FABMUX_SHIFT 17
+#define MCDE_CTRL_F01MUX_MASK MASK_BIT16
+#define MCDE_CTRL_F01MUX_SHIFT 16
+#define MCDE_CTRL_IFIFICTRL_MASK MASK_BIT15
+#define MCDE_CTRL_IFIFICTRL_SHIFT 15
+#define MCDE_CTRL_DPIA_EN_MASK MASK_BIT9
+#define MCDE_CTRL_DPIA_EN_SHIFT 9
+#define MCDE_CTRL_DPIB_EN_MASK MASK_BIT8
+#define MCDE_CTRL_DPIB_EN_SHIFT 8
+#define MCDE_CTRL_DBIC0_EN_MASK MASK_BIT7
+#define MCDE_CTRL_DBIC0_EN_SHIFT 7
+#define MCDE_CTRL_DBIC1_EN_MASK MASK_BIT6
+#define MCDE_CTRL_DBIC1_EN_SHIFT 6
+#define MCDE_DSIVID0_EN_MASK MASK_BIT5
+#define MCDE_DSIVID1_EN_MASK MASK_BIT4
+#define MCDE_DSIVID2_EN_MASK MASK_BIT3
+#define MCDE_DSICMD0_EN_MASK MASK_BIT2
+#define MCDE_DSICMD1_EN_MASK MASK_BIT1
+#define MCDE_DSICMD2_EN_MASK MASK_BIT0
+#define MCDE_DSIVID0_EN_SHIFT 5
+#define MCDE_DSIVID1_EN_SHIFT 4
+#define MCDE_DSIVID2_EN_SHIFT 3
+#define MCDE_DSICMD0_EN_SHIFT 2
+#define MCDE_DSICMD1_EN_SHIFT 1
+#define MCDE_SYNCMUX_MASK 0xFF
+#define MCDE_TVA_DPIC0_LCDB_MASK 0x06
+#define MCDE_TVB_DPIC1_LCDA_MASK 0xD4
+#define MCDE_DPIC1_LCDA_MASK 0xF8
+#define MCDE_DPIC0_LCDB_MASK 0x07
+#define MCDE_LCDA_LCDB_MASK 0x00
+#define MCDE_DSI_MASK 0x01
+#define MCDE_OVR_ALPHAPMEN_SHIFT 6
+#define MCDE_OVR_CLIPEN_SHIFT 7
+
+#define MCDE_CFG_OUTMUX4_MASK (MASK_BIT28 | MASK_BIT29 | MASK_BIT30)
+#define MCDE_CFG_OUTMUX3_MASK (MASK_BIT25 | MASK_BIT26 | MASK_BIT27)
+#define MCDE_CFG_OUTMUX2_MASK (MASK_BIT22 | MASK_BIT23 | MASK_BIT24)
+#define MCDE_CFG_OUTMUX1_MASK (MASK_BIT19 | MASK_BIT20 | MASK_BIT21)
+#define MCDE_CFG_OUTMUX0_MASK (MASK_BIT16 | MASK_BIT17 | MASK_BIT18)
+#define MCDE_CFG_IFIFOCTRLWTRMRKLVL_MASK (MASK_BIT12 | MASK_BIT13 | MASK_BIT14)
+#define MCDE_CFG_FSYNCTRLB_MASK MASK_BIT11
+#define MCDE_CFG_FSYNCTRLA_MASK MASK_BIT10
+#define MCDE_CFG_SWAP_B_C1_MASK MASK_BIT9
+#define MCDE_CFG_SWAP_A_C0_MASK MASK_BIT8
+#define MCDE_CFG_SYNCMUX7_MASK MASK_BIT7
+#define MCDE_CFG_SYNCMUX6_MASK MASK_BIT6
+#define MCDE_CFG_SYNCMUX5_MASK MASK_BIT5
+#define MCDE_CFG_SYNCMUX4_MASK MASK_BIT4
+#define MCDE_CFG_SYNCMUX3_MASK MASK_BIT3
+#define MCDE_CFG_SYNCMUX2_MASK MASK_BIT2
+#define MCDE_CFG_SYNCMUX1_MASK MASK_BIT1
+#define MCDE_CFG_SYNCMUX0_MASK MASK_BIT0
+
+#define MCDE_CFG_OUTMUX4_SHIFT 28
+#define MCDE_CFG_OUTMUX3_SHIFT 25
+#define MCDE_CFG_OUTMUX2_SHIFT 22
+#define MCDE_CFG_OUTMUX1_SHIFT 19
+#define MCDE_CFG_OUTMUX0_SHIFT 16
+#define MCDE_CFG_IFIFOCTRLWTRMRKLVL_SHIFT 12
+#define MCDE_CFG_FSYNCTRLB_SHIFT 11
+#define MCDE_CFG_FSYNCTRLA_SHIFT 10
+#define MCDE_CFG_SWAP_B_C1_SHIFT 9
+#define MCDE_CFG_SWAP_A_C0_SHIFT 8
+#define MCDE_CFG_SYNCMUX7_SHIFT 7
+#define MCDE_CFG_SYNCMUX6_SHIFT 6
+#define MCDE_CFG_SYNCMUX5_SHIFT 5
+#define MCDE_CFG_SYNCMUX4_SHIFT 4
+#define MCDE_CFG_SYNCMUX3_SHIFT 3
+#define MCDE_CFG_SYNCMUX2_SHIFT 2
+#define MCDE_CFG_SYNCMUX1_SHIFT 1
+#define MCDE_CFG_SYNCMUX0_SHIFT 0
+
+
+/*******************************************************************
+ MCDE External Source Register Fields
+********************************************************************/
+#define MCDE_EXT_BUFFER_MASK /*(MASK_HALFWORD1 | MASK_BYTE1 | MASK_QUARTET1 | MASK_BIT3)*/0xFFFFFFFF
+#define MCDE_EXT_PRI_OVR_MASK MASK_QUARTET1
+#define MCDE_EXT_BUFFER_NUM_MASK (MASK_BIT2 | MASK_BIT3)
+#define MCDE_EXT_BUFFER_ID_MASK (MASK_BIT0 | MASK_BIT1)
+#define MCDE_EXT_FORCEFSDIV_MASK MASK_BIT4
+#define MCDE_EXT_FSDISABLE_MASK MASK_BIT3
+#define MCDE_EXT_OVR_CTRL_MASK MASK_BIT2
+#define MCDE_EXT_BUF_MODE_MASK (MASK_BIT0 | MASK_BIT1)
+#define MCDE_EXT_BEPO_MASK MASK_BIT14
+#define MCDE_EXT_BEBO_MASK MASK_BIT13
+#define MCDE_EXT_BGR_MASK MASK_BIT12
+#define MCDE_EXT_BPP_MASK (MASK_BIT11 | MASK_BIT10 | MASK_BIT9 | MASK_BIT8)
+
+
+#define MCDE_EXT_BUFFER_SHIFT 0
+#define MCDE_EXT_PRI_OVR_SHIFT SHIFT_QUARTET1
+#define MCDE_EXT_BUFFER_NUM_SHIFT 2
+#define MCDE_EXT_OVR_CTRL_SHIFT 2
+#define MCDE_EXT_FORCEFSDIV_SHIFT 4
+#define MCDE_EXT_FSDISABLE_SHIFT 3
+#define MCDE_EXT_BEPO_SHIFT 14
+#define MCDE_EXT_BEBO_SHIFT 13
+#define MCDE_EXT_BGR_SHIFT 12
+#define MCDE_EXT_BPP_SHIFT 8
+/*******************************************************************
+ MCDE Overlay Register Fields
+********************************************************************/
+#define MCDE_OVR_OVLEN_MASK MASK_BIT0
+#define MCDE_OVR_COLCTRL_MASK (MASK_BIT1 | MASK_BIT2)
+#define MCDE_OVR_PALCTRL_MASK (MASK_BIT3 | MASK_BIT4)
+#define MCDE_OVR_CKEYEN_MASK (MASK_BIT5)
+#define MCDE_OVR_STBPRIO_MASK MASK_QUARTET4
+#define MCDE_OVR_BURSTSZ_MASK MASK_QUARTET5
+#define MCDE_OVR_MAXREQ_MASK MASK_QUARTET6
+#define MCDE_OVR_ROTBURSTSIZE_MASK MASK_QUARTET7
+#define MCDE_OVR_BLEND_MASK MASK_BIT0
+#define MCDE_OVR_OPQ_MASK MASK_BIT9
+#define MCDE_OVR_INTERMDE_MASK MASK_BIT29
+#define MCDE_OVR_INTERON_MASK MASK_BIT28
+#define MCDE_OVR_ALPHAPMEN_MASK MASK_BIT6
+#define MCDE_OVR_CLIPEN_MASK MASK_BIT7
+#define MCDE_OVR_LPF_MASK (MASK_BYTE2 | MASK_BIT24 |MASK_BIT25 | MASK_BIT26)
+#define MCDE_OVR_PPL_MASK (MASK_BYTE0 | MASK_BIT8 |MASK_BIT9 |MASK_BIT10)
+#define MCDE_ALPHAVALUE_MASK (MASK_BYTE0 << 1)
+/**#define MCDE_EXT_SRCID_MASK (MASK_BIT9 | MASK_BIT8 | MASK_BIT7 | MASK_BIT6)*/
+#define MCDE_EXT_SRCID_MASK (MASK_BIT14 | MASK_BIT13 | MASK_BIT12 | MASK_BIT11)
+#define MCDE_PIXOFF_MASK (MASK_BIT10 | MASK_BIT11 |MASK_QUARTET3)
+#define MCDE_OVR_ZLEVEL_MASK (MASK_BIT30 | MASK_BIT27 | MASK_BIT28 | MASK_BIT29)
+#define MCDE_OVR_YPOS_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
+#define MCDE_OVR_CHID_MASK (MASK_BIT14 | MASK_BIT13 | MASK_BIT12 | MASK_BIT11)
+#define MCDE_OVR_XPOS_MASK (MASK_BYTE0 | MASK_BIT8 |MASK_BIT9 |MASK_BIT10)
+#define MCDE_OVR_READ_MASK MASK_BIT9
+#define MCDE_OVR_FETCH_MASK MASK_BIT8
+#define MCDE_OVR_BLOCKED_MASK MASK_BIT10
+//#define MCDE_OVR_READ_MASK MASK_BIT1
+//#define MCDE_OVR_FETCH_MASK MASK_BIT0
+#define MCDE_WATERMARK_MASK (MASK_BYTE2 | MASK_QUARTET6 | MASK_BIT28)
+#define MCDE_LINEINCREMENT_MASK 0xFFFFFFFF
+#define MCDE_YCLIP_MASK 0xFFFFFFFF
+#define MCDE_XCLIP_MASK 0xFFFFFFFF
+#define MCDE_XBRCOOR_MASK 0x7FF
+#define MCDE_YBRCOOR_MASK 0x07FF0000
+
+#define MCDE_OVR_COLCTRL_SHIFT 1
+#define MCDE_OVR_PALCTRL_SHIFT 3
+#define MCDE_OVR_CKEYEN_SHIFT 5
+#define MCDE_OVR_STBPRIO_SHIFT SHIFT_QUARTET4
+#define MCDE_OVR_BURSTSZ_SHIFT SHIFT_QUARTET5
+#define MCDE_OVR_MAXREQ_SHIFT SHIFT_QUARTET6
+#define MCDE_OVR_ROTBURSTSIZE_SHIFT SHIFT_QUARTET7
+#define MCDE_OVR_OPQ_SHIFT 9
+#define MCDE_OVR_INTERMDE_SHIFT 29
+#define MCDE_OVR_INTERON_SHIFT 28
+#define MCDE_OVR_LPF_SHIFT SHIFT_HALFWORD1
+#define MCDE_ALPHAVALUE_SHIFT 1
+//#define MCDE_EXT_SRCID_SHIFT 6
+#define MCDE_EXT_SRCID_SHIFT 11
+#define MCDE_OVR_ZLEVEL_SHIFT 27
+#define MCDE_OVR_YPOS_SHIFT SHIFT_HALFWORD1
+#define MCDE_OVR_CHID_SHIFT 11
+#define MCDE_OVR_READ_SHIFT 1
+#define MCDE_WATERMARK_SHIFT SHIFT_HALFWORD1
+#define MCDE_PIXOFF_SHIFT 10
+#define MCDE_LINEINCREMENT_SHIFT 0
+#define MCDE_YCLIP_SHIFT 0
+#define MCDE_XCLIP_SHIFT 0
+#define MCDE_YBRCOOR_SHIFT 16
+
+/*******************************************************************
+ MCDE Channel Configuration Register Fields
+********************************************************************/
+#define MCDE_INITDELAY_MASK MASK_HALFWORD1
+#define MCDE_PPDELAY_MASK MASK_HALFWORD0
+#define MCDE_SWINTVCNT_MASK (MASK_BYTE3 | MASK_QUARTET5 | MASK_BIT18 |MASK_BIT19)
+#define MCDE_SWINTVEVENT_MASK (MASK_BIT16 | MASK_BIT17)
+#define MCDE_HWREQVCNT_MASK (MASK_BYTE1 | MASK_QUARTET1 | MASK_BIT3 | MASK_BIT2)
+#define MCDE_HWREQVEVENT_MASK (MASK_BIT0 | MASK_BIT1)
+#define MCDE_OUTINTERFACE_MASK (MASK_BIT4 | MASK_BIT3 |MASK_BIT2)
+#define MCDE_SRCSYNCH_MASK (MASK_BIT0 | MASK_BIT1)
+#define MCDE_SW_TRIG_MASK MASK_BIT0
+#define MCDE_REDCOLOR_MASK MASK_BYTE2
+#define MCDE_GREENCOLOR_MASK MASK_BYTE1
+#define MCDE_BLUECOLOR_MASK MASK_BYTE0
+#define MCDE_CHPRIORITY_MASK MASK_QUARTET0
+#define MCDE_CHXLPF_MASK (0x03FF0000)
+#define MCDE_CHXPPL_MASK (MASK_BYTE0 | MASK_BIT8 |MASK_BIT9 |MASK_BIT10)
+#define MCDE_CHX_ABORT_MASK MASK_BIT1
+#define MCDE_CHX_READ_MASK MASK_BIT0
+
+#define MCDE_INITDELAY_SHIFT SHIFT_HALFWORD1
+#define MCDE_SWINTVCNT_SHIFT 18
+#define MCDE_SWINTVEVENT_SHIFT SHIFT_HALFWORD1
+#define MCDE_HWREQVCNT_SHIFT 2
+#define MCDE_OUTINTERFACE_SHIFT 2
+#define MCDE_REDCOLOR_SHIFT SHIFT_HALFWORD1
+#define MCDE_GREENCOLOR_SHIFT SHIFT_BYTE1
+#define MCDE_CHPRIORITY_SHIFT SHIFT_QUARTET7
+#define MCDE_CHXLPF_SHIFT 16
+#define MCDE_CHX_ABORT_SHIFT 1
+
+/*******************************************************************
+ MCDE Channel A/B Register Fields
+********************************************************************/
+#define MCDE_CHX_BURSTSIZE_MASK (MASK_QUARTET6 & 0x07000000)
+#define MCDE_CHX_ALPHA_MASK (MASK_BYTE2)
+#define MCDE_CHX_ROTDIR_MASK (MASK_BIT15)
+#define MCDE_CHX_GAMAEN_MASK (MASK_BIT14)
+#define MCDE_FLICKFORMAT_MASK (MASK_BIT13)
+#define MCDE_FLICKMODE_MASK (MASK_BIT11 | MASK_BIT12)
+#define MCDE_BLENDCONTROL_MASK (MASK_BIT10)
+#define MCDE_KEYCTRL_MASK (MASK_BIT7|MASK_BIT8|MASK_BIT9)
+#define MCDE_ROTEN_MASK (MASK_BIT6)
+#define MCDE_DITHEN_MASK (MASK_BIT5)
+#define MCDE_CEAEN_MASK (MASK_BIT4)
+#define MCDE_AFLICKEN_MASK (MASK_BIT3)
+#define MCDE_BLENDEN_MASK (MASK_BIT2)
+#define MCDE_CLK_MASK (MASK_BIT30)
+#define MCDE_BCD_MASK (MASK_BIT29)
+#define MCDE_OUTBPP_MASK (MASK_BIT25 |MASK_BIT26 | MASK_BIT27 | MASK_BIT28)
+#define MCDE_CDWIN_MASK (MASK_BIT13 | MASK_BIT14 | MASK_BIT15)
+#define MCDE_CLOCKSEL_MASK (MASK_BIT12 | MASK_BIT11 | MASK_BIT10)
+#define MCDE_PCD_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9)
+#define MCDE_KEYA_MASK (MASK_BYTE3)
+#define MCDE_KEYR_MASK (MASK_BYTE2)
+#define MCDE_KEYG_MASK (MASK_BYTE1)
+#define MCDE_KEYB_MASK (MASK_BYTE0)
+#define MCDE_RGB_MASK1 (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25)
+#define MCDE_RGB_MASK2 (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9)
+#define MCDE_THRESHOLD_MASK (MASK_QUARTET6)
+#define MCDE_COEFFN3_MASK (MASK_BYTE2)
+#define MCDE_COEFFN2_MASK (MASK_BYTE1)
+#define MCDE_COEFFN1_MASK (MASK_BYTE0)
+#define MCDE_TV_LINES_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
+#define MCDE_TVMODE_MASK (MASK_BIT3 | MASK_BIT4)
+#define MCDE_IFIELD_MASK (MASK_BIT2)
+#define MCDE_INTEREN_MASK (MASK_BIT1)
+#define MCDE_SELMODE_MASK (MASK_BIT0)
+#define MCDE_BSL_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
+#define MCDE_BEL_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
+#define MCDE_FSL2_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
+#define MCDE_FSL1_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
+#define MCDE_DVO2_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
+#define MCDE_DVO1_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
+#define MCDE_SWH2_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
+#define MCDE_SWH1_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
+#define MCDE_SWW_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
+#define MCDE_DHO_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
+#define MCDE_ALW_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
+#define MCDE_LBW_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
+#define MCDE_TVBCR_MASK MASK_BYTE2
+#define MCDE_TVBCB_MASK MASK_BYTE1
+#define MCDE_TVBLU_MASK MASK_BYTE0
+#define MCDE_REVVAEN_MASK MASK_BIT31
+#define MCDE_REVTGEN_MASK MASK_BIT30
+#define MCDE_REVLOADSEL_MASK (MASK_BIT28 | MASK_BIT29)
+#define MCDE_REVDEL1_MASK (MASK_QUARTET6)
+#define MCDE_REVDEL0_MASK (MASK_BYTE2)
+#define MCDE_PSVAEN_MASK (MASK_BIT15)
+#define MCDE_PSTGEN_MASK (MASK_BIT14)
+#define MCDE_PSLOADSEL_MASK (MASK_BIT12 | MASK_BIT13)
+#define MCDE_PSDEL1_MASK (MASK_QUARTET2)
+#define MCDE_PSDEL0_MASK (MASK_BYTE0)
+#define MCDE_IOE_MASK (MASK_BIT23)
+#define MCDE_IPC_MASK (MASK_BIT22)
+#define MCDE_IHS_MASK (MASK_BIT21)
+#define MCDE_IVS_MASK (MASK_BIT20)
+#define MCDE_IVP_MASK (MASK_BIT19)
+#define MCDE_ICLSPL_MASK (MASK_BIT18)
+#define MCDE_ICLREV_MASK (MASK_BIT17)
+#define MCDE_ICLSP_MASK (MASK_BIT16)
+#define MCDE_SPLVAEN_MASK (MASK_BIT15)
+#define MCDE_SPLTGEN_MASK (MASK_BIT14)
+#define MCDE_SPLLOADSEL_MASK (MASK_BIT12 | MASK_BIT13)
+#define MCDE_SPLDEL1_MASK (MASK_QUARTET2)
+#define MCDE_SPLDEL0_MASK (MASK_BYTE0)
+#define MCDE_FOFFY_MASK (MASK_BIT14 | MASK_BIT13 | MASK_BIT12 | MASK_BIT11 | MASK_BIT10)
+#define MCDE_FOFFX_MASK (MASK_BIT5 | MASK_BIT6 | MASK_BIT7 | MASK_BIT8 | MASK_BIT9)
+#define MCDE_MASK_BITCTRL_MASK (MASK_BIT4)
+#define MCDE_MODE_MASK (MASK_BIT2 | MASK_BIT3)
+#define MCDE_COMP_MASK (MASK_BIT1)
+#define MCDE_TEMP_MASK (MASK_BIT0)
+#define MCDE_YB_MASK (MASK_BIT28 | MASK_BIT27 | MASK_BIT26 | MASK_BIT25 | MASK_BIT24)
+#define MCDE_XB_MASK (MASK_BIT20 | MASK_BIT19 | MASK_BIT18 | MASK_BIT17 | MASK_BIT16)
+#define MCDE_YG_MASK (MASK_BIT12 | MASK_BIT11 | MASK_BIT10 | MASK_BIT9 | MASK_BIT8 | MASK_BIT7 | MASK_BIT6 | MASK_BIT5)
+#define MCDE_XG_MASK (MASK_BIT0 | MASK_BIT1 | MASK_BIT2 | MASK_BIT3 | MASK_BIT4)
+#define MCDE_ARED_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25)
+#define MCDE_GREEN_MASK (MASK_BYTE1)
+#define MCDE_BLUE_MASK (MASK_BYTE0)
+#define MCDE_RED_MASK (MASK_BYTE2)
+
+#define MCDE_CHX_BURSTSIZE_SHIFT SHIFT_QUARTET6
+#define MCDE_CHX_ALPHA_SHIFT SHIFT_HALFWORD1
+#define MCDE_CHX_ROTDIR_SHIFT 15
+#define MCDE_CHX_GAMAEN_SHIFT 14
+#define MCDE_FLICKFORMAT_SHIFT 13
+#define MCDE_FLICKMODE_SHIFT 11
+#define MCDE_BLENDCONTROL_SHIFT 10
+#define MCDE_KEYCTRL_SHIFT 7
+#define MCDE_ROTEN_SHIFT 6
+#define MCDE_DITHEN_SHIFT 5
+#define MCDE_CEAEN_SHIFT 4
+#define MCDE_AFLICKEN_SHIFT 3
+#define MCDE_BLENDEN_SHIFT 2
+#define MCDE_CLK_SHIFT 30
+#define MCDE_BCD_SHIFT 29
+#define MCDE_OUTBPP_SHIFT 25
+#define MCDE_CDWIN_SHIFT 13
+#define MCDE_CLOCKSEL_SHIFT 10
+#define MCDE_KEYA_SHIFT SHIFT_BYTE3
+#define MCDE_KEYR_SHIFT SHIFT_BYTE2
+#define MCDE_KEYG_SHIFT SHIFT_BYTE1
+#define MCDE_RGB_SHIFT SHIFT_HALFWORD1
+#define MCDE_THRESHOLD_SHIFT SHIFT_QUARTET6
+#define MCDE_COEFFN3_SHIFT SHIFT_BYTE2
+#define MCDE_COEFFN2_SHIFT SHIFT_BYTE1
+#define MCDE_COEFFN1_SHIFT (SHIFT_BYTE0)
+#define MCDE_TV_LINES_SHIFT SHIFT_HALFWORD1
+#define MCDE_TVMODE_SHIFT 3
+#define MCDE_IFIELD_SHIFT 2
+#define MCDE_INTEREN_SHIFT 1
+#define MCDE_BSL_SHIFT 16
+#define MCDE_FSL2_SHIFT 16
+#define MCDE_DVO2_SHIFT 16
+#define MCDE_SWW_SHIFT 16
+#define MCDE_ALW_SHIFT 16
+#define MCDE_TVBCR_SHIFT SHIFT_BYTE2
+#define MCDE_TVBCB_SHIFT SHIFT_BYTE1
+#define MCDE_REVVAEN_SHIFT 31
+#define MCDE_REVTGEN_SHIFT 30
+#define MCDE_REVLOADSEL_SHIFT 28
+#define MCDE_REVDEL1_SHIFT SHIFT_QUARTET6
+#define MCDE_REVDEL0_SHIFT SHIFT_HALFWORD1
+#define MCDE_PSVAEN_SHIFT 15
+#define MCDE_PSTGEN_SHIFT 14
+#define MCDE_PSLOADSEL_SHIFT 12
+#define MCDE_PSDEL1_SHIFT 8
+#define MCDE_IOE_SHIFT 23
+#define MCDE_IPC_SHIFT 22
+#define MCDE_IHS_SHIFT 21
+#define MCDE_IVS_SHIFT 20
+#define MCDE_IVP_SHIFT 19
+#define MCDE_ICLSPL_SHIFT 18
+#define MCDE_ICLREV_SHIFT 17
+#define MCDE_ICLSP_SHIFT 16
+#define MCDE_SPLVAEN_SHIFT 15
+#define MCDE_SPLTGEN_SHIFT 14
+#define MCDE_SPLLOADSEL_SHIFT 12
+#define MCDE_SPLDEL1_SHIFT 8
+#define MCDE_FOFFY_SHIFT 10
+#define MCDE_FOFFX_SHIFT 5
+#define MCDE_MASK_BITCTRL_SHIFT 4
+#define MCDE_MODE_SHIFT 2
+#define MCDE_COMP_SHIFT 1
+#define MCDE_YB_SHIFT 24
+#define MCDE_XB_SHIFT SHIFT_HALFWORD1
+#define MCDE_YG_SHIFT 5
+#define MCDE_ARED_SHIFT SHIFT_HALFWORD1
+#define MCDE_GREEN_SHIFT SHIFT_BYTE1
+/*******************************************************************
+ MCDE Channel C Register Fields
+********************************************************************/
+#define MCDE_SYNCCTRL_MASK (MASK_BIT30 | MASK_BIT29)
+#define MCDE_RESEN_MASK (MASK_BIT18)
+#define MCDE_CLKSEL_MASK (MASK_BIT14 | MASK_BIT13)
+#define MCDE_SYNCSEL_MASK MASK_BIT6
+#define MCDE_RES2_MASK MASK_BIT28
+#define MCDE_RES1_MASK MASK_BIT27
+#define MCDE_RD2_MASK MASK_BIT26
+#define MCDE_RD1_MASK MASK_BIT25
+#define MCDE_WR2_MASK MASK_BIT24
+#define MCDE_WR1_MASK MASK_BIT23
+#define MCDE_CD2_MASK MASK_BIT22
+#define MCDE_CD1_MASK MASK_BIT21
+#define MCDE_CS2_MASK MASK_BIT20
+#define MCDE_CS1_MASK MASK_BIT19
+#define MCDE_CS2EN_MASK MASK_BIT17
+#define MCDE_CS1EN_MASK MASK_BIT16
+#define MCDE_INBAND2_MASK MASK_BIT12
+#define MCDE_INBAND1_MASK MASK_BIT11
+#define MCDE_BUSSIZE2_MASK MASK_BIT10
+#define MCDE_BUSSIZE1_MASK MASK_BIT9
+#define MCDE_SYNCEN2_MASK MASK_BIT8
+#define MCDE_SYNCEN1_MASK MASK_BIT7
+#define MCDE_WMLVL2_MASK MASK_BIT5
+#define MCDE_WMLVL1_MASK MASK_BIT4
+#define MCDE_C2EN_MASK MASK_BIT3
+#define MCDE_C1EN_MASK MASK_BIT2
+#define MCDE_POWEREN_MASK MASK_BIT1
+#define MCDE_FLOEN_MASK MASK_BIT0
+#define MCDE_PDCTRL_MASK (MASK_BIT10 |MASK_BIT11 | MASK_BIT12)
+#define MCDE_DUPLEXER_MASK (MASK_BIT7 |MASK_BIT8 | MASK_BIT9)
+#define MCDE_BSDM_MASK (MASK_BIT6 | MASK_BIT5 | MASK_BIT4)
+#define MCDE_BSCM_MASK (MASK_BIT2 | MASK_BIT1 | MASK_BIT0)
+#define MCDE_VSDBL_MASK (MASK_BIT29 | MASK_BIT30 | MASK_BIT31)
+#define MCDE_VSSEL_MASK MASK_BIT28
+#define MCDE_VSPOL_MASK MASK_BIT27
+#define MCDE_VSPDIV_MASK (MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
+#define MCDE_VSPMAX_MASK (MASK_BYTE2 | MASK_QUARTET3)
+#define MCDE_VSPMIN_MASK (MASK_BYTE0 | MASK_QUARTET2)
+#define MCDE_TRDELC_MASK (MASK_BYTE2 | MASK_QUARTET6)
+#define MCDE_SYNCDELC1_MASK (MASK_BYTE1)
+#define MCDE_SYNCDELC0_MASK (MASK_BYTE0)
+#define MCDE_VSTAC1_MASK MASK_BIT1
+#define MCDE_VSTAC0_MASK MASK_BIT0
+#define MCDE_BCN_MASK MASK_BYTE0
+#define MCDE_CSCDDEACT_MASK MASK_BYTE1
+#define MCDE_CSCDACT_MASK MASK_BYTE0
+#define MCDE_MOTINT_MASK MASK_BIT16
+#define MCDE_RWDEACT_MASK MASK_BYTE1
+#define MCDE_RWACT_MASK MASK_BYTE0
+#define MCDE_DODEACT_MASK MASK_BYTE1
+#define MCDE_DOACT_MASK MASK_BYTE0
+#define MCDE_READDATA_MASK MASK_HALFWORD0
+#define MCDE_DATACOMMANDMASK 0x01FFFFFF
+
+#define MCDE_SYNCCTRL_SHIFT 29
+#define MCDE_RESEN_SHIFT 18
+#define MCDE_CLKSEL_SHIFT 13
+#define MCDE_SYNCSEL_SHIFT 6
+#define MCDE_RES2_SHIFT 28
+#define MCDE_RES1_SHIFT 27
+#define MCDE_RD2_SHIFT 26
+#define MCDE_RD1_SHIFT 25
+#define MCDE_WR2_SHIFT 24
+#define MCDE_WR1_SHIFT 23
+#define MCDE_CD2_SHIFT 22
+#define MCDE_CD1_SHIFT 21
+#define MCDE_CS2_SHIFT 20
+#define MCDE_CS1_SHIFT 19
+#define MCDE_CS2EN_SHIFT 17
+#define MCDE_CS1EN_SHIFT 16
+#define MCDE_INBAND2_SHIFT 12
+#define MCDE_INBAND1_SHIFT 11
+#define MCDE_BUSSIZE2_SHIFT 10
+#define MCDE_BUSSIZE1_SHIFT 9
+#define MCDE_SYNCEN2_SHIFT 8
+#define MCDE_SYNCEN1_SHIFT 7
+#define MCDE_WMLVL2_SHIFT 5
+#define MCDE_WMLVL1_SHIFT 4
+#define MCDE_C2EN_SHIFT 3
+#define MCDE_C1EN_SHIFT 2
+#define MCDE_POWEREN_SHIFT 1
+#define MCDE_PDCTRL_SHIFT 12
+#define MCDE_DUPLEXER_SHIFT 7
+#define MCDE_BSDM_SHIFT 4
+#define MCDE_VSDBL_SHIFT 29
+#define MCDE_VSSEL_SHIFT 28
+#define MCDE_VSPOL_SHIFT 27
+#define MCDE_VSPDIV_SHIFT 24
+#define MCDE_VSPMAX_SHIFT 12
+#define MCDE_TRDELC_SHIFT SHIFT_HALFWORD1
+#define MCDE_SYNCDELC1_SHIFT SHIFT_BYTE1
+#define MCDE_VSTAC1_SHIFT 1
+#define MCDE_CSCDDEACT_SHIFT SHIFT_BYTE1
+#define MCDE_MOTINT_SHIFT SHIFT_HALFWORD1
+#define MCDE_RWDEACT_SHIFT 8
+#define MCDE_DODEACT_SHIFT SHIFT_BYTE1
+
+/*******************************************************************
+ MCDE DSI Register Fields
+********************************************************************/
+#define MCDE_PLLOUT_DIVSEL1_MASK (MASK_BIT22 | MASK_BIT23)
+#define MCDE_PLLOUT_DIVSEL0_MASK (MASK_BIT20 | MASK_BIT21)
+#define MCDE_PLL4IN_SEL_MASK (MASK_BIT16 | MASK_BIT17)
+#define MCDE_TXESCDIV_SEL_MASK MASK_BIT8
+#define MCDE_TXESCDIV_MASK 0xFF
+#define MCDE_CMDBYTE_LSB_MASK 0xFF
+#define MCDE_CMDBYTE_MSB_MASK 0xFF00
+#define MCDE_DSI_SW_MASK 0xFFF0000
+#define MCDE_DSI_DMA_MASK 0xFFF
+#define MCDE_DSI_PACK_MASK (MASK_BIT20 | MASK_BIT21 | MASK_BIT22)
+#define MCDE_DSI_DCSVID_MASK MASK_BIT18
+#define MCDE_DSI_BYTE_SWAP_MASK MASK_BIT17
+#define MCDE_DSI_BIT_SWAP_MASK MASK_BIT16
+#define MCDE_DSI_CMD8_MASK MASK_BIT13
+#define MCDE_DSI_VID_MODE_MASK MASK_BIT12
+#define MCDE_BLANKING_MASK MASK_QUARTET0
+#define MCDE_DSI_FRAME_MASK (MASK_HALFWORD0 | MASK_BYTE2)
+#define MCDE_DSI_PACKET_MASK MASK_HALFWORD0
+
+#define MCDE_PLLOUT_DIVSEL1_SHIFT 22
+#define MCDE_PLLOUT_DIVSEL0_SHIFT 20
+#define MCDE_PLL4IN_SEL_SHIFT 16
+#define MCDE_TXESCDIV_SEL_SHIFT 8
+#define MCDE_CMDBYTE_MSB_SHIFT 8
+#define MCDE_DSI_SW_SHIFT 16
+#define MCDE_DSI_PACK_SHIFT 20
+#define MCDE_DSI_DCSVID_SHIFT 18
+#define MCDE_DSI_BYTE_SWAP_SHIFT 17
+#define MCDE_DSI_BIT_SWAP_SHIFT 16
+#define MCDE_DSI_CMD8_SHIFT 13
+#define MCDE_DSI_VID_MODE_SHIFT 12
+
+/*******************************************************************
+ Register Structure
+********************************************************************/
+
+#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
+
+struct mcde_ext_src_reg
+{
+ volatile u32 mcde_extsrc_a0;
+ volatile u32 mcde_extsrc_a1;
+ volatile u32 mcde_extsrc_a2;
+ volatile u32 mcde_extsrc_conf;
+ volatile u32 mcde_extsrc_cr;
+ volatile u32 mcde_unused1[3];
+};
+
+struct mcde_ovl_reg
+{
+ volatile u32 mcde_ovl_cr;
+ volatile u32 mcde_ovl_conf;
+ volatile u32 mcde_ovl_conf2;
+ volatile u32 mcde_ovl_ljinc;
+ volatile u32 mcde_ovl_crop;
+ volatile u32 mcde_ovl_comp;
+ volatile u32 mcde_unused1[2];
+};
+
+struct mcde_chnl_conf_reg
+{
+ volatile u32 mcde_chnl_conf;
+ volatile u32 mcde_chnl_stat;
+ volatile u32 mcde_chnl_synchmod;
+ volatile u32 mcde_chnl_synchsw;
+ volatile u32 mcde_chnl_bckgndcol;
+ volatile u32 mcde_chnl_prio;
+ volatile u32 mcde_unused[2];
+};
+
+struct mcde_chAB_reg
+{
+ volatile u32 mcde_cr0;
+ volatile u32 mcde_cr1;
+ volatile u32 mcde_colkey;
+ volatile u32 mcde_fcolkey;
+ volatile u32 mcde_rgbconv1;
+ volatile u32 mcde_rgbconv2;
+ volatile u32 mcde_rgbconv3;
+ volatile u32 mcde_rgbconv4;
+ volatile u32 mcde_rgbconv5;
+ volatile u32 mcde_rgbconv6;
+ volatile u32 mcde_ffcoef0;
+ volatile u32 mcde_ffcoef1;
+ volatile u32 mcde_ffcoef2;
+ volatile u32 mcde_unused1[1];
+ volatile u32 mcde_tvcr;
+ volatile u32 mcde_tvbl1;
+ volatile u32 mcde_tvisl;
+ volatile u32 mcde_tvdvo;
+ volatile u32 mcde_unused2[1];
+ volatile u32 mcde_tvtim1;
+ volatile u32 mcde_tvlbalw;
+ volatile u32 mcde_tvbl2;
+ volatile u32 mcde_tvblu;
+ volatile u32 mcde_lcdtim0;
+ volatile u32 mcde_lcdtim1;
+ volatile u32 mcde_ditctrl;
+ volatile u32 mcde_ditoff;
+ volatile u32 mcde_pal0;
+ volatile u32 mcde_pal1;
+ volatile u32 mcde_rotadd0;
+ volatile u32 mcde_rotadd1;
+ volatile u32 mcde_rot_conf;
+ volatile u32 mcde_synchconf;
+ volatile u32 mcde_unused3[1];
+ volatile u32 mcde_gam0;
+ volatile u32 mcde_gam1;
+ volatile u32 mcde_gam2;
+ volatile u32 mcde_oledconv1;
+ volatile u32 mcde_oledconv2;
+ volatile u32 mcde_oledconv3;
+ volatile u32 mcde_oledconv4;
+ volatile u32 mcde_oledconv5;
+ volatile u32 mcde_oledconv6;
+ volatile u32 mcde_unused4[85];
+};
+
+struct mcde_chC0C1_reg
+{
+ volatile u32 mcde_crc;
+ volatile u32 mcde_pbccrc[2];
+ volatile u32 mcde_pbcbmrc0[5];
+ volatile u32 mcde_pbcbmrc1[5];
+ volatile u32 mcde_pbcbcrc0[2];
+ volatile u32 mcde_unused1[3];
+ volatile u32 mcde_pbcbcrc1[2];
+ volatile u32 mcde_unused2[3];
+ volatile u32 mcde_vscrc[2];
+ volatile u32 mcde_sctrc;
+ volatile u32 mcde_scsrc;
+ volatile u32 mcde_bcnr[2];
+ volatile u32 mcde_cscdtr[2];
+ volatile u32 mcde_rdwrtr[2];
+ volatile u32 mcde_dotr[2];
+ volatile u32 mcde_wcmdc[2];
+ volatile u32 mcde_wdatadc[2];
+ volatile u32 mcde_rdatadc[2];
+ volatile u32 mcde_statc;
+ volatile u32 mcde_ctrlc[2];
+};
+
+struct mcde_dsi_reg
+{
+ volatile u32 mcde_dsi_conf0;
+ volatile u32 mcde_dsi_frame;
+ volatile u32 mcde_dsi_pkt;
+ volatile u32 mcde_dsi_sync;
+ volatile u32 mcde_dsi_cmdw;
+ volatile u32 mcde_dsi_delay0;
+ volatile u32 mcde_dsi_delay1;
+ volatile u32 mcde_unused1[1];
+};
+
+struct mcde_top_reg
+{
+ volatile u32 mcde_cr;
+ volatile u32 mcde_conf0;
+ volatile u32 mcde_ssp;
+ volatile u32 mcde_reserved1[61];
+ volatile u32 mcde_ais;
+ volatile u32 mcde_imscpp;
+ volatile u32 mcde_imscovl;
+ volatile u32 mcde_imscchnl;
+ volatile u32 mcde_imscerr;
+ volatile u32 mcde_rispp;
+ volatile u32 mcde_risovl;
+ volatile u32 mcde_rischnl;
+ volatile u32 mcde_riserr;
+ volatile u32 mcde_mispp;
+ volatile u32 mcde_misovl;
+ volatile u32 mcde_mischnl;
+ volatile u32 mcde_miserr;
+ volatile u32 mcde_sispp;
+ volatile u32 mcde_sisovl;
+ volatile u32 mcde_sischnl;
+ volatile u32 mcde_siserr;
+ volatile u32 mcde_reserved2[46];
+ volatile u32 mcde_pid;
+};
+
+#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
+
+struct mcde_ext_src_reg
+{
+ volatile u32 mcde_extsrc_a0;
+ volatile u32 mcde_extsrc_a1;
+ volatile u32 mcde_extsrc_a2;
+ volatile u32 mcde_extsrc_conf;
+ volatile u32 mcde_extsrc_cr;
+ volatile u32 mcde_unused1[3];
+};
+
+struct mcde_ovl_reg
+{
+ volatile u32 mcde_ovl_cr;
+ volatile u32 mcde_ovl_conf;
+ volatile u32 mcde_ovl_conf2;
+ volatile u32 mcde_ovl_ljinc;
+ volatile u32 mcde_ovl_crop;
+ volatile u32 mcde_ovl_top_left_clip;
+ volatile u32 mcde_ovl_bot_rht_clip;
+ volatile u32 mcde_ovl_comp;
+};
+
+struct mcde_ch_synch_reg
+{
+ volatile u32 mcde_ch_conf;
+ volatile u32 mcde_ch_stat;
+ volatile u32 mcde_chsyn_mod;
+ volatile u32 mcde_chsyn_sw;
+ volatile u32 mcde_chsyn_bck;
+ volatile u32 mcde_chsyn_prio;
+ volatile u32 mcde_unused3[2];
+};
+
+struct mcde_ch_reg
+{
+ volatile u32 mcde_ch_cr0;
+ volatile u32 mcde_ch_cr1;
+ volatile u32 mcde_ch_colkey;
+ volatile u32 mcde_ch_fcolkey;
+ volatile u32 mcde_ch_rgbconv1;
+ volatile u32 mcde_ch_rgbconv2;
+ volatile u32 mcde_ch_rgbconv3;
+ volatile u32 mcde_ch_rgbconv4;
+ volatile u32 mcde_ch_rgbconv5;
+ volatile u32 mcde_ch_rgbconv6;
+ volatile u32 mcde_ch_ffcoef0;
+ volatile u32 mcde_ch_ffcoef1;
+ volatile u32 mcde_ch_ffcoef2;
+ volatile u32 unused;
+ volatile u32 mcde_ch_tvcr;
+ volatile u32 mcde_ch_tvbl1;
+ volatile u32 mcde_ch_tvisl;
+ volatile u32 mcde_ch_tvdvo;
+ volatile u32 mcde_ch_tvswh;
+ volatile u32 mcde_ch_tvtim1;
+ volatile u32 mcde_ch_tvbalw;
+ volatile u32 mcde_ch_tvbl2;
+ volatile u32 mcde_ch_tvblu;
+ volatile u32 mcde_ch_lcdtim0;
+ volatile u32 mcde_ch_lcdtim1;
+ volatile u32 mcde_ch_ditctrl;
+ volatile u32 mcde_ch_ditoff;
+ volatile u32 mcde_ch_pal;
+ volatile u32 mcde_ch_gam;
+ volatile u32 mcde_rotadd0;
+ volatile u32 mcde_rotadd1;
+ volatile u32 mcde_chsyn_con;
+ volatile u32 mcde_unused7[96];
+};
+
+struct mcde_dsi_reg
+{
+ volatile u32 mcde_dsi_conf0;
+ volatile u32 mcde_dsi_frame;
+ volatile u32 mcde_dsi_pkt;
+ volatile u32 mcde_dsi_sync;
+ volatile u32 mcde_dsi_cmd;
+ volatile u32 mcde_reserved2[3];
+};
+
+struct mcde_chc_reg
+{
+ volatile u32 mcde_chc_crc;
+ volatile u32 mcde_chc_pbcrc0;
+ volatile u32 mcde_chc_pbcrc1;
+ volatile u32 mcde_chc_pbcbmrc0[5];
+ volatile u32 mcde_chc_pbcbmrc1[5];
+ volatile u32 mcde_chc_pbcbcrc0[2];
+ volatile u32 mcde_unused5[3];
+ volatile u32 mcde_chc_pbcbcrc1[2];
+ volatile u32 mcde_unused6[3];
+ volatile u32 mcde_chc_vscrc[2];
+ volatile u32 mcde_chc_sctrc;
+ volatile u32 mcde_chc_scsr;
+ volatile u32 mcde_chc_bcnr[2];
+ volatile u32 mcde_chc_cscdtr[2];
+ volatile u32 mcde_chc_rdwrtr[2];
+ volatile u32 mcde_chc_dotr[2];
+ volatile u32 mcde_chc_wcmd[2];
+ volatile u32 mcde_chc_wd[2];
+ volatile u32 mcde_chc_rdata[2];
+};
+
+struct mcde_register_base
+{
+ volatile u32 mcde_cr;
+ volatile u32 mcde_cfg0;
+ volatile u32 mcde_reserved1[62];
+ volatile u32 mcde_ais;
+ volatile u32 mcde_imsc;
+ volatile u32 mcde_ris;
+ volatile u32 mcde_mis;
+ volatile u32 mcde_sis;
+ volatile u32 mcde_ssi;
+ volatile u32 mcde_reserved2[57];
+ volatile u32 mcde_pid;
+};
+
+#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/memory.h b/arch/arm/mach-ux500/include/mach/memory.h
new file mode 100755
index 00000000000..8a9d1324dec
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/memory.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET UL(0x00000000)
+#define BUS_OFFSET UL(0x00000000)
+
+#define CONSISTENT_DMA_SIZE (32 << 20)
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/mmc.h b/arch/arm/mach-ux500/include/mach/mmc.h
new file mode 100755
index 00000000000..3dd72603c7f
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/mmc.h
@@ -0,0 +1,341 @@
+/*
+ * Overview:
+ * SD/EMMC driver for u8500 platform
+ *
+ * Copyright (C) 2009 ST Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/*-------------------------------------------------------------------------
+ * SDI controller configuration
+ * Kernel entry point for sdmmc/emmc chip
+ *-------------------------------------------------------------------------
+ * <VERSION>v1.0.0
+ *-------------------------------------------------------------------------
+ */
+/*------------------------------i-----------------------------------------*/
+
+
+/*
+ * SDI Power register offset
+ */
+#define MMCIPOWER 0x000
+/*
+ * SDI Power register bits
+ */
+#define MCI_PWR_OFF 0x00
+#define MCI_PWR_UP 0x02
+#define MCI_PWR_ON 0x03
+#define MCI_STATE_ENABLE 0x38
+#define MCI_OPEN_DRAIN (1 << 6)
+#define MCI_FBCLK_ENABLE (1 << 7)
+#define MCI_POWER_IOS_MASK \
+ (MCI_PWR_ON | MCI_DIREN_CMD | MCI_DIREN_DAT0 | MCI_DIREN_DAT2 | \
+ MCI_DIREN_DAT31 | MCI_DIREN_DAT74 | MCI_OPEN_DRAIN)
+#define MCI_DIREN_CMD (1<<3)
+#define MCI_DIREN_DAT0 (1<<4)
+#define MCI_DIREN_DAT2 (1<<2)
+#define MCI_DIREN_DAT31 (1<<5)
+#define MCI_DIREN_DAT74 (1<<8)
+#define MCI_DIREN_1BIT (MCI_DIREN_CMD|MCI_DIREN_DAT0)
+#define MCI_DIREN_4BIT (MCI_DIREN_CMD|MCI_DIREN_DAT0|MCI_DIREN_DAT31)
+/* #define MCI_DIREN_8BIT (MCI_DIREN_CMD|MCI_DIREN_DAT0|MCI_DIREN_DAT31)*/
+#define MCI_DIREN_BIT (MCI_DIREN_CMD|MCI_DIREN_DAT0|MCI_DIREN_DAT31|\
+ MCI_DIREN_DAT2|MCI_DIREN_DAT74)
+/*
+ * SDI Clock register offset
+ */
+#define MMCICLOCK 0x004
+/*
+ * SDI Power register bits
+ */
+#define MCI_CLK_ENABLE (1 << 8)
+#define MCI_CLK_PWRSAVE (1 << 9)
+#define MCI_CLK_BYPASS (1 << 10)
+#define MCI_BUS_WIDTH_1 (0 << 11)
+#define MCI_BUS_WIDTH_4 (1 << 11)
+#define MCI_BUS_WIDTH_8 (2 << 11)
+#define MCI_HWFC_EN (1 << 14)
+#define MCI_NEG_EDGE (1 << 13)
+/*
+ * SDI Arguement register offset
+ */
+#define MMCIARGUMENT 0x008
+/*
+ * SDI Command register offset
+ */
+#define MMCICOMMAND 0x00c
+/*
+ * SDI command register bits
+ */
+#define MCI_CPSM_RESPONSE (1 << 6)
+#define MCI_CPSM_LONGRSP (1 << 7)
+#define MCI_CPSM_INTERRUPT (1 << 8)
+#define MCI_CPSM_PENDING (1 << 9)
+#define MCI_CPSM_ENABLE (1 << 10)
+
+/*
+ * SDI RespCMD register offset
+ */
+#define MMCIRESPCMD 0x010
+/*
+ * SDI Response0 register offset
+ */
+#define MMCIRESPONSE0 0x014
+/*
+ * SDI Response1 register offset
+ */
+#define MMCIRESPONSE1 0x018
+/*
+ * SDI Response2 register offset
+ */
+#define MMCIRESPONSE2 0x01c
+/*
+ * SDI Response3 register offset
+ */
+#define MMCIRESPONSE3 0x020
+/*
+ * SDI Datatimer register offset
+ */
+#define MMCIDATATIMER 0x024
+/*
+ * SDI DataLength register offset
+ */
+#define MMCIDATALENGTH 0x028
+/*
+ * SDI Data control register offset
+ */
+#define MMCIDATACTRL 0x02c
+/*
+ * SDI Data control register bits
+ */
+#define MCI_DPSM_ENABLE (1 << 0)
+#define MCI_DPSM_DIRECTION (1 << 1)
+#define MCI_DPSM_MODE (1 << 2)
+#define MCI_DPSM_DMAENABLE (1 << 3)
+#define MCI_DPSM_DMAreqctl (1 << 12)
+#define MCI_SDIO_ENABLE (1 << 11)
+
+/*
+ * SDI Data Count register offset
+ */
+#define MMCIDATACNT 0x030
+/*
+ * SDI Status register offset
+ */
+#define MMCISTATUS 0x034
+/*
+ * SDI Status register bits
+ */
+#define MCI_CMDCRCFAIL (1 << 0)
+#define MCI_DATACRCFAIL (1 << 1)
+#define MCI_CMDTIMEOUT (1 << 2)
+#define MCI_DATATIMEOUT (1 << 3)
+#define MCI_TXUNDERRUN (1 << 4)
+#define MCI_RXOVERRUN (1 << 5)
+#define MCI_CMDRESPEND (1 << 6)
+#define MCI_CMDSENT (1 << 7)
+#define MCI_DATAEND (1 << 8)
+#define MCI_STBITERR (1 << 9)
+#define MCI_DATABLOCKEND (1 << 10)
+#define MCI_CMDACTIVE (1 << 11)
+#define MCI_TXACTIVE (1 << 12)
+#define MCI_RXACTIVE (1 << 13)
+#define MCI_TXFIFOHALFEMPTY (1 << 14)
+#define MCI_RXFIFOHALFFULL (1 << 15)
+#define MCI_TXFIFOFULL (1 << 16)
+#define MCI_RXFIFOFULL (1 << 17)
+#define MCI_TXFIFOEMPTY (1 << 18)
+#define MCI_RXFIFOEMPTY (1 << 19)
+#define MCI_TXDATAAVLBL (1 << 20)
+#define MCI_RXDATAAVLBL (1 << 21)
+#define MCI_SDIOIT (1 << 22)
+/*
+ * SDI Clear register offset
+ */
+#define MMCICLEAR 0x038
+#define MCI_CMDCRCFAILCLR (1 << 0)
+#define MCI_DATACRCFAILCLR (1 << 1)
+#define MCI_CMDTIMEOUTCLR (1 << 2)
+#define MCI_DATATIMEOUTCLR (1 << 3)
+#define MCI_TXUNDERRUNCLR (1 << 4)
+#define MCI_RXOVERRUNCLR (1 << 5)
+#define MCI_CMDRESPENDCLR (1 << 6)
+#define MCI_CMDSENTCLR (1 << 7)
+#define MCI_DATAENDCLR (1 << 8)
+#define MCI_DATABLOCKENDCLR (1 << 10)
+#define MCI_SDIOITCLR (1 << 22)
+/*
+ * SDI Mask register offset
+ */
+#define MMCIMASK0 0x03c
+/*
+ * SDI Mask register bits
+ */
+#define MCI_CMDCRCFAILMASK (1 << 0)
+#define MCI_DATACRCFAILMASK (1 << 1)
+#define MCI_CMDTIMEOUTMASK (1 << 2)
+#define MCI_DATATIMEOUTMASK (1 << 3)
+#define MCI_TXUNDERRUNMASK (1 << 4)
+#define MCI_RXOVERRUNMASK (1 << 5)
+#define MCI_CMDRESPENDMASK (1 << 6)
+#define MCI_CMDSENTMASK (1 << 7)
+#define MCI_DATAENDMASK (1 << 8)
+#define MCI_DATABLOCKENDMASK (1 << 10)
+#define MCI_CMDACTIVEMASK (1 << 11)
+#define MCI_TXACTIVEMASK (1 << 12)
+#define MCI_RXACTIVEMASK (1 << 13)
+#define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
+#define MCI_RXFIFOHALFFULLMASK (1 << 15)
+#define MCI_TXFIFOFULLMASK (1 << 16)
+#define MCI_RXFIFOFULLMASK (1 << 17)
+#define MCI_TXFIFOEMPTYMASK (1 << 18)
+#define MCI_RXFIFOEMPTYMASK (1 << 19)
+#define MCI_TXDATAAVLBLMASK (1 << 20)
+#define MCI_RXDATAAVLBLMASK (1 << 21)
+#define MCI_SDIOITMASK (1 << 22)
+
+#define MMCIMASK1 0x040
+#define MMCIFIFOCNT 0x048
+#define MMCIFIFO 0x080 /* to 0x0bc */
+
+#define MCI_DATA_ERR \
+ (MCI_RXOVERRUN | MCI_TXUNDERRUN | MCI_DATATIMEOUT | \
+ MCI_DATACRCFAIL | MCI_STBITERR)
+#define MCI_IRQENABLE \
+ (MCI_CMDCRCFAIL | MCI_DATACRCFAIL | MCI_CMDTIMEOUT | \
+ MCI_DATATIMEOUT | MCI_TXUNDERRUN | MCI_RXOVERRUN | \
+ MCI_CMDRESPEND | MCI_CMDSENT | MCI_DATABLOCKEND)
+#define MCI_DATA_IRQ (MCI_DATA_ERR | MCI_DATAEND)
+#define MCI_XFER_IRQ_MASK \
+ (MCI_TXFIFOEMPTY | MCI_TXFIFOHALFEMPTY | \
+ MCI_RXFIFOHALFFULL | MCI_RXDATAAVLBL)
+#define MCI_CMD_IRQ \
+ (MCI_CMDCRCFAIL | MCI_CMDTIMEOUT | MCI_CMDRESPEND | \
+ MCI_CMDSENT)
+#define MCI_XFER_IRQ \
+ (MCI_TXFIFOHALFEMPTY | MCI_RXFIFOHALFFULL)
+
+/*
+ * The size of the FIFO in bytes.
+ */
+#define MCI_FIFOSIZE 16
+#define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2)
+#define NR_SG 16
+
+#define OCR_AVAIL (MMC_VDD_17_18 | MMC_VDD_18_19 | \
+ /*MMC_VDD_28_29 |*/ \
+ MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_32_33 | \
+ MMC_VDD_33_34)
+#define INVALID_PIPEID (-1)
+
+/**
+ * struct u8500_mmci_host - host device structure
+ * @base: pointer to the device baseaddress
+ * @mrq: pointer to the request structure
+ * @data: pointer to the data structure
+ * @mmc: pointer to the mmc_host structure
+ * @clk: pointer to the clock
+ * @data_xfered: variable which updates the data_transfered
+ * @lock: spinlock variable
+ * @sg_ptr: scatter list pointer
+ *
+ * host controller Internal device structure
+ */
+struct u8500_mmci_host {
+ void __iomem *base;
+ struct mmc_request *mrq;
+ struct mmc_command *cmd;
+ struct mmc_data *data;
+ struct mmc_host *mmc;
+ struct clk *clk;
+#ifdef CONFIG_REGULATOR
+ struct regulator *regulator;
+#endif
+ unsigned int data_xfered;
+ spinlock_t lock;
+ unsigned int mclk;
+ unsigned int cclk;
+ int (*card_detect_intr_value) (void);
+ unsigned int oldstat;
+ unsigned int dmach_mmc2mem;
+ unsigned int dmach_mem2mmc;
+ unsigned int dma_fifo_addr;
+ unsigned int dma_fifo_dev_type_rx;
+ unsigned int dma_fifo_dev_type_tx;
+ unsigned int level_shifter;
+ dma_addr_t dma;
+ unsigned long caps; /* Host capabilities */
+ unsigned int sg_len;
+ /* pio stuff */
+ struct scatterlist *sg_ptr;
+ unsigned int sg_off;
+ unsigned int size;
+ unsigned int *buffer;
+ unsigned int *dma_buffer;
+ void *dma_done; /* completion data */
+ int devicemode;
+ unsigned int is_sdio;
+ int sdio_setirq;
+ int sdio_irqstatus;
+ int aligned_blksz;
+ int aligned_size;
+ struct mmc_board *board;
+ unsigned long reg_context[2];
+};
+
+/* Define the current mode */
+#define MCI_DMAMODE 0x01
+#define MCI_POLLINGMODE 0x02
+#define MCI_INTERRUPTMODE 0x03
+#define MCI_ALLINTERRUPTS (0x007FFFFF)
+#define MMCCLRSTATICFLAGS (0x000007FF)
+#define MCI_MAXVOLTTRIAL (200) /* 200 times */
+#define MAX_FREQ (24000000)
+#define MAX_DATA (64*512)
+#define CLK_MAX 50000000
+#define CLK_DIV 0xFF
+/*
+ * different card states
+ */
+enum card_state {
+ CARD_STATE_EMPTY = -1,
+ CARD_STATE_IDLE,
+ CARD_STATE_READY,
+ CARD_STATE_IDENT,
+ CARD_STATE_STBY,
+ CARD_STATE_TRAN,
+ CARD_STATE_DATA,
+ CARD_STATE_RCV,
+ CARD_STATE_PRG,
+ CARD_STATE_DIS,
+};
+/*
+ * struct mmc_board - mmc board dependent structure
+ * @init: function pointer for mmc board related initialization
+ * @exit: function pointer for mmc board related de-initialization
+ *
+ * SDMMC platfoem dependent structure
+ */
+struct mmc_board {
+ int (*init) (struct amba_device *dev);
+ void (*exit) (struct amba_device *dev);
+ int (*set_power) (struct device *dev, int power_on);
+ int (*card_detect)(void (*callback)(void *parameter), void *);
+ int (*card_detect_intr_value) (void);
+ unsigned int dma_fifo_addr;
+ unsigned int dma_fifo_dev_type_rx;
+ unsigned int dma_fifo_dev_type_tx;
+ unsigned int level_shifter;
+ unsigned long caps; /* Host capabilities */
+ int is_sdio; /* To check if the bus is SD/MMC or sdio */
+#ifdef CONFIG_REGULATOR
+ const char *supply;
+#endif
+};
+
+
diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h
new file mode 100755
index 00000000000..af512cd7b09
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/msp.h
@@ -0,0 +1,963 @@
+/*
+ * Copyright (c) 2009 STMicroelectronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+#ifndef _STM_MSP_HEADER
+#define _STM_MSP_HEADER
+#include <linux/device.h>
+#include <linux/spinlock.h>
+#include <linux/i2s/i2s.h>
+#include <asm/dma.h>
+#include <mach/dma.h>
+#include <linux/irqreturn.h>
+/* Generic config struct. Use the actual values defined below for global
+ * control register
+ */
+typedef enum {
+ MSP_MULTICHANNEL_DISABLED = 0,
+ MSP_MULTICHANNEL_ENABLED = 1
+} t_msp_multichannel_enable;
+
+typedef enum {
+ MSP_STATE_IDLE = 0,
+ MSP_STATE_CONFIGURED = 1,
+ MSP_STATE_RUN = 2,
+} t_msp_state;
+
+typedef enum {
+ MSP_COMPARISON_DISABLED = 0,
+ MSP_COMPARISON_NONEQUAL_ENABLED = 2,
+ MSP_COMPARISON_EQUAL_ENABLED = 3
+} t_msp_rx_comparison_enable_mode;
+
+#define RMCEN_BIT 0
+#define RMCSF_BIT 1
+#define RCMPM_BIT 3
+#define TMCEN_BIT 5
+#define TNCSF_BIT 6
+
+typedef struct {
+ t_msp_multichannel_enable rx_multichannel_enable;
+ t_msp_multichannel_enable tx_multichannel_enable;
+ t_msp_rx_comparison_enable_mode rx_comparison_enable_mode;
+ u8 padding;
+ u32 comparison_value;
+ u32 comparison_mask;
+ u32 rx_channel_0_enable;
+ u32 rx_channel_1_enable;
+ u32 rx_channel_2_enable;
+ u32 rx_channel_3_enable;
+ u32 tx_channel_0_enable;
+ u32 tx_channel_1_enable;
+ u32 tx_channel_2_enable;
+ u32 tx_channel_3_enable;
+} t_msp_multichannel_config;
+
+enum msp_data_size {
+ MSP_DATA_SIZE_DEFAULT = -1,
+ MSP_DATA_SIZE_8BIT,
+ MSP_DATA_SIZE_10BIT,
+ MSP_DATA_SIZE_12BIT,
+ MSP_DATA_SIZE_14BIT,
+ MSP_DATA_SIZE_16BIT,
+ MSP_DATA_SIZE_20BIT,
+ MSP_DATA_SIZE_24BIT,
+ MSP_DATA_SIZE_32BIT,
+};
+
+/**
+ * struct msp_protocol_desc- MSP Protocol desc structure per MSP.
+ * @rx_phase_mode: rx_phase_mode whether single or dual.
+ * @tx_phase_mode: tx_phase_mode whether single or dual.
+ * @rx_phase2_start_mode: rx_phase2_start_mode whether imediate or after
+ * some delay.
+ * @tx_phase2_start_mode: tx_phase2_start_mode whether imediate or after
+ * some delay.
+ * @rx_bit_transfer_format: MSP or LSB.
+ * @tx_bit_transfer_format: MSP or LSB.
+ * @rx_frame_length_1: Frame1 length 1,2,3..
+ * @rx_frame_length_2: Frame2 length 1,2,3..
+ * @tx_frame_length_1: Frame1 length 1,2,3..
+ * @tx_frame_length_2: Frame2 length 1,2,3..
+ * @rx_element_length_1: Element1 length 1,2,...
+ * @rx_element_length_2: Element2 length 1,2,...
+ * @tx_element_length_1: Element1 length 1,2,...
+ * @tx_element_length_2: Element2 length 1,2,...
+ * @rx_data_delay: Delay in clk cycle after frame sync
+ * @tx_data_delay: Delay in clk cycle after frame sync
+ * @rx_clock_pol: Rxpol whether rising or falling.It indicates pol of bit clock.
+ * @tx_clock_pol: Txpol whether rising or falling.It indicates pol of bit clock.
+ * @rx_frame_sync_pol: Frame sync pol whether rising or Falling.
+ * @tx_frame_sync_pol: Frame sync pol whether rising or Falling.
+ * @rx_half_word_swap: Word swap half word, full word.
+ * @tx_half_word_swap: Word swap half word, full word.
+ * @compression_mode: Compression mode whether Alaw or Ulaw or disabled.
+ * @expansion_mode: Compression mode whether Alaw or Ulaw or disabled.
+ * @spi_clk_mode: Spi clock mode to be enabled or not.
+ * @spi_burst_mode: Spi burst mode to be enabled or not.
+ * @frame_sync_ignore: Frame sync to be ignored or not. Ignore in case of Audio
+ * codec acting as Master.
+ * @frame_period: Frame period (clk cycles) after which new frame sync occurs.
+ * @frame_width: Frame width (clk cycles) after which frame sycn changes state.
+ * @total_clocks_for_one_frame: No. of clk cycles per frame.
+ *
+ * Main Msp protocol descriptor data structure to be used to store various info
+ * in transmit or recevie configuration registers of an MSP.
+ */
+
+struct msp_protocol_desc {
+ u32 rx_phase_mode;
+ u32 tx_phase_mode;
+ u32 rx_phase2_start_mode;
+ u32 tx_phase2_start_mode;
+ u32 rx_bit_transfer_format;
+ u32 tx_bit_transfer_format;
+ u32 rx_frame_length_1;
+ u32 rx_frame_length_2;
+ u32 tx_frame_length_1;
+ u32 tx_frame_length_2;
+ u32 rx_element_length_1;
+ u32 rx_element_length_2;
+ u32 tx_element_length_1;
+ u32 tx_element_length_2;
+ u32 rx_data_delay;
+ u32 tx_data_delay;
+ u32 rx_clock_pol;
+ u32 tx_clock_pol;
+ u32 rx_frame_sync_pol;
+ u32 tx_frame_sync_pol;
+ u32 rx_half_word_swap;
+ u32 tx_half_word_swap;
+ u32 compression_mode;
+ u32 expansion_mode;
+ u32 spi_clk_mode;
+ u32 spi_burst_mode;
+ u32 frame_sync_ignore;
+ u32 frame_period;
+ u32 frame_width;
+ u32 total_clocks_for_one_frame;
+};
+
+/**
+ * struct trans_data - MSP transfer data structure used during xfer.
+ * @message: i2s message.
+ * @msp: msp structure.
+ * @tx_handler: callback handler for transmit path.
+ * @rx_handler: callback handler for receive path.
+ * @tx_callback_data: callback data for transmit.
+ * @rx_callback_data: callback data for receive.
+ *
+ */
+struct trans_data {
+ struct i2s_message message;
+ struct msp_struct *msp;
+ irqreturn_t(*tx_handler) (void *data, int irq);
+ irqreturn_t(*rx_handler) (void *data, int irq);
+ void *tx_callback_data;
+ void *rx_callback_data;
+};
+
+/**
+ * struct msp_generic_config- MSP configuration structure used by i2s client.
+ * @input_clock_freq: Input clock frequency default is 48MHz.
+ * @rx_clock_sel: Receive clock selection (Provided by Sample Gen or external
+ * source).
+ * @tx_clock_sel: Transmit clock selection (Provided by Sample Gen or external.
+ * source).
+ * @srg_clock_sel: APB clock or clock dervied from Slave (Audio codec).
+ * @rx_frame_sync_pol: Receive frame sync polarity.
+ * @tx_frame_sync_pol: Transmit frame sync polarity.
+ * @rx_frame_sync_sel: Rx frame sync signal is provided by which source.
+ * External source or by frame generator logic.
+ * @tx_frame_sync_sel: Tx frame sync signal is provided by which source.
+ * External source or by frame generator logic.
+ * @rx_fifo_config: Receive fifo enable or not.
+ * @tx_fifo_config: Transmit fifo enable or not.
+ * @spi_clk_mode: In case of SPI protocol spi modes: Normal, Zero delay or
+ * half cycle delay.
+ * @spi_burst_mode: Spi burst mode is enabled or not.
+ * @loopback_enable: Loopback mode.
+ * @tx_data_enable: Transmit extra delay enable.
+ * @default_protocol_desc: Flag to indicate client defined protocol desc or
+ * statically defined in msp.h.
+ * @protocol_desc: Protocol desc structure filled by i2s client driver.
+ * In case client defined default_prtocol_desc as 0.
+ * @multichannel_configured: multichannel configuration structure.
+ * @multichannel_config: multichannel is enabled or not.
+ * @direction: Transmit, Receive or Both.
+ * @work_mode: Dma, Polling or Interrupt.
+ * @protocol: I2S, PCM, etc.
+ * @frame_freq: Sampling freq at which data is sampled.
+ * @frame_size: size of element.
+ * @data_size: data size which defines the format in which data is written on
+ * transmit or receive fifo. Only three modes 8,16,32 are supported.
+ * @def_elem_len: Flag to indicate whether default element length is to be used
+ * or should be changed acc to data size defined by user at run time.
+ * @handler: callback handler in case of interrupt or dma.
+ * @tx_callback_data: Callback data for transmit.
+ * @rx_callback_data: Callback data for receive.
+ *
+ * Main Msp configuration data structure used by i2s client driver to fill
+ * various info like data size, frequency etc.
+ */
+struct msp_generic_config {
+ unsigned int input_clock_freq;
+ unsigned int rx_clock_sel;
+ unsigned int tx_clock_sel;
+ unsigned int srg_clock_sel;
+ unsigned int rx_frame_sync_pol;
+ unsigned int tx_frame_sync_pol;
+ unsigned int rx_frame_sync_sel;
+ unsigned int tx_frame_sync_sel;
+ unsigned int rx_fifo_config;
+ unsigned int tx_fifo_config;
+ unsigned int spi_clk_mode;
+ unsigned int spi_burst_mode;
+ unsigned int loopback_enable;
+ unsigned int tx_data_enable;
+ unsigned int default_protocol_desc;
+ struct msp_protocol_desc protocol_desc;
+ int multichannel_configured;
+ t_msp_multichannel_config multichannel_config;
+ unsigned int direction;
+ unsigned int work_mode;
+ unsigned int protocol;
+ unsigned int frame_freq;
+ unsigned int frame_size;
+ enum msp_data_size data_size;
+ unsigned int def_elem_len;
+ irqreturn_t(*handler) (void *data, int err_or_data);
+ void *tx_callback_data;
+ void *rx_callback_data;
+
+};
+
+/*** Protocols ***/
+enum {
+ MSP_I2S_PROTOCOL,
+ MSP_PCM_PROTOCOL,
+ MSP_PCM_COMPAND_PROTOCOL,
+ MSP_AC97_PROTOCOL,
+ MSP_MASTER_SPI_PROTOCOL,
+ MSP_SLAVE_SPI_PROTOCOL,
+ MSP_INVALID_PROTOCOL
+};
+
+/*** Sample Frequencies ***/
+/* These are no longer required, frequencies in Hz can be used directly */
+enum {
+ MSP_SAMPLE_FREQ_NOT_SUPPORTED = -1,
+ MSP_SAMPLE_FREQ_8KHZ = 8000,
+ MSP_SAMPLE_FREQ_12KHZ = 12000,
+ MSP_SAMPLE_FREQ_16KHZ = 16000,
+ MSP_SAMPLE_FREQ_24KHZ = 24000,
+ MSP_SAMPLE_FREQ_32KHZ = 32000,
+ MSP_SAMPLE_FREQ_44KHZ = 44000,
+ MSP_SAMPLE_FREQ_48KHZ = 48000,
+ MSP_SAMPLE_FREQ_64KHZ = 64000,
+ MSP_SAMPLE_FREQ_88KHZ = 88000,
+ MSP_SAMPLE_FREQ_96KHZ = 96000,
+ MSP_SAMPLE_FREQ_22KHZ = 22000,
+ MSP_SAMPLE_FREQ_11KHZ = 11000
+};
+
+/*** Input Frequencies ***/
+/* These are no longer required, frequencies in Hz can be used directly */
+typedef enum {
+ MSP_INPUT_FREQ_1MHZ = 1000,
+ MSP_INPUT_FREQ_2MHZ = 2000,
+ MSP_INPUT_FREQ_3MHZ = 3000,
+ MSP_INPUT_FREQ_4MHZ = 4000,
+ MSP_INPUT_FREQ_5MHZ = 5000,
+ MSP_INPUT_FREQ_6MHZ = 6000,
+ MSP_INPUT_FREQ_8MHZ = 8000,
+ MSP_INPUT_FREQ_11MHZ = 11000,
+ MSP_INPUT_FREQ_12MHZ = 12000,
+ MSP_INPUT_FREQ_16MHZ = 16000,
+ MSP_INPUT_FREQ_22MHZ = 22000,
+ MSP_INPUT_FREQ_24MHZ = 24000,
+ MSP_INPUT_FREQ_48MHZ = 48000
+} t_msp_in_clock_freq;
+
+#define MSP_INPUT_FREQ_APB 48000000
+
+/*** Stereo mode. Used for APB data accesses as 16 bits accesses (mono),
+ * 32 bits accesses (stereo).
+ ***/
+enum {
+ MSP_MONO,
+ MSP_STEREO
+};
+
+/* Direction (Transmit/Receive mode) */
+enum {
+ MSP_TRANSMIT_MODE,
+ MSP_RECEIVE_MODE,
+ MSP_BOTH_T_R_MODE
+};
+
+/* Dma mode should be used for large transfers,
+ * polling mode should be used for transfers of a few bytes
+ */
+enum {
+ MSP_DMA_MODE,
+ MSP_POLLING_MODE,
+ MSP_INTERRUPT_MODE
+};
+
+/* User client for the MSP */
+typedef enum {
+ MSP_NO_USER = 0,
+ MSP_USER_SPI,
+ MSP_USER_ALSA,
+ MSP_USER_SAA,
+} t_msp_user;
+
+/*Flag structure for MSPx*/
+typedef struct {
+ struct semaphore lock;
+ t_msp_user user;
+} msp_flag;
+
+/* User client for the MSP */
+typedef enum {
+ MSP_NO_MODE = 0,
+ MSP_MODE_SPI,
+ MSP_MODE_NON_SPI,
+} t_msp_mode;
+
+/* Transmit and receive configuration register */
+#define MSP_BIG_ENDIAN 0x00000000
+#define MSP_LITTLE_ENDIAN 0x00001000
+#define MSP_UNEXPECTED_FS_ABORT 0x00000000
+#define MSP_UNEXPECTED_FS_IGNORE 0x00008000
+#define MSP_NON_MODE_BIT_MASK 0x00009000
+
+/* Global configuration register
+--------------------------------*/
+#define RX_ENABLE 0x00000001
+#define RX_FIFO_ENABLE 0x00000002
+#define RX_SYNC_SRG 0x00000010
+#define RX_CLK_POL_RISING 0x00000020
+#define RX_CLK_SEL_SRG 0x00000040
+#define TX_ENABLE 0x00000100
+#define TX_FIFO_ENABLE 0x00000200
+#define TX_SYNC_SRG_PROG 0x00001800
+#define TX_SYNC_SRG_AUTO 0x00001000
+#define TX_CLK_POL_RISING 0x00002000
+#define TX_CLK_SEL_SRG 0x00004000
+#define TX_EXTRA_DELAY_ENABLE 0x00008000
+#define SRG_ENABLE 0x00010000
+#define FRAME_GEN_ENABLE 0x00100000
+#define SRG_CLK_SEL_APB 0x00000000
+#define RX_FIFO_SYNC_HI 0x00000000
+#define TX_FIFO_SYNC_HI 0x00000000
+#define SPI_CLK_MODE_NORMAL 0x00000000
+
+/* SPI Clock Modes enumertion
+ * SPI clock modes of MSP provides compatibility with
+ * the SPI protocol.MSP supports 2 SPI transfer formats.
+ * MSP_ZERO_DELAY_SPI_MODE:MSP transmits data over Tx/Rx
+ * Lines immediately after MSPTCK/MSPRCK rising/falling edge.
+ * MSP_HALF_CYCLE_DELY_SPI_MODE:MSP transmits data one-half cycle
+ * ahead of the rising/falling edge of the MSPTCK
+ */
+enum {
+ MSP_NON_SPI_PROTOCOL = 0,
+ MSP_ZERO_DELAY_SPI_MODE = 2,
+ MSP_HALF_CYCLE_DELY_SPI_MODE = 3
+};
+
+#define MSP_FRAME_SIZE_AUTO -1
+
+
+#define MSP_DR 0x00
+#define MSP_GCR 0x04
+#define MSP_TCF 0x08
+#define MSP_RCF 0x0c
+#define MSP_SRG 0x10
+#define MSP_FLR 0x14
+#define MSP_DMACR 0x18
+
+#define MSP_IMSC 0x20
+#define MSP_RIS 0x24
+#define MSP_MIS 0x28
+#define MSP_ICR 0x2c
+#define MSP_MCR 0x30
+#define MSP_RCV 0x34
+#define MSP_RCM 0x38
+
+#define MSP_TCE0 0x40
+#define MSP_TCE1 0x44
+#define MSP_TCE2 0x48
+#define MSP_TCE3 0x4c
+
+#define MSP_RCE0 0x60
+#define MSP_RCE1 0x64
+#define MSP_RCE2 0x68
+#define MSP_RCE3 0x6c
+
+#define MSP_ITCR 0x80
+#define MSP_ITIP 0x84
+#define MSP_ITOP 0x88
+#define MSP_TSTDR 0x8c
+
+#define MSP_PID0 0xfe0
+#define MSP_PID1 0xfe4
+#define MSP_PID2 0xfe8
+#define MSP_PID3 0xfec
+
+#define MSP_CID0 0xff0
+#define MSP_CID1 0xff4
+#define MSP_CID2 0xff8
+#define MSP_CID3 0xffc
+
+/* Single or dual phase mode */
+enum {
+ MSP_SINGLE_PHASE,
+ MSP_DUAL_PHASE
+};
+
+/* Frame length
+------------------*/
+enum {
+ MSP_FRAME_LENGTH_1 = 0,
+ MSP_FRAME_LENGTH_2 = 1,
+ MSP_FRAME_LENGTH_4 = 3,
+ MSP_FRAME_LENGTH_8 = 7,
+ MSP_FRAME_LENGTH_12 = 11,
+ MSP_FRAME_LENGTH_16 = 15,
+ MSP_FRAME_LENGTH_20 = 19,
+ MSP_FRAME_LENGTH_32 = 31,
+ MSP_FRAME_LENGTH_48 = 47,
+ MSP_FRAME_LENGTH_64 = 63
+};
+
+/* Element length */
+enum {
+ MSP_ELEM_LENGTH_8 = 0,
+ MSP_ELEM_LENGTH_10 = 1,
+ MSP_ELEM_LENGTH_12 = 2,
+ MSP_ELEM_LENGTH_14 = 3,
+ MSP_ELEM_LENGTH_16 = 4,
+ MSP_ELEM_LENGTH_20 = 5,
+ MSP_ELEM_LENGTH_24 = 6,
+ MSP_ELEM_LENGTH_32 = 7
+};
+enum {
+ MSP_DATA_TRANSFER_WIDTH_BYTE,
+ MSP_DATA_TRANSFER_WIDTH_HALFWORD,
+ MSP_DATA_TRANSFER_WIDTH_WORD
+};
+enum {
+ MSP_FRAME_SYNC_UNIGNORE = 0,
+ MSP_FRAME_SYNC_IGNORE = 1,
+
+};
+enum {
+ MSP_PHASE2_START_MODE_IMEDIATE,
+ MSP_PHASE2_START_MODE_FRAME_SYNC
+};
+enum {
+ MSP_BTF_MS_BIT_FIRST = 0,
+ MSP_BTF_LS_BIT_FIRST = 1
+};
+
+enum {
+ MSP_FRAME_SYNC_POL_ACTIVE_HIGH = 0,
+ MSP_FRAME_SYNC_POL_ACTIVE_LOW = 1
+};
+/* Data delay (in bit clock cycles)
+---------------------------------------*/
+enum {
+ MSP_DELAY_0 = 0,
+ MSP_DELAY_1 = 1,
+ MSP_DELAY_2 = 2,
+ MSP_DELAY_3 = 3
+};
+
+/* Configurations of clocks (transmit, receive or sample rate generator)
+-------------------------------------------------------------------------*/
+enum {
+ MSP_FALLING_EDGE = 0,
+ MSP_RISING_EDGE = 1,
+};
+
+enum {
+ MSP_HWS_NO_SWAP = 0,
+ MSP_HWS_BYTE_SWAP_IN_WORD = 1,
+ MSP_HWS_BYTE_SWAP_IN_EACH_HALF_WORD = 2,
+ MSP_HWS_HALF_WORD_SWAP_IN_WORD = 3
+};
+enum {
+ MSP_COMPRESS_MODE_LINEAR = 0,
+ MSP_COMPRESS_MODE_MU_LAW = 2,
+ MSP_COMPRESS_MODE_A_LAW = 3
+};
+enum {
+ MSP_SPI_CLOCK_MODE_NON_SPI = 0,
+ MSP_SPI_CLOCK_MODE_ZERO_DELAY = 2,
+ MSP_SPI_CLOCK_MODE_HALF_CYCLE_DELAY = 3
+};
+enum {
+ MSP_SPI_BURST_MODE_DISABLE = 0,
+ MSP_SPI_BURST_MODE_ENABLE = 1
+};
+enum {
+ MSP_EXPAND_MODE_LINEAR = 0,
+ MSP_EXPAND_MODE_LINEAR_SIGNED = 1,
+ MSP_EXPAND_MODE_MU_LAW = 2,
+ MSP_EXPAND_MODE_A_LAW = 3
+};
+/* Protocol dependant parameters list */
+#define RX_ENABLE_MASK 0x00000001
+#define RX_FIFO_ENABLE_MASK 0x00000002
+#define RX_FRAME_SYNC_MASK 0x00000004
+#define DIRECT_COMPANDING_MASK 0x00000008
+#define RX_SYNC_SEL_MASK 0x00000010
+#define RX_CLK_POL_MASK 0x00000020
+#define RX_CLK_SEL_MASK 0x00000040
+#define LOOPBACK_MASK 0x00000080
+#define TX_ENABLE_MASK 0x00000100
+#define TX_FIFO_ENABLE_MASK 0x00000200
+#define TX_FRAME_SYNC_MASK 0x00000400
+#define TX_MSP_TDR_TSR 0x00000800
+#define TX_SYNC_SEL_MASK 0x00001800
+#define TX_CLK_POL_MASK 0x00002000
+#define TX_CLK_SEL_MASK 0x00004000
+#define TX_EXTRA_DELAY_MASK 0x00008000
+#define SRG_ENABLE_MASK 0x00010000
+#define SRG_CLK_POL_MASK 0x00020000
+#define SRG_CLK_SEL_MASK 0x000C0000
+#define FRAME_GEN_EN_MASK 0x00100000
+#define SPI_CLK_MODE_MASK 0x00600000
+#define SPI_BURST_MODE_MASK 0x00800000
+
+#define RXEN_BIT 0
+#define RFFEN_BIT 1
+#define RFSPOL_BIT 2
+#define DCM_BIT 3
+#define RFSSEL_BIT 4
+#define RCKPOL_BIT 5
+#define RCKSEL_BIT 6
+#define LBM_BIT 7
+#define TXEN_BIT 8
+#define TFFEN_BIT 9
+#define TFSPOL_BIT 10
+#define TFSSEL_BIT 11
+#define TCKPOL_BIT 13
+#define TCKSEL_BIT 14
+#define TXDDL_BIT 15
+#define SGEN_BIT 16
+#define SCKPOL_BIT 17
+#define SCKSEL_BIT 18
+#define FGEN_BIT 20
+#define SPICKM_BIT 21
+#define TBSWAP_BIT 28
+
+#define msp_rx_clkpol_bit(n) ((n & 1) << RCKPOL_BIT)
+#define msp_tx_clkpol_bit(n) ((n & 1) << TCKPOL_BIT)
+#define msp_spi_clk_mode_bits(n) ((n & 3) << SPICKM_BIT)
+
+/* Use this to clear the clock mode bits to non-spi */
+#define MSP_NON_SPI_CLK_MASK 0x00600000
+
+#define P1ELEN_BIT 0
+#define P1FLEN_BIT 3
+#define DTYP_BIT 10
+#define ENDN_BIT 12
+#define DDLY_BIT 13
+#define FSIG_BIT 15
+#define P2ELEN_BIT 16
+#define P2FLEN_BIT 19
+#define P2SM_BIT 26
+#define P2EN_BIT 27
+#define FRAME_SYNC_BIT 15
+
+#define msp_p1_elem_len_bits(n) (n & 0x00000007)
+#define msp_p2_elem_len_bits(n) (((n) << P2ELEN_BIT) & 0x00070000)
+#define msp_p1_frame_len_bits(n) (((n) << P1FLEN_BIT) & 0x00000378)
+#define msp_p2_frame_len_bits(n) (((n) << P2FLEN_BIT) & 0x03780000)
+#define msp_data_delay_bits(n) (((n) << DDLY_BIT) & 0x00003000)
+#define msp_data_type_bits(n) (((n) << DTYP_BIT) & 0x00000600)
+#define msp_p2_start_mode_bit(n) ((n << P2SM_BIT) & 0x04000000)
+#define msp_p2_enable_bit(n) ((n << P2EN_BIT) & 0x08000000)
+#define msp_set_endiannes_bit(n) ((n << ENDN_BIT) & 0x00001000)
+#define msp_frame_sync_pol(n) ((n << TFSPOL_BIT) & 0x00000400)
+#define msp_data_word_swap(n) ((n << TBSWAP_BIT) & 0x30000000)
+#define msp_set_companding_mode(n) ((n << DTYP_BIT) & 0x00000c00)
+#define msp_set_frame_sync_ignore(n) ((n << FRAME_SYNC_BIT) & 0x00008000)
+
+/* Flag register
+--------------------*/
+#define RX_BUSY 0x00000001
+#define RX_FIFO_EMPTY 0x00000002
+#define RX_FIFO_FULL 0x00000004
+#define TX_BUSY 0x00000008
+#define TX_FIFO_EMPTY 0x00000010
+#define TX_FIFO_FULL 0x00000020
+
+#define RBUSY_BIT 0
+#define RFE_BIT 1
+#define RFU_BIT 2
+#define TBUSY_BIT 3
+#define TFE_BIT 4
+#define TFU_BIT 5
+
+/* Multichannel control register
+---------------------------------*/
+#define RMCEN_BIT 0
+#define RMCSF_BIT 1
+#define RCMPM_BIT 3
+#define TMCEN_BIT 5
+#define TNCSF_BIT 6
+
+/* Sample rate generator register
+------------------------------------*/
+#define SCKDIV_BIT 0
+#define FRWID_BIT 10
+#define FRPER_BIT 16
+
+#define SCK_DIV_MASK 0x0000003FF
+#define frame_width_bits(n) (((n) << FRWID_BIT) & 0x0000FC00)
+#define frame_period_bits(n) (((n) << FRPER_BIT) & 0x1FFF0000)
+
+/* DMA controller register
+---------------------------*/
+#define RX_DMA_ENABLE 0x00000001
+#define TX_DMA_ENABLE 0x00000002
+
+#define RDMAE_BIT 0
+#define TDMAE_BIT 1
+
+/*Interrupt Register
+-----------------------------------------*/
+#define RECEIVE_SERVICE_INT 0x00000001
+#define RECEIVE_OVERRUN_ERROR_INT 0x00000002
+#define RECEIVE_FRAME_SYNC_ERR_INT 0x00000004
+#define RECEIVE_FRAME_SYNC_INT 0x00000008
+#define TRANSMIT_SERVICE_INT 0x00000010
+#define TRANSMIT_UNDERRUN_ERR_INT 0x00000020
+#define TRANSMIT_FRAME_SYNC_ERR_INT 0x00000040
+#define TRANSMIT_FRAME_SYNC_INT 0x00000080
+#define ALL_INT 0x000000ff
+
+/* Protocol configuration values
+* I2S: Single phase, 16 bits, 2 words per frame
+-----------------------------------------------*/
+#define I2S_PROTOCOL_DESC \
+{ \
+ MSP_SINGLE_PHASE, \
+ MSP_SINGLE_PHASE, \
+ MSP_PHASE2_START_MODE_IMEDIATE, \
+ MSP_PHASE2_START_MODE_IMEDIATE, \
+ MSP_BTF_MS_BIT_FIRST, \
+ MSP_BTF_MS_BIT_FIRST, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_ELEM_LENGTH_32, \
+ MSP_ELEM_LENGTH_32, \
+ MSP_ELEM_LENGTH_32, \
+ MSP_ELEM_LENGTH_32, \
+ MSP_DELAY_1, \
+ MSP_DELAY_1, \
+ MSP_RISING_EDGE, \
+ MSP_RISING_EDGE, \
+ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \
+ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \
+ MSP_HWS_NO_SWAP, \
+ MSP_HWS_NO_SWAP, \
+ MSP_COMPRESS_MODE_LINEAR, \
+ MSP_EXPAND_MODE_LINEAR, \
+ MSP_SPI_CLOCK_MODE_NON_SPI, \
+ MSP_SPI_BURST_MODE_DISABLE, \
+ MSP_FRAME_SYNC_IGNORE, \
+ 31, \
+ 15, \
+ 32, \
+}
+#define PCM_PROTOCOL_DESC \
+{ \
+ MSP_DUAL_PHASE, \
+ MSP_DUAL_PHASE, \
+ MSP_PHASE2_START_MODE_FRAME_SYNC, \
+ MSP_PHASE2_START_MODE_FRAME_SYNC, \
+ MSP_BTF_MS_BIT_FIRST, \
+ MSP_BTF_MS_BIT_FIRST, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_ELEM_LENGTH_16, \
+ MSP_ELEM_LENGTH_16, \
+ MSP_ELEM_LENGTH_16, \
+ MSP_ELEM_LENGTH_16, \
+ MSP_DELAY_0, \
+ MSP_DELAY_0, \
+ MSP_FALLING_EDGE, \
+ MSP_FALLING_EDGE, \
+ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \
+ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \
+ MSP_HWS_NO_SWAP, \
+ MSP_HWS_NO_SWAP, \
+ MSP_COMPRESS_MODE_LINEAR, \
+ MSP_EXPAND_MODE_LINEAR, \
+ MSP_SPI_CLOCK_MODE_NON_SPI, \
+ MSP_SPI_BURST_MODE_DISABLE, \
+ MSP_FRAME_SYNC_IGNORE, \
+ 255, \
+ 0, \
+ 256, \
+}
+/* Companded PCM: Single phase, 8 bits, 1 word per frame
+--------------------------------------------------------*/
+#define PCM_COMPAND_PROTOCOL_DESC \
+{ \
+ MSP_SINGLE_PHASE, \
+ MSP_SINGLE_PHASE, \
+ MSP_PHASE2_START_MODE_FRAME_SYNC, \
+ MSP_PHASE2_START_MODE_FRAME_SYNC, \
+ MSP_BTF_MS_BIT_FIRST, \
+ MSP_BTF_MS_BIT_FIRST, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_ELEM_LENGTH_8, \
+ MSP_ELEM_LENGTH_8, \
+ MSP_ELEM_LENGTH_8, \
+ MSP_ELEM_LENGTH_8, \
+ MSP_DELAY_0, \
+ MSP_DELAY_0, \
+ MSP_FALLING_EDGE, \
+ MSP_RISING_EDGE, \
+ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \
+ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \
+ MSP_HWS_NO_SWAP, \
+ MSP_HWS_NO_SWAP, \
+ MSP_COMPRESS_MODE_LINEAR, \
+ MSP_EXPAND_MODE_LINEAR, \
+ MSP_SPI_CLOCK_MODE_NON_SPI, \
+ MSP_SPI_BURST_MODE_DISABLE, \
+ MSP_FRAME_SYNC_IGNORE, \
+ 255, \
+ 0, \
+ 256, \
+}
+
+/* AC97: Double phase, 1 element of 16 bits during first phase,
+* 12 elements of 20 bits in second phase.
+--------------------------------------------------------------*/
+#define AC97_PROTOCOL_DESC \
+{ \
+ MSP_DUAL_PHASE, \
+ MSP_DUAL_PHASE, \
+ MSP_PHASE2_START_MODE_FRAME_SYNC, \
+ MSP_PHASE2_START_MODE_FRAME_SYNC, \
+ MSP_BTF_MS_BIT_FIRST, \
+ MSP_BTF_MS_BIT_FIRST, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_12, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_12, \
+ MSP_ELEM_LENGTH_16, \
+ MSP_ELEM_LENGTH_20, \
+ MSP_ELEM_LENGTH_16, \
+ MSP_ELEM_LENGTH_20, \
+ MSP_DELAY_1, \
+ MSP_DELAY_1, \
+ MSP_FALLING_EDGE, \
+ MSP_RISING_EDGE, \
+ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \
+ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \
+ MSP_HWS_NO_SWAP, \
+ MSP_HWS_NO_SWAP, \
+ MSP_COMPRESS_MODE_LINEAR, \
+ MSP_EXPAND_MODE_LINEAR, \
+ MSP_SPI_CLOCK_MODE_NON_SPI, \
+ MSP_SPI_BURST_MODE_DISABLE, \
+ MSP_FRAME_SYNC_IGNORE, \
+ 255, \
+ 0, \
+ 256, \
+}
+
+#define SPI_MASTER_PROTOCOL_DESC \
+{ \
+ MSP_SINGLE_PHASE, \
+ MSP_SINGLE_PHASE, \
+ MSP_PHASE2_START_MODE_FRAME_SYNC, \
+ MSP_PHASE2_START_MODE_FRAME_SYNC, \
+ MSP_BTF_MS_BIT_FIRST, \
+ MSP_BTF_MS_BIT_FIRST, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_ELEM_LENGTH_8, \
+ MSP_ELEM_LENGTH_8, \
+ MSP_ELEM_LENGTH_8, \
+ MSP_ELEM_LENGTH_8, \
+ MSP_DELAY_1, \
+ MSP_DELAY_1, \
+ MSP_RISING_EDGE, \
+ MSP_FALLING_EDGE, \
+ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \
+ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \
+ MSP_HWS_NO_SWAP, \
+ MSP_HWS_NO_SWAP, \
+ MSP_COMPRESS_MODE_LINEAR, \
+ MSP_EXPAND_MODE_LINEAR, \
+ MSP_SPI_CLOCK_MODE_NON_SPI, \
+ MSP_SPI_BURST_MODE_DISABLE, \
+ MSP_FRAME_SYNC_IGNORE, \
+ 255, \
+ 0, \
+ 256, \
+}
+
+#define SPI_SLAVE_PROTOCOL_DESC \
+{ \
+ MSP_SINGLE_PHASE, \
+ MSP_SINGLE_PHASE, \
+ MSP_PHASE2_START_MODE_FRAME_SYNC, \
+ MSP_PHASE2_START_MODE_FRAME_SYNC, \
+ MSP_BTF_MS_BIT_FIRST, \
+ MSP_BTF_MS_BIT_FIRST, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_FRAME_LENGTH_1, \
+ MSP_ELEM_LENGTH_8, \
+ MSP_ELEM_LENGTH_8, \
+ MSP_ELEM_LENGTH_8, \
+ MSP_ELEM_LENGTH_8, \
+ MSP_DELAY_1, \
+ MSP_DELAY_1, \
+ MSP_RISING_EDGE, \
+ MSP_FALLING_EDGE, \
+ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \
+ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \
+ MSP_HWS_NO_SWAP, \
+ MSP_HWS_NO_SWAP, \
+ MSP_COMPRESS_MODE_LINEAR, \
+ MSP_EXPAND_MODE_LINEAR, \
+ MSP_SPI_CLOCK_MODE_NON_SPI, \
+ MSP_SPI_BURST_MODE_DISABLE, \
+ MSP_FRAME_SYNC_IGNORE, \
+ 255, \
+ 0, \
+ 256, \
+}
+
+#define MSP_FRAME_PERIOD_IN_MONO_MODE 256
+#define MSP_FRAME_PERIOD_IN_STEREO_MODE 32
+#define MSP_FRAME_WIDTH_IN_STEREO_MODE 16
+
+/* No of registers to backup during
+ * suspend resume */
+#define MAX_MSP_BACKUP_REGS 36
+
+typedef enum {
+ MSP_0_I2S_CONTROLLER = 1,
+ MSP_1_I2S_CONTROLLER,
+ MSP_2_I2S_CONTROLLER,
+} t_i2s_controller;
+
+/**
+ * struct msp_struct - Main msp controller data structure per MSP.
+ * @work_mode: Mode i.e dma, polling or interrupt.
+ * @id: Controller id like MSP1 or MSP2 etc.
+ * @msp_io_error: To indicate error while transferring.
+ * @registers: MSP's register base address.
+ * @actual_data_size: Data size in which data needs to send or receive.
+ * @irq: MSP's irq number.
+ * @i2s_cont: MSP's Controller's structure pointer created per MSP.
+ * @gpio_alt_func: Gpio Alt function id of particular msp.
+ * @lock: semaphore lock acquired while configuring msp.
+ * @pipe_params_rx: Receive dma pipe structure.
+ * @pipe_params_tx: Transmit dma pipe structure.
+ * @msp_tx_dma_addr: Transmit Base Address of msp for DMA.
+ * @msp_rx_dma_addr: Receive Base Address of msp for DMA.
+ * @msp_base_addr: Physical Base Address of msp.
+ * @tx_pipeid: Txpipeid for DMA.
+ * @rx_pipeid: Rxpipeid for DMA.
+ * @msp_state: Current state of msp.
+ * @read: Function pointer for read, u8_msp_read,u16_msp_read,u32_msp_read.
+ * @write: Function pointer for write, u8_msp_write,u16_msp_write,u32_msp_write.
+ * @transfer: Function pointer for type of transfer i.e dma,polling or interrupt
+ * @xfer_data: MSP's transfer data structure. Contains info about current xfer.
+ * @plat_init: MSP's initialization function.
+ * @plat_exit: MSP's Exit function.
+ * @notify_timer: Timer used in Polling mode to prevent hang.
+ * @polling_flag: Flag used in error handling while polling.
+ * @def_elem_len: Flag indicates whether default elem len to be used in
+ * protocol_desc or not.
+ *
+ * Main Msp private data structure to be used to store various info of a
+ * particular MSP.Longer description
+ */
+struct msp_struct {
+ int work_mode;
+ t_i2s_controller id;
+ int msp_io_error;
+ void __iomem *registers;
+ enum msp_data_size actual_data_size;
+ int irq;
+ struct i2s_controller *i2s_cont;
+ u32 gpio_alt_func;
+ struct semaphore lock;
+ struct stm_dma_pipe_info pipe_params_rx;
+ struct stm_dma_pipe_info pipe_params_tx;
+ u32 msp_tx_dma_addr;
+ u32 msp_rx_dma_addr;
+ u32 msp_base_addr;
+ dmach_t tx_pipeid;
+ dmach_t rx_pipeid;
+ t_msp_state msp_state;
+ void (*read) (struct trans_data *xfer_data);
+ void (*write) (struct trans_data *xfer_data);
+ int (*transfer) (struct msp_struct *msp, struct i2s_message *message);
+ struct trans_data xfer_data;
+ int (*plat_init) (u32);
+ int (*plat_exit) (u32);
+ struct timer_list notify_timer;
+ int polling_flag;
+ int def_elem_len;
+ struct clk *clk;
+ unsigned int direction;
+ int users;
+ int loopback_enable;
+ u32 backup_regs[MAX_MSP_BACKUP_REGS];
+};
+
+/**
+ * struct msp_i2s_platform_datat - Main msp controller platform data structure.
+ * @id: Controller id like MSP1 or MSP2 etc.
+ * @gpio_alt_func: Gpio Alt function id of particular msp.
+ * @msp_tx_dma_addr: Transmit Base Address of msp for DMA.
+ * @msp_rx_dma_addr: Receive Base Address of msp for DMA.
+ * @msp_base_addr: Physical Base Address of msp.
+ * msp_i2s_init@: MSP's initialization function.
+ * @msp_i2s_exit: MSP's Exit function.
+ * @backup_regs: used for backup registers during suspend resume.
+ *
+ * Platform data structure passed by devices.c file.
+ */
+struct msp_i2s_platform_data {
+ t_i2s_controller id;
+ u32 gpio_alt_func;
+ u32 msp_tx_dma_addr;
+ u32 msp_rx_dma_addr;
+ u32 msp_base_addr;
+ int (*msp_i2s_init) (u32);
+ int (*msp_i2s_exit) (u32);
+};
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/mtu.h b/arch/arm/mach-ux500/include/mach/mtu.h
new file mode 100755
index 00000000000..d3725fec7de
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/mtu.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson
+ * MultiTimerUnit register definitions, copied from Nomadik 8815
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __ASM_ARCH_MTU_H
+#define __ASM_ARCH_MTU_H
+
+/*
+ * The MTU device hosts four different counters, with 4 set of
+ * registers. These are register names.
+ */
+
+#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
+#define MTU_RIS 0x04 /* Raw interrupt status */
+#define MTU_MIS 0x08 /* Masked interrupt status */
+#define MTU_ICR 0x0C /* Interrupt clear register */
+
+/* per-timer registers take 0..3 as argument */
+#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
+#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
+#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
+#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
+
+/* bits for the control register */
+#define MTU_CRn_ENA 0x80
+#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
+#define MTU_CRn_PRESCALE_MASK 0x0c
+#define MTU_CRn_PRESCALE_1 0x00
+#define MTU_CRn_PRESCALE_16 0x04
+#define MTU_CRn_PRESCALE_256 0x08
+#define MTU_CRn_32BITS 0x02
+#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
+
+/* Other registers are usual amba/primecell registers, currently not used */
+#define MTU_ITCR 0xff0
+#define MTU_ITOP 0xff4
+
+#define MTU_PERIPH_ID0 0xfe0
+#define MTU_PERIPH_ID1 0xfe4
+#define MTU_PERIPH_ID2 0xfe8
+#define MTU_PERIPH_ID3 0xfeC
+
+#define MTU_PCELL0 0xff0
+#define MTU_PCELL1 0xff4
+#define MTU_PCELL2 0xff8
+#define MTU_PCELL3 0xffC
+
+
+#ifdef CONFIG_LOCAL_TIMERS
+extern void __iomem *twd_base;
+#endif
+
+#endif /* __ASM_ARCH_MTU_H */
+
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h b/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h
new file mode 100755
index 00000000000..02dabe166cb
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_PRCMU_FW_API_H
+#define __MACH_PRCMU_FW_API_H
+
+#include <linux/interrupt.h>
+#include "prcmu-fw-defs_v1.h"
+
+enum hw_acc_dev{
+ HW_ACC_SVAMMDSP = 0,
+ HW_ACC_SVAPIPE = 1,
+ HW_ACC_SIAMMDSP = 2,
+ HW_ACC_SIAPIPE = 3,
+ HW_ACC_SGA = 4,
+ HW_ACC_B2R2 = 5,
+ HW_ACC_MCDE = 6,
+ HW_ACC_ESRAM1 = 7,
+ HW_ACC_ESRAM2 = 8,
+ HW_ACC_ESRAM3 = 9,
+ HW_ACC_ESRAM4 = 10,
+};
+
+int prcmu_get_boot_status(void);
+int prcmu_set_rc_a2p(enum romcode_write_t);
+enum romcode_read_t prcmu_get_rc_p2a(void);
+int prcmu_set_fifo_4500wu(enum intr_wakeup_t);
+enum ap_pwrst_t prcmu_get_xp70_current_state(void);
+int prcmu_set_ap_mode(enum ap_pwrst_trans_t);
+int prcmu_set_ddr_pwrst(enum ddr_pwrst_t);
+int prcmu_set_arm_opp(enum arm_opp_t);
+int prcmu_get_arm_opp(void);
+int prcmu_set_ape_opp(enum ape_opp_t);
+int prcmu_get_ape_opp(void);
+int prcmu_set_hwacc(enum hw_acc_dev, enum hw_accst_t);
+/*mbox_2_arm_stat_t prcmu_get_m2a_status(void); */
+/*mbox_to_arm_err_t prcmu_get_m2a_error(void); */
+enum dvfs_stat_t prcmu_get_m2a_dvfs_status(void);
+enum mbox_2_arm_hwacc_pwr_stat_t prcmu_get_m2a_hwacc_status(void);
+int prcmu_set_irq_wakeup(uint32_t);
+int prcmu_apply_ap_state_transition(enum ap_pwrst_trans_t transition,
+ enum ddr_pwrst_t ddr_state_req,
+ int _4500_fifo_wakeup);
+
+int prcmu_i2c_read(u8, u8);
+int prcmu_i2c_write(u8, u8, u8);
+int prcmu_i2c_get_status(void);
+int prcmu_i2c_get_bank(void);
+int prcmu_i2c_get_reg(void);
+int prcmu_i2c_get_val(void);
+
+int prcmu_ac_wake_req(void);
+int prcmu_ac_sleep_req(void);
+int prcmu_configure_wakeup_events(u32, u32);
+int prcmu_get_wakeup_reason(u32 *, u8 *);
+int prcmu_ack_wakeup_reason(void);
+void prcmu_set_callback_cawakereq(void (*func)(u8));
+void prcmu_system_reset(void);
+int prcmu_is_ca_wake_req_pending(void);
+int prcmu_read_ack_mb7(void);
+irqreturn_t prcmu_ack_mbox_irq_handler(int, void *);
+
+#endif /* __MACH_PRCMU_FW_API_V1_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-fw-defs_ed.h b/arch/arm/mach-ux500/include/mach/prcmu-fw-defs_ed.h
new file mode 100755
index 00000000000..849bacf0f8f
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-fw-defs_ed.h
@@ -0,0 +1,415 @@
+/*
+ * Copyright (c) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+
+
+#ifndef __MACH_PRCMU_FW_DEFS_ED_H
+#define __MACH_PRCMU_FW_DEFS_ED_H
+
+/**
+ * enum state_t - ON/OFF state definition
+ *
+ * OFF: State is ON
+ * ON: State is OFF
+ */
+enum state_ed_t {
+ OFF_ED = 0x00,
+ ON_ED = 0x01
+};
+
+/**
+ * enum clk_arm_t - ARM Cortex A9 clock schemes
+ *
+ * A9_OFF:
+ * A9_BOOT:
+ * A9_OPPT1:
+ * A9_OPPT2:
+ * A9_EXTCLK:
+ */
+enum clk_arm_ed_t {
+ A9_OFF_ED,
+ A9_BOOT_ED,
+ A9_OPPT1_ED,
+ A9_OPPT2_ED,
+ A9_EXTCLK_ED
+};
+
+/**
+ * enum clk_gen_t - GEN#0/GEN#1 clock schemes
+ *
+ * GEN_OFF:
+ * GEN_BOOT:
+ * GEN_OPPT1:
+ */
+enum clk_gen_ed_t {
+ GEN_OFF_ED,
+ GEN_BOOT_ED,
+ GEN_OPPT1_ED,
+};
+
+/* some information between arm and xp70 */
+
+/**
+ * enum romcode_write_t - Romcode message written by A9 AND read by XP70
+ *
+ * RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
+ * RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
+ * romcode. The xp70 will go into self-reset
+ */
+enum romcode_write_ed_t {
+ RDY_2_DS_ED = 0x09,
+ RDY_2_XP70_RST_ED = 0x10
+};
+
+/**
+ * enum romcode_read_t - Romcode message written by XP70 and read by A9
+ *
+ * INIT: Init value when romcode field is not used
+ * FS_2_DS: Value set when power state is going from ApExecute to
+ * ApDeepSleep
+ * END_DS: Value set when ApDeepSleep power state is reached coming from
+ * ApExecute state
+ * DS_TO_FS: Value set when power state is going from ApDeepSleep to
+ * ApExecute
+ * END_FS: Value set when ApExecute power state is reached coming from
+ * ApDeepSleep state
+ * SWR: Value set when power state is going to ApReset
+ * END_SWR: Value set when the xp70 finished executing ApReset actions and
+ * waits for romcode acknowledgment to go to self-reset
+ */
+enum romcode_read_ed_t {
+ INIT_ED = 0x00,
+ FS_2_DS_ED = 0x0A,
+ END_DS_ED = 0x0B,
+ DS_TO_FS_ED = 0x0C,
+ END_FS_ED = 0x0D,
+ SWR_ED = 0x0E,
+ END_SWR_ED = 0x0F
+};
+
+/**
+ * enum ap_pwrst_t - current power states defined in PRCMU firmware
+ *
+ * NO_PWRST: Current power state init
+ * AP_BOOT: Current power state is apBoot
+ * AP_EXECUTE: Current power state is apExecute
+ * AP_DEEP_SLEEP: Current power state is apDeepSleep
+ * AP_SLEEP: Current power state is apSleep
+ * AP_IDLE: Current power state is apIdle
+ * AP_RESET: Current power state is apReset
+ */
+enum ap_pwrst_ed_t {
+ NO_PWRST_ED = 0x00,
+ AP_BOOT_ED = 0x01,
+ AP_EXECUTE_ED = 0x02,
+ AP_DEEP_SLEEP_ED = 0x03,
+ AP_SLEEP_ED = 0x04,
+ AP_IDLE_ED = 0x05,
+ AP_RESET_ED = 0x06
+};
+
+/**
+ * enum ap_pwrst_trans_t - Transition states defined in PRCMU firmware
+ *
+ * NO_TRANSITION: No power state transition
+ * APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep
+ * APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep
+ * APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute
+ * APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to
+ * ApDeepSleep
+ * APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
+ */
+enum ap_pwrst_trans_ed_t {
+ NO_TRANSITION_ED = 0x00,
+ APEXECUTE_TO_APSLEEP_ED = 0xFB,
+ APIDLE_TO_APSLEEP_ED = 0xFC,
+ APBOOT_TO_APEXECUTE_ED = 0xFD,
+ APEXECUTE_TO_APDEEPSLEEP_ED = 0xFE,
+ APEXECUTE_TO_APIDLE_ED = 0xFF
+};
+
+/**
+ * enum ddr_pwrst_t - DDR power states definition
+ *
+ * DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
+ * TOBEDEFINED: to be defined
+ */
+enum ddr_pwrst_ed_t {
+ DDR_PWR_STATE_UNCHANGED_ED = 0x00,
+ TOBEDEFINED_ED = 0x01
+};
+
+/**
+ * enum arm_opp_t - ARM OPP states definition
+ *
+ * ARM_NO_CHANGE: The ARM operating point is unchanged
+ * ARM_100_OPP: The new ARM operating point is arm100opp
+ * ARM_50_OPP: The new ARM operating point is arm100opp
+ * ARM_EXTCLK: The new ARM operating point is armExtClk
+ */
+enum arm_opp_ed_t {
+ ARM_NO_CHANGE_ED = 0x00,
+ ARM_100_OPP_ED = 0x01,
+ ARM_50_OPP_ED = 0x02,
+ ARM_EXTCLK_ED = 0x03
+};
+
+/**
+ * enum ape_opp_t - APE OPP states definition
+ *
+ * APE_NO_CHANGE: The APE operating point is unchanged
+ * APE_100_OPP: The new APE operating point is ape100opp
+ */
+enum ape_opp_ed_t {
+ APE_NO_CHANGE_ED = 0x00,
+ APE_100_OPP_ED = 0x01
+};
+
+/**
+ * enum hw_accst_t - State definition for hardware accelerator
+ *
+ * HW_NO_CHANGE: The hardware accelerator state must remain unchanged
+ * HW_OFF: The hardware accelerator must be switched off
+ * HW_OFF_RAMRET: The hardware accelerator must be switched off with its
+ * internal RAM in retention
+ * HW_ON: The hwa hadware accelerator hwa must be switched on
+ */
+enum hw_accst_ed_t {
+ HW_NO_CHANGE_ED = 0x00,
+ HW_OFF_ED = 0x01,
+ HW_OFF_RAMRET_ED = 0x02,
+ HW_ON_ED = 0x03
+};
+
+/**
+ * enum mbox_2_arm_stat_t - Status messages definition for mbox_arm
+ *
+ * Status messages definition for mbox_arm coming from XP70 to ARM
+ *
+ * BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been
+ * completed
+ * DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been
+ * completed
+ * SLEEPOK: The apExecute to apSleep state transition has been completed
+ * IDLEOK: The apExecute to apIdle state transition has been completed
+ * SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed
+ * SOFTRESETGO : The A9 watchdog/SoftReset state is on going
+ * BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going
+ * EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on
+ * going
+ * DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on
+ * going
+ * DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has
+ * been completed
+ * EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going
+ * SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going
+ * SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been
+ * completed
+ * EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going
+ * IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going
+ * IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been
+ * completed
+ * INIT_STATUS: Status init
+ */
+enum mbox_2_arm_stat_ed_t {
+ BOOT_TO_EXECUTEOK_ED = 0xFF,
+ DEEPSLEEPOK_ED = 0xFE,
+ SLEEPOK_ED = 0xFD,
+ IDLEOK_ED = 0xFC,
+ SOFTRESETOK_ED = 0xFB,
+ SOFTRESETGO_ED = 0xFA,
+ BOOT_TO_EXECUTE_ED = 0xF9,
+ EXECUTE_TO_DEEPSLEEP_ED = 0xF8,
+ DEEPSLEEP_TO_EXECUTE_ED = 0xF7,
+ DEEPSLEEP_TO_EXECUTEOK_ED = 0xF6,
+ EXECUTE_TO_SLEEP_ED = 0xF5,
+ SLEEP_TO_EXECUTE_ED = 0xF4,
+ SLEEP_TO_EXECUTEOK_ED = 0xF3,
+ EXECUTE_TO_IDLE_ED = 0xF2,
+ IDLE_TO_EXECUTE_ED = 0xF1,
+ IDLE_TO_EXECUTEOK_ED = 0xF0,
+ INIT_STATUS_ED = 0x00
+};
+
+/**
+ * enum mbox_2_armdvfs_stat_t - DVFS status messages definition
+ *
+ * DVFS status messages definition for mbox_arm coming from XP70 to ARM
+ * DVFS_GO: A state transition DVFS is on going
+ * DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP
+ * DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP
+ * DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK
+ * DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for
+ * NOCHGCLK
+ * DVFS_INITSTATUS: Value init
+ */
+enum mbox_2_armdvfs_stat_ed_t {
+ DVFS_GO_ED = 0xFF,
+ DVFS_ARM100OPPOK_ED = 0xFE,
+ DVFS_ARM50OPPOK_ED = 0xFD,
+ DVFS_ARMEXTCLKOK_ED = 0xFC,
+ DVFS_NOCHGTCLKOK_ED = 0xFB,
+ DVFS_INITSTATUS_ED = 0x00
+};
+
+/**
+ * enum mbox_2_arm_hwacc_pwr_stat_t - Hardware Accelarator status message
+ *
+ * HWACC_PWRST_GO: A state transition on hardware accelerator is on going
+ * HWACC_PWRST_OK: The state transition on hardware accelerator has been
+ * completed
+ * HWACC_PWRSTATUS_INIT: Value init
+ */
+enum mbox_2_arm_hwacc_pwr_stat_ed_t {
+ HWACC_PWRST_GO_ED = 0xFF,
+ HWACC_PWRST_OK_ED = 0xFE,
+ HWACC_PWRSTATUS_INIT_ED = 0x00
+};
+
+/**
+ * enum sva_mmdsp_stat_t - SVA MMDSP status messages
+ *
+ * SVA_MMDSP_GO: SVAMMDSP interrupt has happened
+ * SVA_MMDSP_INIT: Status init
+ */
+enum sva_mmdsp_stat_ed_t {
+ SVA_MMDSP_GO_ED = 0xFF,
+ SVA_MMDSP_INIT_ED = 0x00
+};
+
+/**
+ * enum sia_mmdsp_stat_t - SIA MMDSP status messages
+ *
+ * SIA_MMDSP_GO: SIAMMDSP interrupt has happened
+ * SIA_MMDSP_INIT: Status init
+ */
+enum sia_mmdsp_stat_ed_t {
+ SIA_MMDSP_GO_ED = 0xFF,
+ SIA_MMDSP_INIT_ED = 0x00
+};
+
+/**
+ * enum intr_wakeup_t - Configure STW4500 FIFO interrupt as wake-up
+ *
+ * INTR_NOT_AS_WAKEUP: The 4500 fifo interrupt is not configured as a
+ * wake-up event
+ * INTR_AS_WAKEUP: The 4500 fifo interrupt is configured as a wake-up event
+ */
+enum intr_wakeup_ed_t {
+ INTR_NOT_AS_WAKEUP_ED = 0x0,
+ INTR_AS_WAKEUP_ED = 0x1
+} intr_wakeup_ed_t;
+
+/**
+ * enum mbox_to_arm_err_t - Error messages definition
+ *
+ * Error messages definition for mbox_arm coming from XP70 to ARM
+ *
+ * INIT_ERR: Init value
+ * PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time
+ * PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time
+ * PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time
+ * PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time
+ * ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time
+ * SYSCLKOK_ERR: The SYSCLK is not available in the given time
+ * BOOT_ERR: Romcode has not validated the XP70 self reset in the given time
+ * ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context
+ * VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered
+ * through I2C has not been correctly executed in the given time
+ * VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered
+ * through I2C has not been correctly executed in the given time
+ * VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through
+ * I2C has not been correctly executed in the given time
+ * VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered
+ * through I2C has not been correctly executed in the given time
+ * VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through
+ * I2C has not been correctly executed in the given time
+ * VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered
+ * through I2C has not been correctly executed in the given time
+ * VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through
+ * I2C has not been correctly executed in the given time
+ * VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C
+ * has not been correctly executed in the given time
+ * VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has
+ * not been correctly executed in the given time
+ * VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has
+ * not been correctly executed in the given time
+ * VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through
+ * I2C has not been correctly executed in the given time
+ * VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through
+ * I2C has not been correctly executed in the given time
+ * VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered
+ * through I2C has not been correctly executed in the given time
+ * CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition
+ * ApBoot to ApExecute but the power current state is not Apboot
+ * CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state
+ * transition from ApExecute to others power state but the
+ * power current state is not ApExecute
+ * CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted
+ * but the power current state is not ApDeepSleep/ApSleep/ApIdle
+ * CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted
+ * but the power current state is not correct
+ * ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not
+ * been correctly executed in the given time
+ * ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not
+ * been correctly executed in the given time
+ * VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not
+ * been correctly executed in the given time
+ * VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not
+ * been correctly executed in the given time
+ * VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not
+ * been correctly executed in the given time
+ */
+enum mbox_to_arm_err_ed_t {
+ INIT_ERR_ED = 0x00,
+ PLLARMLOCKP_ERR_ED = 0x01,
+ PLLDDRLOCKP_ERR_ED = 0x02,
+ PLLSOC0LOCKP_ERR_ED = 0x03,
+ PLLSOC1LOCKP_ERR_ED = 0x04,
+ ARMWFI_ERR_ED = 0x05,
+ SYSCLKOK_ERR_ED = 0x06,
+ BOOT_ERR_ED = 0x07,
+ ROMCODESAVECONTEXT_ED = 0x08,
+ VARMHIGHSPEEDVALTO_ERR_ED = 0x10,
+ VARMHIGHSPEEDACCESS_ERR_ED = 0x11,
+ VARMLOWSPEEDVALTO_ERR_ED = 0x12,
+ VARMLOWSPEEDACCESS_ERR_ED = 0x13,
+ VARMRETENTIONVALTO_ERR_ED = 0x14,
+ VARMRETENTIONACCESS_ERR_ED = 0x15,
+ VAPEHIGHSPEEDVALTO_ERR_ED = 0x16,
+ VSAFEHPVALTO_ERR_ED = 0x17,
+ VMODSEL1VALTO_ERR_ED = 0x18,
+ VMODSEL2VALTO_ERR_ED = 0x19,
+ VARMOFFACCESS_ERR_ED = 0x1A,
+ VAPEOFFACCESS_ERR_ED = 0x1B,
+ VARMRETACCES_ERR_ED = 0x1C,
+ CURAPPWRSTISNOTBOOT_ED = 0x20,
+ CURAPPWRSTISNOTEXECUTE_ED = 0x21,
+ CURAPPWRSTISNOTSLEEPMODE_ED = 0x22,
+ CURAPPWRSTISNOTCORRECTDBG_ED = 0x23,
+ ARMREGU1VALTO_ERR_ED = 0x24,
+ ARMREGU2VALTO_ERR_ED = 0x25,
+ VAPEREGUVALTO_ERR_ED = 0x26,
+ VSMPS3REGUVALTO_ERR_ED = 0x27,
+ VMODREGUVALTO_ERR_ED = 0x28
+};
+
+enum hw_acc_ed_t {
+ SVAMMDSP_ED = 0,
+ SVAPIPE_ED = 1,
+ SIAMMDSP_ED = 2,
+ SIAPIPE_ED = 3,
+ SGA_ED = 4,
+ B2R2MCDE_ED = 5,
+ ESRAM1_ED = 6,
+ ESRAM2_ED = 7,
+ ESRAM3_ED = 8,
+ ESRAM4_ED = 9
+} hw_acc_ed_t;
+
+#endif /* __MACH_PRCMU_FW_API_DEFS_ED_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-fw-defs_v1.h b/arch/arm/mach-ux500/include/mach/prcmu-fw-defs_v1.h
new file mode 100755
index 00000000000..c1442a5c9c2
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-fw-defs_v1.h
@@ -0,0 +1,549 @@
+/*
+ * Copyright (c) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_PRCMU_FW_DEFS_V1_H
+#define __MACH_PRCMU_FW_DEFS_V1_H
+
+#include <linux/interrupt.h>
+
+/**
+ * enum state_t - ON/OFF state definition
+ * @OFF: State is ON
+ * @ON: State is OFF
+ */
+enum state_t {
+ OFF = 0x00,
+ ON = 0x01
+};
+/**
+ * enum ret_state_t - general purpose On/Off/Retention states
+ *
+ */
+enum ret_state_t {
+ OFFST = 0,
+ ONST = 1,
+ RETST = 2
+};
+
+
+/**
+ * enum clk_arm_t - ARM Cortex A9 clock schemes
+ * @A9_OFF:
+ * @A9_BOOT:
+ * @A9_OPPT1:
+ * @A9_OPPT2:
+ * @A9_EXTCLK:
+ */
+enum clk_arm_t {
+ A9_OFF,
+ A9_BOOT,
+ A9_OPPT1,
+ A9_OPPT2,
+ A9_EXTCLK
+};
+
+/**
+ * enum clk_gen_t - GEN#0/GEN#1 clock schemes
+ * @GEN_OFF:
+ * @GEN_BOOT:
+ * @GEN_OPPT1:
+ */
+enum clk_gen_t {
+ GEN_OFF,
+ GEN_BOOT,
+ GEN_OPPT1,
+};
+
+/* some information between arm and xp70 */
+
+/**
+ * enum romcode_write_t - Romcode message written by A9 AND read by XP70
+ * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
+ * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
+ * romcode. The xp70 will go into self-reset
+ */
+enum romcode_write_t {
+ RDY_2_DS = 0x09,
+ RDY_2_XP70_RST = 0x10
+};
+
+/**
+ * enum romcode_read_t - Romcode message written by XP70 and read by A9
+ * @INIT: Init value when romcode field is not used
+ * @FS_2_DS: Value set when power state is going from ApExecute to
+ * ApDeepSleep
+ * @END_DS: Value set when ApDeepSleep power state is reached coming from
+ * ApExecute state
+ * @DS_TO_FS: Value set when power state is going from ApDeepSleep to
+ * ApExecute
+ * @END_FS: Value set when ApExecute power state is reached coming from
+ * ApDeepSleep state
+ * @SWR: Value set when power state is going to ApReset
+ * @END_SWR: Value set when the xp70 finished executing ApReset actions and
+ * waits for romcode acknowledgment to go to self-reset
+ */
+enum romcode_read_t {
+ INIT = 0x00,
+ FS_2_DS = 0x0A,
+ END_DS = 0x0B,
+ DS_TO_FS = 0x0C,
+ END_FS = 0x0D,
+ SWR = 0x0E,
+ END_SWR = 0x0F
+};
+
+
+/**
+ * enum pingpong_t
+ * @PING: value is 0
+ * @PONG: value is 1
+ *
+ * implementation issue: the values are chosen the way that
+ * we can change from ping to pong (resp. pong to ping) by
+ * simply using the 'not' operator in C, e.g. toggling operation:
+ * t_PingPong p = ping; p = ~p;
+ */
+enum pingpong_t {
+ PING = 0x00,
+ PONG = 0xFF
+};
+
+/**
+ * enum wkup_reason_fdst_t
+ * @EVTWR: event has been read by ARM
+ * @EVTST: event has been sent by PRCMU FW
+ * @EVTRD: event has been written by PRCMU FW
+ */
+enum wkup_reason_fdst_t {
+ /* WRF has been written but neither sent nor read by the arm */
+ EVTWR = 1,
+ /* WRF has been written and sent, but not yet read by the arm */
+ EVTST = 2,
+ /* WRF has been written, sent and read by the arm */
+ EVTRD = 0
+}; /* Wake-up reason Field State */
+
+
+
+/**
+ * enum ap_pwrst_t - current power states defined in PRCMU firmware
+ * @NO_PWRST: Current power state init
+ * @AP_BOOT: Current power state is apBoot
+ * @AP_EXECUTE: Current power state is apExecute
+ * @AP_DEEP_SLEEP: Current power state is apDeepSleep
+ * @AP_SLEEP: Current power state is apSleep
+ * @AP_IDLE: Current power state is apIdle
+ * @AP_RESET: Current power state is apReset
+ */
+enum ap_pwrst_t {
+ NO_PWRST = 0x00,
+ AP_BOOT = 0x01,
+ AP_EXECUTE = 0x02,
+ AP_DEEP_SLEEP = 0x03,
+ AP_SLEEP = 0x04,
+ AP_IDLE = 0x05,
+ AP_RESET = 0x06
+};
+
+/**
+ * enum ap_pwrst_trans_t - Transition states defined in PRCMU firmware
+ * @NO_TRANSITION: No power state transition
+ * @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep
+ * @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep
+ * @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute
+ * @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to
+ * ApDeepSleep
+ * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
+ */
+enum ap_pwrst_trans_t {
+ NO_TRANSITION = 0x00,
+ APEXECUTE_TO_APSLEEP = 0x01,
+ APIDLE_TO_APSLEEP = 0x02,
+ APBOOT_TO_APEXECUTE = 0x03,
+ APEXECUTE_TO_APDEEPSLEEP = 0x04,
+ APEXECUTE_TO_APIDLE = 0x05
+};
+
+/**
+ * enum ddr_pwrst_t - DDR power states definition
+ * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
+ * @DDR_PWR_STATE_ON:
+ * @DDR_PWR_STATE_OFFLOWLAT:
+ * @DDR_PWR_STATE_OFFHIGHLAT:
+ */
+enum ddr_pwrst_t {
+ DDR_PWR_STATE_UNCHANGED = 0x00,
+ DDR_PWR_STATE_ON = 0x01,
+ DDR_PWR_STATE_OFFLOWLAT = 0x02,
+ DDR_PWR_STATE_OFFHIGHLAT = 0x03
+};
+
+/**
+ * enum arm_opp_t - ARM OPP states definition
+ * @ARM_NO_CHANGE: The ARM operating point is unchanged
+ * @ARM_100_OPP: The new ARM operating point is arm100opp
+ * @ARM_50_OPP: The new ARM operating point is arm100opp
+ * @ARM_EXTCLK: The new ARM operating point is armExtClk
+ */
+enum arm_opp_t {
+ ARM_NO_CHANGE = 0x00,
+ ARM_100_OPP = 0x02,
+ ARM_50_OPP = 0x03,
+ ARM_EXTCLK = 0x07
+};
+
+/**
+ * enum ape_opp_t - APE OPP states definition
+ * @APE_NO_CHANGE: The APE operating point is unchanged
+ * @APE_100_OPP: The new APE operating point is ape100opp
+ */
+enum ape_opp_t {
+ APE_NO_CHANGE = 0x00,
+ APE_100_OPP = 0x02,
+ APE_50_OPP = 0x03
+};
+
+/**
+ * enum hw_accst_t - State definition for hardware accelerator
+ * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
+ * @HW_OFF: The hardware accelerator must be switched off
+ * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its
+ * internal RAM in retention
+ * @HW_ON: The hwa hadware accelerator hwa must be switched on
+ */
+enum hw_accst_t {
+ HW_NO_CHANGE = 0x00,
+ HW_OFF = 0x01,
+ HW_OFF_RAMRET = 0x02,
+ HW_ON = 0x03
+};
+
+/**
+ * enum mbox_2_arm_stat_t - Status messages definition for mbox_arm
+ * @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been
+ * completed
+ * @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been
+ * completed
+ * @SLEEPOK: The apExecute to apSleep state transition has been completed
+ * @IDLEOK: The apExecute to apIdle state transition has been completed
+ * @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed
+ * @SOFTRESETGO : The A9 watchdog/SoftReset state is on going
+ * @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going
+ * @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on
+ * going
+ * @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on
+ * going
+ * @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has
+ * been completed
+ * @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going
+ * @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going
+ * @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been
+ * completed
+ * @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going
+ * @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going
+ * @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been
+ * completed
+ * @INIT_STATUS: Status init
+ */
+enum ap_pwrsttr_status_t {
+ BOOT_TO_EXECUTEOK = 0xFF,
+ DEEPSLEEPOK = 0xFE,
+ SLEEPOK = 0xFD,
+ IDLEOK = 0xFC,
+ SOFTRESETOK = 0xFB,
+ SOFTRESETGO = 0xFA,
+ BOOT_TO_EXECUTE = 0xF9,
+ EXECUTE_TO_DEEPSLEEP = 0xF8,
+ DEEPSLEEP_TO_EXECUTE = 0xF7,
+ DEEPSLEEP_TO_EXECUTEOK = 0xF6,
+ EXECUTE_TO_SLEEP = 0xF5,
+ SLEEP_TO_EXECUTE = 0xF4,
+ SLEEP_TO_EXECUTEOK = 0xF3,
+ EXECUTE_TO_IDLE = 0xF2,
+ IDLE_TO_EXECUTE = 0xF1,
+ IDLE_TO_EXECUTEOK = 0xF0,
+ RDYTODS_RETURNTOEXE = 0xEF,
+ NORDYTODS_RETURNTOEXE = 0xEE,
+ EXETOSLEEP_RETURNTOEXE = 0xED,
+ EXETOIDLE_RETURNTOEXE = 0xEC,
+ INIT_STATUS = 0xEB,
+
+ /*error messages */
+ INITERROR = 0x00,
+ PLLARMLOCKP_ER = 0x01,
+ PLLDDRLOCKP_ER = 0x02,
+ PLLSOCLOCKP_ER = 0x03,
+ PLLSOCK1LOCKP_ER = 0x04,
+ ARMWFI_ER = 0x05,
+ SYSCLKOK_ER = 0x06,
+ I2C_NACK_DATA_ER = 0x07,
+ BOOT_ER = 0x08,
+ I2C_STATUS_ALWAYS_1 = 0x0A,
+ I2C_NACK_REG_ADDR_ER = 0x0B,
+ I2C_NACK_DATA0123_ER = 0x1B,
+ I2C_NACK_ADDR_ER = 0x1F,
+ CURAPPWRSTISNOT_BOOT = 0x20,
+ CURAPPWRSTISNOT_EXECUTE = 0x21,
+ CURAPPWRSTISNOT_SLEEPMODE = 0x22,
+ CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23,
+ FIFO4500WUISNOT_WUPEVENT = 0x24,
+ PLL32KLOCKP_ER = 0x29,
+ DDRDEEPSLEEPOK_ER = 0x2A,
+ ROMCODEREADY_ER = 0x50,
+ WUPBEFOREDS = 0x51,
+ DDRCONFIG_ER = 0x52,
+ WUPBEFORESLEEP = 0x53,
+ WUPBEFOREIDLE = 0x54
+}; /* earlier called as mbox_2_arm_stat_t */
+
+
+/**
+ * enum dvfs_stat_t - DVFS status messages definition
+ * @DVFS_GO: A state transition DVFS is on going
+ * @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP
+ * @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP
+ * @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK
+ * @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for
+ * NOCHGCLK
+ * @DVFS_INITSTATUS: Value init
+ */
+enum dvfs_stat_t {
+ DVFS_GO = 0xFF,
+ DVFS_ARM100OPPOK = 0xFE,
+ DVFS_ARM50OPPOK = 0xFD,
+ DVFS_ARMEXTCLKOK = 0xFC,
+ DVFS_NOCHGTCLKOK = 0xFB,
+ DVFS_INITSTATUS = 0x00
+};
+
+/**
+ * enum mbox_2_arm_hwacc_pwr_stat_t - Hardware Accelarator status message
+ * @HWACC_PWRST_GO: A state transition on hardware accelerator is on going
+ * @HWACC_PWRST_OK: The state transition on hardware accelerator has been
+ * completed
+ * @HWACC_PWRSTATUS_INIT: Value init
+ */
+enum mbox_2_arm_hwacc_pwr_stat_t {
+ HWACC_PWRST_GO = 0xFF,
+ HWACC_PWRST_OK = 0xFE,
+ HWACC_PWRSTATUS_INIT = 0x00
+};
+
+/**
+ * enum sva_mmdsp_stat_t - SVA MMDSP status messages
+ * @SVA_MMDSP_GO: SVAMMDSP interrupt has happened
+ * @SVA_MMDSP_INIT: Status init
+ */
+enum sva_mmdsp_stat_t {
+ SVA_MMDSP_GO = 0xFF,
+ SVA_MMDSP_INIT = 0x00
+};
+
+/**
+ * enum sia_mmdsp_stat_t - SIA MMDSP status messages
+ * @SIA_MMDSP_GO: SIAMMDSP interrupt has happened
+ * @SIA_MMDSP_INIT: Status init
+ */
+enum sia_mmdsp_stat_t {
+ SIA_MMDSP_GO = 0xFF,
+ SIA_MMDSP_INIT = 0x00
+};
+
+/**
+ * enum intr_wakeup_t - Configure STW4500 FIFO interrupt as wake-up
+ * @NTR_NOT_AS_WAKEUP: The 4500 fifo interrupt is not configured as a
+ * wake-up event
+ * @INTR_AS_WAKEUP: The 4500 fifo interrupt is configured as a wake-up event
+ */
+enum intr_wakeup_t {
+ INTR_NOT_AS_WAKEUP = 0x0,
+ INTR_AS_WAKEUP = 0x1
+};
+
+/**
+ * enum mbox_to_arm_err_t - Error messages definition
+ * @INIT_ERR: Init value
+ * @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time
+ * @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time
+ * @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time
+ * @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time
+ * @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time
+ * @SYSCLKOK_ERR: The SYSCLK is not available in the given time
+ * @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time
+ * @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context
+ * @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered
+ * through I2C has not been correctly executed in the given time
+ * @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered
+ * through I2C has not been correctly executed in the given time
+ * @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through
+ * I2C has not been correctly executed in the given time
+ * @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered
+ * through I2C has not been correctly executed in the given time
+ * @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through
+ * I2C has not been correctly executed in the given time
+ * @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered
+ * through I2C has not been correctly executed in the given time
+ * @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through
+ * I2C has not been correctly executed in the given time
+ * @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C
+ * has not been correctly executed in the given time
+ * @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has
+ * not been correctly executed in the given time
+ * @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has
+ * not been correctly executed in the given time
+ * @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through
+ * I2C has not been correctly executed in the given time
+ * @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through
+ * I2C has not been correctly executed in the given time
+ * @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered
+ * through I2C has not been correctly executed in the given time
+ * @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition
+ * ApBoot to ApExecute but the power current state is not Apboot
+ * @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state
+ * transition from ApExecute to others power state but the
+ * power current state is not ApExecute
+ * @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted
+ * but the power current state is not ApDeepSleep/ApSleep/ApIdle
+ * @CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted
+ * but the power current state is not correct
+ * @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not
+ * been correctly executed in the given time
+ * @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not
+ * been correctly executed in the given time
+ * @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not
+ * been correctly executed in the given time
+ * @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not
+ * been correctly executed in the given time
+ * @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not
+ * been correctly executed in the given time
+ */
+enum mbox_to_arm_err_t {
+ INIT_ERR = 0x00,
+ PLLARMLOCKP_ERR = 0x01,
+ PLLDDRLOCKP_ERR = 0x02,
+ PLLSOC0LOCKP_ERR = 0x03,
+ PLLSOC1LOCKP_ERR = 0x04,
+ ARMWFI_ERR = 0x05,
+ SYSCLKOK_ERR = 0x06,
+ BOOT_ERR = 0x07,
+ ROMCODESAVECONTEXT = 0x08,
+ VARMHIGHSPEEDVALTO_ERR = 0x10,
+ VARMHIGHSPEEDACCESS_ERR = 0x11,
+ VARMLOWSPEEDVALTO_ERR = 0x12,
+ VARMLOWSPEEDACCESS_ERR = 0x13,
+ VARMRETENTIONVALTO_ERR = 0x14,
+ VARMRETENTIONACCESS_ERR = 0x15,
+ VAPEHIGHSPEEDVALTO_ERR = 0x16,
+ VSAFEHPVALTO_ERR = 0x17,
+ VMODSEL1VALTO_ERR = 0x18,
+ VMODSEL2VALTO_ERR = 0x19,
+ VARMOFFACCESS_ERR = 0x1A,
+ VAPEOFFACCESS_ERR = 0x1B,
+ VARMRETACCES_ERR = 0x1C,
+ CURAPPWRSTISNOTBOOT = 0x20,
+ CURAPPWRSTISNOTEXECUTE = 0x21,
+ CURAPPWRSTISNOTSLEEPMODE = 0x22,
+ CURAPPWRSTISNOTCORRECTDBG = 0x23,
+ ARMREGU1VALTO_ERR = 0x24,
+ ARMREGU2VALTO_ERR = 0x25,
+ VAPEREGUVALTO_ERR = 0x26,
+ VSMPS3REGUVALTO_ERR = 0x27,
+ VMODREGUVALTO_ERR = 0x28
+};
+
+enum hw_acc_t {
+ SVAMMDSP = 0,
+ SVAPIPE = 1,
+ SIAMMDSP = 2,
+ SIAPIPE = 3,
+ SGA = 4,
+ B2R2MCDE = 5,
+ ESRAM1 = 6,
+ ESRAM2 = 7,
+ ESRAM3 = 8,
+ ESRAM4 = 9
+};
+
+enum reqmb0_header_t {
+ PWRSTTRH = 0,
+ WKUPCFGH = 1,
+ WKUPH = 2,
+ RDWKUPACKH = 3
+};
+
+enum cs_pwrmgt_t {
+ PWRDNCS0 = 0,
+ WKUPCS0 = 1,
+ PWRDNCS1 = 2,
+ WKUPCS1 = 3
+};
+
+enum reqmb2_header_t {
+ DPS_H = 0,
+ HW_ACCT_AUTO_PWR_H = 1,
+};
+
+/**
+ * enum reqmb4_header_t -Header type for mail box 4
+ * @MEMSTH: The ARM can set what are the expected memory states depending on
+ * the AP power states.
+ * @PARTIALREFRESHH: ARM has to update MR16 & MR17 of SDRAM register, for
+ * partial-refresh of SDRAM, via this mailbox
+ * @AUTOREFRESHH: Enable to change cycle count before enabling automatic
+ * DDR self-refresh
+ * @CSPWRDNH: Enables to lock/unlock one of SDRAM memory cut in self-refresh
+ * In V2,this service will enable to put CS in pwrdn
+ * @SYSCLKH: Enables to switch SYSCLK ON/OFF on the AP side
+ * @USBWKUPH: Used to enable USB wakeup event of PRCMU
+ */
+enum reqmb4_header_t {
+ MEM_ST_H = 0,
+ PARTIAL_S_REFRESH_H = 1,
+ AUTO_REFRESH_H = 2,
+ CS_PWRDN_H = 3,
+ SYSCLK_H = 5,
+ AUTO_PWR_H = 6,
+ USB_WKUP_H = 7
+};
+
+enum ack_mb4_status_t {
+ ACKMB4_INIT = 0,
+ SYSCLKON_OK = 1,
+ DDRON_OK = 2
+};
+
+enum I2C_op_t {
+ I2CWRITE = 0,
+ I2CREAD = 1
+};
+
+enum ack_mb5_status_t {
+ ACKMB5_INIT = 0x00,
+ I2C_WR_OK = 0x01,
+ I2C_RD_OK = 0x02,
+ SYSCLK_OK = 0x03,
+ I2C_TIMEOUT = 0x11,
+ SYSCLK_ER = 0x12,
+ /*Error Status resent by PRCM_HWI2C_SR*/
+ I2CWR_NACK_DATA_ER = 0x07,
+ I2CWR_NACK_REG_ADDR_ER = 0x0B,
+ I2CRDWR_NACK_DATA0123_ER = 0x1B,
+ I2CWR_NACK_ADDR_ER = 0x1F,
+ I2CRD_NACK_ADDR_INIT_ER = 0x0F,
+ I2CRD_NACK_REG_ADDR_INIT_ER = 0x13,
+ I2CRD_NACK_ADDR_ER = 0x17
+};
+
+enum ack_mb7_status_t {
+ MOD_SW_RESET_REQ = 0x03,
+ CA_SLEEP_REQ = 0x02,
+ HOST_PORT_ACK = 0x01,
+ ACKMB7_INIT = 0x00
+};
+
+#endif /* __MACH_PRCMU_FW_DEFS_V1_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
new file mode 100755
index 00000000000..6f4c36cd7f5
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+
+
+#ifndef __MACH_PRCMU_REGS_H
+#define __MACH_PRCMU_REGS_H
+
+#include <mach/hardware.h>
+
+#define _PRCMU_BASE IO_ADDRESS(U8500_PRCMU_BASE)
+
+#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118)
+#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114)
+#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98)
+#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0)
+#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4)
+#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0)
+#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c)
+#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308)
+
+/* ARM WFI Standby signal register */
+#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130)
+#define PRCMU_IOCR (_PRCMU_BASE + 0x310)
+
+
+/* CPU mailbox registers */
+#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc)
+#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100)
+#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104)
+
+/* Dual A9 core interrupt management unit registers */
+#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328)
+#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c)
+#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c)
+#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120)
+#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124)
+#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128)
+#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260)
+#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264)
+#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268)
+#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C)
+
+#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334)
+#define ARM_WAKEUP_MODEM 0x1
+
+/* register for Ack mailbox interrupts */
+#define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C)
+#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494)
+#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174)
+
+#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148)
+#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150)
+#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158)
+#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160)
+#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168)
+#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484)
+#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488)
+#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018)
+
+/* System reset register */
+#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228)
+
+/* Clock management */
+#define PRCM_YYCLKEN0_MGT_SET (_PRCMU_BASE + 0x510)
+#define PRCM_YYCLKEN1_MGT_SET (_PRCMU_BASE + 0x514)
+#define PRCM_YYCLKEN0_MGT_CLR (_PRCMU_BASE + 0x518)
+#define PRCM_YYCLKEN1_MGT_CLR (_PRCMU_BASE + 0x51C)
+#define PRCM_YYCLKEN0_MGT_VAL (_PRCMU_BASE + 0x520)
+#define PRCM_YYCLKEN1_MGT_VAL (_PRCMU_BASE + 0x524)
+
+#define PRCM_SVAMMDSPCLK_MGT (_PRCMU_BASE + 0x008)
+#define PRCM_SIAMMDSPCLK_MGT (_PRCMU_BASE + 0x00C)
+#define PRCM_SGACLK_MGT (_PRCMU_BASE + 0x014)
+#define PRCM_UARTCLK_MGT (_PRCMU_BASE + 0x018)
+#define PRCM_MSP02CLK_MGT (_PRCMU_BASE + 0x01C)
+#define PRCM_MSP1CLK_MGT (_PRCMU_BASE + 0x288)
+#define PRCM_I2CCLK_MGT (_PRCMU_BASE + 0x020)
+#define PRCM_SDMMCCLK_MGT (_PRCMU_BASE + 0x024)
+#define PRCM_SLIMCLK_MGT (_PRCMU_BASE + 0x028)
+#define PRCM_PER1CLK_MGT (_PRCMU_BASE + 0x02C)
+#define PRCM_PER2CLK_MGT (_PRCMU_BASE + 0x030)
+#define PRCM_PER3CLK_MGT (_PRCMU_BASE + 0x034)
+#define PRCM_PER5CLK_MGT (_PRCMU_BASE + 0x038)
+#define PRCM_PER6CLK_MGT (_PRCMU_BASE + 0x03C)
+#define PRCM_PER7CLK_MGT (_PRCMU_BASE + 0x040)
+#define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044)
+#define PRCM_BMLCLK_MGT (_PRCMU_BASE + 0x04C)
+#define PRCM_HSITXCLK_MGT (_PRCMU_BASE + 0x050)
+#define PRCM_HSIRXCLK_MGT (_PRCMU_BASE + 0x054)
+#define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058)
+#define PRCM_APEATCLK_MGT (_PRCMU_BASE + 0x05C)
+#define PRCM_APETRACECLK_MGT (_PRCMU_BASE + 0x060)
+#define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064)
+#define PRCM_IPI2CCLK_MGT (_PRCMU_BASE + 0x068)
+#define PRCM_DSIALTCLK_MGT (_PRCMU_BASE + 0x06C)
+#define PRCM_DMACLK_MGT (_PRCMU_BASE + 0x074)
+#define PRCM_B2R2CLK_MGT (_PRCMU_BASE + 0x078)
+#define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07C)
+#define PRCM_UNIPROCLK_MGT (_PRCMU_BASE + 0x278)
+#define PRCM_SSPCLK_MGT (_PRCMU_BASE + 0x280)
+#define PRCM_RNGCLK_MGT (_PRCMU_BASE + 0x284)
+#define PRCM_UICCCLK_MGT (_PRCMU_BASE + 0x27C)
+
+#endif /* __MACH_PRCMU__REGS_H */
diff --git a/arch/arm/mach-ux500/include/mach/scu.h b/arch/arm/mach-ux500/include/mach/scu.h
new file mode 100755
index 00000000000..492c98c4810
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/scu.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2009 ST Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASMARM_ARCH_SCU_H
+#define __ASMARM_ARCH_SCU_H
+
+#include <mach/hardware.h>
+
+#define SCU_BASE U8500_SCU_BASE
+/*
+ * * SCU registers
+ * */
+#define SCU_CTRL 0x00
+#define SCU_CONFIG 0x04
+#define SCU_CPU_STATUS 0x08
+#define SCU_INVALIDATE 0x0c
+#define SCU_FPGA_REVISION 0x10
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
new file mode 100644
index 00000000000..7da8d8d6a92
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * These symbols are needed for board-specific files to call their
+ * own cpu-specific files
+ */
+#ifndef __ASM_ARCH_SETUP_H
+#define __ASM_ARCH_SETUP_H
+
+#include <asm/mach/time.h>
+#include <linux/init.h>
+
+struct sys_timer;
+struct amba_device;
+
+extern void __init ux500_map_io(void);
+extern void __init u5500_map_io(void);
+extern void __init u8500_map_io(void);
+
+extern void __init ux500_init_devices(void);
+extern void __init u5500_init_devices(void);
+extern void __init u8500_init_devices(void);
+extern void __init u8500_init_regulators(void);
+
+extern void __init u8500_init_irq(void);
+
+extern void __init amba_add_devices(struct amba_device *devs[], int num);
+
+extern struct sys_timer u8500_timer;
+
+#define __IO_DEV_DESC(x, sz) { \
+ .virtual = IO_ADDRESS(x), \
+ .pfn = __phys_to_pfn(x), \
+ .length = sz, \
+ .type = MT_DEVICE, \
+}
+
+#endif /* __ASM_ARCH_SETUP_H */
diff --git a/arch/arm/mach-ux500/include/mach/shrm.h b/arch/arm/mach-ux500/include/mach/shrm.h
new file mode 100755
index 00000000000..99a5608c865
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/shrm.h
@@ -0,0 +1,33 @@
+/*----------------------------------------------------------------------------*/
+/* Copyright (C) ST Ericsson, 2009. */
+/* */
+/* This program is free software; you can redistribute it and/or modify it */
+/* under the terms of the GNU General Public License as published by the Free */
+/* Software Foundation; either version 2.1 of the License, or (at your option */
+/* any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for */
+/*more details. */
+/* */
+/* You should have received a copy of the GNU General Public License */
+/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
+/*----------------------------------------------------------------------------*/
+
+#ifndef __SHM_DRIVER_IF_H__
+#define __SHM_DRIVER_IF_H__
+
+#include <linux/device.h>
+
+struct shrm_plat_data {
+
+ int *pshm_dev_data;
+ struct shm_device *shm_ctrlr;
+};
+
+typedef void (*rx_cb)(void *data, unsigned int length);
+typedef void (*received_msg_handler)(unsigned char l2_header, \
+ void *msg_ptr, unsigned int length);
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
new file mode 100755
index 00000000000..3c1ec85c7dc
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2009 ST Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef ASMARM_ARCH_SMP_H
+#define ASMARM_ARCH_SMP_H
+
+
+#include <asm/hardware/gic.h>
+
+#define hard_smp_processor_id() \
+ ({ \
+ unsigned int cpunum; \
+ __asm__("mrc p15, 0, %0, c0, c0, 5" \
+ : "=r" (cpunum)); \
+ cpunum &= 0x0F; \
+ })
+
+/*
+ * We use IRQ1 as the IPI
+ */
+static inline void smp_cross_call(const struct cpumask *mask)
+{
+ gic_raise_softirq(mask, 1);
+}
+
+/*
+ * Do nothing on MPcore.
+ */
+static inline void smp_cross_call_done(const struct cpumask *mask)
+{
+}
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/ste_conn_devices.h b/arch/arm/mach-ux500/include/mach/ste_conn_devices.h
new file mode 100755
index 00000000000..66846fc5276
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/ste_conn_devices.h
@@ -0,0 +1,227 @@
+/*
+ * file ste_conn_devices.h
+ *
+ * Copyright (C) ST-Ericsson AB 2010
+ *
+ * Board specific device support for the Linux Bluetooth HCI H4 Driver
+ * for ST-Ericsson connectivity controller.
+ * License terms: GNU General Public License (GPL), version 2
+ *
+ * Authors:
+ * Pär-Gunnar Hjälmdahl (par-gunnar.p.hjalmdahl@stericsson.com) for ST-Ericsson.
+ * Henrik Possung (henrik.possung@stericsson.com) for ST-Ericsson.
+ * Josef Kindberg (josef.kindberg@stericsson.com) for ST-Ericsson.
+ * Dariusz Szymszak (dariusz.xd.szymczak@stericsson.com) for ST-Ericsson.
+ * Kjell Andersson (kjell.k.andersson@stericsson.com) for ST-Ericsson.
+ */
+
+#ifndef _STE_CONN_DEVICES_H_
+#define _STE_CONN_DEVICES_H_
+
+#include <linux/types.h>
+#include <linux/skbuff.h>
+
+#define STE_CONN_MAX_NAME_SIZE 30
+
+/** STE_CONN_DEVICES_BT_CMD - Bluetooth HCI H4 channel for Bluetooth commands in the ST-Ericsson connectivity controller.
+ */
+#define STE_CONN_DEVICES_BT_CMD "ste_conn_bt_cmd\0"
+
+/** STE_CONN_DEVICES_BT_ACL - Bluetooth HCI H4 channel for Bluetooth ACL data in the ST-Ericsson connectivity controller.
+ */
+#define STE_CONN_DEVICES_BT_ACL "ste_conn_bt_acl\0"
+
+/** STE_CONN_DEVICES_BT_EVT - Bluetooth HCI H4 channel for Bluetooth events in the ST-Ericsson connectivity controller.
+ */
+#define STE_CONN_DEVICES_BT_EVT "ste_conn_bt_evt\0"
+
+/** STE_CONN_DEVICES_FM_RADIO - Bluetooth HCI H4 channel for FM radio in the ST-Ericsson connectivity controller.
+ */
+#define STE_CONN_DEVICES_FM_RADIO "ste_conn_fm_radio\0"
+
+/** STE_CONN_DEVICES_GNSS - Bluetooth HCI H4 channel for GNSS in the ST-Ericsson connectivity controller.
+ */
+#define STE_CONN_DEVICES_GNSS "ste_conn_gnss\0"
+
+/** STE_CONN_DEVICES_DEBUG - Bluetooth HCI H4 channel for internal debug data in the ST-Ericsson connectivity controller.
+ */
+#define STE_CONN_DEVICES_DEBUG "ste_conn_debug\0"
+
+/** STE_CONN_DEVICES_STE_TOOLS - Bluetooth HCI H4 channel for development tools data in the ST-Ericsson connectivity controller.
+ */
+#define STE_CONN_DEVICES_STE_TOOLS "ste_conn_ste_tools\0"
+
+/** STE_CONN_DEVICES_HCI_LOGGER - Bluetooth HCI H4 channel for logging all transmitted H4 packets (on all channels).
+ */
+#define STE_CONN_DEVICES_HCI_LOGGER "ste_conn_hci_logger\0"
+
+/** STE_CONN_DEVICES_US_CTRL - Bluetooth HCI H:4 channel
+ * for user space initialization and control of the ST-Ericsson connectivity controller.
+ */
+#define STE_CONN_DEVICES_US_CTRL "ste_conn_us_ctrl\0"
+
+/** STE_CONN_DEVICES_BT_AUDIO - Bluetooth HCI H:4 channel
+ * for Bluetooth audio configuration related commands in the ST-Ericsson connectivity controller.
+ */
+#define STE_CONN_DEVICES_BT_AUDIO "ste_conn_bt_audio\0"
+
+/** STE_CONN_DEVICES_FM_RADIO_AUDIO - HCI H:4 channel
+ * for FM audio configuration related commands in the ST-Ericsson connectivity controller.
+ */
+#define STE_CONN_DEVICES_FM_RADIO_AUDIO "ste_conn_fm_audio\0"
+
+/** STE_CONN_DEVICES_CORE- HCI H:4 channel
+ * for core configuration related commands in the ST-Ericsson connectivity controller.
+ */
+#define STE_CONN_DEVICES_CORE "ste_conn_core\0"
+
+/** STE_CONN_NO_CHAR_DEV - Module parameter for
+ * no character devices to be initiated.
+ */
+#define STE_CONN_NO_CHAR_DEV 0x00000000
+
+/** STE_CONN_CHAR_DEV_BT - Module parameter for character device Bluetooth.
+ */
+#define STE_CONN_CHAR_DEV_BT 0x00000001
+
+/** STE_CONN_CHAR_DEV_FM_RADIO - Module parameter for character device FM radio.
+ */
+#define STE_CONN_CHAR_DEV_FM_RADIO 0x00000002
+
+/** STE_CONN_CHAR_DEV_GNSS - Module parameter for character device GNSS.
+ */
+#define STE_CONN_CHAR_DEV_GNSS 0x00000004
+
+/** STE_CONN_CHAR_DEV_DEBUG - Module parameter for character device Debug.
+ */
+#define STE_CONN_CHAR_DEV_DEBUG 0x00000008
+
+/** STE_CONN_CHAR_DEV_STE_TOOLS - Module parameter for character device STE tools.
+ */
+#define STE_CONN_CHAR_DEV_STE_TOOLS 0x00000010
+
+/** STE_CONN_CHAR_DEV_CCD_DEBUG - Module parameter for character device CCD debug.
+ */
+#define STE_CONN_CHAR_DEV_CCD_DEBUG 0x00000020
+
+/** STE_CONN_CHAR_DEV_HCI_LOGGER - Module parameter for character device HCI logger.
+ */
+#define STE_CONN_CHAR_DEV_HCI_LOGGER 0x00000040
+
+/** STE_CONN_CHAR_DEV_US_CTRL - Module parameter for
+ * character device user space control.
+ */
+#define STE_CONN_CHAR_DEV_US_CTRL 0x00000080
+
+/** STE_CONN_CHAR_TEST_DEV - Module parameter for character device test device.
+ */
+#define STE_CONN_CHAR_TEST_DEV 0x00000100
+
+/** STE_CONN_CHAR_DEV_BT_AUDIO - Module parameter for character device BT CMD audio application.
+ */
+#define STE_CONN_CHAR_DEV_BT_AUDIO 0x00000200
+
+/** STE_CONN_CHAR_DEV_FM_RADIO_AUDIO - Module parameter for character device FM audio application.
+ */
+#define STE_CONN_CHAR_DEV_FM_RADIO_AUDIO 0x00000400
+
+/** STE_CONN_CHAR_DEV_CORE - Module parameter for character device core.
+ */
+#define STE_CONN_CHAR_DEV_CORE 0x00000800
+
+/** STE_CONN_CHAR_TEST_DEV - Module parameter for all character devices to be initiated.
+ */
+#define STE_CONN_ALL_CHAR_DEVS 0xFFFFFFFF
+
+/**
+ * ste_conn_devices_get_h4_channel() - Get H4 channel by name.
+ * @name: Name of connectivity user.
+ * @h4_channel: HCI H4 channel to register to.
+ *
+ * Returns:
+ * 0 if there is no error.
+ * -ENXIO if channel was not found.
+ */
+extern int ste_conn_devices_get_h4_channel(char *name, int *h4_channel);
+
+/**
+ * ste_conn_devices_enable_chip() - Enable the controller.
+ */
+extern void ste_conn_devices_enable_chip(void);
+
+/**
+ * ste_conn_devices_disable_chip() - Disable the controller.
+ */
+extern void ste_conn_devices_disable_chip(void);
+
+/**
+ * ste_conn_devices_set_hci_revision() - Stores HCI revision info for the connected connectivity controller.
+ * @hci_version: HCI version from the controller.
+ * @hci_revision: HCI revision from the controller.
+ * @lmp_version: LMP version from the controller.
+ * @lmp_subversion: LMP subversion from the controller.
+ * @manufacturer: Manufacturer ID from the controller.
+ *
+ * See Bluetooth specification and white paper for used controller for details about parameters.
+ */
+extern void ste_conn_devices_set_hci_revision(uint8_t hci_version,
+ uint16_t hci_revision,
+ uint8_t lmp_version,
+ uint8_t lmp_subversion,
+ uint16_t manufacturer);
+
+/**
+ * ste_conn_devices_get_reset_cmd() - Get HCI reset command to use based on connected connectivity controller.
+ * @op_lsb: LSB of HCI opcode in generated packet. NULL if not needed.
+ * @op_msb: MSB of HCI opcode in generated packet. NULL if not needed.
+ *
+ * This command does not add the H4 channel header in front of the message.
+ *
+ * Returns:
+ * NULL if no command shall be sent,
+ * sk_buffer with command otherwise.
+ */
+extern struct sk_buff *ste_conn_devices_get_reset_cmd(uint8_t *op_lsb, uint8_t *op_msb);
+
+/**
+ * ste_conn_devices_get_power_switch_off_cmd() - Get HCI power switch off command to use based on connected connectivity controller.
+ * @op_lsb: LSB of HCI opcode in generated packet. NULL if not needed.
+ * @op_msb: MSB of HCI opcode in generated packet. NULL if not needed.
+ *
+ * This command does not add the H4 channel header in front of the message.
+ *
+ * Returns:
+ * NULL if no command shall be sent,
+ * sk_buffer with command otherwise.
+ */
+extern struct sk_buff *ste_conn_devices_get_power_switch_off_cmd(uint8_t *op_lsb, uint8_t *op_msb);
+
+/**
+ * ste_conn_devices_get_bt_enable_cmd() - Get HCI BT enable command to use based on connected connectivity controller.
+ * @op_lsb: LSB of HCI opcode in generated packet. NULL if not needed.
+ * @op_msb: MSB of HCI opcode in generated packet. NULL if not needed.
+ * @bt_enable: true if Bluetooth IP shall be enabled, false otherwise.
+ *
+ * This command does not add the H4 channel header in front of the message.
+ *
+ * Returns:
+ * NULL if no command shall be sent,
+ * sk_buffer w