diff options
| author | Sundar R Iyer <sundar.iyer@stericsson.com> | 2010-06-24 12:08:37 +0530 |
|---|---|---|
| committer | John Rigby <john.rigby@linaro.org> | 2010-09-02 22:45:51 -0600 |
| commit | 3956b4a499ce066d04fc7e21aee244cf4f582e90 (patch) | |
| tree | 804ad4db7e9e3d9e40a2a6fa72965c5a472594a2 /arch/arm/mach-ux500/include/mach/prcmu-regs.h | |
| parent | 48d5fa309fc3a106e531528867406d6a3adb3059 (diff) | |
| download | linux-2.6.34-ux500-3956b4a499ce066d04fc7e21aee244cf4f582e90.tar.gz | |
ux500: add PRCM timer as an always on clock source
The PRCMU timers are available in the Periph4 or the always-on
power domain, ensuring that these will be functional even when the
system goes to sleep/deep sleep states. The decision to enable/disable
the timers from the ARM is now decisional based on the PRCMU f/w version
(dummy placeholder for now)
ST-Ericsson Change ID: 256290
Signed-off-by: Sundar R Iyer <sundar.iyer@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/1987
Reviewed-by: Jonas ABERG <jonas.aberg@stericsson.com>
Reviewed-by: Rickard ANDERSSON <rickard.andersson@stericsson.com>
Signed-off-by: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
Change-Id: Iec790b71c23c5661652decdfa299a068be50975e
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/2842
Diffstat (limited to 'arch/arm/mach-ux500/include/mach/prcmu-regs.h')
| -rwxr-xr-x | arch/arm/mach-ux500/include/mach/prcmu-regs.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h index 0972342dfb5..fadf75ed896 100755 --- a/arch/arm/mach-ux500/include/mach/prcmu-regs.h +++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h @@ -67,6 +67,11 @@ /* System reset register */ #define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228) +/* PRCM Timer 5 */ +#define PRCM_TIMER_5_REF (_PRCMU_BASE + 0x45C) +#define PRCM_TIMER_5_DOWNCOUNT (_PRCMU_BASE + 0x460) +#define PRCM_TIMER_5_MODE (_PRCMU_BASE + 0x464) + /* Level shifter and clamp control registers */ #define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420) #define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424) |