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| author | Eric Miao <eric.miao@linaro.org> | 2011-10-21 10:06:45 +0800 |
|---|---|---|
| committer | Eric Miao <eric.miao@linaro.org> | 2011-10-27 14:16:56 +0800 |
| commit | 64a4c7166ec9cf0c602078cdbf8db407fbf2d35f (patch) | |
| tree | c6967e1919faa49ab3e48a130ef31c787592411d | |
| parent | c3f3101d0b5becf70030ce046c1a1a7ce5ea5603 (diff) | |
L2 is rather transparent on Cortex-A8 and could be turned on
very early during startup. It's only going to take effect once
the C bit is turned on.
Signed-off-by: Eric Miao <eric.miao@linaro.org>
| -rw-r--r-- | arch/arm/cpu/armv7/mx5/lowlevel_init.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 7e37221e0..b98b4ea8d 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -49,6 +49,11 @@ #endif mcr 15, 1, r0, c9, c0, 2 +#ifndef CONFIG_SYS_L2CACHE_OFF + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #0x2 /* L2EN */ + mcr 15, 0, r0, c1, c0, 1 +#endif .endm /* init_l2cc */ /* AIPS setup - Only setup MPROTx registers. |