From 165e3419eca1a978f84253890d75ce6549ab2f60 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Fri, 2 Sep 2011 10:12:35 +0800 Subject: mx53_loco: add srtc device Signed-off-by: Richard Zhao --- include/linux/mxc_srtc.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 include/linux/mxc_srtc.h (limited to 'include/linux') diff --git a/include/linux/mxc_srtc.h b/include/linux/mxc_srtc.h new file mode 100644 index 00000000000..1d3c7b6feef --- /dev/null +++ b/include/linux/mxc_srtc.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_srtc.h + * + * @brief SRTC IOCTL definitions + * + * @ingroup RTC + */ + + +#define RTC_READ_TIME_47BIT _IOR('p', 0x20, unsigned long long) +/* blocks until LPSCMR is set, returns difference */ +#define RTC_WAIT_TIME_SET _IOR('p', 0x21, int64_t) -- cgit v1.2.3 From d10718e53829019bfdd73acd97280a7081b9d3c0 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Wed, 31 Aug 2011 17:41:43 +0800 Subject: iim: add IIM driver support Signed-off-by: Frank Li Signed-off-by: Eric Miao --- include/linux/fsl_devices.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'include/linux') diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index fffdf00f87b..3a45181b35e 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -120,6 +120,25 @@ struct fsl_spi_platform_data { u32 sysclk; }; +struct mxc_iim_platform_data { + const s8 *name; + u32 virt_base; + u32 reg_base; + u32 reg_end; + u32 reg_size; + u32 bank_start; + u32 bank_end; + u32 irq; + u32 action; + struct mutex mutex; + struct completion completion; + spinlock_t lock; + struct clk *clk; + struct device *dev; + void (*enable_fuse)(void); + void (*disable_fuse)(void); +}; + struct mpc8xx_pcmcia_ops { void(*hw_ctrl)(int slot, int enable); int(*voltage_set)(int slot, int vcc, int vpp); -- cgit v1.2.3 From 9ec34d70c2a0ae0cefaa4c724e3aaea80ac89cc9 Mon Sep 17 00:00:00 2001 From: "Ying-Chun Liu (PaulLiu)" Date: Fri, 10 Jun 2011 10:36:35 +0800 Subject: PMIC: Add DA9053 headers from Dialog Add DA9053 headers source code. Signed-off-by: Zhou Jingyu Acked-by: Lily Zhang Signed-off-by: Ying-Chun Liu (PaulLiu) --- include/linux/mfd/da9052/adc.h | 66 +++ include/linux/mfd/da9052/bat.h | 264 +++++++++ include/linux/mfd/da9052/bl.h | 289 ++++++++++ include/linux/mfd/da9052/da9052.h | 209 +++++++ include/linux/mfd/da9052/eh.h | 77 +++ include/linux/mfd/da9052/gpio.h | 253 +++++++++ include/linux/mfd/da9052/led.h | 39 ++ include/linux/mfd/da9052/pm.h | 81 +++ include/linux/mfd/da9052/reg.h | 929 +++++++++++++++++++++++++++++++ include/linux/mfd/da9052/rtc.h | 322 +++++++++++ include/linux/mfd/da9052/tsi.h | 427 ++++++++++++++ include/linux/mfd/da9052/tsi_calibrate.h | 47 ++ include/linux/mfd/da9052/tsi_cfg.h | 132 +++++ include/linux/mfd/da9052/tsi_filter.h | 58 ++ include/linux/mfd/da9052/wdt.h | 83 +++ 15 files changed, 3276 insertions(+) create mode 100644 include/linux/mfd/da9052/adc.h create mode 100644 include/linux/mfd/da9052/bat.h create mode 100644 include/linux/mfd/da9052/bl.h create mode 100644 include/linux/mfd/da9052/da9052.h create mode 100644 include/linux/mfd/da9052/eh.h create mode 100644 include/linux/mfd/da9052/gpio.h create mode 100644 include/linux/mfd/da9052/led.h create mode 100644 include/linux/mfd/da9052/pm.h create mode 100644 include/linux/mfd/da9052/reg.h create mode 100644 include/linux/mfd/da9052/rtc.h create mode 100644 include/linux/mfd/da9052/tsi.h create mode 100644 include/linux/mfd/da9052/tsi_calibrate.h create mode 100644 include/linux/mfd/da9052/tsi_cfg.h create mode 100644 include/linux/mfd/da9052/tsi_filter.h create mode 100644 include/linux/mfd/da9052/wdt.h (limited to 'include/linux') diff --git a/include/linux/mfd/da9052/adc.h b/include/linux/mfd/da9052/adc.h new file mode 100644 index 00000000000..49c7d181d15 --- /dev/null +++ b/include/linux/mfd/da9052/adc.h @@ -0,0 +1,66 @@ +/* + * da9052 ADC module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_ADC_H +#define __LINUX_MFD_DA9052_ADC_H + +#include "gpio.h" + +#define DA9052_ADC_DEVICE_NAME "da9052_adc" + +/* Channel Definations */ +#define DA9052_ADC_VDDOUT 0 +#define DA9052_ADC_ICH 1 +#define DA9052_ADC_TBAT 2 +#define DA9052_ADC_VBAT 3 +#define DA9052_ADC_ADCIN4 4 +#define DA9052_ADC_ADCIN5 5 +#define DA9052_ADC_ADCIN6 6 +#define DA9052_ADC_TSI 7 +#define DA9052_ADC_TJUNC 8 +#define DA9052_ADC_VBBAT 9 + +#if (DA9052_GPIO_PIN_0 == DA9052_GPIO_CONFIG_ADC) +#define DA9052_ADC_CONF_ADC4 1 +#else +#define DA9052_ADC_CONF_ADC4 0 +#endif +#if (DA9052_GPIO_PIN_1 == DA9052_GPIO_CONFIG_ADC) +#define DA9052_ADC_CONF_ADC5 1 +#else +#define DA9052_ADC_CONF_ADC5 0 +#endif +#if (DA9052_GPIO_PIN_2 == DA9052_GPIO_CONFIG_ADC) +#define DA9052_ADC_CONF_ADC6 1 +#else +#define DA9052_ADC_CONF_ADC6 0 +#endif + +/* Maximum retry count to check manual conversion over */ +#define DA9052_ADC_MAX_MANCONV_RETRY_COUNT 8 + +struct da9052_adc_priv { + struct da9052 *da9052; + struct device *hwmon_dev; + struct mutex manconv_lock; +}; + +#endif /* __LINUX_MFD_DA9052_ADC_H */ diff --git a/include/linux/mfd/da9052/bat.h b/include/linux/mfd/da9052/bat.h new file mode 100644 index 00000000000..4643c457931 --- /dev/null +++ b/include/linux/mfd/da9052/bat.h @@ -0,0 +1,264 @@ +/* + * da9052 BAT module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_BAT_H +#define __LINUX_MFD_DA9052_BAT_H + +#include + +/* STATIC CONFIGURATION */ +#define DA9052_LOOK_UP_TABLE_SIZE 68 +#define DA9052_NO_OF_LOOKUP_TABLE 3 +#define DA9052_FILTER_SIZE 4 +#define DA9052_NUMBER_OF_STORE_CURENT_READING 4 +#define DA9052_BAT_FILTER_HYS 0 + + +static const u16 temperature_lookup_ref + [DA9052_NO_OF_LOOKUP_TABLE] = {10, 25, 40}; +static u32 const vbat_vs_capacity_look_up[DA9052_NO_OF_LOOKUP_TABLE] + [DA9052_LOOK_UP_TABLE_SIZE][2] = { + /* For temperature 10 degree celisus*/ + { + {4082, 100}, {4036, 98}, + {4020, 96}, {4008, 95}, + {3997, 93}, {3983, 91}, + {3964, 90}, {3943, 88}, + {3926, 87}, {3912, 85}, + {3900, 84}, {3890, 82}, + {3881, 80}, {3873, 79}, + {3865, 77}, {3857, 76}, + {3848, 74}, {3839, 73}, + {3829, 71}, {3820, 70}, + {3811, 68}, {3802, 67}, + {3794, 65}, {3785, 64}, + {3778, 62}, {3770, 61}, + {3763, 59}, {3756, 58}, + {3750, 56}, {3744, 55}, + {3738, 53}, {3732, 52}, + {3727, 50}, {3722, 49}, + {3717, 47}, {3712, 46}, + {3708, 44}, {3703, 43}, + {3700, 41}, {3696, 40}, + {3693, 38}, {3691, 37}, + {3688, 35}, {3686, 34}, + {3683, 32}, {3681, 31}, + {3678, 29}, {3675, 28}, + {3672, 26}, {3669, 25}, + {3665, 23}, {3661, 22}, + {3656, 21}, {3651, 19}, + {3645, 18}, {3639, 16}, + {3631, 15}, {3622, 13}, + {3611, 12}, {3600, 10}, + {3587, 9}, {3572, 7}, + {3548, 6}, {3503, 5}, + {3420, 3}, {3268, 2}, + {2992, 1}, {2746, 0} + }, + /* For temperature 25 degree celisus */ + { + {4102, 100}, {4065, 98}, + {4048, 96}, {4034, 95}, + {4021, 93}, {4011, 92}, + {4001, 90}, {3986, 88}, + {3968, 87}, {3952, 85}, + {3938, 84}, {3926, 82}, + {3916, 81}, {3908, 79}, + {3900, 77}, {3892, 76}, + {3883, 74}, {3874, 73}, + {3864, 71}, {3855, 70}, + {3846, 68}, {3836, 67}, + {3827, 65}, {3819, 64}, + {3810, 62}, {3801, 61}, + {3793, 59}, {3786, 58}, + {3778, 56}, {3772, 55}, + {3765, 53}, {3759, 52}, + {3754, 50}, {3748, 49}, + {3743, 47}, {3738, 46}, + {3733, 44}, {3728, 43}, + {3724, 41}, {3720, 40}, + {3716, 38}, {3712, 37}, + {3709, 35}, {3706, 34}, + {3703, 33}, {3701, 31}, + {3698, 30}, {3696, 28}, + {3693, 27}, {3690, 25}, + {3687, 24}, {3683, 22}, + {3680, 21}, {3675, 19}, + {3671, 18}, {3666, 17}, + {3660, 15}, {3654, 14}, + {3647, 12}, {3639, 11}, + {3630, 9}, {3621, 8}, + {3613, 6}, {3606, 5}, + {3597, 4}, {3582, 2}, + {3546, 1}, {2747, 0} + }, + /* For temperature 40 degree celisus*/ + { + {4114, 100}, {4081, 98}, + {4065, 96}, {4050, 95}, + {4036, 93}, {4024, 92}, + {4013, 90}, {4002, 88}, + {3990, 87}, {3976, 85}, + {3962, 84}, {3950, 82}, + {3939, 81}, {3930, 79}, + {3921, 77}, {3912, 76}, + {3902, 74}, {3893, 73}, + {3883, 71}, {3874, 70}, + {3865, 68}, {3856, 67}, + {3847, 65}, {3838, 64}, + {3829, 62}, {3820, 61}, + {3812, 59}, {3803, 58}, + {3795, 56}, {3787, 55}, + {3780, 53}, {3773, 52}, + {3767, 50}, {3761, 49}, + {3756, 47}, {3751, 46}, + {3746, 44}, {3741, 43}, + {3736, 41}, {3732, 40}, + {3728, 38}, {3724, 37}, + {3720, 35}, {3716, 34}, + {3713, 33}, {3710, 31}, + {3707, 30}, {3704, 28}, + {3701, 27}, {3698, 25}, + {3695, 24}, {3691, 22}, + {3686, 21}, {3681, 19}, + {3676, 18}, {3671, 17}, + {3666, 15}, {3661, 14}, + {3655, 12}, {3648, 11}, + {3640, 9}, {3632, 8}, + {3622, 6}, {3616, 5}, + {3611, 4}, {3604, 2}, + {3594, 1}, {2747, 0} + } +}; + +enum charger_type_enum { + DA9052_NOCHARGER = 1, + DA9052_USB_HUB, + DA9052_USB_CHARGER, + DA9052_WALL_CHARGER +}; + +struct da9052_bat_event_registration { + u8 da9052_event_tbat:1; +}; + +struct da9052_bat_hysteresis { + u16 bat_volt_arr[3]; + u16 array_hys_batvoltage[2]; + u16 upper_limit; + u16 lower_limit; + u8 index; + u8 hys_flag; +}; + +struct da9052_charger_device { + struct da9052 *da9052; + struct workqueue_struct *monitor_wqueue; + struct delayed_work monitor_work; + struct power_supply psy; + struct da9052_eh_nb tbat_eh_data; + u8 cal_capacity; + u8 charger_type; + u8 health; + u8 status; + u8 illegal; + u16 technology; + u16 chg_current; + u16 bat_voltage; + u16 bat_capacity_limit_low; + u16 bat_capacity_full; + u16 bat_capacity_limit_high; + u16 bat_volt_cutoff; + u16 bat_with_no_resistor; + u16 bat_temp; + u8 hys_flag; + u16 charger_voltage_drop; + u16 bat_target_voltage; + u16 chg_end_current; + u16 hysteresis_window_size; + u16 chg_hysteresis_const; + u16 hysteresis_reading_interval; + u16 hysteresis_no_of_reading; + u16 vbat_first_valid_detect_iteration; +}; + + +static inline u8 bat_temp_reg_to_C(u16 value) { return (55 - value); } +static inline u8 bat_mV_to_reg(u16 value) { return (((value-4100)/100)<<4); } +static inline u8 bat_drop_mV_to_reg(u16 value) + { return (((value-100)/100)<<6); } +static inline u16 bat_reg_to_mV(u8 value) { return ((value*100) + 4100); } +static inline u16 bat_drop_reg_to_mV(u8 value) { return ((value*100)+100); } +static inline u8 vch_thr_mV_to_reg(u16 value) { return ((value-3700)/100); } +static inline u8 precharge_mA_to_reg(u8 value) { return ((value/20)<<6); } +static inline u8 vddout_mon_mV_to_reg(u16 value) + { return (((value-2500)*128)/1000); } +static inline u16 vddout_reg_to_mV(u8 value) + { return ((value*1000)/128)+2500; } +static inline u16 volt_reg_to_mV(u16 value) + { return ((value*1000)/512)+2500; } +static inline u8 ichg_mA_to_reg(u16 value) { return (value/4); } +static inline u16 ichg_reg_to_mA(u8 value) { return ((value*3900)/1000); } +static inline u8 iset_mA_to_reg(u16 iset_value) + {\ + if ((70 <= iset_value) && (iset_value <= 120)) \ + return (iset_value-70)/10; \ + else if ((400 <= iset_value) && (iset_value <= 700)) \ + return ((iset_value-400)/50)+6; \ + else if ((900 <= iset_value) && (iset_value <= 1300)) \ + return ((iset_value-900)/200)+13; else return 0; + } + +#define DA9052_BAT_DEBUG 0 + +#define DA9052_BAT_PROFILE 0 +#define SUCCESS 0 +#define FAILURE 1 + +#define TRUE 1 +#define FALSE 0 + +#define set_bits(value, mask) (value | mask) +#define clear_bits(value, mask) (value & ~(mask)) + +#undef DA9052_DEBUG +#if DA9052_BAT_DEBUG +#define DA9052_DEBUG(fmt, args...) printk(KERN_CRIT "" fmt, ##args) +#else +#define DA9052_DEBUG(fmt, args...) +#endif + + +/* SSC Read or Write Error */ +#define DA9052_SSC_FAIL 150 + +/* To enable debug output for your module, set this to 1 */ +#define DA9052_SSC_DEBUG 0 + +#undef DA9052_DEBUG +#if DA9052_SSC_DEBUG +#define DA9052_DEBUG(fmt, args...) printk(KERN_CRIT "" fmt, ##args) +#else +#define DA9052_DEBUG(fmt, args...) +#endif + + +#endif /* __LINUX_MFD_DA9052_BAT_H */ diff --git a/include/linux/mfd/da9052/bl.h b/include/linux/mfd/da9052/bl.h new file mode 100644 index 00000000000..9217eb95a77 --- /dev/null +++ b/include/linux/mfd/da9052/bl.h @@ -0,0 +1,289 @@ +/* + * da9052 Backlight module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_BL_H +#define __LINUX_MFD_DA9052_BL_H + +/* + * enum da9052_bl_current_value - Enum for current values of LED + * DA9052_BL_CURRENT_50_0UA: represents 50.0 uA current value + */ +enum da9052_bl_current_value { +/* Current Value for LEDMIN, LED1_CONF, LED2_CONF, LED3_CONF Registers */ + DA9052_BL_CURRENT_50_0UA = 0, + DA9052_BL_CURRENT_51_2UA, + DA9052_BL_CURRENT_52_5UA, + DA9052_BL_CURRENT_53_7UA, + DA9052_BL_CURRENT_55_1UA, + DA9052_BL_CURRENT_56_4UA, + DA9052_BL_CURRENT_57_8UA, + DA9052_BL_CURRENT_59_3UA, + DA9052_BL_CURRENT_60_7UA, + DA9052_BL_CURRENT_62_2UA, + DA9052_BL_CURRENT_63_8UA, + DA9052_BL_CURRENT_65_3UA, + DA9052_BL_CURRENT_67_0UA, + DA9052_BL_CURRENT_68_6UA, + DA9052_BL_CURRENT_70_3UA, + DA9052_BL_CURRENT_72_0UA, + DA9052_BL_CURRENT_73_8UA, + DA9052_BL_CURRENT_75_7UA, + DA9052_BL_CURRENT_77_5UA, + DA9052_BL_CURRENT_79_4UA, + DA9052_BL_CURRENT_81_4UA, + DA9052_BL_CURRENT_83_4UA, + DA9052_BL_CURRENT_85_5UA, + DA9052_BL_CURRENT_87_6UA, + DA9052_BL_CURRENT_89_8UA, + DA9052_BL_CURRENT_92_0UA, + DA9052_BL_CURRENT_94_2UA, + DA9052_BL_CURRENT_96_6UA, + DA9052_BL_CURRENT_99_0UA, + DA9052_BL_CURRENT_101_4UA, + DA9052_BL_CURRENT_103_9UA, + DA9052_BL_CURRENT_106_5UA, + DA9052_BL_CURRENT_109_1UA, + DA9052_BL_CURRENT_111_8UA, + DA9052_BL_CURRENT_114_6UA, + DA9052_BL_CURRENT_117_4UA, + DA9052_BL_CURRENT_120_6UA, + DA9052_BL_CURRENT_123_3UA, + DA9052_BL_CURRENT_126_3UA, + DA9052_BL_CURRENT_129_4UA, + DA9052_BL_CURRENT_132_6UA, + DA9052_BL_CURRENT_135_9UA, + DA9052_BL_CURRENT_139_3UA, + DA9052_BL_CURRENT_142_7UA, + DA9052_BL_CURRENT_146_2UA, + DA9052_BL_CURRENT_149_9UA, + DA9052_BL_CURRENT_153_6UA, + DA9052_BL_CURRENT_157_4UA, + DA9052_BL_CURRENT_161_2UA, + DA9052_BL_CURRENT_165_2UA, + DA9052_BL_CURRENT_169_3UA, + DA9052_BL_CURRENT_173_5UA, + DA9052_BL_CURRENT_177_8UA, + DA9052_BL_CURRENT_182_2UA, + DA9052_BL_CURRENT_186_7UA, + DA9052_BL_CURRENT_191_3UA, + DA9052_BL_CURRENT_196_0UA, + DA9052_BL_CURRENT_200_9UA, + DA9052_BL_CURRENT_205_8UA, + DA9052_BL_CURRENT_210_9UA, + DA9052_BL_CURRENT_216_1UA, + DA9052_BL_CURRENT_221_4UA, + DA9052_BL_CURRENT_226_9UA, + DA9052_BL_CURRENT_232_5UA, + DA9052_BL_CURRENT_238_3UA, + DA9052_BL_CURRENT_244_2UA, + DA9052_BL_CURRENT_250_2UA, + DA9052_BL_CURRENT_256_4UA, + DA9052_BL_CURRENT_262_7UA, + DA9052_BL_CURRENT_269_2UA, + DA9052_BL_CURRENT_275_8UA, + DA9052_BL_CURRENT_282_7UA, + DA9052_BL_CURRENT_289_6UA, + DA9052_BL_CURRENT_296_8UA, + DA9052_BL_CURRENT_304_1UA, + DA9052_BL_CURRENT_311_6UA, + DA9052_BL_CURRENT_319_3UA, + DA9052_BL_CURRENT_327_2UA, + DA9052_BL_CURRENT_335_3UA, + DA9052_BL_CURRENT_343_6UA, + DA9052_BL_CURRENT_352_1UA, + DA9052_BL_CURRENT_360_8UA, + DA9052_BL_CURRENT_369_7UA, + DA9052_BL_CURRENT_378_8UA, + DA9052_BL_CURRENT_388_2UA, + DA9052_BL_CURRENT_397_8UA, + DA9052_BL_CURRENT_407_6UA, + DA9052_BL_CURRENT_417_7UA, + DA9052_BL_CURRENT_428_0UA, + DA9052_BL_CURRENT_438_6UA, + DA9052_BL_CURRENT_449_4UA, + DA9052_BL_CURRENT_460_5UA, + DA9052_BL_CURRENT_471_9UA, + DA9052_BL_CURRENT_483_5UA, + DA9052_BL_CURRENT_495_5UA, + DA9052_BL_CURRENT_507_7UA, + DA9052_BL_CURRENT_520_3UA, + DA9052_BL_CURRENT_533_1UA, + DA9052_BL_CURRENT_546_3UA, + DA9052_BL_CURRENT_559_8UA, + DA9052_BL_CURRENT_573_6UA, + DA9052_BL_CURRENT_587_8UA, + DA9052_BL_CURRENT_602_3UA, + DA9052_BL_CURRENT_617_2UA, + DA9052_BL_CURRENT_632_4UA, + DA9052_BL_CURRENT_648_0UA, + DA9052_BL_CURRENT_664_0UA, + DA9052_BL_CURRENT_680_4UA, + DA9052_BL_CURRENT_697_2UA, + DA9052_BL_CURRENT_714_5UA, + DA9052_BL_CURRENT_732_1UA, + DA9052_BL_CURRENT_750_2UA, + DA9052_BL_CURRENT_768_7UA, + DA9052_BL_CURRENT_787_7UA, + DA9052_BL_CURRENT_807_2UA, + DA9052_BL_CURRENT_827_1UA, + DA9052_BL_CURRENT_847_6UA, + DA9052_BL_CURRENT_868_5UA, + DA9052_BL_CURRENT_889_9UA, + DA9052_BL_CURRENT_911_9UA, + DA9052_BL_CURRENT_934_4UA, + DA9052_BL_CURRENT_957_5UA, + DA9052_BL_CURRENT_981_2UA, + DA9052_BL_CURRENT_1005_4UA, + DA9052_BL_CURRENT_1030_3UA, + DA9052_BL_CURRENT_1055_7UA, + DA9052_BL_CURRENT_1081_8UA, + DA9052_BL_CURRENT_1108_5UA, + DA9052_BL_CURRENT_1135_9UA, + DA9052_BL_CURRENT_1163_9UA, + DA9052_BL_CURRENT_1192_7UA, + DA9052_BL_CURRENT_1222_2UA, + DA9052_BL_CURRENT_1252_3UA, + DA9052_BL_CURRENT_1283_3UA, + DA9052_BL_CURRENT_1315_0UA, + DA9052_BL_CURRENT_1347_5UA, + DA9052_BL_CURRENT_1380_7UA, + DA9052_BL_CURRENT_1414_8UA, + DA9052_BL_CURRENT_1449_8UA, + DA9052_BL_CURRENT_1485_6UA, + DA9052_BL_CURRENT_1522_3UA, + DA9052_BL_CURRENT_1559_9UA, + DA9052_BL_CURRENT_1598_4UA, + DA9052_BL_CURRENT_1637_9UA, + DA9052_BL_CURRENT_1678_4UA, + DA9052_BL_CURRENT_1719_8UA, + DA9052_BL_CURRENT_1762_3UA, + DA9052_BL_CURRENT_1805_8UA, + DA9052_BL_CURRENT_1850_4UA, + DA9052_BL_CURRENT_1896_1UA, + DA9052_BL_CURRENT_1943_0UA, + DA9052_BL_CURRENT_1991_0UA, + DA9052_BL_CURRENT_2040_2UA, + DA9052_BL_CURRENT_2090_5UA, + DA9052_BL_CURRENT_2142_2UA, + DA9052_BL_CURRENT_2195_1UA, + DA9052_BL_CURRENT_2249_3UA, + DA9052_BL_CURRENT_2304_9UA, + DA9052_BL_CURRENT_2361_8UA, + DA9052_BL_CURRENT_2420_1UA, + DA9052_BL_CURRENT_2479_9UA, + DA9052_BL_CURRENT_2541_2UA, + DA9052_BL_CURRENT_2604_0UA, + DA9052_BL_CURRENT_2668_3UA, + DA9052_BL_CURRENT_2734_2UA, + DA9052_BL_CURRENT_2801_7UA, + DA9052_BL_CURRENT_2870_9UA, + DA9052_BL_CURRENT_2941_8UA, + DA9052_BL_CURRENT_3014_5UA, + DA9052_BL_CURRENT_3089_0UA, + DA9052_BL_CURRENT_3165_3UA, + DA9052_BL_CURRENT_3243_4UA, + DA9052_BL_CURRENT_3323_5UA, + DA9052_BL_CURRENT_3405_6UA, + DA9052_BL_CURRENT_3489_8UA, + DA9052_BL_CURRENT_3576_0UA, + DA9052_BL_CURRENT_3664_3UA, + DA9052_BL_CURRENT_3754_8UA, + DA9052_BL_CURRENT_3847_5UA, + DA9052_BL_CURRENT_3942_6UA, + DA9052_BL_CURRENT_4040_0UA, + DA9052_BL_CURRENT_4139_7UA, + DA9052_BL_CURRENT_4242_0UA, + DA9052_BL_CURRENT_4346_8UA, + DA9052_BL_CURRENT_4454_1UA, + DA9052_BL_CURRENT_4564_2UA, + DA9052_BL_CURRENT_4676_9UA, + DA9052_BL_CURRENT_4792_4UA, + DA9052_BL_CURRENT_4910_8UA, + DA9052_BL_CURRENT_5032_1UA, + DA9052_BL_CURRENT_5156_4UA, + DA9052_BL_CURRENT_5283_7UA, + DA9052_BL_CURRENT_5414_3UA, + DA9052_BL_CURRENT_5548_0UA, + DA9052_BL_CURRENT_5685_0UA, + DA9052_BL_CURRENT_5825_5UA, + DA9052_BL_CURRENT_5969_3UA, + DA9052_BL_CURRENT_6116_8UA, + DA9052_BL_CURRENT_6267_9UA, + DA9052_BL_CURRENT_6422_7UA, + DA9052_BL_CURRENT_6581_3UA, + DA9052_BL_CURRENT_6743_9UA, + DA9052_BL_CURRENT_6910_5UA, + DA9052_BL_CURRENT_7081_2UA, + DA9052_BL_CURRENT_7256_1UA, + DA9052_BL_CURRENT_7435_3UA, + DA9052_BL_CURRENT_7618_9UA, + DA9052_BL_CURRENT_7807_1UA, + DA9052_BL_CURRENT_8000_0UA, + DA9052_BL_CURRENT_8197_6UA, + DA9052_BL_CURRENT_8400_0UA, + DA9052_BL_CURRENT_8607_5UA, + DA9052_BL_CURRENT_8820_1UA, + DA9052_BL_CURRENT_9038_0UA, + DA9052_BL_CURRENT_9261_2UA, + DA9052_BL_CURRENT_9490_0UA, + DA9052_BL_CURRENT_9724_4UA, + DA9052_BL_CURRENT_9964_6UA, + DA9052_BL_CURRENT_10210_7UA, + DA9052_BL_CURRENT_10462_9UA, + DA9052_BL_CURRENT_10721_4UA, + DA9052_BL_CURRENT_10986_4UA, + DA9052_BL_CURRENT_11257_5UA, + DA9052_BL_CURRENT_11535_6UA, + DA9052_BL_CURRENT_11820_5UA, + DA9052_BL_CURRENT_12112_5UA, + DA9052_BL_CURRENT_12411_7UA, + DA9052_BL_CURRENT_12718_2UA, + DA9052_BL_CURRENT_13032_4UA, + DA9052_BL_CURRENT_13354_3UA, + DA9052_BL_CURRENT_13684_1UA, + DA9052_BL_CURRENT_14022_1UA, + DA9052_BL_CURRENT_14368_5UA, + DA9052_BL_CURRENT_14723_4UA, + DA9052_BL_CURRENT_15087_1UA, + DA9052_BL_CURRENT_15459_7UA, + DA9052_BL_CURRENT_15841_6UA, + DA9052_BL_CURRENT_16232_9UA, + DA9052_BL_CURRENT_16633_8UA, + DA9052_BL_CURRENT_17044_7UA, + DA9052_BL_CURRENT_17465_7UA, + DA9052_BL_CURRENT_17897_1UA, + DA9052_BL_CURRENT_18339_1UA, + DA9052_BL_CURRENT_18792_1UA, + DA9052_BL_CURRENT_19256_3UA, + DA9052_BL_CURRENT_19731_9UA, + DA9052_BL_CURRENT_20219_3UA, + DA9052_BL_CURRENT_20718_7UA, + DA9052_BL_CURRENT_21230_5UA, + DA9052_BL_CURRENT_21754_8UA, + DA9052_BL_CURRENT_22292_2UA, + DA9052_BL_CURRENT_22842_8UA, + DA9052_BL_CURRENT_23407_0UA, + DA9052_BL_CURRENT_23985_2UA, + DA9052_BL_CURRENT_24577_6UA, + DA9052_BL_CURRENT_25000_0UA, +}; + +#endif /* __LINUX_MFD_DA9052_BL_H */ diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h new file mode 100644 index 00000000000..88d34cacbb9 --- /dev/null +++ b/include/linux/mfd/da9052/da9052.h @@ -0,0 +1,209 @@ +/* + * da9052 declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_DA9052_H +#define __LINUX_MFD_DA9052_DA9052_H + +#include +#include + +#include +#include +#include + + +#define SPI 1 +#define I2C 2 + +#define DA9052_SSC_DEVICE_NAME "da9052_ssc" +#define DA9052_EH_DEVICE_NAME "da9052_eh" + +#define DA9052_IRQ S3C_EINT(9) + +/* Module specific error codes */ +#define INVALID_REGISTER 2 +#define INVALID_READ 3 +#define INVALID_PAGE 4 + +/* Defines for Volatile and Non Volatile register types */ +#define VOLATILE 0 +#define NON_VOLATILE 1 + +/* Defines for cache state */ +#define VALID 0 +#define INVALID 1 + +/* Total number of registers in DA9057 */ +#define DA9052_REG_CNT DA9052_PAGE1_REG_END + +/* Maximum number of registers that can be read/written by a singe request */ +#define MAX_READ_WRITE_CNT 16 + + +#define DA9052_SSC_SPI_DEVICE_NAME "da9052_ssc_spi" +#define PAGE_0_START 1 +#define PAGE_0_END 127 +#define PAGE_1_START 128 +#define PAGE_1_END 255 +#define ACTIVE_PAGE_0 0 +#define ACTIVE_PAGE_1 1 +#define PAGECON_0 0 +#define PAGECON_128 128 +#define RW_POL 1 + +#define DA9052_SSC_I2C_DEVICE_NAME "da9052_ssc_i2c" +#define DA9052_I2C_ADDR 0x90 +#define DA9052_SSC_I2C_PAGE_WRITE_MODE 0 +#define DA9052_SSC_I2C_REPEAT_WRITE_MODE 1 +#define DA9052_SSC_I2C_WRITE_MODE DA9052_SSC_I2C_REPEAT_WRITE_MODE + +struct da9052_ssc_msg { + unsigned char data; + unsigned char addr; +}; + +struct ssc_cache_entry { + unsigned char val; + unsigned char type:4; + unsigned char status:4; +}; + +struct da9052_eh_nb { + struct list_head nb_list; + unsigned char eve_type; + void (*call_back)(struct da9052_eh_nb *, unsigned int); +}; + +struct da9052_regulator_init_data { + struct regulator_init_data *init_data; + int id; + +}; + +struct da9052_regulator_platform_data { + struct regulator_init_data *regulators; +}; + +struct da9052_tsi_platform_data { + u32 pen_up_interval; + u16 tsi_delay_bit_shift; + u16 tsi_skip_bit_shift; + u16 num_gpio_tsi_register; + u16 tsi_supply_voltage; + u16 tsi_ref_source; + u16 max_tsi_delay; + u16 max_tsi_skip_slot; +}; + + +struct da9052 { + struct mutex ssc_lock; + struct mutex eve_nb_lock; + struct mutex manconv_lock; + struct work_struct eh_isr_work; + struct ssc_cache_entry ssc_cache[DA9052_REG_CNT]; + int (*read) (struct da9052 *da9052, struct da9052_ssc_msg *sscmsg); + int (*write) (struct da9052 *da9052, struct da9052_ssc_msg *sscmsg); + int (*read_many) (struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int cnt); + int (*write_many)(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int cnt); + int (*register_event_notifier)(struct da9052 *da9052, + struct da9052_eh_nb *nb); + int (*unregister_event_notifier)(struct da9052 *da9052, + struct da9052_eh_nb *nb); + int num_regulators; + int connecting_device; + int irq; + struct spi_device *spi_dev; + unsigned int spi_active_page; + unsigned char rw_pol; + unsigned char *spi_rx_buf; + unsigned char *spi_tx_buf; + + struct i2c_client *i2c_client; + struct device *dev; + struct i2c_adapter *adapter; + unsigned char slave_addr; +}; + + +struct da9052_platform_data { + int (*init)(struct da9052 *da9052); + int irq_high; + int irq_base; + int gpio_base; + int num_regulators; + struct da9052 *da9052; + struct regulator_init_data *regulators; + struct da9052_leds_platform_data *led_data; + struct da9052_tsi_platform_data *tsi_data; +}; + +struct da9052_ssc_ops { + int (*write)(struct da9052 *da9052, struct da9052_ssc_msg *msg); + int (*read)(struct da9052 *da9052, struct da9052_ssc_msg *msg); + int (*write_many)(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int msg_no); + int (*read_many)(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int msg_no); + int (*device_register)(struct da9052 *da9052); + void (*device_unregister)(void); +}; + +int da9052_ssc_write(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg); +int da9052_ssc_read(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg); +int da9052_ssc_write_many(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int cnt); +int da9052_ssc_read_many(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int cnt); + +int da9052_spi_write(struct da9052 *da9052, + struct da9052_ssc_msg *msg); +int da9052_spi_read(struct da9052 *da9052, + struct da9052_ssc_msg *msg); + +int da9052_spi_write_many(struct da9052 *da9052, struct da9052_ssc_msg *sscmsg, + int msg_no); +int da9052_spi_read_many(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, + int msg_no); + +void da9052_ssc_exit(struct da9052 *da9052); +int da9052_ssc_init(struct da9052 *da9052); + +/* I2C specific Functions */ +int da9052_i2c_write(struct da9052 *da9052, struct da9052_ssc_msg *msg); +int da9052_i2c_read(struct da9052 *da9052, struct da9052_ssc_msg *msg); +int da9052_i2c_write_many(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int msg_no); +int da9052_i2c_read_many(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int msg_no); + +void da9052_lock(struct da9052 *da9052); +void da9052_unlock(struct da9052 *da9052); +int eh_register_nb(struct da9052 *da9052, struct da9052_eh_nb *nb); +int eh_unregister_nb(struct da9052 *da9052, struct da9052_eh_nb *nb); +int da9052_manual_read(struct da9052 *da9052, + unsigned char channel); +#endif /* __LINUX_MFD_DA9052_DA9052_H */ diff --git a/include/linux/mfd/da9052/eh.h b/include/linux/mfd/da9052/eh.h new file mode 100644 index 00000000000..c46df5d8962 --- /dev/null +++ b/include/linux/mfd/da9052/eh.h @@ -0,0 +1,77 @@ +/* + * da9052 Event Handler module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_EH_H +#define __LINUX_MFD_DA9052_EH_H + +#define DA9052_EVE_REGISTERS 4 +#define DA9052_EVE_REGISTER_SIZE 8 + +/* Define for all possible events */ +#define DCIN_DET_EVE 0 +#define VBUS_DET_EVE 1 +#define DCIN_REM_EVE 2 +#define VBUS_REM_EVE 3 +#define VDD_LOW_EVE 4 +#define ALARM_EVE 5 +#define SEQ_RDY_EVE 6 +#define COMP_1V2 7 +#define ONKEY_EVE 8 +#define ID_FLOAT_EVE 9 +#define ID_GND_EVE 10 +#define CHG_END_EVE 11 +#define TBAT_EVE 12 +#define ADC_EOM_EVE 13 +#define PEN_DOWN_EVE 14 +#define TSI_READY_EVE 15 +#define GPI0_EVE 16 +#define GPI1_EVE 17 +#define GPI2_EVE 18 +#define GPI3_EVE 19 +#define GPI4_EVE 20 +#define GPI5_EVE 21 +#define GPI6_EVE 22 +#define GPI7_EVE 23 +#define GPI8_EVE 24 +#define GPI9_EVE 25 +#define GPI10_EVE 26 +#define GPI11_EVE 27 +#define GPI12_EVE 28 +#define GPI13_EVE 29 +#define GPI14_EVE 30 +#define GPI15_EVE 31 + +/* Total number of events */ +#define EVE_CNT (GPI15_EVE+1) + +/* Error code for register/unregister functions */ +#define INVALID_NB 2 +#define INVALID_EVE 3 + +/* State for EH thread */ +#define ACTIVE 0 +#define INACTIVE 1 + +/* Status of nIRQ line */ +#define IRQ_HIGH 0 +#define IRQ_LOW 1 + +#endif /* __LINUX_MFD_DA9052_EH_H */ diff --git a/include/linux/mfd/da9052/gpio.h b/include/linux/mfd/da9052/gpio.h new file mode 100644 index 00000000000..68a24ad9d82 --- /dev/null +++ b/include/linux/mfd/da9052/gpio.h @@ -0,0 +1,253 @@ +/* + * da9052 GPIO module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_GPIO_H +#define __LINUX_MFD_DA9052_GPIO_H + +#include +#define DA9052_GPIO_DEVICE_NAME "da9052_gpio" + +#define DA9052_GPIO_INVALID_TYPE 1 +#define DA9052_GPIO_INVALID_MODE 2 +#define DA9052_GPIO_INVALID_PORTNUMBER 3 +#define DA9052_GPIO_INVALID_FUNCTION 4 + +#define DA9052_GPIO_CONFIG_ADC 1 +#define DA9052_GPIO_CONFIG_TSI 2 +#define DA9052_GPIO_CONFIG_PM 3 +#define DA9052_GPIO_CONFIG_ACC_ID_DET 4 +#define DA9052_GPIO_CONFIG_GP_FB1 5 +#define DA9052_GPIO_CONFIG_VDD_FAULT 6 +#define DA9052_GPIO_CONFIG_I2C 7 +#define DA9052_GPIO_CONFIG 8 + +/* Currently used defines for GPIO PINs */ +#define DA9052_GPIO_PIN_0 DA9052_GPIO_CONFIG_ADC +#define DA9052_GPIO_PIN_1 DA9052_GPIO_CONFIG_ADC +#define DA9052_GPIO_PIN_2 DA9052_GPIO_CONFIG_ADC + +#define DA9052_GPIO_PIN_3 DA9052_GPIO_CONFIG_TSI +#define DA9052_GPIO_PIN_4 DA9052_GPIO_CONFIG_TSI +#define DA9052_GPIO_PIN_5 DA9052_GPIO_CONFIG_TSI +#define DA9052_GPIO_PIN_6 DA9052_GPIO_CONFIG_TSI +#define DA9052_GPIO_PIN_7 DA9052_GPIO_CONFIG_TSI + +#define DA9052_GPIO_PIN_8 DA9052_GPIO_CONFIG +#define DA9052_GPIO_PIN_9 DA9052_GPIO_CONFIG +#define DA9052_GPIO_PIN_10 DA9052_GPIO_CONFIG +#define DA9052_GPIO_PIN_11 DA9052_GPIO_CONFIG + +#define DA9052_GPIO_PIN_12 DA9052_GPIO_CONFIG +#define DA9052_GPIO_PIN_13 DA9052_GPIO_CONFIG + +#define DA9052_GPIO_PIN_14 DA9052_GPIO_CONFIG +#define DA9052_GPIO_PIN_15 DA9052_GPIO_CONFIG + +enum ip_op_type { + ALTERNATE_FUNCTIONALITY = 0, + INPUT, + OUTPUT_OPENDRAIN, + OUTPUT_PUSHPULL +}; + +enum ip_type { + ACTIVE_LOW = 0, + ACTIVE_HIGH +}; + +enum op_type { + SUPPLY_VDD_IO1 = 0, + SUPPLY_VDD_IO2 +}; + + +enum op_mode { + OUTPUT_LOWLEVEL = 0, + OUTPUT_HIGHLEVEL +}; + + +enum ip_mode { + DEBOUNCING_OFF = 0, + DEBOUNCING_ON +}; + +/*DEFAULT CONFIG FOR GPIO 0*/ +#if (DA9052_GPIO_PIN_0 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO0_FUNCTION INPUT +#define DEFAULT_GPIO0_TYPE ACTIVE_LOW +#define DEFAULT_GPIO0_MODE DEBOUNCING_ON +#endif + +/*DEFAULT CONFIG FOR GPIO 1*/ +#if (DA9052_GPIO_PIN_1 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO1_FUNCTION INPUT +#define DEFAULT_GPIO1_TYPE ACTIVE_LOW +#define DEFAULT_GPIO1_MODE DEBOUNCING_ON +#endif + +/*DEFAULT CONFIG FOR GPIO 2*/ +#if (DA9052_GPIO_PIN_2 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO2_FUNCTION INPUT +#define DEFAULT_GPIO2_TYPE ACTIVE_LOW +#define DEFAULT_GPIO2_MODE DEBOUNCING_ON +#endif + +/*DEFAULT CONFIG FOR GPIO 3*/ +#if (DA9052_GPIO_PIN_3 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO3_FUNCTION INPUT +#define DEFAULT_GPIO3_TYPE ACTIVE_LOW +#define DEFAULT_GPIO3_MODE DEBOUNCING_ON +#endif + +/*DEFAULT CONFIG FOR GPIO 4*/ +#if (DA9052_GPIO_PIN_4 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO4_FUNCTION OUTPUT_PUSHPULL +#define DEFAULT_GPIO4_TYPE SUPPLY_VDD_IO1 +#define DEFAULT_GPIO4_MODE OUTPUT_LOWLEVEL +#endif +/*DEFAULT CONFIG FOR GPIO 5*/ +#if (DA9052_GPIO_PIN_5 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO5_FUNCTION OUTPUT_PUSHPULL +#define DEFAULT_GPIO5_TYPE SUPPLY_VDD_IO1 +#define DEFAULT_GPIO5_MODE OUTPUT_LOWLEVEL +#endif + +/*DEFAULT CONFIG FOR GPIO 6*/ +#if (DA9052_GPIO_PIN_6 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO6_FUNCTION OUTPUT_PUSHPULL +#define DEFAULT_GPIO6_TYPE SUPPLY_VDD_IO1 +#define DEFAULT_GPIO6_MODE OUTPUT_LOWLEVEL +#endif + +/*DEFAULT CONFIG FOR GPIO 7*/ +#if (DA9052_GPIO_PIN_7 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO7_FUNCTION OUTPUT_PUSHPULL +#define DEFAULT_GPIO7_TYPE SUPPLY_VDD_IO1 +#define DEFAULT_GPIO7_MODE OUTPUT_LOWLEVEL +#endif + +/*DEFAULT CONFIG FOR GPIO 8*/ +#if (DA9052_GPIO_PIN_8 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO8_FUNCTION INPUT +#define DEFAULT_GPIO8_TYPE ACTIVE_LOW +#define DEFAULT_GPIO8_MODE DEBOUNCING_ON +#endif + +/*DEFAULT CONFIG FOR GPIO 9*/ +#if (DA9052_GPIO_PIN_9 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO9_FUNCTION INPUT +#define DEFAULT_GPIO9_TYPE ACTIVE_LOW +#define DEFAULT_GPIO9_MODE DEBOUNCING_ON +#endif + +#if (DA9052_GPIO_PIN_10 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO10_FUNCTION OUTPUT_PUSHPULL +#define DEFAULT_GPIO10_TYPE SUPPLY_VDD_IO2 +#define DEFAULT_GPIO10_MODE OUTPUT_HIGHLEVEL +#endif + +/*DEFAULT CONFIG FOR GPIO 11 - for RTC blinking LED */ +#if (DA9052_GPIO_PIN_11 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO11_FUNCTION OUTPUT_PUSHPULL +#define DEFAULT_GPIO11_TYPE SUPPLY_VDD_IO2 +#define DEFAULT_GPIO11_MODE OUTPUT_HIGHLEVEL +#endif + +/*DEFAULT CONFIG FOR GPIO 12*/ +#if (DA9052_GPIO_PIN_12 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO12_FUNCTION OUTPUT_PUSHPULL +#define DEFAULT_GPIO12_TYPE SUPPLY_VDD_IO1 +#define DEFAULT_GPIO12_MODE OUTPUT_LOWLEVEL +#endif +/*DEFAULT CONFIG FOR GPIO 13*/ +#if (DA9052_GPIO_PIN_13 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO13_FUNCTION OUTPUT_PUSHPULL +#define DEFAULT_GPIO13_TYPE SUPPLY_VDD_IO1 +#define DEFAULT_GPIO13_MODE OUTPUT_LOWLEVEL +#endif + +/*DEFAULT CONFIG FOR GPIO 14 - for LED4 */ +#if (DA9052_GPIO_PIN_14 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO14_FUNCTION OUTPUT_OPENDRAIN +#define DEFAULT_GPIO14_TYPE SUPPLY_VDD_IO1 +#define DEFAULT_GPIO14_MODE OUTPUT_HIGHLEVEL +#endif + +/*DEFAULT CONFIG FOR GPIO 15 - for LED5 */ +#if (DA9052_GPIO_PIN_15 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO15_FUNCTION OUTPUT_OPENDRAIN +#define DEFAULT_GPIO15_TYPE SUPPLY_VDD_IO1 +#define DEFAULT_GPIO15_MODE OUTPUT_HIGHLEVEL +#endif + +#define DA9052_GPIO_MAX_PORTNUMBER 16 +#define DA9052_GPIO_MAX_PORTS_PER_REGISTER 8 +#define DA9052_GPIO_SHIFT_COUNT(no) ((no)%8) +#define DA9052_GPIO_EVEN_PORT_FUNCTIONALITY 0x03 +#define DA9052_GPIO_ODD_PORT_FUNCTIONALITY 0x30 +#define DA9052_GPIO_MASK_UPPER_NIBBLE 0xF0 +#define DA9052_GPIO_MASK_LOWER_NIBBLE 0x0F +#define DA9052_GPIO_NIBBLE_SHIFT 4 +#define DA9052_GPIO_EVEN_PORT_WRITE_MODE (1 << 3) +#define DA9052_GPIO_ODD_PORT_WRITE_MODE (1 << 7) + + +struct da9052_gpio_read_write { + u8 port_number:4; + u8 read_write_value:1; +} ; + +struct da9052_gpio_multiple_read { + u8 signal_value[16]; +}; + +struct da9052_gpi_config { + enum ip_type type; + enum ip_mode mode; +}; + +struct da9052_gpo_config { + enum op_type type; + enum op_mode mode; +} ; + +union da9052_gpio_config { + struct da9052_gpi_config input; + struct da9052_gpo_config output; +}; + +struct da9052_gpio { + union da9052_gpio_config gpio_config; + enum ip_op_type gpio_function; + u8 port_number:4; +}; + +struct da9052_gpio_chip { + struct da9052_gpio gpio; + struct da9052_gpio_read_write read_write; + struct da9052 *da9052; + /* For testing*/ + struct da9052_eh_nb eh_data; + struct gpio_chip gp; +}; + +#endif /* __LINUX_MFD_DA9052_GPIO_H */ diff --git a/include/linux/mfd/da9052/led.h b/include/linux/mfd/da9052/led.h new file mode 100644 index 00000000000..b4145cd2023 --- /dev/null +++ b/include/linux/mfd/da9052/led.h @@ -0,0 +1,39 @@ +/* + * da9052 LED module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_LED_H +#define __LINUX_MFD_DA9052_LED_H + +struct da9052_led_platform_data { +#define DA9052_LED_4 4 +#define DA9052_LED_5 5 +#define DA9052_LED_MAX 2 + int id; + const char *name; + const char *default_trigger; +}; + +struct da9052_leds_platform_data { + int num_leds; + struct da9052_led_platform_data *led; +}; + +#endif /* __LINUX_MFD_DA9052_LED_H */ diff --git a/include/linux/mfd/da9052/pm.h b/include/linux/mfd/da9052/pm.h new file mode 100644 index 00000000000..95487fdb422 --- /dev/null +++ b/include/linux/mfd/da9052/pm.h @@ -0,0 +1,81 @@ +/* + * da9052 Power Management module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_PM_H +#define __LINUX_MFD_DA9052_PM_H + +/* PM Device name and static Major number macros */ +#define DRIVER_NAME "da9052-regulator" + +/* PM Device Macros */ +#define DA9052_LDO1 0 +#define DA9052_LDO2 1 +#define DA9052_LDO3 2 +#define DA9052_LDO4 3 +#define DA9052_LDO5 4 +#define DA9052_LDO6 5 +#define DA9052_LDO7 6 +#define DA9052_LDO8 7 +#define DA9052_LDO9 8 +#define DA9052_LDO10 9 +#define DA9052_BUCK_CORE 10 +#define DA9052_BUCK_PRO 11 +#define DA9052_BUCK_MEM 12 +#define DA9052_BUCK_PERI 13 + +/* PM Device Error Codes */ + +/* Buck Config Validation Macros */ +#define DA9052_BUCK_CORE_PRO_VOLT_UPPER 2075 +#define DA9052_BUCK_CORE_PRO_VOLT_LOWER 500 +#define DA9052_BUCK_CORE_PRO_STEP 25 +#define DA9052_BUCK_MEM_VOLT_UPPER 2500 +#define DA9052_BUCK_MEM_VOLT_LOWER 925 +#define DA9052_BUCK_MEM_STEP 25 +#if defined(CONFIG_PMIC_DA9052) +#define DA9052_BUCK_PERI_VOLT_UPPER 3600 +#define DA9052_BUCK_PERI_VOLT_LOWER 1800 +#define DA9052_BUCK_PERI_STEP_BELOW_3000 50 +#define DA9052_BUCK_PERI_STEP_ABOVE_3000 100000 +#define DA9052_BUCK_PERI_VALUES_UPTO_3000 24 +#define DA9052_BUCK_PERI_VALUES_3000 3000000 +#elif defined(CONFIG_PMIC_DA9053AA) || (CONFIG_PMIC_DA9053Bx) +#define DA9052_BUCK_PERI_VOLT_UPPER 2500 +#define DA9052_BUCK_PERI_VOLT_LOWER 925 +#define DA9052_BUCK_PERI_STEP 25 +#endif +#define DA9052_LDO1_VOLT_UPPER 1800 +#define DA9052_LDO1_VOLT_LOWER 600 +#define DA9052_LDO1_VOLT_STEP 50 +#define DA9052_LDO2_VOLT_UPPER 1800 +#define DA9052_LDO2_VOLT_LOWER 600 +#define DA9052_LDO2_VOLT_STEP 25 +#define DA9052_LDO34_VOLT_UPPER 3300 +#define DA9052_LDO34_VOLT_LOWER 1725 +#define DA9052_LDO34_VOLT_STEP 25 +#define DA9052_LDO567810_VOLT_UPPER 3600 +#define DA9052_LDO567810_VOLT_LOWER 1200 +#define DA9052_LDO567810_VOLT_STEP 50 +#define DA9052_LDO9_VOLT_STEP 50 +#define DA9052_LDO9_VOLT_LOWER 1250 +#define DA9052_LDO9_VOLT_UPPER 3650 + +#endif /* __LINUX_MFD_DA9052_PM_H */ diff --git a/include/linux/mfd/da9052/reg.h b/include/linux/mfd/da9052/reg.h new file mode 100644 index 00000000000..ba6ad6306a4 --- /dev/null +++ b/include/linux/mfd/da9052/reg.h @@ -0,0 +1,929 @@ +/* + * da9052 register declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_REG_H +#define __LINUX_MFD_DA9052_REG_H + +#define DA9052_PAGECON0_REG 0 +#define DA9052_STATUSA_REG 1 +#define DA9052_STATUSB_REG 2 +#define DA9052_STATUSC_REG 3 +#define DA9052_STATUSD_REG 4 +#define DA9052_EVENTA_REG 5 +#define DA9052_EVENTB_REG 6 +#define DA9052_EVENTC_REG 7 +#define DA9052_EVENTD_REG 8 +#define DA9052_FAULTLOG_REG 9 +#define DA9052_IRQMASKA_REG 10 +#define DA9052_IRQMASKB_REG 11 +#define DA9052_IRQMASKC_REG 12 +#define DA9052_IRQMASKD_REG 13 +#define DA9052_CONTROLA_REG 14 +#define DA9052_CONTROLB_REG 15 +#define DA9052_CONTROLC_REG 16 +#define DA9052_CONTROLD_REG 17 +#define DA9052_PDDIS_REG 18 +#define DA9052_INTERFACE_REG 19 +#define DA9052_RESET_REG 20 +#define DA9052_GPIO0001_REG 21 +#define DA9052_GPIO0203_REG 22 +#define DA9052_GPIO0405_REG 23 +#define DA9052_GPIO0607_REG 24 +#define DA9052_GPIO0809_REG 25 +#define DA9052_GPIO1011_REG 26 +#define DA9052_GPIO1213_REG 27 +#define DA9052_GPIO1415_REG 28 +#define DA9052_ID01_REG 29 +#define DA9052_ID23_REG 30 +#define DA9052_ID45_REG 31 +#define DA9052_ID67_REG 32 +#define DA9052_ID89_REG 33 +#define DA9052_ID1011_REG 34 +#define DA9052_ID1213_REG 35 +#define DA9052_ID1415_REG 36 +#define DA9052_ID1617_REG 37 +#define DA9052_ID1819_REG 38 +#define DA9052_ID2021_REG 39 +#define DA9052_SEQSTATUS_REG 40 +#define DA9052_SEQA_REG 41 +#define DA9052_SEQB_REG 42 +#define DA9052_SEQTIMER_REG 43 +#define DA9052_BUCKA_REG 44 +#define DA9052_BUCKB_REG 45 +#define DA9052_BUCKCORE_REG 46 +#define DA9052_BUCKPRO_REG 47 +#define DA9052_BUCKMEM_REG 48 +#define DA9052_BUCKPERI_REG 49 +#define DA9052_LDO1_REG 50 +#define DA9052_LDO2_REG 51 +#define DA9052_LDO3_REG 52 +#define DA9052_LDO4_REG 53 +#define DA9052_LDO5_REG 54 +#define DA9052_LDO6_REG 55 +#define DA9052_LDO7_REG 56 +#define DA9052_LDO8_REG 57 +#define DA9052_LDO9_REG 58 +#define DA9052_LDO10_REG 59 +#define DA9052_SUPPLY_REG 60 +#define DA9052_PULLDOWN_REG 61 +#define DA9052_CHGBUCK_REG 62 +#define DA9052_WAITCONT_REG 63 +#define DA9052_ISET_REG 64 +#define DA9052_BATCHG_REG 65 +#define DA9052_CHGCONT_REG 66 +#define DA9052_INPUTCONT_REG 67 +#define DA9052_CHGTIME_REG 68 +#define DA9052_BBATCONT_REG 69 +#define DA9052_BOOST_REG 70 +#define DA9052_LEDCONT_REG 71 +#define DA9052_LEDMIN123_REG 72 +#define DA9052_LED1CONF_REG 73 +#define DA9052_LED2CONF_REG 74 +#define DA9052_LED3CONF_REG 75 +#define DA9052_LED1CONT_REG 76 +#define DA9052_LED2CONT_REG 77 +#define DA9052_LED3CONT_REG 78 +#define DA9052_LED4CONT_REG 79 +#define DA9052_LED5CONT_REG 80 +#define DA9052_ADCMAN_REG 81 +#define DA9052_ADCCONT_REG 82 +#define DA9052_ADCRESL_REG 83 +#define DA9052_ADCRESH_REG 84 +#define DA9052_VDDRES_REG 85 +#define DA9052_VDDMON_REG 86 +#define DA9052_ICHGAV_REG 87 +#define DA9052_ICHGTHD_REG 88 +#define DA9052_ICHGEND_REG 89 +#define DA9052_TBATRES_REG 90 +#define DA9052_TBATHIGHP_REG 91 +#define DA9052_TBATHIGHIN_REG 92 +#define DA9052_TBATLOW_REG 93 +#define DA9052_TOFFSET_REG 94 +#define DA9052_ADCIN4RES_REG 95 +#define DA9052_AUTO4HIGH_REG 96 +#define DA9052_AUTO4LOW_REG 97 +#define DA9052_ADCIN5RES_REG 98 +#define DA9052_AUTO5HIGH_REG 99 +#define DA9052_AUTO5LOW_REG 100 +#define DA9052_ADCIN6RES_REG 101 +#define DA9052_AUTO6HIGH_REG 102 +#define DA9052_AUTO6LOW_REG 103 +#define DA9052_TJUNCRES_REG 104 +#define DA9052_TSICONTA_REG 105 +#define DA9052_TSICONTB_REG 106 +#define DA9052_TSIXMSB_REG 107 +#define DA9052_TSIYMSB_REG 108 +#define DA9052_TSILSB_REG 109 +#define DA9052_TSIZMSB_REG 110 +#define DA9052_COUNTS_REG 111 +#define DA9052_COUNTMI_REG 112 +#define DA9052_COUNTH_REG 113 +#define DA9052_COUNTD_REG 114 +#define DA9052_COUNTMO_REG 115 +#define DA9052_COUNTY_REG 116 +#define DA9052_ALARMMI_REG 117 +#define DA9052_ALARMH_REG 118 +#define DA9052_ALARMD_REG 119 +#define DA9052_ALARMMO_REG 120 +#define DA9052_ALARMY_REG 121 +#define DA9052_SECONDA_REG 122 +#define DA9052_SECONDB_REG 123 +#define DA9052_SECONDC_REG 124 +#define DA9052_SECONDD_REG 125 +#define DA9052_PAGECON128_REG 128 +#define DA9052_CHIPID_REG 129 +#define DA9052_CONFIGID_REG 130 +#define DA9052_OTPCONT_REG 131 +#define DA9052_OSCTRIM_REG 132 +#define DA9052_GPID0_REG 133 +#define DA9052_GPID1_REG 134 +#define DA9052_GPID2_REG 135 +#define DA9052_GPID3_REG 136 +#define DA9052_GPID4_REG 137 +#define DA9052_GPID5_REG 138 +#define DA9052_GPID6_REG 139 +#define DA9052_GPID7_REG 140 +#define DA9052_GPID8_REG 141 +#define DA9052_GPID9_REG 142 + +#define DA9052_PAGE0_REG_START (DA9052_STATUSA_REG) +#define DA9052_PAGE0_REG_END (DA9052_SECONDD_REG) + +#define DA9052_PAGE1_REG_START (DA9052_CHIPID_REG) +#define DA9052_PAGE1_REG_END (DA9052_GPID9_REG) + +/* PAGE CONFIGURATION */ + +/* Reg Page Configuration */ +#define DA9052_PAGECON0_REGPAGE (1<<7) + +/* PAGE CONFIGURATION 128 REGISTER */ +#define DA9052_PAGECON128_REGPAGE (1<<7) + +/* SYSTEM REGISTER */ + +/* STATUS REGISTER A */ +#define DA9052_STATUSA_VDATDET (1<<7) +#define DA9052_STATUSA_VBUSSEL (1<<6) +#define DA9052_STATUSA_DCINSEL (1<<5) +#define DA9052_STATUSA_VBUSDET (1<<4) +#define DA9052_STATUSA_DCINDET (1<<3) +#define DA9052_STATUSA_IDGND (1<<2) +#define DA9052_STATUSA_IDFLOAT (1<<1) +#define DA9052_STATUSA_NONKEY (1<<0) + + +/* STATUS REGISTER B */ +#define DA9052_STATUSB_COMPDET (1<<7) +#define DA9052_STATUSB_SEQUENCING (1<<6) +#define DA9052_STATUSB_GPFB2 (1<<5) +#define DA9052_STATUSB_CHGTO (1<<4) +#define DA9052_STATUSB_CHGEND (1<<3) +#define DA9052_STATUSB_CHGLIM (1<<2) +#define DA9052_STATUSB_CHGPRE (1<<1) +#define DA9052_STATUSB_CHGATT (1<<0) + + +/* STATUS REGISTER C */ +#define DA9052_STATUSC_GPI7 (1<<7) +#define DA9052_STATUSC_GPI6 (1<<6) +#define DA9052_STATUSC_GPI5 (1<<5) +#define DA9052_STATUSC_GPI4 (1<<4) +#define DA9052_STATUSC_GPI3 (1<<3) +#define DA9052_STATUSC_GPI2 (1<<2) +#define DA9052_STATUSC_GPI1 (1<<1) +#define DA9052_STATUSC_GPI0 (1<<0) + + +/* STATUS REGISTER D */ +#define DA9052_STATUSD_GPI15 (1<<7) +#define DA9052_STATUSD_GPI14 (1<<6) +#define DA9052_STATUSD_GPI13 (1<<5) +#define DA9052_STATUSD_GPI12 (1<<4) +#define DA9052_STATUSD_GPI11 (1<<3) +#define DA9052_STATUSD_GPI10 (1<<2) +#define DA9052_STATUSD_GPI9 (1<<1) +#define DA9052_STATUSD_GPI8 (1<<0) + + +/* EVENT REGISTER A */ +#define DA9052_EVENTA_ECOMP1V2 (1<<7) +#define DA9052_EVENTA_ESEQRDY (1<<6) +#define DA9052_EVENTA_EALRAM (1<<5) +#define DA9052_EVENTA_EVDDLOW (1<<4) +#define DA9052_EVENTA_EVBUSREM (1<<3) +#define DA9052_EVENTA_EDCINREM (1<<2) +#define DA9052_EVENTA_EVBUSDET (1<<1) +#define DA9052_EVENTA_EDCINDET (1<<0) + +/* EVENT REGISTER B */ +#define DA9052_EVENTB_ETSIREADY (1<<7) +#define DA9052_EVENTB_EPENDOWN (1<<6) +#define DA9052_EVENTB_EADCEOM (1<<5) +#define DA9052_EVENTB_ETBAT (1<<4) +#define DA9052_EVENTB_ECHGEND (1<<3) +#define DA9052_EVENTB_EIDGND (1<<2) +#define DA9052_EVENTB_EIDFLOAT (1<<1) +#define DA9052_EVENTB_ENONKEY (1<<0) + +/* EVENT REGISTER C */ +#define DA9052_EVENTC_EGPI7 (1<<7) +#define DA9052_EVENTC_EGPI6 (1<<6) +#define DA9052_EVENTC_EGPI5 (1<<5) +#define DA9052_EVENTC_EGPI4 (1<<4) +#define DA9052_EVENTC_EGPI3 (1<<3) +#define DA9052_EVENTC_EGPI2 (1<<2) +#define DA9052_EVENTC_EGPI1 (1<<1) +#define DA9052_EVENTC_EGPI0 (1<<0) + +/* EVENT REGISTER D */ +#define DA9052_EVENTC_EGPI15 (1<<7) +#define DA9052_EVENTC_EGPI14 (1<<6) +#define DA9052_EVENTC_EGPI13 (1<<5) +#define DA9052_EVENTC_EGPI12 (1<<4) +#define DA9052_EVENTC_EGPI11 (1<<3) +#define DA9052_EVENTC_EGPI10 (1<<2) +#define DA9052_EVENTC_EGPI9 (1<<1) +#define DA9052_EVENTC_EGPI8 (1<<0) + + +/* FAULT LOG REGISTER */ +#define DA9052_FAULTLOG_WAITSET (1<<7) +#define DA9052_FAULTLOG_NSDSET (1<<6) +#define DA9052_FAULTLOG_KEYSHUT (1<<5) +#define DA9052_FAULTLOG_TEMPOVER (1<<3) +#define DA9052_FAULTLOG_VDDSTART (1<<2) +#define DA9052_FAULTLOG_VDDFAULT (1<<1) +#define DA9052_FAULTLOG_TWDERROR (1<<0) + +/* IRQ_MASK REGISTER A */ +#define DA9052_IRQMASKA_MCOMP1V2 (1<<7) +#define DA9052_IRQMASKA_MSEQRDY (1<<6) +#define DA9052_IRQMASKA_MALRAM (1<<5) +#define DA9052_IRQMASKA_MVDDLOW (1<<4) +#define DA9052_IRQMASKA_MVBUSREM (1<<3) +#define DA9052_IRQMASKA_MDCINREM (1<<2) +#define DA9052_IRQMASKA_MVBUSVLD (1<<1) +#define DA9052_IRQMASKA_MDCINVLD (1<<0) + +/* IRQ_MASK REGISTER B */ +#define DA9052_IRQMASKB_MTSIREADY (1<<7) +#define DA9052_IRQMASKB_MPENDOWN (1<<6) +#define DA9052_IRQMASKB_MADCEOM (1<<5) +#define DA9052_IRQMASKB_MTBAT (1<<4) +#define DA9052_IRQMASKB_MCHGEND (1<<3) +#define DA9052_IRQMASKB_MIDGND (1<<2) +#define DA9052_IRQMASKB_MIDFLOAT (1<<1) +#define DA9052_IRQMASKB_MNONKEY (1<<0) + +/* IRQ_MASK REGISTER C */ +#define DA9052_IRQMASKC_MGPI7 (1<<7) +#define DA9052_IRQMASKC_MGPI6 (1<<6) +#define DA9052_IRQMASKC_MGPI5 (1<<5) +#define DA9052_IRQMASKC_MGPI4 (1<<4) +#define DA9052_IRQMASKC_MGPI3 (1<<3) +#define DA9052_IRQMASKC_MGPI2 (1<<2) +#define DA9052_IRQMASKC_MGPI1 (1<<1) +#define DA9052_IRQMASKC_MGPI0 (1<<0) + +/* IRQ_MASK REGISTER D */ +#define DA9052_IRQMASKD_MGPI15 (1<<7) +#define DA9052_IRQMASKD_MGPI14 (1<<6) +#define DA9052_IRQMASKD_MGPI13 (1<<5) +#define DA9052_IRQMASKD_MGPI12 (1<<4) +#define DA9052_IRQMASKD_MGPI11 (1<<3) +#define DA9052_IRQMASKD_MGPI10 (1<<2) +#define DA9052_IRQMASKD_MGPI9 (1<<1) +#define DA9052_IRQMASKD_MGPI8 (1<<0) + +/* CONTROL REGISTER A */ +#define DA9052_CONTROLA_GPIV (1<<7) +#define DA9052_CONTROLA_PMOTYPE (1<<5) +#define DA9052_CONTROLA_PMOV (1<<4) +#define DA9052_CONTROLA_PMIV (1<<3) +#define DA9052_CONTROLA_PMIFV (1<<3) +#define DA9052_CONTROLA_PWR1EN (1<<2) +#define DA9052_CONTROLA_PWREN (1<<1) +#define DA9052_CONTROLA_SYSEN (1<<0) + +/* CONTROL REGISTER B */ +#define DA9052_CONTROLB_SHUTDOWN (1<<7) +#define DA9052_CONTROLB_DEEPSLEEP (1<<6) +#define DA9052_CONTROLB_WRITEMODE (1<<5) +#define DA9052_CONTROLB_BBATEN (1<<4) +#define DA9052_CONTROLB_OTPREADEN (1<<3) +#define DA9052_CONTROLB_AUTOBOOT (1<<2) +#define DA9052_CONTROLB_ACTDIODE (1<<1) +#define DA9052_CONTROLB_BUCKMERGE (1<<0) + +/* CONTROL REGISTER C */ +#define DA9052_CONTROLC_BLINKDUR (1<<7) +#define DA9052_CONTROLC_BLINKFRQ (3<<5) +#define DA9052_CONTROLC_DEBOUNCING (7<<2) +#define DA9052_CONTROLC_PMFB2PIN (1<<1) +#define DA9052_CONTROLC_PMFB1PIN (1<<0) + +/* CONTROL REGISTER D */ +#define DA9052_CONTROLD_WATCHDOG (1<<7) +#define DA9052_CONTROLD_ACCDETEN (1<<6) +#define DA9052_CONTROLD_GPI1415SD (1<<5) +#define DA9052_CONTROLD_NONKEYSD (1<<4) +#define DA9052_CONTROLD_KEEPACTEN (1<<3) +#define DA9052_CONTROLD_TWDSCALE (7<<0) + +/* POWER DOWN DISABLE REGISTER */ +#define DA9052_PDDIS_PMCONTPD (1<<7) +#define DA9052_PDDIS_OUT32KPD (1<<6) +#define DA9052_PDDIS_CHGBBATPD (1<<5) +#define DA9052_PDDIS_CHGPD (1<<4) +#define DA9052_PDDIS_HS2WIREPD (1<<3) +#define DA9052_PDDIS_PMIFPD (1<<2) +#define DA9052_PDDIS_GPADCPD (1<<1) +#define DA9052_PDDIS_GPIOPD (1<<0) + +/* CONTROL REGISTER D */ +#define DA9052_INTERFACE_IFBASEADDR (7<<5) +#define DA9052_INTERFACE_NCSPOL (1<<4) +#define DA9052_INTERFACE_RWPOL (1<<3) +#define DA9052_INTERFACE_CPHA (1<<2) +#define DA9052_INTERFACE_CPOL (1<<1) +#define DA9052_INTERFACE_IFTYPE (1<<0) + +/* CONTROL REGISTER D */ +#define DA9052_RESET_RESETEVENT (3<<6) +#define DA9052_RESET_RESETTIMER (63<<0) + +/* GPIO REGISTERS */ + +/* GPIO control register for PIN 0 and 1 */ +#define DA9052_GPIO0001_GPIO1MODE (1<<7) +#define DA9052_GPIO0001_GPIO1TYPE (1<<6) +#define DA9052_GPIO0001_GPIO1PIN (3<<4) +#define DA9052_GPIO0001_GPIO0MODE (1<<3) +#define DA9052_GPIO0001_GPIO0TYPE (1<<2) +#define DA9052_GPIO0001_GPIO0PIN (3<<0) + +/* GPIO control register for PIN 2 and 3 */ +#define DA9052_GPIO0203_GPIO3MODE (1<<7) +#define DA9052_GPIO0203_GPIO3TYPE (1<<6) +#define DA9052_GPIO0203_GPIO3PIN (3<<4) +#define DA9052_GPIO0203_GPIO2MODE (1<<3) +#define DA9052_GPIO0203_GPIO2TYPE (1<<2) +#define DA9052_GPIO0203_GPIO2PIN (3<<0) + +/* GPIO control register for PIN 4 and 5 */ +#define DA9052_GPIO0405_GPIO5MODE (1<<7) +#define DA9052_GPIO0405_GPIO5TYPE (1<<6) +#define DA9052_GPIO0405_GPIO5PIN (3<<4) +#define DA9052_GPIO0405_GPIO4MODE (1<<3) +#define DA9052_GPIO0405_GPIO4TYPE (1<<2) +#define DA9052_GPIO0405_GPIO4PIN (3<<0) + +/* GPIO control register for PIN 6 and 7 */ +#define DA9052_GPIO0607_GPIO7MODE (1<<7) +#define DA9052_GPIO0607_GPIO7TYPE (1<<6) +#define DA9052_GPIO0607_GPIO7PIN (3<<4) +#define DA9052_GPIO0607_GPIO6MODE (1<<3) +#define DA9052_GPIO0607_GPIO6TYPE (1<<2) +#define DA9052_GPIO0607_GPIO6PIN (3<<0) + +/* GPIO control register for PIN 8 and 9 */ +#define DA9052_GPIO0809_GPIO9MODE (1<<7) +#define DA9052_GPIO0809_GPIO9TYPE (1<<6) +#define DA9052_GPIO0809_GPIO9PIN (3<<4) +#define DA9052_GPIO0809_GPIO8MODE (1<<3) +#define DA9052_GPIO0809_GPIO8TYPE (1<<2) +#define DA9052_GPIO0809_GPIO8PIN (3<<0) + +/* GPIO control register for PIN 10 and 11 */ +#define DA9052_GPIO1011_GPIO11MODE (1<<7) +#define DA9052_GPIO1011_GPIO11TYPE (1<<6) +#define DA9052_GPIO1011_GPIO11PIN (3<<4) +#define DA9052_GPIO1011_GPIO10MODE (1<<3) +#define DA9052_GPIO1011_GPIO10TYPE (1<<2) +#define DA9052_GPIO1011_GPIO10PIN (3<<0) + +/* GPIO control register for PIN 12 and 13 */ +#define DA9052_GPIO1213_GPIO13MODE (1<<7) +#define DA9052_GPIO1213_GPIO13TYPE (1<<6) +#define DA9052_GPIO1213_GPIO13PIN (3<<4) +#define DA9052_GPIO1213_GPIO12MODE (1<<3) +#define DA9052_GPIO1213_GPIO12TYPE (1<<2) +#define DA9052_GPIO1213_GPIO12PIN (3<<0) + +/* GPIO control register for PIN 14 and 15 */ +#define DA9052_GPIO1415_GPIO15MODE (1<<7) +#define DA9052_GPIO1415_GPIO15TYPE (1<<6) +#define DA9052_GPIO1415_GPIO15PIN (3<<4) +#define DA9052_GPIO1415_GPIO14MODE (1<<3) +#define DA9052_GPIO1415_GPIO14TYPE (1<<2) +#define DA9052_GPIO1415_GPIO14PIN (3<<0) + +/*POWER SEQUENCER REGISTER*/ + +/* SEQ control register for ID 0 and 1 */ +#define DA9052_ID01_LDO1STEP (15<<4) +#define DA9052_ID01_SYSPRE (1<<2) +#define DA9052_ID01_DEFSUPPLY (1<<1) +#define DA9052_ID01_nRESMODE (1<<0) + +/* SEQ control register for ID 2 and 3 */ +#define DA9052_ID23_LDO3STEP (15<<4) +#define DA9052_ID23_LDO2STEP (15<<0) + +/* SEQ control register for ID 4 and 5 */ +#define DA9052_ID45_LDO5STEP (15<<4) +#define DA9052_ID45_LDO4STEP (15<<0) + +/* SEQ control register for ID 6 and 7 */ +#define DA9052_ID67_LDO7STEP (15<<4) +#define DA9052_ID67_LDO6STEP (15<<0) + +/* SEQ control register for ID 8 and 9 */ +#define DA9052_ID89_LDO9STEP (15<<4) +#define DA9052_ID89_LDO8STEP (15<<0) + +/* SEQ control register for ID 10 and 11 */ +#define DA9052_ID1011_PDDISSTEP (15<<4) +#define DA9052_ID1011_LDO10STEP (15<<0) + +/* SEQ control register for ID 12 and 13 */ +#define DA9052_ID1213_VMEMSWSTEP (15<<4) +#define DA9052_ID1213_VPERISWSTEP (15<<0) + +/* SEQ control register for ID 14 and 15 */ +#define DA9052_ID1415_BUCKPROSTEP (15<<4) +#define DA9052_ID1415_BUCKCORESTEP (15<<0) + +/* SEQ control register for ID 16 and 17 */ +#define DA9052_ID1617_BUCKPERISTEP (15<<4) +#define DA9052_ID1617_BUCKMEMSTEP (15<<0) + +/* SEQ control register for ID 18 and 19 */ +#define DA9052_ID1819_GPRISE2STEP (15<<4) +#define DA9052_ID1819_GPRISE1STEP (15<<0) + +/* SEQ control register for ID 20 and 21 */ +#define DA9052_ID2021_GPFALL2STEP (15<<4) +#define DA9052_ID2021_GPFALL1STEP (15<<0) + +/* Power SEQ Status register */ +#define DA9052_SEQSTATUS_SEQPOINTER (15<<4) +#define DA9052_SEQSTATUS_WAITSTEP (15<<0) + +/* Power SEQ A register */ +#define DA9052_SEQA_POWEREND (15<<4) +#define DA9052_SEQA_SYSTEMEND (15<<0) + +/* Power SEQ B register */ +#define DA9052_SEQB_PARTDOWN (15<<4) +#define DA9052_SEQB_MAXCOUNT (15<<0) + +/* Power SEQ TIMER register */ +#define DA9052_SEQTIMER_SEQDUMMY (15<<4) +#define DA9052_SEQTIMER_SEQTIME (15<<0) + +/*POWER SUPPLY CONTROL REGISTER*/ + +/* BUCK REGISTER A */ +#define DA9052_BUCKA_BPROILIM (3<<6) +#define DA9052_BUCKA_BPROMODE (3<<4) +#define DA9052_BUCKA_BCOREILIM (3<<2) +#define DA9052_BUCKA_BCOREMODE (3<<0) + +/* BUCK REGISTER B */ +#define DA9052_BUCKB_BERIILIM (3<<6) +#define DA9052_BUCKB_BPERIMODE (3<<4) +#define DA9052_BUCKB_BMEMILIM (3<<2) +#define DA9052_BUCKB_BMEMMODE (3<<0) + +/* BUCKCORE REGISTER */ +#define DA9052_BUCKCORE_BCORECONF (1<<7) +#define DA9052_BUCKCORE_BCOREEN (1<<6) +#define DA9052_BUCKCORE_VBCORE (63<<0) + +/* BUCKPRO REGISTER */ +#define DA9052_BUCKPRO_BPROCONF (1<<7) +#define DA9052_BUCKPRO_BPROEN (1<<6) +#define DA9052_BUCKPRO_VBPRO (63<<0) + +/* BUCKMEM REGISTER */ +#define DA9052_BUCKMEM_BMEMCONF (1<<7) +#define DA9052_BUCKMEM_BMEMEN (1<<6) +#define DA9052_BUCKMEM_VBMEM (63<<0) + +/* BUCKPERI REGISTER */ +#define DA9052_BUCKPERI_BPERICONF (1<<7) +#define DA9052_BUCKPERI_BPERIEN (1<<6) +#if defined(CONFIG_PMIC_DA9052) +#define DA9052_BUCKPERI_BPERIHS (1<<5) +#define DA9052_BUCKPERI_VBPERI (31<<0) +#elif defined(CONFIG_PMIC_DA9053AA) || (CONFIG_PMIC_DA9053Bx) +#define DA9052_BUCKPERI_VBPERI (63<<0) +#endif + +/* LDO1 REGISTER */ +#define DA9052_LDO1_LDO1CONF (1<<7) +#define DA9052_LDO1_LDO1EN (1<<6) +#define DA9052_LDO1_VLDO1 (31<<0) + +/* LDO2 REGISTER */ +#define DA9052_LDO2_LDO2CONF (1<<7) +#define DA9052_LDO2_LDO2EN (1<<6) +#define DA9052_LDO2_VLDO2 (63<<0) + +/* LDO3 REGISTER */ +#define DA9052_LDO3_LDO3CONF (1<<7) +#define DA9052_LDO3_LDO3EN (1<<6) +#define DA9052_LDO3_VLDO3 (63<<0) + +/* LDO4 REGISTER */ +#define DA9052_LDO4_LDO4CONF (1<<7) +#define DA9052_LDO4_LDO4EN (1<<6) +#define DA9052_LDO4_VLDO4 (63<<0) + +/* LDO5 REGISTER */ +#define DA9052_LDO5_LDO5CONF (1<<7) +#define DA9052_LDO5_LDO5EN (1<<6) +#define DA9052_LDO5_VLDO5 (63<<0) + +/* LDO6 REGISTER */ +#define DA9052_LDO6_LDO6CONF (1<<7) +#define DA9052_LDO6_LDO6EN (1<<6) +#define DA9052_LDO6_VLDO6 (63<<0) + +/* LDO7 REGISTER */ +#define DA9052_LDO7_LDO7CONF (1<<7) +#define DA9052_LDO7_LDO7EN (1<<6) +#define DA9052_LDO7_VLDO7 (63<<0) + +/* LDO8 REGISTER */ +#define DA9052_LDO8_LDO8CONF (1<<7) +#define DA9052_LDO8_LDO8EN (1<<6) +#define DA9052_LDO8_VLDO8 (63<<0) + +/* LDO9 REGISTER */ +#define DA9052_LDO9_LDO9CONF (1<<7) +#define DA9052_LDO9_LDO9EN (1<<6) +#define DA9052_LDO9_VLDO9 (63<<0) + +/* LDO10 REGISTER */ +#define DA9052_LDO10_LDO10CONF (1<<7) +#define DA9052_LDO10_LDO10EN (1<<6) +#define DA9052_LDO10_VLDO10 (63<<0) + +/* SUPPLY REGISTER */ +#define DA9052_SUPPLY_VLOCK (1<<7) +#define DA9052_SUPPLY_VMEMSWEN (1<<6) +#define DA9052_SUPPLY_VPERISWEN (1<<5) +#define DA9052_SUPPLY_VLDO3GO (1<<4) +#define DA9052_SUPPLY_VLDO2GO (1<<3) +#define DA9052_SUPPLY_VBMEMGO (1<<2) +#define DA9052_SUPPLY_VBPROGO (1<<1) +#define DA9052_SUPPLY_VBCOREGO (1<<0) + +/* PULLDOWN REGISTER */ +#define DA9052_PULLDOWN_LDO5PDDIS (1<<5) +#define DA9052_PULLDOWN_LDO2PDDIS (1<<4) +#define DA9052_PULLDOWN_LDO1PDDIS (1<<3) +#define DA9052_PULLDOWN_MEMPDDIS (1<<2) +#define DA9052_PULLDOWN_PROPDDIS (1<<1) +#define DA9052_PULLDOWN_COREPDDIS (1<<0) + +/* BAT CHARGER REGISTER */ + +/* CHARGER BUCK REGISTER */ +#define DA9052_CHGBUCK_CHGTEMP (1<<7) +#define DA9052_CHGBUCK_CHGUSBILIM (1<<6) +#define DA9052_CHGBUCK_CHGBUCKLP (1<<5) +#define DA9052_CHGBUCK_CHGBUCKEN (1<<4) +#define DA9052_CHGBUCK_ISETBUCK (15<<0) + +/* WAIT COUNTER REGISTER */ +#define DA9052_WAITCONT_WAITDIR (1<<7) +#define DA9052_WAITCONT_RTCCLOCK (1<<6) +#define DA9052_WAITCONT_WAITMODE (1<<5) +#define DA9052_WAITCONT_EN32KOUT (1<<4) +#define DA9052_WAITCONT_DELAYTIME (15<<0) + +/* ISET CONTROL REGISTER */ +#define DA9052_ISET_ISETDCIN (15<<4) +#define DA9052_ISET_ISETVBUS (15<<0) + +/* BATTERY CHARGER CONTROL REGISTER */ +#define DA9052_BATCHG_ICHGPRE (3<<6) +#define DA9052_BATCHG_ICHGBAT (63<<0) + +/* CHARGER COUNTER REGISTER */ +#define DA9052_CHGCONT_VCHGBAT (31<<3) +#define DA9052_CHGCONT_TCTR (7<<0) + +/* INPUT CONTROL REGISTER */ +#define DA9052_INPUTCONT_TCTRMODE (1<<7) +#define DA9052_INPUTCONT_ICHGLOW (1<<5) +#define DA9052_INPUTCONT_VBUSSUSP (1<<4) +#define DA9052_INPUTCONT_DCINSUSP (1<<3) +#define DA9052_INPUTCONT_VCHGTHR (7<<0) + +/* CHARGING TIME REGISTER */ +#define DA9052_CHGTIME_CHGTIME (255<<0) + +/* BACKUP BATTERY CONTROL REGISTER */ +#define DA9052_BBATCONT_BCHARGERISET (15<<4) +#define DA9052_BBATCONT_BCHARGERVSET (15<<0) + +/* LED REGISTERS */ + +/* LED BOOST REGISTER */ +#define DA9052_BOOST_EBFAULT (1<<7) +#define DA9052_BOOST_MBFAULT (1<<6) +#define DA9052_BOOST_BOOSTFRQ (1<<5) +#define DA9052_BOOST_BOOSTILIM (1<<4) +#define DA9052_BOOST_LED3INEN (1<<3) +#define DA9052_BOOST_LED2INEN (1<<2) +#define DA9052_BOOST_LED1INEN (1<<1) +#define DA9052_BOOST_BOOSTEN (1<<0) + +/* LED COUNT REGISTER */ +#if defined(CONFIG_PMIC_DA9053Bx) +#define DA9052_LEDCONT_SELLEDMODE (1<<7) +#endif +#define DA9052_LEDCONT_LED3ICONT (1<<6) +#define DA9052_LEDCONT_LED3RAMP (1<<5) +#define DA9052_LEDCONT_LED3EN (1<<4) +#define DA9052_LEDCONT_LED2RAMP (1<<3) +#define DA9052_LEDCONT_LED2EN (1<<2) +#define DA9052_LEDCONT_LED1RAMP (1<<1) +#define DA9052_LEDCONT_LED1EN (1<<0) + +/* LEDMIN123 REGISTER */ +#define DA9052_LEDMIN123_LEDMINCURRENT (255<<0) + +/* LED1CONF REGISTER */ +#define DA9052_LED1CONF_LED1CURRENT (255<<0) + +/* LED2CONF REGISTER */ +#define DA9052_LED2CONF_LED2CURRENT (255<<0) + +/* LED3CONF REGISTER */ +#define DA9052_LED3CONF_LED3CURRENT (255<<0) + +/* LED1 COUNT REGISTER */ +#define DA9052_LED1CONT_LED1DIM (1<<7) +#define DA9052_LED1CONT_LED1PWM (127<<0) + +/* LED2 COUNT REGISTER */ +#define DA9052_LED2CONT_LED2DIM (1<<7) +#define DA9052_LED2CONT_LED2PWM (127<<0) + +/* LED3 COUNT REGISTER */ +#define DA9052_LED3CONT_LED3DIM (1<<7) +#define DA9052_LED3CONT_LED3PWM (127<<0) + +/* LED4 COUNT REGISTER */ +#define DA9052_LED4CONT_LED4DIM (1<<7) +#define DA9052_LED4CONT_LED4PWM (127<<0) + +/* LED5 COUNT REGISTER */ +#define DA9052_LED5CONT_LED5DIM (1<<7) +#define DA9052_LED5CONT_LED5PWM (127<<0) + +/* ADC REGISTERS */ + +/* ADC MAN registers */ +#define DA9052_ADCMAN_MANCONV (1<<4) +#define DA9052_ADCMAN_MUXSEL (15<<0) + +/* ADC COUNT regsisters */ +#define DA9052_ADCCONT_COMP1V2EN (1<<7) +#define DA9052_ADCCONT_ADCMODE (1<<6) +#define DA9052_ADCCONT_TBATISRCEN (1<<5) +#define DA9052_ADCCONT_AD4ISRCEN (1<<4) +#define DA9052_ADCCONT_AUTOAD6EN (1<<3) +#define DA9052_ADCCONT_AUTOAD5EN (1<<2) +#define DA9052_ADCCONT_AUTOAD4EN (1<<1) +#define DA9052_ADCCONT_AUTOVDDEN (1<<0) + +/* ADC 10 BIT MANUAL CONVERSION RESULT LOW register */ +#define DA9052_ADCRESL_ADCRESLSB (3<<0) + +/* ADC 10 BIT MANUAL CONVERSION RESULT HIGH register */ +#define DA9052_ADCRESH_ADCRESMSB (255<<0) + +/* VDD RES regsister*/ +#define DA9052_VDDRES_VDDOUTRES (255<<0) + +/* VDD MON regsister*/ +#define DA9052_VDDMON_VDDOUTMON (255<<0) + +/* ICHG_AV regsister*/ +#define DA9052_ICHGAV_ICHGAV (255<<0) + +/* ICHG_THD regsister*/ +#define DA9052_ICHGTHD_ICHGTHD (255<<0) + +/* ICHG_END regsister*/ +#define DA9052_ICHGEND_ICHGEND (255<<0) + +/* TBAT_RES regsister*/ +#define DA9052_TBATRES_TBATRES (255<<0) + +/* TBAT_HIGHP regsister*/ +#define DA9052_TBATHIGHP_TBATHIGHP (255<<0) + +/* TBAT_HIGHN regsister*/ +#define DA9052_TBATHIGHN_TBATHIGHN (255<<0) + +/* TBAT_LOW regsister*/ +#define DA9052_TBATLOW_TBATLOW (255<<0) + +/* T_OFFSET regsister*/ +#define DA9052_TOFFSET_TOFFSET (255<<0) + +/* ADCIN4_RES regsister*/ +#define DA9052_ADCIN4RES_ADCIN4RES (255<<0) + +/* ADCIN4_HIGH regsister*/ +#define DA9052_AUTO4HIGH_AUTO4HIGH (255<<0) + +/* ADCIN4_LOW regsister*/ +#define DA9052_AUTO4LOW_AUTO4LOW (255<<0) + +/* ADCIN5_RES regsister*/ +#define DA9052_ADCIN5RES_ADCIN5RES (255<<0) + +/* ADCIN5_HIGH regsister*/ +#define DA9052_AUTO5HIGH_AUTOHIGH (255<<0) + +/* ADCIN5_LOW regsister*/ +#define DA9052_AUTO5LOW_AUTO5LOW (255<<0) + +/* ADCIN6_RES regsister*/ +#define DA9052_ADCIN6RES_ADCIN6RES (255<<0) + +/* ADCIN6_HIGH regsister*/ +#define DA9052_AUTO6HIGH_AUTO6HIGH (255<<0) + +/* ADCIN6_LOW regsister*/ +#define DA9052_AUTO6LOW_AUTO6LOW (255<<0) + +/* TJUNC_RES regsister*/ +#define DA9052_TJUNCRES_TJUNCRES (255<<0) + +/* TSI REGISTER */ + +/* TSI Control Register A */ +#define DA9052_TSICONTA_TSIDELAY (3<<6) +#define DA9052_TSICONTA_TSISKIP (7<<3) +#define DA9052_TSICONTA_TSIMODE (1<<2) +#define DA9052_TSICONTA_PENDETEN (1<<1) +#define DA9052_TSICONTA_AUTOTSIEN (1<<0) + +/* TSI Control Register B */ +#define DA9052_TSICONTB_ADCREF (1<<7) +#define DA9052_TSICONTB_TSIMAN (1<<6) +#define DA9052_TSICONTB_TSIMUX (3<<4) +#define DA9052_TSICONTB_TSISEL3 (1<<3) +#define DA9052_TSICONTB_TSISEL2 (1<<2) +#define DA9052_TSICONTB_TSISEL1 (1<<1) +#define DA9052_TSICONTB_TSISEL0 (1<<0) + +/* TSI X Co-ordinate MSB Result register */ +#define DA9052_TSIXMSB_TSIXM (255<<0) + +/* TSI Y Co-ordinate MSB Result register */ +#define DA9052_TSIYMSB_TSIYM (255<<0) + +/* TSI Co-ordinate LSB Result register */ +#define DA9052_TSILSB_PENDOWN (1<<6) +#define DA9052_TSILSB_TSIZL (3<<4) +#define DA9052_TSILSB_TSIYL (3<<2) +#define DA9052_TSILSB_TSIXL (3<<0) + +/* TSI Z Measurement MSB Result register */ +#define DA9052_TSIZMSB_TSIZM (255<<0) + +/* RTC REGISTER */ + +/* RTC TIMER SECONDS REGISTER */ +#define DA9052_COUNTS_MONITOR (1<<6) +#define DA9052_COUNTS_COUNTSEC (63<<0) + +/* RTC TIMER MINUTES REGISTER */ +#define DA9052_COUNTMI_COUNTMIN (63<<0) + +/* RTC TIMER HOUR REGISTER */ +#define DA9052_COUNTH_COUNTHOUR (31<<0) + +/* RTC TIMER DAYS REGISTER */ +#define DA9052_COUNTD_COUNTDAY (31<<0) + +/* RTC TIMER MONTHS REGISTER */ +#define DA9052_COUNTMO_COUNTMONTH (15<<0) + +/* RTC TIMER YEARS REGISTER */ +#define DA9052_COUNTY_COUNTYEAR (63<<0) + +/* RTC ALARM MINUTES REGISTER */ +#define DA9052_ALARMMI_TICKTYPE (1<<7) +#define DA9052_ALARMMI_ALARMTYPE (1<<6) +#define DA9052_ALARMMI_ALARMMIN (63<<0) + +/* RTC ALARM HOURS REGISTER */ +#define DA9052_ALARMH_ALARMHOUR (31<<0) + +/* RTC ALARM DAYS REGISTER */ +#define DA9052_ALARMD_ALARMDAY (31<<0) + +/* RTC ALARM MONTHS REGISTER */ +#define DA9052_ALARMMO_ALARMMONTH (15<<0) + +/* RTC ALARM YEARS REGISTER */ +#define DA9052_ALARMY_TICKON (1<<7) +#define DA9052_ALARMY_ALARMON (1<<6) +#define DA9052_ALARMY_ALARMYEAR (63<<0) + +/* RTC SECONDS REGISTER A*/ +#define DA9052_SECONDA_SECONDSA (255<<0) + +/* RTC SECONDS REGISTER B*/ +#define DA9052_SECONDB_SECONDSB (255<<0) + +/* RTC SECONDS REGISTER C*/ +#define DA9052_SECONDC_SECONDSC (255<<0) + +/* RTC SECONDS REGISTER D*/ +#define DA9052_SECONDD_SECONDSD (255<<0) + +/* OTP REGISTER */ + +/* CHIP IDENTIFICATION REGISTER */ +#define DA9052_CHIPID_MRC (15<<4) +#define DA9052_CHIPID_TRC (15<<0) + +/* CONFIGURATION IDENTIFICATION REGISTER */ +#define DA9052_CONFIGID_CUSTOMERID (31<<3) +#define DA9052_CONFIGID_CONFID (7<<0) + +/* OTP CONTROL REGISTER */ +#define DA9052_OTPCONT_GPWRITEDIS (1<<7) +#define DA9052_OTPCONT_OTPCONFLOCK (1<<6) +#define DA9052_OTPCONT_OTPGPLOCK (1<<5) +#define DA9052_OTPCONT_OTPCONFG (1<<3) +#define DA9052_OTPCONT_OTPGP (1<<2) +#define DA9052_OTPCONT_OTPRP (1<<1) +#define DA9052_OTPCONT_OTPTRANSFER (1<<0) + +/* RTC OSCILLATOR TRIM REGISTER */ +#define DA9052_OSCTRIM_TRIM32K (255<<0) + +/* GP ID REGISTER 0 */ +#define DA9052_GPID0_GP0 (255<<0) + +/* GP ID REGISTER 1 */ +#define DA9052_GPID1_GP1 (255<<0) + +/* GP ID REGISTER 2 */ +#define DA9052_GPID2_GP2 (255<<0) + +/* GP ID REGISTER 3 */ +#define DA9052_GPID3_GP3 (255<<0) + +/* GP ID REGISTER 4 */ +#define DA9052_GPID4_GP4 (255<<0) + +/* GP ID REGISTER 5 */ +#define DA9052_GPID5_GP5 (255<<0) + +/* GP ID REGISTER 6 */ +#define DA9052_GPID6_GP6 (255<<0) + +/* GP ID REGISTER 7 */ +#define DA9052_GPID7_GP7 (255<<0) + +/* GP ID REGISTER 8 */ +#define DA9052_GPID8_GP8 (255<<0) + +/* GP ID REGISTER 9 */ +#define DA9052_GPID9_GP9 (255<<0) + +#endif +/* __LINUX_MFD_DA9052_REG_H */ diff --git a/include/linux/mfd/da9052/rtc.h b/include/linux/mfd/da9052/rtc.h new file mode 100644 index 00000000000..2057e9e001d --- /dev/null +++ b/include/linux/mfd/da9052/rtc.h @@ -0,0 +1,322 @@ +/* + * da9052 RTC module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_RTC_H +#define __LINUX_MFD_DA9052_RTC_H + +#define DA9052_RTC_DEVICE_NAME "da9052_rtc" + +/* Limit values */ +#define DA9052_RTC_SECONDS_LIMIT 59 +#define DA9052_RTC_MINUTES_LIMIT 59 +#define DA9052_RTC_HOURS_LIMIT 23 +#define DA9052_RTC_DAYS_LIMIT 31 +#define DA9052_RTC_MONTHS_LIMIT 12 +#define DA9052_RTC_YEARS_LIMIT 63 + +/* Months */ +#define FEBRUARY 2 +#define APRIL 4 +#define JUNE 6 +#define SEPTEMBER 9 +#define NOVEMBER 11 + +/* BYTE shifts */ +#define DA9052_RTC_FOURTH_BYTE 24 +#define DA9052_RTC_THIRD_BYTE 16 +#define DA9052_RTC_SECOND_BYTE 8 +#define DA9052_RTC_FIRST_BYTE 0 + +/* Oscillator trim values */ +#define DA9052_RTC_OSC_FRQ_0_0ppm 0 +#define DA9052_RTC_OSC_FRQ_1_9ppm 1 +#define DA9052_RTC_OSC_FRQ_3_8ppm 2 +#define DA9052_RTC_OSC_FRQ_5_7ppm 3 +#define DA9052_RTC_OSC_FRQ_7_6ppm 4 +#define DA9052_RTC_OSC_FRQ_9_5ppm 5 +#define DA9052_RTC_OSC_FRQ_11_4ppm 6 +#define DA9052_RTC_OSC_FRQ_13_3ppm 7 +#define DA9052_RTC_OSC_FRQ_15_2ppm 8 +#define DA9052_RTC_OSC_FRQ_17_1ppm 9 +#define DA9052_RTC_OSC_FRQ_19_0ppm 10 +#define DA9052_RTC_OSC_FRQ_20_9ppm 11 +#define DA9052_RTC_OSC_FRQ_22_8ppm 12 +#define DA9052_RTC_OSC_FRQ_24_7ppm 13 +#define DA9052_RTC_OSC_FRQ_26_7ppm 14 +#define DA9052_RTC_OSC_FRQ_28_6ppm 15 +#define DA9052_RTC_OSC_FRQ_30_5ppm 16 +#define DA9052_RTC_OSC_FRQ_32_4ppm 17 +#define DA9052_RTC_OSC_FRQ_34_3ppm 18 +#define DA9052_RTC_OSC_FRQ_36_2ppm 19 +#define DA9052_RTC_OSC_FRQ_38_1ppm 20 +#define DA9052_RTC_OSC_FRQ_40_0ppm 21 +#define DA9052_RTC_OSC_FRQ_41_9ppm 22 +#define DA9052_RTC_OSC_FRQ_43_8ppm 23 +#define DA9052_RTC_OSC_FRQ_45_7ppm 24 +#define DA9052_RTC_OSC_FRQ_47_6ppm 25 +#define DA9052_RTC_OSC_FRQ_49_5ppm 26 +#define DA9052_RTC_OSC_FRQ_51_4ppm 27 +#define DA9052_RTC_OSC_FRQ_53_4ppm 28 +#define DA9052_RTC_OSC_FRQ_55_3ppm 29 +#define DA9052_RTC_OSC_FRQ_57_2ppm 30 +#define DA9052_RTC_OSC_FRQ_59_1ppm 31 +#define DA9052_RTC_OSC_FRQ_61_0ppm 32 +#define DA9052_RTC_OSC_FRQ_62_9ppm 33 +#define DA9052_RTC_OSC_FRQ_64_8ppm 34 +#define DA9052_RTC_OSC_FRQ_66_7ppm 35 +#define DA9052_RTC_OSC_FRQ_68_6ppm 36 +#define DA9052_RTC_OSC_FRQ_70_5ppm 37 +#define DA9052_RTC_OSC_FRQ_72_4ppm 38 +#define DA9052_RTC_OSC_FRQ_74_3ppm 39 +#define DA9052_RTC_OSC_FRQ_76_2ppm 40 +#define DA9052_RTC_OSC_FRQ_78_2ppm 41 +#define DA9052_RTC_OSC_FRQ_80_1ppm 42 +#define DA9052_RTC_OSC_FRQ_82_0ppm 43 +#define DA9052_RTC_OSC_FRQ_83_9ppm 44 +#define DA9052_RTC_OSC_FRQ_85_8ppm 45 +#define DA9052_RTC_OSC_FRQ_87_7ppm 46 +#define DA9052_RTC_OSC_FRQ_89_6ppm 47 +#define DA9052_RTC_OSC_FRQ_91_5ppm 48 +#define DA9052_RTC_OSC_FRQ_93_4ppm 49 +#define DA9052_RTC_OSC_FRQ_95_3ppm 50 +#define DA9052_RTC_OSC_FRQ_97_2ppm 51 +#define DA9052_RTC_OSC_FRQ_99_1ppm 52 +#define DA9052_RTC_OSC_FRQ_101_0ppm 53 +#define DA9052_RTC_OSC_FRQ_102_9ppm 54 +#define DA9052_RTC_OSC_FRQ_104_9ppm 55 +#define DA9052_RTC_OSC_FRQ_106_8ppm 56 +#define DA9052_RTC_OSC_FRQ_108_7ppm 57 +#define DA9052_RTC_OSC_FRQ_110_6ppm 58 +#define DA9052_RTC_OSC_FRQ_112_5ppm 59 +#define DA9052_RTC_OSC_FRQ_114_4ppm 60 +#define DA9052_RTC_OSC_FRQ_116_3ppm 61 +#define DA9052_RTC_OSC_FRQ_118_2ppm 62 +#define DA9052_RTC_OSC_FRQ_120_1ppm 63 +#define DA9052_RTC_OSC_FRQ_122_0ppm 64 +#define DA9052_RTC_OSC_FRQ_123_9ppm 65 +#define DA9052_RTC_OSC_FRQ_125_8ppm 66 +#define DA9052_RTC_OSC_FRQ_127_7ppm 67 +#define DA9052_RTC_OSC_FRQ_129_6ppm 68 +#define DA9052_RTC_OSC_FRQ_131_6ppm 69 +#define DA9052_RTC_OSC_FRQ_133_5ppm 70 +#define DA9052_RTC_OSC_FRQ_135_4ppm 71 +#define DA9052_RTC_OSC_FRQ_137_3ppm 72 +#define DA9052_RTC_OSC_FRQ_139_2ppm 73 +#define DA9052_RTC_OSC_FRQ_141_1ppm 74 +#define DA9052_RTC_OSC_FRQ_143_0ppm 75 +#define DA9052_RTC_OSC_FRQ_144_9ppm 76 +#define DA9052_RTC_OSC_FRQ_146_8ppm 77 +#define DA9052_RTC_OSC_FRQ_148_7ppm 78 +#define DA9052_RTC_OSC_FRQ_150_6ppm 79 +#define DA9052_RTC_OSC_FRQ_152_5ppm 80 +#define DA9052_RTC_OSC_FRQ_154_4ppm 81 +#define DA9052_RTC_OSC_FRQ_156_4ppm 82 +#define DA9052_RTC_OSC_FRQ_158_3ppm 83 +#define DA9052_RTC_OSC_FRQ_160_2ppm 84 +#define DA9052_RTC_OSC_FRQ_162_1ppm 85 +#define DA9052_RTC_OSC_FRQ_164_0ppm 86 +#define DA9052_RTC_OSC_FRQ_165_9ppm 87 +#define DA9052_RTC_OSC_FRQ_167_8ppm 88 +#define DA9052_RTC_OSC_FRQ_169_7ppm 89 +#define DA9052_RTC_OSC_FRQ_171_6ppm 90 +#define DA9052_RTC_OSC_FRQ_173_5ppm 91 +#define DA9052_RTC_OSC_FRQ_175_4ppm 92 +#define DA9052_RTC_OSC_FRQ_177_3ppm 93 +#define DA9052_RTC_OSC_FRQ_179_2ppm 94 +#define DA9052_RTC_OSC_FRQ_181_1ppm 95 +#define DA9052_RTC_OSC_FRQ_183_1ppm 96 +#define DA9052_RTC_OSC_FRQ_185_0ppm 97 +#define DA9052_RTC_OSC_FRQ_186_9ppm 98 +#define DA9052_RTC_OSC_FRQ_188_8ppm 99 +#define DA9052_RTC_OSC_FRQ_190_7ppm 100 +#define DA9052_RTC_OSC_FRQ_192_6ppm 101 +#define DA9052_RTC_OSC_FRQ_194_5ppm 102 +#define DA9052_RTC_OSC_FRQ_196_4ppm 103 +#define DA9052_RTC_OSC_FRQ_198_3ppm 104 +#define DA9052_RTC_OSC_FRQ_200_2ppm 105 +#define DA9052_RTC_OSC_FRQ_202_1ppm 106 +#define DA9052_RTC_OSC_FRQ_204_0ppm 107 +#define DA9052_RTC_OSC_FRQ_205_9ppm 108 +#define DA9052_RTC_OSC_FRQ_207_9ppm 109 +#define DA9052_RTC_OSC_FRQ_209_8ppm 110 +#define DA9052_RTC_OSC_FRQ_211_7ppm 111 +#define DA9052_RTC_OSC_FRQ_213_6ppm 112 +#define DA9052_RTC_OSC_FRQ_215_5ppm 113 +#define DA9052_RTC_OSC_FRQ_217_4ppm 114 +#define DA9052_RTC_OSC_FRQ_219_3ppm 115 +#define DA9052_RTC_OSC_FRQ_221_2ppm 116 +#define DA9052_RTC_OSC_FRQ_223_1ppm 117 +#define DA9052_RTC_OSC_FRQ_225_0ppm 118 +#define DA9052_RTC_OSC_FRQ_226_9ppm 119 +#define DA9052_RTC_OSC_FRQ_228_8ppm 120 +#define DA9052_RTC_OSC_FRQ_230_7ppm 121 +#define DA9052_RTC_OSC_FRQ_232_6ppm 122 +#define DA9052_RTC_OSC_FRQ_234_6ppm 123 +#define DA9052_RTC_OSC_FRQ_236_5ppm 124 +#define DA9052_RTC_OSC_FRQ_238_4ppm 125 +#define DA9052_RTC_OSC_FRQ_240_3ppm 126 +#define DA9052_RTC_OSC_FRQ_242_2ppm 127 +#define DA9052_RTC_OSC_FRQ_MINUS_244_1ppm 128 +#define DA9052_RTC_OSC_FRQ_MINUS_242_2ppm 129 +#define DA9052_RTC_OSC_FRQ_MINUS_240_3ppm 130 +#define DA9052_RTC_OSC_FRQ_MINUS_238_4ppm 131 +#define DA9052_RTC_OSC_FRQ_MINUS_236_5ppm 132 +#define DA9052_RTC_OSC_FRQ_MINUS_234_6ppm 133 +#define DA9052_RTC_OSC_FRQ_MINUS_232_6ppm 134 +#define DA9052_RTC_OSC_FRQ_MINUS_230_7ppm 135 +#define DA9052_RTC_OSC_FRQ_MINUS_228_8ppm 136 +#define DA9052_RTC_OSC_FRQ_MINUS_226_9ppm 137 +#define DA9052_RTC_OSC_FRQ_MINUS_225_0ppm 138 +#define DA9052_RTC_OSC_FRQ_MINUS_223_1ppm 139 +#define DA9052_RTC_OSC_FRQ_MINUS_221_2ppm 140 +#define DA9052_RTC_OSC_FRQ_MINUS_219_3ppm 141 +#define DA9052_RTC_OSC_FRQ_MINUS_217_4ppm 142 +#define DA9052_RTC_OSC_FRQ_MINUS_215_5ppm 143 +#define DA9052_RTC_OSC_FRQ_MINUS_213_6ppm 144 +#define DA9052_RTC_OSC_FRQ_MINUS_211_7ppm 145 +#define DA9052_RTC_OSC_FRQ_MINUS_209_8ppm 146 +#define DA9052_RTC_OSC_FRQ_MINUS_207_9ppm 147 +#define DA9052_RTC_OSC_FRQ_MINUS_205_9ppm 148 +#define DA9052_RTC_OSC_FRQ_MINUS_204_0ppm 149 +#define DA9052_RTC_OSC_FRQ_MINUS_202_1ppm 150 +#define DA9052_RTC_OSC_FRQ_MINUS_200_2ppm 151 +#define DA9052_RTC_OSC_FRQ_MINUS_198_3ppm 152 +#define DA9052_RTC_OSC_FRQ_MINUS_196_4ppm 153 +#define DA9052_RTC_OSC_FRQ_MINUS_194_5ppm 154 +#define DA9052_RTC_OSC_FRQ_MINUS_192_6ppm 155 +#define DA9052_RTC_OSC_FRQ_MINUS_190_7ppm 156 +#define DA9052_RTC_OSC_FRQ_MINUS_188_8ppm 157 +#define DA9052_RTC_OSC_FRQ_MINUS_186_9ppm 158 +#define DA9052_RTC_OSC_FRQ_MINUS_185_0ppm 159 +#define DA9052_RTC_OSC_FRQ_MINUS_183_1ppm 160 +#define DA9052_RTC_OSC_FRQ_MINUS_181_1ppm 161 +#define DA9052_RTC_OSC_FRQ_MINUS_179_2ppm 162 +#define DA9052_RTC_OSC_FRQ_MINUS_177_3ppm 163 +#define DA9052_RTC_OSC_FRQ_MINUS_175_4ppm 164 +#define DA9052_RTC_OSC_FRQ_MINUS_173_5ppm 165 +#define DA9052_RTC_OSC_FRQ_MINUS_171_6ppm 166 +#define DA9052_RTC_OSC_FRQ_MINUS_169_7ppm 167 +#define DA9052_RTC_OSC_FRQ_MINUS_167_8ppm 168 +#define DA9052_RTC_OSC_FRQ_MINUS_165_9ppm 169 +#define DA9052_RTC_OSC_FRQ_MINUS_164_0ppm 170 +#define DA9052_RTC_OSC_FRQ_MINUS_162_1ppm 171 +#define DA9052_RTC_OSC_FRQ_MINUS_160_2ppm 172 +#define DA9052_RTC_OSC_FRQ_MINUS_158_3ppm 173 +#define DA9052_RTC_OSC_FRQ_MINUS_156_4ppm 174 +#define DA9052_RTC_OSC_FRQ_MINUS_154_4ppm 175 +#define DA9052_RTC_OSC_FRQ_MINUS_152_5ppm 176 +#define DA9052_RTC_OSC_FRQ_MINUS_150_6ppm 177 +#define DA9052_RTC_OSC_FRQ_MINUS_148_7ppm 178 +#define DA9052_RTC_OSC_FRQ_MINUS_146_8ppm 179 +#define DA9052_RTC_OSC_FRQ_MINUS_144_9ppm 180 +#define DA9052_RTC_OSC_FRQ_MINUS_143_0ppm 181 +#define DA9052_RTC_OSC_FRQ_MINUS_141_1ppm 182 +#define DA9052_RTC_OSC_FRQ_MINUS_139_2ppm 183 +#define DA9052_RTC_OSC_FRQ_MINUS_137_3ppm 184 +#define DA9052_RTC_OSC_FRQ_MINUS_135_4ppm 185 +#define DA9052_RTC_OSC_FRQ_MINUS_133_5ppm 186 +#define DA9052_RTC_OSC_FRQ_MINUS_131_6ppm 187 +#define DA9052_RTC_OSC_FRQ_MINUS_129_6ppm 188 +#define DA9052_RTC_OSC_FRQ_MINUS_127_7ppm 189 +#define DA9052_RTC_OSC_FRQ_MINUS_125_8ppm 190 +#define DA9052_RTC_OSC_FRQ_MINUS_123_9ppm 191 +#define DA9052_RTC_OSC_FRQ_MINUS_122_0ppm 192 +#define DA9052_RTC_OSC_FRQ_MINUS_120_1ppm 193 +#define DA9052_RTC_OSC_FRQ_MINUS_118_2ppm 194 +#define DA9052_RTC_OSC_FRQ_MINUS_116_3ppm 195 +#define DA9052_RTC_OSC_FRQ_MINUS_114_4ppm 196 +#define DA9052_RTC_OSC_FRQ_MINUS_112_5ppm 197 +#define DA9052_RTC_OSC_FRQ_MINUS_110_6ppm 198 +#define DA9052_RTC_OSC_FRQ_MINUS_108_7ppm 199 +#define DA9052_RTC_OSC_FRQ_MINUS_106_8ppm 200 +#define DA9052_RTC_OSC_FRQ_MINUS_104_9ppm 201 +#define DA9052_RTC_OSC_FRQ_MINUS_102_9ppm 202 +#define DA9052_RTC_OSC_FRQ_MINUS_101_0ppm 203 +#define DA9052_RTC_OSC_FRQ_MINUS_99_1ppm 204 +#define DA9052_RTC_OSC_FRQ_MINUS_97_2ppm 205 +#define DA9052_RTC_OSC_FRQ_MINUS_95_3ppm 206 +#define DA9052_RTC_OSC_FRQ_MINUS_93_4ppm 207 +#define DA9052_RTC_OSC_FRQ_MINUS_91_5ppm 208 +#define DA9052_RTC_OSC_FRQ_MINUS_89_6ppm 209 +#define DA9052_RTC_OSC_FRQ_MINUS_87_7ppm 210 +#define DA9052_RTC_OSC_FRQ_MINUS_85_8ppm 211 +#define DA9052_RTC_OSC_FRQ_MINUS_83_9ppm 212 +#define DA9052_RTC_OSC_FRQ_MINUS_82_0ppm 213 +#define DA9052_RTC_OSC_FRQ_MINUS_80_1ppm 214 +#define DA9052_RTC_OSC_FRQ_MINUS_78_2ppm 215 +#define DA9052_RTC_OSC_FRQ_MINUS_76_2ppm 216 +#define DA9052_RTC_OSC_FRQ_MINUS_74_3ppm 217 +#define DA9052_RTC_OSC_FRQ_MINUS_72_4ppm 218 +#define DA9052_RTC_OSC_FRQ_MINUS_70_5ppm 219 +#define DA9052_RTC_OSC_FRQ_MINUS_68_6ppm 220 +#define DA9052_RTC_OSC_FRQ_MINUS_66_7ppm 221 +#define DA9052_RTC_OSC_FRQ_MINUS_64_8ppm 222 +#define DA9052_RTC_OSC_FRQ_MINUS_62_9ppm 223 +#define DA9052_RTC_OSC_FRQ_MINUS_61_0ppm 224 +#define DA9052_RTC_OSC_FRQ_MINUS_59_1ppm 225 +#define DA9052_RTC_OSC_FRQ_MINUS_57_2ppm 226 +#define DA9052_RTC_OSC_FRQ_MINUS_55_3ppm 227 +#define DA9052_RTC_OSC_FRQ_MINUS_53_4ppm 228 +#define DA9052_RTC_OSC_FRQ_MINUS_51_4ppm 229 +#define DA9052_RTC_OSC_FRQ_MINUS_49_5ppm 230 +#define DA9052_RTC_OSC_FRQ_MINUS_47_6ppm 231 +#define DA9052_RTC_OSC_FRQ_MINUS_45_7ppm 232 +#define DA9052_RTC_OSC_FRQ_MINUS_43_8ppm 233 +#define DA9052_RTC_OSC_FRQ_MINUS_41_9ppm 234 +#define DA9052_RTC_OSC_FRQ_MINUS_40_0ppm 235 +#define DA9052_RTC_OSC_FRQ_MINUS_38_1ppm 236 +#define DA9052_RTC_OSC_FRQ_MINUS_36_2ppm 237 +#define DA9052_RTC_OSC_FRQ_MINUS_34_3ppm 238 +#define DA9052_RTC_OSC_FRQ_MINUS_32_4ppm 239 +#define DA9052_RTC_OSC_FRQ_MINUS_30_5ppm 240 +#define DA9052_RTC_OSC_FRQ_MINUS_28_6ppm 241 +#define DA9052_RTC_OSC_FRQ_MINUS_26_7ppm 242 +#define DA9052_RTC_OSC_FRQ_MINUS_24_7ppm 243 +#define DA9052_RTC_OSC_FRQ_MINUS_22_8ppm 244 +#define DA9052_RTC_OSC_FRQ_MINUS_20_9ppm 245 +#define DA9052_RTC_OSC_FRQ_MINUS_19_0ppm 246 +#define DA9052_RTC_OSC_FRQ_MINUS_17_1ppm 247 +#define DA9052_RTC_OSC_FRQ_MINUS_15_2ppm 248 +#define DA9052_RTC_OSC_FRQ_MINUS_13_3ppm 249 +#define DA9052_RTC_OSC_FRQ_MINUS_11_4ppm 250 +#define DA9052_RTC_OSC_FRQ_MINUS_9_5ppm 251 +#define DA9052_RTC_OSC_FRQ_MINUS_7_6ppm 252 +#define DA9052_RTC_OSC_FRQ_MINUS_5_7ppm 253 +#define DA9052_RTC_OSC_FRQ_MINUS_3_8ppm 254 +#define DA9052_RTC_OSC_FRQ_MINUS_1_9ppm 255 + +/* RTC error codes */ +#define DA9052_RTC_INVALID_SECONDS 3 +#define DA9052_RTC_INVALID_MINUTES 4 +#define DA9052_RTC_INVALID_HOURS 5 +#define DA9052_RTC_INVALID_DAYS 6 +#define DA9052_RTC_INVALID_MONTHS 7 +#define DA9052_RTC_INVALID_YEARS 8 +#define DA9052_RTC_INVALID_EVENT 9 +#define DA9052_RTC_INVALID_IOCTL 10 +#define DA9052_RTC_INVALID_SETTING 11 +#define DA9052_RTC_EVENT_ALREADY_REGISTERED 12 +#define DA9052_RTC_EVENT_UNREGISTERED 13 +#define DA9052_RTC_EVENT_REGISTRATION_FAILED 14 +#define DA9052_RTC_EVENT_UNREGISTRATION_FAILED 15 + +#endif +/* __LINUX_MFD_DA9052_RTC_H */ diff --git a/include/linux/mfd/da9052/tsi.h b/include/linux/mfd/da9052/tsi.h new file mode 100644 index 00000000000..a677bbc012a --- /dev/null +++ b/include/linux/mfd/da9052/tsi.h @@ -0,0 +1,427 @@ +/* + * da9052 TSI module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_TSI_H +#define __LINUX_MFD_DA9052_TSI_H + +#include +#include +#include +#include + +#define DA9052_TSI_DEVICE_NAME "da9052-tsi" +#define DA9052_TSI_INPUT_DEV DA9052_TSI_DEVICE_NAME + +#define TSI_VERSION 0x0101 +#define DA9052_VENDOR_ID 0x15B6 +#define DA9052_PRODUCT_ID 0x9052 + +#define TSI_INPUT_DEVICE_OFF 0 +#define NUM_INPUT_DEVS 1 + +#define DA9052_DISPLAY_X_MAX 0x3FF +#define DA9052_DISPLAY_Y_MAX 0x3FF +#define DA9052_TOUCH_PRESSURE_MAX 0x3FF + +#define DA9052_TCA_AUTO_TSI_ENABLE (1<<0) +#define DA9052_TCA_PEN_DET_ENABLE (1<<1) +#define DA9052_TCA_TSI_XP_MODE_ENABLE (1<<2) + +#define DA9052_TCA_TSI_DELAY_0SLOTS (0<<6) +#define DA9052_TCA_TSI_DELAY_2SLOTS (2<<6) +#define DA9052_TCA_TSI_DELAY_4SLOTS (3<<6) + +#define DA9052_TCA_TSI_SEL_XPLUS (1<<0) +#define DA9052_TCA_TSI_SEL_XMINUS (1<<1) +#define DA9052_TCA_TSI_SEL_YPLUS (1<<2) +#define DA9052_TCA_TSI_SEL_YMINUS (1<<3) + +#define DA9052_TCA_TSI_MUX_XPLUS_ROUTED_ADCIN7 (0<<4) +#define DA9052_TCA_TSI_MUX_YPLUS_ROUTED_ADCIN7 (1<<4) +#define DA9052_TCA_TSI_MUX_XMINUS_ROUTED_ADCIN7 (2<<4) +#define DA9052_TCA_TSI_MUX_YMINUS_ROUTED_ADCIN7 (3<<4) + +#define DA9052_TCA_TSI_MAN_ENABLE (1<<6) +#define DA9052_TCA_TSI_SET_TSIREF (0<<7) +#define DA9052_TCA_TSI_SET_XY_REF (1<<7) + +#define DA9052_EVETN_B_E_PEN_DOWN (1<<6) +#define DA9052_EVENT_B_E_TSI_READY (1<<7) + +#define DA9052_IRQMASK_B_PENDOWN_MASK (1<<6) +#define DA9052_IRQMASK_B_TSI_READY_MASK (1<<7) + +#define X_LSB_SHIFT (0) +#define Y_LSB_SHIFT (2) +#define Z_LSB_SHIFT (4) +#define PEN_DET_SHIFT (6) +#define X_MSB_SHIFT (2) +#define Y_MSB_SHIFT (2) +#define Z_MSB_SHIFT (2) +#define X_LSB_MASK (11 << X_LSB_SHIFT) +#define Y_LSB_MASK (11 << Y_LSB_SHIFT) +#define Z_LSB_MASK (11 << Z_LSB_SHIFT) +#define PEN_DET_MASK (11 << PEN_DET_SHIFT) + +#define TSI_FIFO_SIZE 16 + +#define INVALID_LDO9_VOLT_VALUE 17 + +#define set_bits(value, mask) (value | mask) +#define clear_bits(value, mask) (value & ~(mask)) + +#define SUCCESS 0 +#define FAILURE 1 + +#define SET 1 +#define RESET 0 +#define CLEAR 0 + +#define ENABLE 1 +#define DISABLE 0 + +#define TRUE 1 +#define FALSE 0 + +#define incr_with_wrap_reg_fifo(x) \ + if (++x >= TSI_REG_DATA_BUF_SIZE) \ + x = 0 + +#define incr_with_wrap(x) \ + if (++x >= TSI_FIFO_SIZE) \ + x = 0 + +#undef DA9052_DEBUG +#if DA9052_TSI_DEBUG +#define DA9052_DEBUG(fmt, args...) printk(KERN_CRIT "" fmt, ##args) +#else +#define DA9052_DEBUG(fmt, args...) +#endif + +enum ADC_MODE { + + ECONOMY_MODE = 0, + FAST_MODE = 1 +}; + +enum TSI_DELAY { + TSI_DELAY_0SLOTS = 0, + TSI_DELAY_1SLOTS = 1, + TSI_DELAY_2SLOTS = 2, + TSI_DELAY_4SLOTS = 3 +}; + +enum TSI_SLOT_SKIP { + TSI_SKIP_0SLOTS = 0, + TSI_SKIP_2SLOTS = 1, + TSI_SKIP_5SLOTS = 2, + TSI_SKIP_10SLOTS = 3, + TSI_SKIP_30SLOTS = 4, + TSI_SKIP_80SLOTS = 5, + TSI_SKIP_130SLOTS = 6, + TSI_SKIP_330SLOTS = 7 +}; + + +enum TSI_MUX_SEL { + TSI_MUX_XPLUS = 0, + TSI_MUX_YPLUS = 1, + TSI_MUX_XMINUS = 2, + TSI_MUX_YMINUS = 3 +}; + + +enum TSI_IRQ { + TSI_PEN_DWN, + TSI_DATA_RDY +}; + + +enum TSI_COORDINATE { + X_COORDINATE, + Y_COORDINATE, + Z_COORDINATE +}; + +enum TSI_MEASURE_SEQ { + XYZP_MODE, + XP_MODE +}; + +enum TSI_STATE { + TSI_AUTO_MODE, + TSI_MANUAL_COORD_X, + TSI_MANUAL_COORD_Y, + TSI_MANUAL_COORD_Z, + TSI_MANUAL_SET, + TSI_IDLE +}; + +union da9052_tsi_cont_reg { + u8 da9052_tsi_cont_a; + struct { + u8 auto_tsi_en:1; + u8 pen_det_en:1; + u8 tsi_mode:1; + u8 tsi_skip:3; + u8 tsi_delay:2; + } tsi_cont_a; +}; + +union da9052_tsi_man_cont_reg { + u8 da9052_tsi_cont_b; + struct { + u8 tsi_sel_0:1; + u8 tsi_sel_1:1; + u8 tsi_sel_2:1; + u8 tsi_sel_3:1; + u8 tsi_mux:2; + u8 tsi_man:1; + u8 tsi_adc_ref:1; + } tsi_cont_b; +}; + +struct da9052_tsi_conf { + union da9052_tsi_cont_reg auto_cont; + union da9052_tsi_man_cont_reg man_cont; + u8 tsi_adc_sample_intervel:1; + enum TSI_STATE state; + u8 ldo9_en:1; + u8 ldo9_conf:1; + u8 tsi_ready_irq_mask:1; + u8 tsi_pendown_irq_mask:1; +}; + + +struct da9052_tsi_reg { + u8 x_msb; + u8 y_msb; + u8 z_msb; + u8 lsb; +}; + + +struct da9052_tsi_reg_fifo { + struct semaphore lock; + s32 head; + s32 tail; + struct da9052_tsi_reg data[TSI_REG_DATA_BUF_SIZE]; +}; + +struct da9052_tsi_info { + struct da9052_tsi_conf tsi_conf; + struct input_dev *input_devs[NUM_INPUT_DEVS]; + struct calib_cfg_t *tsi_calib; + u32 tsi_data_poll_interval; + u32 tsi_penup_count; + u32 tsi_zero_data_cnt; + u8 pen_dwn_event; + u8 tsi_rdy_event; + u8 pd_reg_status; + u8 datardy_reg_status; +}; + +struct da9052_tsi { + struct da9052_tsi_reg tsi_fifo[TSI_FIFO_SIZE]; + struct mutex tsi_fifo_lock; + u8 tsi_sampling; + u8 tsi_state; + u32 tsi_fifo_start; + u32 tsi_fifo_end; +}; + +struct da9052_ts_priv { + struct da9052 *da9052; + struct da9052_eh_nb pd_nb; + struct da9052_eh_nb datardy_nb; + + struct tsi_thread_type tsi_reg_proc_thread; + struct tsi_thread_type tsi_raw_proc_thread; + + struct da9052_tsi_platform_data *tsi_pdata; + + struct da9052_tsi_reg_fifo tsi_reg_fifo; + struct da9052_tsi_raw_fifo tsi_raw_fifo; + + u32 tsi_reg_data_poll_interval; + u32 tsi_raw_data_poll_interval; + + u8 early_data_flag; + u8 debounce_over; + u8 win_reference_valid; + + int os_data_cnt; + int raw_data_cnt; +}; + +static inline u8 mask_pendwn_irq(u8 val) +{ + return val |= DA9052_IRQMASKB_MPENDOWN; +} + +static inline u8 unmask_pendwn_irq(u8 val) +{ + return val &= ~DA9052_IRQMASKB_MPENDOWN; +} + +static inline u8 mask_tsi_rdy_irq(u8 val) +{ + return val |= DA9052_IRQMASKB_MTSIREADY; +} + +static inline u8 unmask_tsi_rdy_irq(u8 val) +{ + return val &= ~DA9052_IRQMASKB_MTSIREADY; +} + +static inline u8 enable_ldo9(u8 val) +{ + return val |= DA9052_LDO9_LDO9EN; +} + +static inline u8 disable_ldo9(u8 val) +{ + return val &= ~DA9052_LDO9_LDO9EN; +} + +static inline u8 set_auto_tsi_en(u8 val) +{ + return val |= DA9052_TSICONTA_AUTOTSIEN; +} + +static inline u8 reset_auto_tsi_en(u8 val) +{ + return val &= ~DA9052_TSICONTA_AUTOTSIEN; +} + +static inline u8 enable_pen_detect(u8 val) +{ + return val |= DA9052_TSICONTA_PENDETEN; +} + +static inline u8 disable_pen_detect(u8 val) +{ + return val &= ~DA9052_TSICONTA_PENDETEN; +} + +static inline u8 enable_xyzp_mode(u8 val) +{ + return val &= ~DA9052_TSICONTA_TSIMODE; +} + +static inline u8 enable_xp_mode(u8 val) +{ + return val |= DA9052_TSICONTA_TSIMODE; +} + +static inline u8 enable_tsi_manual_mode(u8 val) +{ + return val |= DA9052_TSICONTB_TSIMAN; +} + +static inline u8 disable_tsi_manual_mode(u8 val) +{ + return val &= ~DA9052_TSICONTB_TSIMAN; +} + +static inline u8 tsi_sel_xplus_close(u8 val) +{ + return val |= DA9052_TSICONTB_TSISEL0; +} + +static inline u8 tsi_sel_xplus_open(u8 val) +{ + return val &= ~DA9052_TSICONTB_TSISEL0; +} + +static inline u8 tsi_sel_xminus_close(u8 val) +{ + return val |= DA9052_TSICONTB_TSISEL1; +} + +static inline u8 tsi_sel_xminus_open(u8 val) +{ + return val &= ~DA9052_TSICONTB_TSISEL1; +} + +static inline u8 tsi_sel_yplus_close(u8 val) +{ + return val |= DA9052_TSICONTB_TSISEL2; +} + +static inline u8 tsi_sel_yplus_open(u8 val) +{ + return val &= ~DA9052_TSICONTB_TSISEL2; +} + +static inline u8 tsi_sel_yminus_close(u8 val) +{ + return val |= DA9052_TSICONTB_TSISEL3; +} + +static inline u8 tsi_sel_yminus_open(u8 val) +{ + return val &= ~DA9052_TSICONTB_TSISEL3; +} + +static inline u8 adc_mode_economy_mode(u8 val) +{ + return val &= ~DA9052_ADCCONT_ADCMODE ; +} + +static inline u8 adc_mode_fast_mode(u8 val) +{ + return val |= DA9052_ADCCONT_ADCMODE; +} +int da9052_tsi_get_calib_display_point(struct da9052_tsi_data *display); + +struct da9052_ldo_config { + u16 ldo_volt; + u8 ldo_num; + u8 ldo_conf:1; + u8 ldo_pd:1; +}; + +static inline u8 ldo9_mV_to_reg(u16 value) +{ + return (value - DA9052_LDO9_VOLT_LOWER)/DA9052_LDO9_VOLT_STEP; +} + +static inline u8 validate_ldo9_mV(u16 value) +{ + if ((value >= DA9052_LDO9_VOLT_LOWER) && \ + (value <= DA9052_LDO9_VOLT_UPPER)) + return + (((value - DA9052_LDO9_VOLT_LOWER) + % DA9052_LDO9_VOLT_STEP > 0) ? -1 : 0); + return FAILURE; +} + +s32 da9052_tsi_raw_proc_thread(void *ptr); +void __init da9052_init_tsi_fifos(struct da9052_ts_priv *priv); +void clean_tsi_fifos(struct da9052_ts_priv *priv); +u32 get_reg_data_cnt(struct da9052_ts_priv *priv); +u32 get_reg_free_space_cnt(struct da9052_ts_priv *priv); +void da9052_tsi_process_reg_data(struct da9052_ts_priv *priv); +void da9052_tsi_pen_down_handler(struct da9052_eh_nb *eh_data, u32 event); +void da9052_tsi_data_ready_handler(struct da9052_eh_nb *eh_data, u32 event); + +#endif /* __LINUX_MFD_DA9052_TSI_H */ diff --git a/include/linux/mfd/da9052/tsi_calibrate.h b/include/linux/mfd/da9052/tsi_calibrate.h new file mode 100644 index 00000000000..a4b42ea079a --- /dev/null +++ b/include/linux/mfd/da9052/tsi_calibrate.h @@ -0,0 +1,47 @@ +/* + * da9052 TSI calibration module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_TSI_CALIBRATE_H +#define __LINUX_MFD_DA9052_TSI_CALIBRATE_H + +#include + +struct Calib_xform_matrix_t { + s32 An; + s32 Bn; + s32 Cn; + s32 Dn; + s32 En; + s32 Fn; + s32 Divider; +} ; + + +struct calib_cfg_t { + u8 calibrate_flag; +} ; + +ssize_t da9052_tsi_set_calib_matrix(struct da9052_tsi_data *displayPtr, + struct da9052_tsi_data *screenPtr); +u8 configure_tsi_calib(struct calib_cfg_t *tsi_calib); +struct calib_cfg_t *get_calib_config(void); +#endif /* __LINUX_MFD_DA9052_TSI_CALIBRATE_H */ + diff --git a/include/linux/mfd/da9052/tsi_cfg.h b/include/linux/mfd/da9052/tsi_cfg.h new file mode 100644 index 00000000000..21c091b1acc --- /dev/null +++ b/include/linux/mfd/da9052/tsi_cfg.h @@ -0,0 +1,132 @@ +/* + * da9052 TSI configuration module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_TSI_CFG_H +#define __LINUX_MFD_DA9052_TSI_CFG_H + +#define DA9052_TSI_DEBUG 0 + +#define AUTO_MODE 0 +#define IDLE 1 +#define DEFAULT_TSI_STATE AUTO_MODE + +#define TSI_SLOT_SKIP_VALUE 0 + +#define TSI_DELAY_VALUE 3 + +#define TSI_MODE_VALUE 0 + +#define ENABLE_AVERAGE_FILTER 1 + +#define DEFAULT_AVERAGE_FILTER_SIZE 3 + +#define ENABLE_WINDOW_FILTER 1 + +#define TSI_X_WINDOW_SIZE 50 +#define TSI_Y_WINDOW_SIZE 50 + +#define SAMPLE_CNT_FOR_WIN_REF 3 + +#define TSI_ECONOMY_MODE 0 +#define TSI_FAST_MODE 1 +#define DEFAULT_TSI_SAMPLING_MODE TSI_FAST_MODE + +#define TSI_USE_CALIBRATION 1 + +#define DA9052_TSI_CALIB_AN 1 +#define DA9052_TSI_CALIB_BN 0 +#define DA9052_TSI_CALIB_CN 0 +#define DA9052_TSI_CALIB_DN 0 +#define DA9052_TSI_CALIB_EN 1 +#define DA9052_TSI_CALIB_FN 0 +#define DA9052_TSI_CALIB_DIVIDER 1 + +#define TS_X_MIN (0) +#define TS_X_MAX (1023) +#define TS_Y_MIN (0) +#define TS_Y_MAX (1023) + +#define DISPLAY_X_MIN (0) +#define DISPLAY_X_MAX (1023) +#define DISPLAY_Y_MIN (0) +#define DISPLAY_Y_MAX (1023) + +#define ENABLE_TSI_DEBOUNCE 0 + +#define TSI_DEBOUNCE_DATA_CNT 3 + + +#define RELEASE +#define DA9052_TSI_RAW_DATA_PROFILING 0 +#define DA9052_TSI_WIN_FLT_DATA_PROFILING 0 +#define DA9052_TSI_AVG_FLT_DATA_PROFILING 0 +#define DA9052_TSI_CALIB_DATA_PROFILING 0 +#define DA9052_TSI_OS_DATA_PROFILING 1 +#define DA9052_TSI_PRINT_DEBOUNCED_DATA 0 +#define DA9052_TSI_PRINT_PREVIOUS_DATA 0 + + +#if ENABLE_AVERAGE_FILTER +#define TSI_AVERAGE_FILTER_SIZE DEFAULT_AVERAGE_FILTER_SIZE +#else +#define TSI_AVERAGE_FILTER_SIZE 1 +#endif + +#define TSI_FAST_MODE_SAMPLE_CNT 1000 +#define TSI_ECO_MODE_SAMPLE_CNT 100 + +#define TSI_POLL_SAMPLE_CNT 10 + +#define TSI_FAST_MODE_REG_DATA_PROCESSING_INTERVAL \ + ((1000 / TSI_FAST_MODE_SAMPLE_CNT) * TSI_POLL_SAMPLE_CNT) +#define TSI_ECO_MODE_REG_DATA_PROCESSING_INTERVAL \ + ((1000 / TSI_ECO_MODE_SAMPLE_CNT) * TSI_POLL_SAMPLE_CNT) + +#if DEFAULT_TSI_SAMPLING_MODE +#define DEFAULT_REG_DATA_PROCESSING_INTERVAL \ + TSI_FAST_MODE_REG_DATA_PROCESSING_INTERVAL +#else +#define DEFAULT_REG_DATA_PROCESSING_INTERVAL \ + TSI_ECO_MODE_REG_DATA_PROCESSING_INTERVAL +#endif + +#define TSI_REG_DATA_BUF_SIZE (2 * TSI_POLL_SAMPLE_CNT) + +#define TSI_FAST_MODE_RAW_DATA_PROCESSING_INTERVAL \ + ((1000 / TSI_FAST_MODE_SAMPLE_CNT) * (TSI_AVERAGE_FILTER_SIZE)) +#define TSI_ECO_MODE_RAW_DATA_PROCESSING_INTERVAL \ + ((1000 / TSI_ECO_MODE_SAMPLE_CNT) * (TSI_AVERAGE_FILTER_SIZE)) + + +#if DEFAULT_TSI_SAMPLING_MODE +#define DEFAULT_RAW_DATA_PROCESSING_INTERVAL \ + TSI_FAST_MODE_RAW_DATA_PROCESSING_INTERVAL +#else +#define DEFAULT_RAW_DATA_PROCESSING_INTERVAL \ + TSI_ECO_MODE_RAW_DATA_PROCESSING_INTERVAL +#endif + + +#define TSI_RAW_DATA_BUF_SIZE \ + (TSI_REG_DATA_BUF_SIZE * \ + ((TSI_AVERAGE_FILTER_SIZE / TSI_POLL_SAMPLE_CNT) + 1)) + +#endif /* __LINUX_MFD_DA9052_TSI_CFG_H */ diff --git a/include/linux/mfd/da9052/tsi_filter.h b/include/linux/mfd/da9052/tsi_filter.h new file mode 100644 index 00000000000..4bb7003cead --- /dev/null +++ b/include/linux/mfd/da9052/tsi_filter.h @@ -0,0 +1,58 @@ +/* + * da9052 TSI filter module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_TSI_FILTER_H +#define __LINUX_MFD_DA9052_TSI_FILTER_H + +#include +#include +#include + +struct da9052_tsi_data { + s16 x; + s16 y; + s16 z; +}; + +struct da9052_tsi_raw_fifo { + struct semaphore lock; + s32 head; + s32 tail; + struct da9052_tsi_data data[TSI_RAW_DATA_BUF_SIZE]; +}; + +struct tsi_thread_type { + u8 pid; + u8 state; + struct completion notifier; + struct task_struct *thread_task; +} ; + +/* State for TSI thread */ +#define ACTIVE 0 +#define INACTIVE 1 + + +extern u32 da9052_tsi_get_input_dev(u8 off); + +ssize_t da9052_tsi_get_calib_display_point(struct da9052_tsi_data *displayPtr); + +#endif /* __LINUX_MFD_DA9052_TSI_FILTER_H */ diff --git a/include/linux/mfd/da9052/wdt.h b/include/linux/mfd/da9052/wdt.h new file mode 100644 index 00000000000..6a77bfc5fd9 --- /dev/null +++ b/include/linux/mfd/da9052/wdt.h @@ -0,0 +1,83 @@ +/* + * da9052 SM (watchdog) module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_WDT_H +#define __LINUX_MFD_DA9052_WDT_H + +#include + +/* To enable debug output for your module, set this to 1 */ +#define DA9052_SM_DEBUG 0 + +/* Error codes */ +#define BUS_ERR 2 +#define INIT_FAIL 3 +#define SM_OPEN_FAIL 4 +#define NO_IOCTL_CMD 5 +#define INVALID_SCALING_VALUE 6 +#define STROBING_FILTER_ERROR 7 +#define TIMER_DELETE_ERR 8 +#define STROBING_MODE_ERROR 9 + +/* IOCTL Switch */ +/* For strobe watchdog function */ +#define DA9052_SM_IOCTL_STROBE_WDT 1 + +/* For setting watchdog timer time */ +#define DA9052_SM_IOCTL_SET_WDT 2 + +/* For enabling/disabling strobing filter */ +#define DA9052_SM_IOCTL_SET_STROBING_FILTER 3 + +/* For enabling/disabling strobing filter */ +#define DA9052_SM_IOCTL_SET_STROBING_MODE 4 + +/* Watchdog time scaling TWDMAX scaling macros */ +#define DA9052_WDT_DISABLE 0 +#define DA9052_SCALE_1X 1 +#define DA9052_SCALE_2X 2 +#define DA9052_SCALE_4X 3 +#define DA9052_SCALE_8X 4 +#define DA9052_SCALE_16X 5 +#define DA9052_SCALE_32X 6 +#define DA9052_SCALE_64X 7 + +#define DA9052_STROBE_WIN_FILTER_PER 80 +#define DA9052_X1_WINDOW ((1 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100) +#define DA9052_X2_WINDOW ((2 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100) +#define DA9052_X4_WINDOW ((4 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100) +#define DA9052_X8_WINDOW ((8 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100) +#define DA9052_X16_WINDOW ((16 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100) +#define DA9052_X32_WINDOW ((32 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100) +#define DA9052_X64_WINDOW ((64 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100) + +#define DA9052_STROBE_AUTO 1 +#define DA9052_STROBE_MANUAL 0 + +#define DA9052_SM_STROBE_CONF DISABLE + +#define DA9052_ADC_TWDMIN_TIME 500 + +void start_strobing(struct work_struct *work); +/* Create a handler for the scheduling start_strobing function */ +DECLARE_WORK(strobing_action, start_strobing); + +#endif /* __LINUX_MFD_DA9052_WDT_H */ -- cgit v1.2.3 From 988a9eadea2b9ff29aedca7c874ccd4f198c998c Mon Sep 17 00:00:00 2001 From: "Ying-Chun Liu (PaulLiu)" Date: Fri, 10 Jun 2011 10:51:39 +0800 Subject: PMIC: Add REGULATOR Driver for Dialog DA9052 Add DA9052 regulator driver from Dialog. Modify Kconfig/Makefile for DA9052 regulator driver. Signed-off-by: Zhou Jingyu Acked-by: Lily Zhang Signed-off-by: Ying-Chun Liu (PaulLiu) --- include/linux/regulator/da9052-regulator.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 include/linux/regulator/da9052-regulator.h (limited to 'include/linux') diff --git a/include/linux/regulator/da9052-regulator.h b/include/linux/regulator/da9052-regulator.h new file mode 100644 index 00000000000..d09b69cb542 --- /dev/null +++ b/include/linux/regulator/da9052-regulator.h @@ -0,0 +1,15 @@ +/* This file is there to support additional attributes in + sysfs - changestate and setvoltage +*/ +#ifndef _DA9052_REGULATOR_H +#define _DA9052_REGULATOR_H + +int da9052_ldo_buck_enable(struct regulator_dev *rdev); +int da9052_ldo_buck_disable(struct regulator_dev *rdev); + + +int da9052_ldo_buck_set_voltage(struct regulator_dev *rdev, + int min_uV, int max_uV); +int da9052_ldo_buck_get_voltage(struct regulator_dev *rdev); + +#endif -- cgit v1.2.3 From 749f585064d8e247d60d16df87ceceff47176ddc Mon Sep 17 00:00:00 2001 From: paulliu Date: Wed, 31 Aug 2011 13:57:32 +0800 Subject: PMIC: Add DA9053 Driver for LOCO board Add DA9053 init in LOCO. Modify Makefile for DA9053 driver. Signed-off-by: Ying-Chun Liu (PaulLiu) --- include/linux/fsl_devices.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/linux') diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index 3a45181b35e..b2c5d751088 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -97,6 +97,11 @@ struct fsl_usb2_platform_data { u32 pm_usbgenctrl; }; +struct mxc_pm_platform_data { + void (*suspend_enter) (void); + void (*suspend_exit) (void); +}; + /* Flags in fsl_usb2_mph_platform_data */ #define FSL_USB2_PORT0_ENABLED 0x00000001 #define FSL_USB2_PORT1_ENABLED 0x00000002 -- cgit v1.2.3 From dbb35b0f1a79a7e6085e05a85b8aabaf52413992 Mon Sep 17 00:00:00 2001 From: Jason Chen Date: Tue, 30 Aug 2011 10:19:58 +0800 Subject: fb: add PREMODE_CHANGE event support. add PREMODE_CHANGE event to handle driver presetting before fb_set_par. Signed-off-by: Jason Chen --- include/linux/fb.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/linux') diff --git a/include/linux/fb.h b/include/linux/fb.h index 1d6836c498d..a67fe1e2b02 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -549,6 +549,8 @@ struct fb_cursor_user { #define FB_EVENT_FB_UNBIND 0x0E /* CONSOLE-SPECIFIC: remap all consoles to new fb - for vga switcheroo */ #define FB_EVENT_REMAP_ALL_CONSOLE 0x0F +/* PRE MODE CHANGE added by fsl */ +#define FB_EVENT_PREMODE_CHANGE 0x10 struct fb_event { struct fb_info *info; -- cgit v1.2.3 From 1d7b5d6edebeb998535f868411fe055e6498c401 Mon Sep 17 00:00:00 2001 From: Jason Chen Date: Tue, 30 Aug 2011 16:00:52 +0800 Subject: ipuv3: add base driver for ipuv3 Base IPUv3 driver copied directly from linux-imx-2.6.38. Signed-off-by: Jason Chen --- include/linux/ipu.h | 248 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 248 insertions(+) create mode 100644 include/linux/ipu.h (limited to 'include/linux') diff --git a/include/linux/ipu.h b/include/linux/ipu.h new file mode 100644 index 00000000000..d6c1588b82c --- /dev/null +++ b/include/linux/ipu.h @@ -0,0 +1,248 @@ +/* + * Copyright 2005-2011 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @defgroup IPU MXC Image Processing Unit (IPU) Driver + */ +/*! + * @file arch-mxc/ipu.h + * + * @brief This file contains the IPU driver API declarations. + * + * @ingroup IPU + */ + +#ifndef __ASM_ARCH_IPU_H__ +#define __ASM_ARCH_IPU_H__ + +#include +#include +#ifdef __KERNEL__ +#include +#else +#ifndef __cplusplus +typedef unsigned char bool; +#endif +#define irqreturn_t int +#define dma_addr_t int +#define uint32_t unsigned int +#define uint16_t unsigned short +#define uint8_t unsigned char +#define u32 unsigned int +#define u8 unsigned char +#define __u32 u32 +#endif + +/*! + * Enumeration of IPU rotation modes + */ +typedef enum { + /* Note the enum values correspond to BAM value */ + IPU_ROTATE_NONE = 0, + IPU_ROTATE_VERT_FLIP = 1, + IPU_ROTATE_HORIZ_FLIP = 2, + IPU_ROTATE_180 = 3, + IPU_ROTATE_90_RIGHT = 4, + IPU_ROTATE_90_RIGHT_VFLIP = 5, + IPU_ROTATE_90_RIGHT_HFLIP = 6, + IPU_ROTATE_90_LEFT = 7, +} ipu_rotate_mode_t; + +/*! + * Enumeration of VDI MOTION select + */ +typedef enum { + MED_MOTION = 0, + LOW_MOTION = 1, + HIGH_MOTION = 2, +} ipu_motion_sel; + +/*! + * Enumeration of DI ports for ADC. + */ +typedef enum { + DISP0, + DISP1, + DISP2, + DISP3 +} display_port_t; + +/* IPU Pixel format definitions */ +/* Four-character-code (FOURCC) */ +#define fourcc(a, b, c, d)\ + (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24)) + +/*! + * @name IPU Pixel Formats + * + * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are + * the same used by V4L2 API. + */ + +/*! @{ */ +/*! @name Generic or Raw Data Formats */ +/*! @{ */ +#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0') /*!< IPU Generic Data */ +#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1') /*!< IPU Generic Data */ +#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6') /*!< IPU Generic Data */ +#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8') /*!< IPU Generic Data */ +/*! @} */ +/*! @name RGB Formats */ +/*! @{ */ +#define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*!< 8 RGB-3-3-2 */ +#define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*!< 16 RGB-5-5-5 */ +#define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*!< 1 6 RGB-5-6-5 */ +#define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*!< 18 RGB-6-6-6 */ +#define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*!< 18 BGR-6-6-6 */ +#define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*!< 24 BGR-8-8-8 */ +#define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*!< 24 RGB-8-8-8 */ +#define IPU_PIX_FMT_GBR24 fourcc('G', 'B', 'R', '3') /*!< 24 GBR-8-8-8 */ +#define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*!< 32 BGR-8-8-8-8 */ +#define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*!< 32 BGR-8-8-8-8 */ +#define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*!< 32 RGB-8-8-8-8 */ +#define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*!< 32 RGB-8-8-8-8 */ +#define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*!< 32 ABGR-8-8-8-8 */ +/*! @} */ +/*! @name YUV Interleaved Formats */ +/*! @{ */ +#define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*!< 16 YUV 4:2:2 */ +#define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*!< 16 YUV 4:2:2 */ +#define IPU_PIX_FMT_YVYU fourcc('Y', 'V', 'Y', 'U') /*!< 16 YVYU 4:2:2 */ +#define IPU_PIX_FMT_VYUY fourcc('V', 'Y', 'U', 'Y') /*!< 16 VYYU 4:2:2 */ +#define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*!< 12 YUV 4:1:1 */ +#define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*!< 24 YUV 4:4:4 */ +#define IPU_PIX_FMT_VYU444 fourcc('V', '4', '4', '4') /*!< 24 VYU 4:4:4 */ +/* two planes -- one Y, one Cb + Cr interleaved */ +#define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ +/*! @} */ +/*! @name YUV Planar Formats */ +/*! @{ */ +#define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*!< 8 Greyscale */ +#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*!< 9 YVU 4:1:0 */ +#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*!< 9 YUV 4:1:0 */ +#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*!< 12 YVU 4:2:0 */ +#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*!< 12 YUV 4:2:0 */ +#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*!< 12 YUV 4:2:0 */ +#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*!< 16 YVU 4:2:2 */ +#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*!< 16 YUV 4:2:2 */ +/*! @} */ + +/* IPU device */ +struct ipu_pos { + u32 x; + u32 y; +}; + +struct ipu_crop { + struct ipu_pos pos; + u32 w; + u32 h; +}; + +struct ipu_deinterlace { + bool enable; + u8 motion; /*see ipu_motion_sel*/ +#define IPU_DEINTERLACE_FIELD_TOP 0 +#define IPU_DEINTERLACE_FIELD_BOTTOM 1 + u8 field_fmt; +}; + +struct ipu_input { + u32 width; + u32 height; + u32 format; + struct ipu_crop crop; + dma_addr_t paddr; + + struct ipu_deinterlace deinterlace; + dma_addr_t paddr_n; /*valid when deinterlace enable*/ +}; + +struct ipu_alpha { +#define IPU_ALPHA_MODE_GLOBAL 0 +#define IPU_ALPHA_MODE_LOCAL 1 + u8 mode; + u8 gvalue; /* 0~255 */ + dma_addr_t loc_alp_paddr; +}; + +struct ipu_colorkey { + bool enable; + u32 value; /* RGB 24bit */ +}; + +struct ipu_overlay { + u32 width; + u32 height; + u32 format; + struct ipu_crop crop; + struct ipu_alpha alpha; + struct ipu_colorkey colorkey; + dma_addr_t paddr; +}; + +struct ipu_output { + u32 width; + u32 height; + u32 format; + u8 rotate; + struct ipu_crop crop; + dma_addr_t paddr; +}; + +struct ipu_task { + struct ipu_input input; + struct ipu_output output; + + bool overlay_en; + struct ipu_overlay overlay; + +#define IPU_TASK_PRIORITY_NORMAL 0 +#define IPU_TASK_PRIORITY_HIGH 1 + u8 priority; + +#define IPU_TASK_ID_ANY 0 +#define IPU_TASK_ID_VF 1 +#define IPU_TASK_ID_PP 2 +#define IPU_TASK_ID_MAX 3 + u8 task_id; + + int timeout; +}; + +enum { + IPU_CHECK_OK = 0, + IPU_CHECK_WARN_INPUT_OFFS_NOT8ALIGN = 0x1, + IPU_CHECK_WARN_OUTPUT_OFFS_NOT8ALIGN = 0x2, + IPU_CHECK_WARN_OVERLAY_OFFS_NOT8ALIGN = 0x4, + IPU_CHECK_ERR_MIN, + IPU_CHECK_ERR_INPUT_CROP, + IPU_CHECK_ERR_OUTPUT_CROP, + IPU_CHECK_ERR_OVERLAY_CROP, + IPU_CHECK_ERR_INPUT_OVER_LIMIT, + IPU_CHECK_ERR_OV_OUT_NO_FIT, + IPU_CHECK_ERR_OVERLAY_WITH_VDI, + IPU_CHECK_ERR_PROC_NO_NEED, + IPU_CHECK_ERR_SPLIT_INPUTW_OVER, + IPU_CHECK_ERR_SPLIT_INPUTH_OVER, + IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER, + IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER, +}; + +/* IOCTL commands */ +#define IPU_CHECK_TASK _IOWR('I', 0x1, struct ipu_task) +#define IPU_QUEUE_TASK _IOW('I', 0x2, struct ipu_task) +#define IPU_ALLOC _IOWR('I', 0x3, int) +#define IPU_FREE _IOW('I', 0x4, int) + +#endif -- cgit v1.2.3 From 6a08b9cedad608b0f474701d6b7bca1e0ede35b1 Mon Sep 17 00:00:00 2001 From: Jason Chen Date: Tue, 30 Aug 2011 16:02:26 +0800 Subject: ipuv3: add framebuffer driver Base framebuffer driver directly copied from linux-imx-2.6.38 Signed-off-by: Jason Chen --- include/linux/mxcfb.h | 161 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 161 insertions(+) create mode 100644 include/linux/mxcfb.h (limited to 'include/linux') diff --git a/include/linux/mxcfb.h b/include/linux/mxcfb.h new file mode 100644 index 00000000000..817bda95c35 --- /dev/null +++ b/include/linux/mxcfb.h @@ -0,0 +1,161 @@ +/* + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/* + * @file arch-mxc/ mxcfb.h + * + * @brief Global header file for the MXC Frame buffer + * + * @ingroup Framebuffer + */ +#ifndef __ASM_ARCH_MXCFB_H__ +#define __ASM_ARCH_MXCFB_H__ + +#include + +#define FB_SYNC_OE_LOW_ACT 0x80000000 +#define FB_SYNC_CLK_LAT_FALL 0x40000000 +#define FB_SYNC_DATA_INVERT 0x20000000 +#define FB_SYNC_CLK_IDLE_EN 0x10000000 +#define FB_SYNC_SHARP_MODE 0x08000000 +#define FB_SYNC_SWAP_RGB 0x04000000 +#define FB_ACCEL_TRIPLE_FLAG 0x00000000 +#define FB_ACCEL_DOUBLE_FLAG 0x00000001 + +struct mxcfb_gbl_alpha { + int enable; + int alpha; +}; + +struct mxcfb_loc_alpha { + int enable; + int alpha_in_pixel; + unsigned long alpha_phy_addr0; + unsigned long alpha_phy_addr1; +}; + +struct mxcfb_color_key { + int enable; + __u32 color_key; +}; + +struct mxcfb_pos { + __u16 x; + __u16 y; +}; + +struct mxcfb_gamma { + int enable; + int constk[16]; + int slopek[16]; +}; + +struct mxcfb_rect { + __u32 top; + __u32 left; + __u32 width; + __u32 height; +}; + +#define GRAYSCALE_8BIT 0x1 +#define GRAYSCALE_8BIT_INVERTED 0x2 + +#define AUTO_UPDATE_MODE_REGION_MODE 0 +#define AUTO_UPDATE_MODE_AUTOMATIC_MODE 1 + +#define UPDATE_SCHEME_SNAPSHOT 0 +#define UPDATE_SCHEME_QUEUE 1 +#define UPDATE_SCHEME_QUEUE_AND_MERGE 2 + +#define UPDATE_MODE_PARTIAL 0x0 +#define UPDATE_MODE_FULL 0x1 + +#define WAVEFORM_MODE_AUTO 257 + +#define TEMP_USE_AMBIENT 0x1000 + +#define EPDC_FLAG_ENABLE_INVERSION 0x01 +#define EPDC_FLAG_FORCE_MONOCHROME 0x02 +#define EPDC_FLAG_USE_ALT_BUFFER 0x100 + +#define FB_POWERDOWN_DISABLE -1 + +struct mxcfb_alt_buffer_data { + __u32 phys_addr; + __u32 width; /* width of entire buffer */ + __u32 height; /* height of entire buffer */ + struct mxcfb_rect alt_update_region; /* region within buffer to update */ +}; + +struct mxcfb_update_data { + struct mxcfb_rect update_region; + __u32 waveform_mode; + __u32 update_mode; + __u32 update_marker; + int temp; + uint flags; + struct mxcfb_alt_buffer_data alt_buffer_data; +}; + +/* + * Structure used to define waveform modes for driver + * Needed for driver to perform auto-waveform selection + */ +struct mxcfb_waveform_modes { + int mode_init; + int mode_du; + int mode_gc4; + int mode_gc8; + int mode_gc16; + int mode_gc32; +}; + +#define MXCFB_WAIT_FOR_VSYNC _IOW('F', 0x20, u_int32_t) +#define MXCFB_SET_GBL_ALPHA _IOW('F', 0x21, struct mxcfb_gbl_alpha) +#define MXCFB_SET_CLR_KEY _IOW('F', 0x22, struct mxcfb_color_key) +#define MXCFB_SET_OVERLAY_POS _IOWR('F', 0x24, struct mxcfb_pos) +#define MXCFB_GET_FB_IPU_CHAN _IOR('F', 0x25, u_int32_t) +#define MXCFB_SET_LOC_ALPHA _IOWR('F', 0x26, struct mxcfb_loc_alpha) +#define MXCFB_SET_LOC_ALP_BUF _IOW('F', 0x27, unsigned long) +#define MXCFB_SET_GAMMA _IOW('F', 0x28, struct mxcfb_gamma) +#define MXCFB_GET_FB_IPU_DI _IOR('F', 0x29, u_int32_t) +#define MXCFB_GET_DIFMT _IOR('F', 0x2A, u_int32_t) +#define MXCFB_GET_FB_BLANK _IOR('F', 0x2B, u_int32_t) +#define MXCFB_SET_DIFMT _IOW('F', 0x2C, u_int32_t) + +/* IOCTLs for E-ink panel updates */ +#define MXCFB_SET_WAVEFORM_MODES _IOW('F', 0x2B, struct mxcfb_waveform_modes) +#define MXCFB_SET_TEMPERATURE _IOW('F', 0x2C, int32_t) +#define MXCFB_SET_AUTO_UPDATE_MODE _IOW('F', 0x2D, __u32) +#define MXCFB_SEND_UPDATE _IOW('F', 0x2E, struct mxcfb_update_data) +#define MXCFB_WAIT_FOR_UPDATE_COMPLETE _IOW('F', 0x2F, __u32) +#define MXCFB_SET_PWRDOWN_DELAY _IOW('F', 0x30, int32_t) +#define MXCFB_GET_PWRDOWN_DELAY _IOR('F', 0x31, int32_t) +#define MXCFB_SET_UPDATE_SCHEME _IOW('F', 0x32, __u32) + +#ifdef __KERNEL__ + +extern struct fb_videomode mxcfb_modedb[]; +extern int mxcfb_modedb_sz; + +enum { + MXCFB_REFRESH_OFF, + MXCFB_REFRESH_AUTO, + MXCFB_REFRESH_PARTIAL, +}; + +int mxcfb_set_refresh_mode(struct fb_info *fbi, int mode, + struct mxcfb_rect *update_region); +int mxc_elcdif_frame_addr_setup(dma_addr_t phys); +#endif /* __KERNEL__ */ +#endif -- cgit v1.2.3 From ab84d148b863c3fe248073500e82a7f0e4b1617d Mon Sep 17 00:00:00 2001 From: Jason Chen Date: Tue, 30 Aug 2011 10:44:26 +0800 Subject: ipuv3: add tve.c driver for TVOUT and VGA output Signed-off-by: Jason Chen --- include/linux/fsl_devices.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/linux') diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index b2c5d751088..fd5f2b37b18 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -159,4 +159,9 @@ int fsl_deep_sleep(void); static inline int fsl_deep_sleep(void) { return 0; } #endif +struct fsl_mxc_tve_platform_data { + char *dac_reg; + char *dig_reg; +}; + #endif /* _FSL_DEVICE_H_ */ -- cgit v1.2.3 From ffb706d38d523a9cca51c116ed106f941e576d0a Mon Sep 17 00:00:00 2001 From: Jason Chen Date: Tue, 30 Aug 2011 10:50:24 +0800 Subject: ipuv3: add driver for sii902x HDMI transceiver Signed-off-by: Jason Chen --- include/linux/fsl_devices.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include/linux') diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index fd5f2b37b18..7d5ee84d34b 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -164,4 +164,18 @@ struct fsl_mxc_tve_platform_data { char *dig_reg; }; +struct fsl_mxc_lcd_platform_data { + char *io_reg; + char *core_reg; + char *analog_reg; + void (*reset) (void); + int (*get_pins) (void); + void (*put_pins) (void); + void (*enable_pins) (void); + void (*disable_pins) (void); + int default_ifmt; + int ipu_id; + int disp_id; +}; + #endif /* _FSL_DEVICE_H_ */ -- cgit v1.2.3 From cd51ee6261306a5876f00bdae196d9c4229d6ba3 Mon Sep 17 00:00:00 2001 From: Jason Chen Date: Tue, 30 Aug 2011 11:46:09 +0800 Subject: ipuv3: add driver for LDB - LVDS Display Bridge Signed-off-by: Jason Chen --- include/linux/fsl_devices.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'include/linux') diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index 7d5ee84d34b..d0e4c9a0b68 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -178,4 +178,24 @@ struct fsl_mxc_lcd_platform_data { int disp_id; }; +struct fsl_mxc_ldb_platform_data { + char *lvds_bg_reg; + u32 ext_ref; +#define LDB_SPL_DI0 1 +#define LDB_SPL_DI1 2 +#define LDB_DUL_DI0 3 +#define LDB_DUL_DI1 4 +#define LDB_SIN0 5 +#define LDB_SIN1 6 +#define LDB_SEP0 7 +#define LDB_SEP1 8 + int mode; + int ipu_id; + int disp_id; + + /*only work for separate mode*/ + int sec_ipu_id; + int sec_disp_id; +}; + #endif /* _FSL_DEVICE_H_ */ -- cgit v1.2.3 From 7188f1c235426992e6bad8100d27c289fce35c6d Mon Sep 17 00:00:00 2001 From: Jason Chen Date: Tue, 30 Aug 2011 17:37:52 +0800 Subject: v4l2: add v4l2 output support for mxc Signed-off-by: Jason Chen --- include/linux/mxc_v4l2.h | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 include/linux/mxc_v4l2.h (limited to 'include/linux') diff --git a/include/linux/mxc_v4l2.h b/include/linux/mxc_v4l2.h new file mode 100644 index 00000000000..e83e5923c2a --- /dev/null +++ b/include/linux/mxc_v4l2.h @@ -0,0 +1,48 @@ +/* + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @file arch-mxc/mxc_v4l2.h + * + * @brief mxc V4L2 private structures + * + * @ingroup MXC_V4L2_CAPTURE + */ + +#ifndef __ASM_ARCH_MXC_V4L2_H__ +#define __ASM_ARCH_MXC_V4L2_H__ + +/* + * For IPUv1 and IPUv3, V4L2_CID_MXC_ROT means encoder ioctl ID. + * And V4L2_CID_MXC_VF_ROT is viewfinder ioctl ID only for IPUv1 and IPUv3. + */ +#define V4L2_CID_MXC_ROT (V4L2_CID_PRIVATE_BASE + 0) +#define V4L2_CID_MXC_FLASH (V4L2_CID_PRIVATE_BASE + 1) +#define V4L2_CID_MXC_VF_ROT (V4L2_CID_PRIVATE_BASE + 2) +#define V4L2_CID_MXC_MOTION (V4L2_CID_PRIVATE_BASE + 3) + +#define V4L2_MXC_ROTATE_NONE 0 +#define V4L2_MXC_ROTATE_VERT_FLIP 1 +#define V4L2_MXC_ROTATE_HORIZ_FLIP 2 +#define V4L2_MXC_ROTATE_180 3 +#define V4L2_MXC_ROTATE_90_RIGHT 4 +#define V4L2_MXC_ROTATE_90_RIGHT_VFLIP 5 +#define V4L2_MXC_ROTATE_90_RIGHT_HFLIP 6 +#define V4L2_MXC_ROTATE_90_LEFT 7 + +struct v4l2_mxc_offset { + uint32_t u_offset; + uint32_t v_offset; +}; + +#endif -- cgit v1.2.3 From e2f98f6aef37cf4bffab75f998123bba2197a651 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Sun, 28 Aug 2011 18:34:45 +0800 Subject: usb: add usb_common.c for common code Copied directly from linux-linaro-2.6.38, commit b313cadcc: ENGR00141217-3 MX53 MSL part upgrade to 2.6.38 Signed-off-by: Richard Zhao Signed-off-by: Frank Li Signed-off-by: Jason Chen Signed-off-by: Zeng Zhaoming Signed-off-by: Richard Zhu Signed-off-by: Zhou Jingyu Signed-off-by: Zhang Yan Signed-off-by: Eric Miao --- include/linux/fsl_devices.h | 94 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/usb/fsl_xcvr.h | 58 +++++++++++++++++++++++++++ 2 files changed, 152 insertions(+) create mode 100644 include/linux/usb/fsl_xcvr.h (limited to 'include/linux') diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index d0e4c9a0b68..058b39ec290 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -50,6 +50,15 @@ enum fsl_usb2_operating_modes { FSL_USB2_DR_OTG, }; +/* this used for usb port type */ +enum fsl_usb2_modes { + FSL_USB_DR_HOST, + FSL_USB_DR_DEVICE, + FSL_USB_MPH_HOST1, + FSL_USB_MPH_HOST2, + FSL_USB_UNKNOWN, /* unkonwn status */ +}; + enum fsl_usb2_phy_modes { FSL_USB2_PHY_NONE, FSL_USB2_PHY_ULPI, @@ -61,6 +70,90 @@ enum fsl_usb2_phy_modes { struct clk; struct platform_device; +#ifdef CONFIG_USB_EHCI_ARC +#include +#include +#include + +struct fsl_usb2_wakeup_platform_data; + +struct fsl_usb2_platform_data { + /* board specific information */ + enum fsl_usb2_operating_modes operating_mode; + enum fsl_usb2_phy_modes phy_mode; + unsigned int port_enables; + unsigned int workaround; + + int (*init)(struct platform_device *); + void (*exit)(struct platform_device *); + void __iomem *regs; /* ioremap'd register base */ + struct clk *clk; + unsigned big_endian_mmio:1; + unsigned big_endian_desc:1; + unsigned es:1; /* need USBMODE:ES */ + unsigned le_setup_buf:1; + unsigned have_sysif_regs:1; + unsigned invert_drvvbus:1; + unsigned invert_pwr_fault:1; + + /* Freescale private */ + char *name; + u32 phy_regs; /* usb phy register base */ + u32 xcvr_type; /* PORTSC_PTS_* */ + char *transceiver; /* transceiver name */ + unsigned power_budget; /* for hcd->power_budget */ + u32 id_gpio; + + struct fsl_xcvr_ops *xcvr_ops; + struct fsl_xcvr_power *xcvr_pwr; + int (*gpio_usb_active) (void); + void (*gpio_usb_inactive) (void); + void (*usb_clock_for_pm) (bool); + void (*platform_suspend)(struct fsl_usb2_platform_data *); + void (*platform_resume)(struct fsl_usb2_platform_data *); + void (*wake_up_enable)(struct fsl_usb2_platform_data *, bool); + void (*phy_lowpower_suspend)(struct fsl_usb2_platform_data *, bool); + void (*platform_driver_vbus)(bool on); /* for vbus shutdown/open */ + enum usb_wakeup_event (*is_wakeup_event)(struct fsl_usb2_platform_data *); + void (*wakeup_handler)(struct fsl_usb2_platform_data *); + + struct fsl_usb2_wakeup_platform_data *wakeup_pdata; + struct platform_device *pdev; + unsigned change_ahb_burst:1; + unsigned ahb_burst_mode:3; + unsigned lowpower:1; + unsigned irq_delay:1; + unsigned wakeup_event:1; + u32 pmflags; /* PM from otg or system */ + + /* register save area for suspend/resume */ + u32 pm_command; + u32 pm_status; + u32 pm_intr_enable; + u32 pm_frame_index; + u32 pm_segment; + u32 pm_frame_list; + u32 pm_async_next; + u32 pm_configured_flag; + u32 pm_portsc; +}; + +struct fsl_usb2_wakeup_platform_data { + char *name; + void (*usb_clock_for_pm) (bool); + void (*usb_wakeup_exhandle) (void); + struct fsl_usb2_platform_data *usb_pdata[3]; + /* This waitqueue is used to wait "usb_wakeup thread" to finish + * during system resume routine. "usb_wakeup theard" should be finished + * prior to usb resume routine. + */ + wait_queue_head_t wq; + /* This flag is used to indicate the "usb_wakeup thread" is finished during + * usb wakeup routine. + */ + bool usb_wakeup_is_pending; +}; +#else struct fsl_usb2_platform_data { /* board specific information */ enum fsl_usb2_operating_modes operating_mode; @@ -96,6 +189,7 @@ struct fsl_usb2_platform_data { u32 pm_portsc; u32 pm_usbgenctrl; }; +#endif struct mxc_pm_platform_data { void (*suspend_enter) (void); diff --git a/include/linux/usb/fsl_xcvr.h b/include/linux/usb/fsl_xcvr.h new file mode 100644 index 00000000000..4c57e03ef2d --- /dev/null +++ b/include/linux/usb/fsl_xcvr.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ +#ifndef __LINUX_USB_FSL_XCVR_H +#define __LINUX_USB_FSL_XCVR_H +#include +#include + +struct fsl_usb2_platform_data; + +enum usb_test_mode{ + USB_TEST_J = 1, + USB_TEST_K = 2, +}; + +/** + * @name: transceiver name + * @xcvr_type: one of PORTSC_PTS_{UTMI,SERIAL,ULPI} + * @init: transceiver- and board-specific initialization function + * @uninit: transceiver- and board-specific uninitialization function + * @set_host: + * @set_device: + * @pullup: enable or disable D+ pullup + * + */ +struct fsl_xcvr_ops { + char *name; + u32 xcvr_type; + + void (*init)(struct fsl_xcvr_ops *ops); + void (*uninit)(struct fsl_xcvr_ops *ops); + void (*suspend)(struct fsl_xcvr_ops *ops); + void (*set_host)(void); + void (*set_device)(void); + void (*set_vbus_power)(struct fsl_xcvr_ops *ops, + struct fsl_usb2_platform_data *pdata, int on); + void (*set_vbus_draw)(struct fsl_xcvr_ops *ops, + struct fsl_usb2_platform_data *pdata, unsigned mA); + void (*set_remote_wakeup)(u32 *view); + void (*pullup)(int on); + void(*set_test_mode)(u32 *view, enum usb_test_mode mode); +}; + +struct fsl_xcvr_power { + struct platform_device *usb_pdev; + struct regulator *regu1; + struct regulator *regu2; +}; +#endif -- cgit v1.2.3 From eafa475d18391f7930a46e0e0c7ccf35c3949c2f Mon Sep 17 00:00:00 2001 From: Haitao Zhang Date: Wed, 31 Aug 2011 16:36:40 +0800 Subject: mx53_loco: enabled USB Host1 forward ported code from 2.6.38 Signed-off-by: Haitao Zhang Signed-off-by: Eric Miao --- include/linux/fsl_devices.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include/linux') diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index 058b39ec290..4386d3c0f97 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -67,6 +67,13 @@ enum fsl_usb2_phy_modes { FSL_USB2_PHY_SERIAL, }; +enum usb_wakeup_event { + WAKEUP_EVENT_INVALID, + WAKEUP_EVENT_VBUS, + WAKEUP_EVENT_ID, + WAKEUP_EVENT_DPDM, /* for remote wakeup */ +}; + struct clk; struct platform_device; -- cgit v1.2.3 From aa324ee73d8b137df1bd210af168e58cefebeeb3 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Thu, 8 Sep 2011 17:24:01 -0700 Subject: sound: add imx-sgtl5000 Signed-off-by: Richard Zhu Signed-off-by: Eric Miao --- include/linux/fsl_devices.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'include/linux') diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index 4386d3c0f97..f82c91f8319 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -250,6 +250,32 @@ struct mpc8xx_pcmcia_ops { int(*voltage_set)(int slot, int vcc, int vpp); }; +/* + * This struct is to define the number of SSIs on a platform, + * DAM source port config, DAM external port config, + * regulator names, and other stuff audio needs. + */ +struct mxc_audio_platform_data { + int ssi_num; + int src_port; + int ext_port; + + int intr_id_hp; + int ext_ram; + struct clk *ssi_clk[2]; + + int hp_gpio; + int hp_active_low; /* headphone irq is active loaw */ + + int sysclk; + + int (*init) (void); /* board specific init */ + int (*amp_enable) (int enable); + int (*clock_enable) (int enable); + int (*finit) (void); /* board specific finit */ + void *priv; /* used by board specific functions */ +}; + /* Returns non-zero if the current suspend operation would * lead to a deep sleep (i.e. power removed from the core, * instead of just the clock). -- cgit v1.2.3 From 1c6a16b3afe1106542026b957de8332cb67bb1e7 Mon Sep 17 00:00:00 2001 From: Alan Tull Date: Tue, 7 Jun 2011 12:59:03 -0500 Subject: SAUCE: ENGR00139461-2 mxc alsa soc spdif driver BugLink: http://bugs.launchpad.net/bugs/837155 S/PDIF tx and rx using ASoC layer. Signed-off-by: Alan Tull Signed-off-by: Eric Miao --- include/linux/fsl_devices.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include/linux') diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index f82c91f8319..cb624eaff19 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -276,6 +276,17 @@ struct mxc_audio_platform_data { void *priv; /* used by board specific functions */ }; +struct mxc_spdif_platform_data { + int spdif_tx; /* S/PDIF tx enabled for this board */ + int spdif_rx; /* S/PDIF rx enabled for this board */ + int spdif_clk_44100; /* tx clk mux in SPDIF_REG_STC; -1 for none */ + int spdif_clk_48000; /* tx clk mux in SPDIF_REG_STC; -1 for none */ + int spdif_clkid; /* rx clk mux select in SPDIF_REG_SRPC */ + struct clk *spdif_clk; + struct clk *spdif_core_clk; + struct clk *spdif_audio_clk; +}; + /* Returns non-zero if the current suspend operation would * lead to a deep sleep (i.e. power removed from the core, * instead of just the clock). -- cgit v1.2.3 From ff04834455778b3971f814b47c074dbd680e1010 Mon Sep 17 00:00:00 2001 From: Jason Chen Date: Wed, 14 Sep 2011 14:41:27 +0800 Subject: ipu3: Backport to freescale commit commit ad19aef4a80094221b1b826185aea924627e8642 ENGR00155140 ipuv3: add support of power suspend/resume add support of power suspend/resume. because IPU has issue of restore current buffer register, this code only work for single buffer mode. Signed-off-by: Jason Chen --- include/linux/ipu.h | 948 +++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 938 insertions(+), 10 deletions(-) (limited to 'include/linux') diff --git a/include/linux/ipu.h b/include/linux/ipu.h index d6c1588b82c..06d8c64a6d6 100644 --- a/include/linux/ipu.h +++ b/include/linux/ipu.h @@ -58,6 +58,25 @@ typedef enum { IPU_ROTATE_90_LEFT = 7, } ipu_rotate_mode_t; +/*! + * Enumeration of Post Filter modes + */ +typedef enum { + PF_DISABLE_ALL = 0, + PF_MPEG4_DEBLOCK = 1, + PF_MPEG4_DERING = 2, + PF_MPEG4_DEBLOCK_DERING = 3, + PF_H264_DEBLOCK = 4, +} pf_operation_t; + +/*! + * Enumeration of Synchronous (Memory-less) panel types + */ +typedef enum { + IPU_PANEL_SHARP_TFT, + IPU_PANEL_TFT, +} ipu_panel_t; + /*! * Enumeration of VDI MOTION select */ @@ -67,16 +86,6 @@ typedef enum { HIGH_MOTION = 2, } ipu_motion_sel; -/*! - * Enumeration of DI ports for ADC. - */ -typedef enum { - DISP0, - DISP1, - DISP2, - DISP3 -} display_port_t; - /* IPU Pixel format definitions */ /* Four-character-code (FOURCC) */ #define fourcc(a, b, c, d)\ @@ -137,6 +146,925 @@ typedef enum { #define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*!< 16 YUV 4:2:2 */ /*! @} */ +/* IPU Driver channels definitions. */ +/* Note these are different from IDMA channels */ +#ifdef CONFIG_MXC_IPU_V1 +#define _MAKE_CHAN(num, in, out, sec) ((num << 24) | (sec << 16) | (out << 8) | in) +#define IPU_CHAN_ID(ch) (ch >> 24) +#define IPU_CHAN_SEC_DMA(ch) ((uint32_t) (ch >> 16) & 0xFF) +#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch >> 8) & 0xFF) +#define IPU_CHAN_IN_DMA(ch) ((uint32_t) (ch & 0xFF)) + +#else +#define IPU_MAX_CH 32 +#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \ + ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out) +#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24)) +#define IPU_CHAN_ID(ch) (ch >> 24) +#define IPU_CHAN_ALT(ch) (ch & 0x02000000) +#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F) +#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F) +#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F) +#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F)) +#define NO_DMA 0x3F +#define ALT 1 +#endif +/*! + * Enumeration of IPU logical channels. An IPU logical channel is defined as a + * combination of an input (memory to IPU), output (IPU to memory), and/or + * secondary input IDMA channels and in some cases an Image Converter task. + * Some channels consist of only an input or output. + */ +typedef enum { + CHAN_NONE = -1, +#ifdef CONFIG_MXC_IPU_V1 + CSI_MEM = _MAKE_CHAN(1, 0xFF, 7, 0xFF), /*!< CSI raw sensor data to memory */ + + CSI_PRP_ENC_MEM = _MAKE_CHAN(2, 0xFF, 0, 0xFF), /*!< CSI to IC Encoder PreProcessing to Memory */ + MEM_PRP_ENC_MEM = _MAKE_CHAN(3, 6, 0, 0xFF), /*!< Memory to IC Encoder PreProcessing to Memory */ + MEM_ROT_ENC_MEM = _MAKE_CHAN(4, 10, 8, 0xFF), /*!< Memory to IC Encoder Rotation to Memory */ + + CSI_PRP_VF_MEM = _MAKE_CHAN(5, 0xFF, 1, 0xFF), /*!< CSI to IC Viewfinder PreProcessing to Memory */ + CSI_PRP_VF_ADC = _MAKE_CHAN(6, 0xFF, 1, 0xFF), /*!< CSI to IC Viewfinder PreProcessing to ADC */ + MEM_PRP_VF_MEM = _MAKE_CHAN(7, 6, 1, 3), /*!< Memory to IC Viewfinder PreProcessing to Memory */ + MEM_PRP_VF_ADC = _MAKE_CHAN(8, 6, 1, 3), /*!< Memory to IC Viewfinder PreProcessing to ADC */ + MEM_ROT_VF_MEM = _MAKE_CHAN(9, 11, 9, 0xFF), /*!< Memory to IC Viewfinder Rotation to Memory */ + + MEM_PP_MEM = _MAKE_CHAN(10, 5, 2, 4), /*!< Memory to IC PostProcessing to Memory */ + MEM_ROT_PP_MEM = _MAKE_CHAN(11, 13, 12, 0xFF), /*!< Memory to IC PostProcessing Rotation to Memory */ + MEM_PP_ADC = _MAKE_CHAN(12, 5, 2, 4), /*!< Memory to IC PostProcessing to ADC */ + + MEM_SDC_BG = _MAKE_CHAN(14, 14, 0xFF, 0xFF), /*!< Memory to SDC Background plane */ + MEM_SDC_FG = _MAKE_CHAN(15, 15, 0xFF, 0xFF), /*!< Memory to SDC Foreground plane */ + MEM_SDC_MASK = _MAKE_CHAN(16, 16, 0xFF, 0xFF), /*!< Memory to SDC Mask */ + + MEM_BG_SYNC = MEM_SDC_BG, + MEM_FG_SYNC = MEM_SDC_FG, + + ADC_SYS1 = _MAKE_CHAN(17, 18, 22, 20), /*!< Memory to ADC System Channel 1 */ + ADC_SYS2 = _MAKE_CHAN(18, 19, 23, 21), /*!< Memory to ADC System Channel 2 */ + + MEM_PF_Y_MEM = _MAKE_CHAN(19, 26, 29, 24), /*!< Y and PF Memory to Post-filter to Y Memory */ + MEM_PF_U_MEM = _MAKE_CHAN(20, 27, 30, 25), /*!< U and PF Memory to Post-filter to U Memory */ + MEM_PF_V_MEM = _MAKE_CHAN(21, 28, 31, 0xFF), /*!< V Memory to Post-filter to V Memory */ + + MEM_DC_SYNC = CHAN_NONE, + DIRECT_ASYNC0 = CHAN_NONE, + DIRECT_ASYNC1 = CHAN_NONE, + MEM_VDI_PRP_VF_MEM_P = CHAN_NONE, + MEM_VDI_PRP_VF_MEM = CHAN_NONE, + MEM_VDI_PRP_VF_MEM_N = CHAN_NONE, +#else + MEM_ROT_ENC_MEM = _MAKE_CHAN(1, 45, NO_DMA, NO_DMA, 48), + MEM_ROT_VF_MEM = _MAKE_CHAN(2, 46, NO_DMA, NO_DMA, 49), + MEM_ROT_PP_MEM = _MAKE_CHAN(3, 47, NO_DMA, NO_DMA, 50), + + MEM_PRP_ENC_MEM = _MAKE_CHAN(4, 12, 14, 17, 20), + MEM_PRP_VF_MEM = _MAKE_CHAN(5, 12, 14, 17, 21), + MEM_PP_MEM = _MAKE_CHAN(6, 11, 15, 18, 22), + + MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA), + MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA), + MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA), + MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA), + + MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA), + MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA), + MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0), + MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0), + + DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + + CSI_MEM0 = _MAKE_CHAN(15, NO_DMA, NO_DMA, NO_DMA, 0), + CSI_MEM1 = _MAKE_CHAN(16, NO_DMA, NO_DMA, NO_DMA, 1), + CSI_MEM2 = _MAKE_CHAN(17, NO_DMA, NO_DMA, NO_DMA, 2), + CSI_MEM3 = _MAKE_CHAN(18, NO_DMA, NO_DMA, NO_DMA, 3), + + CSI_MEM = CSI_MEM0, + + CSI_PRP_ENC_MEM = _MAKE_CHAN(19, NO_DMA, NO_DMA, NO_DMA, 20), + CSI_PRP_VF_MEM = _MAKE_CHAN(20, NO_DMA, NO_DMA, NO_DMA, 21), + + MEM_VDI_PRP_VF_MEM_P = _MAKE_CHAN(21, 8, 14, 17, 21), + MEM_VDI_PRP_VF_MEM = _MAKE_CHAN(22, 9, 14, 17, 21), + MEM_VDI_PRP_VF_MEM_N = _MAKE_CHAN(23, 10, 14, 17, 21), + + MEM_PP_ADC = CHAN_NONE, + ADC_SYS2 = CHAN_NONE, +#endif + +} ipu_channel_t; + +/*! + * Enumeration of types of buffers for a logical channel. + */ +typedef enum { + IPU_OUTPUT_BUFFER = 0, /*!< Buffer for output from IPU */ + IPU_ALPHA_IN_BUFFER = 1, /*!< Buffer for input to IPU */ + IPU_GRAPH_IN_BUFFER = 2, /*!< Buffer for input to IPU */ + IPU_VIDEO_IN_BUFFER = 3, /*!< Buffer for input to IPU */ + IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER, + IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER, +} ipu_buffer_t; + +#define IPU_PANEL_SERIAL 1 +#define IPU_PANEL_PARALLEL 2 + +/*! + * Enumeration of DI ports for ADC. + */ +typedef enum { + DISP0, + DISP1, + DISP2, + DISP3 +} display_port_t; + +/*! + * Enumeration of ADC channel operation mode. + */ +typedef enum { + Disable, + WriteTemplateNonSeq, + ReadTemplateNonSeq, + WriteTemplateUnCon, + ReadTemplateUnCon, + WriteDataWithRS, + WriteDataWoRS, + WriteCmd +} mcu_mode_t; + +/*! + * Enumeration of ADC channel addressing mode. + */ +typedef enum { + FullWoBE, + FullWithBE, + XY +} display_addressing_t; + +/*! + * Union of initialization parameters for a logical channel. + */ +typedef union { + struct { + uint32_t csi; + uint32_t mipi_id; + bool mipi_en; + bool interlaced; + } csi_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t csi; + } csi_prp_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + } mem_prp_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + } mem_rot_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t csi; + } csi_prp_vf_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + display_port_t disp; + uint32_t out_left; + uint32_t out_top; + } csi_prp_vf_adc; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t in_g_pixel_fmt; + uint8_t alpha; + uint32_t key_color; + bool alpha_chan_en; + ipu_motion_sel motion_sel; + enum v4l2_field field_fmt; + } mem_prp_vf_mem; + struct { + uint32_t temp; + } mem_prp_vf_adc; + struct { + uint32_t temp; + } mem_rot_vf_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t in_g_pixel_fmt; + uint8_t alpha; + uint32_t key_color; + bool alpha_chan_en; + } mem_pp_mem; + struct { + uint32_t temp; + } mem_rot_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + display_port_t disp; + uint32_t out_left; + uint32_t out_top; + } mem_pp_adc; + struct { + pf_operation_t operation; + } mem_pf_mem; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + } mem_dc_sync; + struct { + uint32_t temp; + } mem_sdc_fg; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + bool alpha_chan_en; + } mem_dp_bg_sync; + struct { + uint32_t temp; + } mem_sdc_bg; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + bool alpha_chan_en; + } mem_dp_fg_sync; + struct { + uint32_t di; + } direct_async; + struct { + display_port_t disp; + mcu_mode_t ch_mode; + uint32_t out_left; + uint32_t out_top; + } adc_sys1; + struct { + display_port_t disp; + mcu_mode_t ch_mode; + uint32_t out_left; + uint32_t out_top; + } adc_sys2; +} ipu_channel_params_t; + +/*! + * Enumeration of IPU interrupt sources. + */ +enum ipu_irq_line { +#ifdef CONFIG_MXC_IPU_V1 + IPU_IRQ_DC_FC_1 = -1, + + IPU_IRQ_PRP_ENC_OUT_EOF = 0, + IPU_IRQ_PRP_VF_OUT_EOF = 1, + IPU_IRQ_PP_OUT_EOF = 2, + IPU_IRQ_PRP_GRAPH_IN_EOF = 3, + IPU_IRQ_PP_GRAPH_IN_EOF = 4, + IPU_IRQ_PP_IN_EOF = 5, + IPU_IRQ_PRP_IN_EOF = 6, + IPU_IRQ_SENSOR_OUT_EOF = 7, + IPU_IRQ_CSI0_OUT_EOF = IPU_IRQ_SENSOR_OUT_EOF, + IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 8, + IPU_IRQ_PRP_VF_ROT_OUT_EOF = 9, + IPU_IRQ_PRP_ENC_ROT_IN_EOF = 10, + IPU_IRQ_PRP_VF_ROT_IN_EOF = 11, + IPU_IRQ_PP_ROT_OUT_EOF = 12, + IPU_IRQ_PP_ROT_IN_EOF = 13, + IPU_IRQ_BG_SYNC_EOF = 14, + IPU_IRQ_SDC_BG_EOF = IPU_IRQ_BG_SYNC_EOF, + IPU_IRQ_FG_SYNC_EOF = 15, + IPU_IRQ_SDC_FG_EOF = IPU_IRQ_FG_SYNC_EOF, + IPU_IRQ_SDC_MASK_EOF = 16, + IPU_IRQ_SDC_BG_PART_EOF = 17, + IPU_IRQ_ADC_SYS1_WR_EOF = 18, + IPU_IRQ_ADC_SYS2_WR_EOF = 19, + IPU_IRQ_ADC_SYS1_CMD_EOF = 20, + IPU_IRQ_ADC_SYS2_CMD_EOF = 21, + IPU_IRQ_ADC_SYS1_RD_EOF = 22, + IPU_IRQ_ADC_SYS2_RD_EOF = 23, + IPU_IRQ_PF_QP_IN_EOF = 24, + IPU_IRQ_PF_BSP_IN_EOF = 25, + IPU_IRQ_PF_Y_IN_EOF = 26, + IPU_IRQ_PF_U_IN_EOF = 27, + IPU_IRQ_PF_V_IN_EOF = 28, + IPU_IRQ_PF_Y_OUT_EOF = 29, + IPU_IRQ_PF_U_OUT_EOF = 30, + IPU_IRQ_PF_V_OUT_EOF = 31, + + IPU_IRQ_PRP_ENC_OUT_NF = 32, + IPU_IRQ_PRP_VF_OUT_NF = 33, + IPU_IRQ_PP_OUT_NF = 34, + IPU_IRQ_PRP_GRAPH_IN_NF = 35, + IPU_IRQ_PP_GRAPH_IN_NF = 36, + IPU_IRQ_PP_IN_NF = 37, + IPU_IRQ_PRP_IN_NF = 38, + IPU_IRQ_SENSOR_OUT_NF = 39, + IPU_IRQ_PRP_ENC_ROT_OUT_NF = 40, + IPU_IRQ_PRP_VF_ROT_OUT_NF = 41, + IPU_IRQ_PRP_ENC_ROT_IN_NF = 42, + IPU_IRQ_PRP_VF_ROT_IN_NF = 43, + IPU_IRQ_PP_ROT_OUT_NF = 44, + IPU_IRQ_PP_ROT_IN_NF = 45, + IPU_IRQ_SDC_FG_NF = 46, + IPU_IRQ_SDC_BG_NF = 47, + IPU_IRQ_SDC_MASK_NF = 48, + IPU_IRQ_SDC_BG_PART_NF = 49, + IPU_IRQ_ADC_SYS1_WR_NF = 50, + IPU_IRQ_ADC_SYS2_WR_NF = 51, + IPU_IRQ_ADC_SYS1_CMD_NF = 52, + IPU_IRQ_ADC_SYS2_CMD_NF = 53, + IPU_IRQ_ADC_SYS1_RD_NF = 54, + IPU_IRQ_ADC_SYS2_RD_NF = 55, + IPU_IRQ_PF_QP_IN_NF = 56, + IPU_IRQ_PF_BSP_IN_NF = 57, + IPU_IRQ_PF_Y_IN_NF = 58, + IPU_IRQ_PF_U_IN_NF = 59, + IPU_IRQ_PF_V_IN_NF = 60, + IPU_IRQ_PF_Y_OUT_NF = 61, + IPU_IRQ_PF_U_OUT_NF = 62, + IPU_IRQ_PF_V_OUT_NF = 63, + + IPU_IRQ_BREAKRQ = 64, + IPU_IRQ_SDC_BG_OUT_EOF = 65, + IPU_IRQ_BG_SF_END = IPU_IRQ_SDC_BG_OUT_EOF, + IPU_IRQ_SDC_FG_OUT_EOF = 66, + IPU_IRQ_SDC_MASK_OUT_EOF = 67, + IPU_IRQ_ADC_SERIAL_DATA_OUT = 68, + IPU_IRQ_SENSOR_NF = 69, + IPU_IRQ_SENSOR_EOF = 70, + IPU_IRQ_SDC_DISP3_VSYNC = 80, + IPU_IRQ_ADC_DISP0_VSYNC = 81, + IPU_IRQ_ADC_DISP12_VSYNC = 82, + IPU_IRQ_ADC_PRP_EOF = 83, + IPU_IRQ_ADC_PP_EOF = 84, + IPU_IRQ_ADC_SYS1_EOF = 85, + IPU_IRQ_ADC_SYS2_EOF = 86, + + IPU_IRQ_PRP_ENC_OUT_NFB4EOF_ERR = 96, + IPU_IRQ_PRP_VF_OUT_NFB4EOF_ERR = 97, + IPU_IRQ_PP_OUT_NFB4EOF_ERR = 98, + IPU_IRQ_PRP_GRAPH_IN_NFB4EOF_ERR = 99, + IPU_IRQ_PP_GRAPH_IN_NFB4EOF_ERR = 100, + IPU_IRQ_PP_IN_NFB4EOF_ERR = 101, + IPU_IRQ_PRP_IN_NFB4EOF_ERR = 102, + IPU_IRQ_SENSOR_OUT_NFB4EOF_ERR = 103, + IPU_IRQ_PRP_ENC_ROT_OUT_NFB4EOF_ERR = 104, + IPU_IRQ_PRP_VF_ROT_OUT_NFB4EOF_ERR = 105, + IPU_IRQ_PRP_ENC_ROT_IN_NFB4EOF_ERR = 106, + IPU_IRQ_PRP_VF_ROT_IN_NFB4EOF_ERR = 107, + IPU_IRQ_PP_ROT_OUT_NFB4EOF_ERR = 108, + IPU_IRQ_PP_ROT_IN_NFB4EOF_ERR = 109, + IPU_IRQ_SDC_FG_NFB4EOF_ERR = 110, + IPU_IRQ_SDC_BG_NFB4EOF_ERR = 111, + IPU_IRQ_SDC_MASK_NFB4EOF_ERR = 112, + IPU_IRQ_SDC_BG_PART_NFB4EOF_ERR = 113, + IPU_IRQ_ADC_SYS1_WR_NFB4EOF_ERR = 114, + IPU_IRQ_ADC_SYS2_WR_NFB4EOF_ERR = 115, + IPU_IRQ_ADC_SYS1_CMD_NFB4EOF_ERR = 116, + IPU_IRQ_ADC_SYS2_CMD_NFB4EOF_ERR = 117, + IPU_IRQ_ADC_SYS1_RD_NFB4EOF_ERR = 118, + IPU_IRQ_ADC_SYS2_RD_NFB4EOF_ERR = 119, + IPU_IRQ_PF_QP_IN_NFB4EOF_ERR = 120, + IPU_IRQ_PF_BSP_IN_NFB4EOF_ERR = 121, + IPU_IRQ_PF_Y_IN_NFB4EOF_ERR = 122, + IPU_IRQ_PF_U_IN_NFB4EOF_ERR = 123, + IPU_IRQ_PF_V_IN_NFB4EOF_ERR = 124, + IPU_IRQ_PF_Y_OUT_NFB4EOF_ERR = 125, + IPU_IRQ_PF_U_OUT_NFB4EOF_ERR = 126, + IPU_IRQ_PF_V_OUT_NFB4EOF_ERR = 127, + + IPU_IRQ_BAYER_BUFOVF_ERR = 128, + IPU_IRQ_ENC_BUFOVF_ERR = 129, + IPU_IRQ_VF_BUFOVF_ERR = 130, + IPU_IRQ_ADC_PP_TEAR_ERR = 131, + IPU_IRQ_ADC_SYS1_TEAR_ERR = 132, + IPU_IRQ_ADC_SYS2_TEAR_ERR = 133, + IPU_IRQ_SDC_BGD_ERR = 134, + IPU_IRQ_SDC_FGD_ERR = 135, + IPU_IRQ_SDC_MASKD_ERR = 136, + IPU_IRQ_BAYER_FRM_LOST_ERR = 137, + IPU_IRQ_ENC_FRM_LOST_ERR = 138, + IPU_IRQ_VF_FRM_LOST_ERR = 139, + IPU_IRQ_ADC_LOCK_ERR = 140, + IPU_IRQ_DI_LLA_LOCK_ERR = 141, + IPU_IRQ_AHB_M1_ERR = 142, + IPU_IRQ_AHB_M12_ERR = 143, +#else + IPU_IRQ_CSI0_OUT_EOF = 0, + IPU_IRQ_CSI1_OUT_EOF = 1, + IPU_IRQ_CSI2_OUT_EOF = 2, + IPU_IRQ_CSI3_OUT_EOF = 3, + IPU_IRQ_VDI_P_IN_EOF = 8, + IPU_IRQ_VDI_C_IN_EOF = 9, + IPU_IRQ_VDI_N_IN_EOF = 10, + IPU_IRQ_PP_IN_EOF = 11, + IPU_IRQ_PRP_IN_EOF = 12, + IPU_IRQ_PRP_GRAPH_IN_EOF = 14, + IPU_IRQ_PP_GRAPH_IN_EOF = 15, + IPU_IRQ_PRP_ALPHA_IN_EOF = 17, + IPU_IRQ_PP_ALPHA_IN_EOF = 18, + IPU_IRQ_PRP_ENC_OUT_EOF = 20, + IPU_IRQ_PRP_VF_OUT_EOF = 21, + IPU_IRQ_PP_OUT_EOF = 22, + IPU_IRQ_BG_SYNC_EOF = 23, + IPU_IRQ_BG_ASYNC_EOF = 24, + IPU_IRQ_FG_SYNC_EOF = 27, + IPU_IRQ_DC_SYNC_EOF = 28, + IPU_IRQ_FG_ASYNC_EOF = 29, + IPU_IRQ_FG_ALPHA_SYNC_EOF = 31, + + IPU_IRQ_FG_ALPHA_ASYNC_EOF = 33, + IPU_IRQ_DC_READ_EOF = 40, + IPU_IRQ_DC_ASYNC_EOF = 41, + IPU_IRQ_DC_CMD1_EOF = 42, + IPU_IRQ_DC_CMD2_EOF = 43, + IPU_IRQ_DC_MASK_EOF = 44, + IPU_IRQ_PRP_ENC_ROT_IN_EOF = 45, + IPU_IRQ_PRP_VF_ROT_IN_EOF = 46, + IPU_IRQ_PP_ROT_IN_EOF = 47, + IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 48, + IPU_IRQ_PRP_VF_ROT_OUT_EOF = 49, + IPU_IRQ_PP_ROT_OUT_EOF = 50, + IPU_IRQ_BG_ALPHA_SYNC_EOF = 51, + IPU_IRQ_BG_ALPHA_ASYNC_EOF = 52, + + IPU_IRQ_DP_SF_START = 448 + 2, + IPU_IRQ_DP_SF_END = 448 + 3, + IPU_IRQ_BG_SF_END = IPU_IRQ_DP_SF_END, + IPU_IRQ_DC_FC_0 = 448 + 8, + IPU_IRQ_DC_FC_1 = 448 + 9, + IPU_IRQ_DC_FC_2 = 448 + 10, + IPU_IRQ_DC_FC_3 = 448 + 11, + IPU_IRQ_DC_FC_4 = 448 + 12, + IPU_IRQ_DC_FC_6 = 448 + 13, + IPU_IRQ_VSYNC_PRE_0 = 448 + 14, + IPU_IRQ_VSYNC_PRE_1 = 448 + 15, +#endif + + IPU_IRQ_COUNT +}; + +/*! + * Bitfield of Display Interface signal polarities. + */ +typedef struct { + unsigned datamask_en:1; + unsigned int_clk:1; + unsigned interlaced:1; + unsigned odd_field_first:1; + unsigned clksel_en:1; + unsigned clkidle_en:1; + unsigned data_pol:1; /* true = inverted */ + unsigned clk_pol:1; /* true = rising edge */ + unsigned enable_pol:1; + unsigned Hsync_pol:1; /* true = active high */ + unsigned Vsync_pol:1; +} ipu_di_signal_cfg_t; + +/*! + * Bitfield of CSI signal polarities and modes. + */ + +typedef struct { + unsigned data_width:4; + unsigned clk_mode:3; + unsigned ext_vsync:1; + unsigned Vsync_pol:1; + unsigned Hsync_pol:1; + unsigned pixclk_pol:1; + unsigned data_pol:1; + unsigned sens_clksrc:1; + unsigned pack_tight:1; + unsigned force_eof:1; + unsigned data_en_pol:1; + unsigned data_fmt; + unsigned csi; + unsigned mclk; +} ipu_csi_signal_cfg_t; + +/*! + * Enumeration of CSI data bus widths. + */ +enum { + IPU_CSI_DATA_WIDTH_4, + IPU_CSI_DATA_WIDTH_8, + IPU_CSI_DATA_WIDTH_10, + IPU_CSI_DATA_WIDTH_16, +}; + +/*! + * Enumeration of CSI clock modes. + */ +enum { + IPU_CSI_CLK_MODE_GATED_CLK, + IPU_CSI_CLK_MODE_NONGATED_CLK, + IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE, + IPU_CSI_CLK_MODE_CCIR656_INTERLACED, + IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR, + IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR, + IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR, + IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR, +}; + +enum { + IPU_CSI_MIPI_DI0, + IPU_CSI_MIPI_DI1, + IPU_CSI_MIPI_DI2, + IPU_CSI_MIPI_DI3, +}; + +typedef enum { + RGB, + YCbCr, + YUV +} ipu_color_space_t; + +/*! + * Enumeration of ADC vertical sync mode. + */ +typedef enum { + VsyncNone, + VsyncInternal, + VsyncCSI, + VsyncExternal +} vsync_t; + +typedef enum { + DAT, + CMD +} cmddata_t; + +/*! + * Enumeration of ADC display update mode. + */ +typedef enum { + IPU_ADC_REFRESH_NONE, + IPU_ADC_AUTO_REFRESH, + IPU_ADC_AUTO_REFRESH_SNOOP, + IPU_ADC_SNOOPING, +} ipu_adc_update_mode_t; + +/*! + * Enumeration of ADC display interface types (serial or parallel). + */ +enum { + IPU_ADC_IFC_MODE_SYS80_TYPE1, + IPU_ADC_IFC_MODE_SYS80_TYPE2, + IPU_ADC_IFC_MODE_SYS68K_TYPE1, + IPU_ADC_IFC_MODE_SYS68K_TYPE2, + IPU_ADC_IFC_MODE_3WIRE_SERIAL, + IPU_ADC_IFC_MODE_4WIRE_SERIAL, + IPU_ADC_IFC_MODE_5WIRE_SERIAL_CLK, + IPU_ADC_IFC_MODE_5WIRE_SERIAL_CS, +}; + +enum { + IPU_ADC_IFC_WIDTH_8, + IPU_ADC_IFC_WIDTH_16, +}; + +/*! + * Enumeration of ADC display interface burst mode. + */ +enum { + IPU_ADC_BURST_WCS, + IPU_ADC_BURST_WBLCK, + IPU_ADC_BURST_NONE, + IPU_ADC_BURST_SERIAL, +}; + +/*! + * Enumeration of ADC display interface RW signal timing modes. + */ +enum { + IPU_ADC_SER_NO_RW, + IPU_ADC_SER_RW_BEFORE_RS, + IPU_ADC_SER_RW_AFTER_RS, +}; + +/*! + * Bitfield of ADC signal polarities and modes. + */ +typedef struct { + unsigned data_pol:1; + unsigned clk_pol:1; + unsigned cs_pol:1; + unsigned rs_pol:1; + unsigned addr_pol:1; + unsigned read_pol:1; + unsigned write_pol:1; + unsigned Vsync_pol:1; + unsigned burst_pol:1; + unsigned burst_mode:2; + unsigned ifc_mode:3; + unsigned ifc_width:5; + unsigned ser_preamble_len:4; + unsigned ser_preamble:8; + unsigned ser_rw_mode:2; +} ipu_adc_sig_cfg_t; + +/*! + * Enumeration of ADC template commands. + */ +enum { + RD_DATA, + RD_ACK, + RD_WAIT, + WR_XADDR, + WR_YADDR, + WR_ADDR, + WR_CMND, + WR_DATA, +}; + +/*! + * Enumeration of ADC template command flow control. + */ +enum { + SINGLE_STEP, + PAUSE, + STOP, +}; + + +/*Define template constants*/ +#define ATM_ADDR_RANGE 0x20 /*offset address of DISP */ +#define TEMPLATE_BUF_SIZE 0x20 /*size of template */ + +/*! + * Define to create ADC template command entry. + */ +#define ipu_adc_template_gen(oc, rs, fc, dat) (((rs) << 29) | ((fc) << 27) | \ + ((oc) << 24) | (dat)) + +typedef struct { + u32 reg; + u32 value; +} ipu_lpmc_reg_t; + +#define IPU_LPMC_REG_READ 0x80000000L + +#define CSI_MCLK_VF 1 +#define CSI_MCLK_ENC 2 +#define CSI_MCLK_RAW 4 +#define CSI_MCLK_I2C 8 + +struct ipu_soc; +/* Common IPU API */ +struct ipu_soc *ipu_get_soc(int id); +int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params); +void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel); + +static inline bool ipu_can_rotate_in_place(ipu_rotate_mode_t rot) +{ +#ifdef CONFIG_MXC_IPU_V3D + return (rot < IPU_ROTATE_HORIZ_FLIP); +#else + return (rot < IPU_ROTATE_90_RIGHT); +#endif +} + +int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + ipu_rotate_mode_t rot_mode, + dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, + dma_addr_t phyaddr_2, + uint32_t u_offset, uint32_t v_offset); + +int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum, dma_addr_t phyaddr); + +int32_t ipu_update_channel_offset(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + uint32_t u, uint32_t v, + uint32_t vertical_offset, uint32_t horizontal_offset); + +int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel, + ipu_buffer_t type, uint32_t bufNum); +int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum); + +int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch); +int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch); + +int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel); +int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum); +void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum); +uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type); +int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel); +int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop); +int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch); + +int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi); +int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi); + +int ipu_lowpwr_display_enable(void); +int ipu_lowpwr_display_disable(void); + +void ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq); +void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq); +void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq); +int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq, + irqreturn_t(*handler) (int, void *), + uint32_t irq_flags, const char *devname, void *dev_id); +void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id); +bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq); +void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]); + +/* two stripe calculations */ +struct stripe_param{ + unsigned int input_width; /* width of the input stripe */ + unsigned int output_width; /* width of the output stripe */ + unsigned int input_column; /* the first column on the input stripe */ + unsigned int output_column; /* the first column on the output stripe */ + unsigned int idr; + /* inverse downisizing ratio parameter; expressed as a power of 2 */ + unsigned int irr; + /* inverse resizing ratio parameter; expressed as a multiple of 2^-13 */ +}; +int ipu_calc_stripes_sizes(const unsigned int input_frame_width, + unsigned int output_frame_width, + const unsigned int maximal_stripe_width, + const unsigned long long cirr, + const unsigned int equal_stripes, + u32 input_pixelformat, + u32 output_pixelformat, + struct stripe_param *left, + struct stripe_param *right); + +/* SDC API */ +int32_t ipu_sdc_init_panel(ipu_panel_t panel, + uint32_t pixel_clk, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint16_t hStartWidth, uint16_t hSyncWidth, + uint16_t hEndWidth, uint16_t vStartWidth, + uint16_t vSyncWidth, uint16_t vEndWidth, + ipu_di_signal_cfg_t sig); + +int32_t ipu_sdc_set_global_alpha(bool enable, uint8_t alpha); +int32_t ipu_sdc_set_color_key(ipu_channel_t channel, bool enable, + uint32_t colorKey); +int32_t ipu_sdc_set_brightness(uint8_t value); + +int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp, + uint32_t pixel_clk, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint16_t h_start_width, uint16_t h_sync_width, + uint16_t h_end_width, uint16_t v_start_width, + uint16_t v_sync_width, uint16_t v_end_width, + uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig); + +void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp); + +int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t x_pos, + int16_t y_pos); +int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t *x_pos, + int16_t *y_pos); +int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, + uint8_t alpha); +int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, + uint32_t colorKey); +int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, + int constk[], int slopek[]); + +int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time, + uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig); +void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset); +void ipu_reset_disp_panel(struct ipu_soc *ipu); + +/* ADC API */ +int32_t ipu_adc_write_template(display_port_t disp, uint32_t *pCmd, + bool write); + +int32_t ipu_adc_set_update_mode(ipu_channel_t channel, + ipu_adc_update_mode_t mode, + uint32_t refresh_rate, unsigned long addr, + uint32_t *size); + +int32_t ipu_adc_get_snooping_status(uint32_t *statl, uint32_t *stath); + +int32_t ipu_adc_write_cmd(display_port_t disp, cmddata_t type, + uint32_t cmd, const uint32_t *params, + uint16_t numParams); + +int32_t ipu_adc_init_panel(display_port_t disp, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint32_t stride, + ipu_adc_sig_cfg_t sig, + display_addressing_t addr, + uint32_t vsync_width, vsync_t mode); + +int32_t ipu_adc_init_ifc_timing(display_port_t disp, bool read, + uint32_t cycle_time, + uint32_t up_time, + uint32_t down_time, + uint32_t read_latch_time, uint32_t pixel_clk); + +/* CMOS Sensor Interface API */ +int32_t ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height, + uint32_t pixel_fmt, ipu_csi_signal_cfg_t sig); + +int32_t ipu_csi_get_sensor_protocol(struct ipu_soc *ipu, uint32_t csi); + +int32_t ipu_csi_enable_mclk(struct ipu_soc *ipu, int src, bool flag, bool wait); + +static inline int32_t ipu_csi_enable_mclk_if(struct ipu_soc *ipu, int src, uint32_t csi, + bool flag, bool wait) +{ +#ifdef CONFIG_MXC_IPU_V1 + return ipu_csi_enable_mclk(ipu, src, flag, wait); +#else + return ipu_csi_enable_mclk(ipu, csi, flag, wait); +#endif +} + +int ipu_csi_read_mclk_flag(void); + +void ipu_csi_flash_strobe(bool flag); + +void ipu_csi_get_window_size(struct ipu_soc *ipu, uint32_t *width, uint32_t *height, uint32_t csi); + +void ipu_csi_set_window_size(struct ipu_soc *ipu, uint32_t width, uint32_t height, uint32_t csi); + +void ipu_csi_set_window_pos(struct ipu_soc *ipu, uint32_t left, uint32_t top, uint32_t csi); + +/* Post Filter functions */ +int32_t ipu_pf_set_pause_row(uint32_t pause_row); + +uint32_t bytes_per_pixel(uint32_t fmt); + /* IPU device */ struct ipu_pos { u32 x; -- cgit v1.2.3 From c5ce3b9689900d0f3447271260d53e52221b8971 Mon Sep 17 00:00:00 2001 From: Jason Chen Date: Wed, 14 Sep 2011 10:25:42 +0800 Subject: ENGR00156673-1 ipuv3: move mach related definition to mach dir for include/linux/ipu.h. Signed-off-by: Jason Chen --- include/linux/ipu.h | 948 +--------------------------------------------------- 1 file changed, 10 insertions(+), 938 deletions(-) (limited to 'include/linux') diff --git a/include/linux/ipu.h b/include/linux/ipu.h index 06d8c64a6d6..d6c1588b82c 100644 --- a/include/linux/ipu.h +++ b/include/linux/ipu.h @@ -58,25 +58,6 @@ typedef enum { IPU_ROTATE_90_LEFT = 7, } ipu_rotate_mode_t; -/*! - * Enumeration of Post Filter modes - */ -typedef enum { - PF_DISABLE_ALL = 0, - PF_MPEG4_DEBLOCK = 1, - PF_MPEG4_DERING = 2, - PF_MPEG4_DEBLOCK_DERING = 3, - PF_H264_DEBLOCK = 4, -} pf_operation_t; - -/*! - * Enumeration of Synchronous (Memory-less) panel types - */ -typedef enum { - IPU_PANEL_SHARP_TFT, - IPU_PANEL_TFT, -} ipu_panel_t; - /*! * Enumeration of VDI MOTION select */ @@ -86,6 +67,16 @@ typedef enum { HIGH_MOTION = 2, } ipu_motion_sel; +/*! + * Enumeration of DI ports for ADC. + */ +typedef enum { + DISP0, + DISP1, + DISP2, + DISP3 +} display_port_t; + /* IPU Pixel format definitions */ /* Four-character-code (FOURCC) */ #define fourcc(a, b, c, d)\ @@ -146,925 +137,6 @@ typedef enum { #define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*!< 16 YUV 4:2:2 */ /*! @} */ -/* IPU Driver channels definitions. */ -/* Note these are different from IDMA channels */ -#ifdef CONFIG_MXC_IPU_V1 -#define _MAKE_CHAN(num, in, out, sec) ((num << 24) | (sec << 16) | (out << 8) | in) -#define IPU_CHAN_ID(ch) (ch >> 24) -#define IPU_CHAN_SEC_DMA(ch) ((uint32_t) (ch >> 16) & 0xFF) -#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch >> 8) & 0xFF) -#define IPU_CHAN_IN_DMA(ch) ((uint32_t) (ch & 0xFF)) - -#else -#define IPU_MAX_CH 32 -#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \ - ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out) -#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24)) -#define IPU_CHAN_ID(ch) (ch >> 24) -#define IPU_CHAN_ALT(ch) (ch & 0x02000000) -#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F) -#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F) -#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F) -#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F)) -#define NO_DMA 0x3F -#define ALT 1 -#endif -/*! - * Enumeration of IPU logical channels. An IPU logical channel is defined as a - * combination of an input (memory to IPU), output (IPU to memory), and/or - * secondary input IDMA channels and in some cases an Image Converter task. - * Some channels consist of only an input or output. - */ -typedef enum { - CHAN_NONE = -1, -#ifdef CONFIG_MXC_IPU_V1 - CSI_MEM = _MAKE_CHAN(1, 0xFF, 7, 0xFF), /*!< CSI raw sensor data to memory */ - - CSI_PRP_ENC_MEM = _MAKE_CHAN(2, 0xFF, 0, 0xFF), /*!< CSI to IC Encoder PreProcessing to Memory */ - MEM_PRP_ENC_MEM = _MAKE_CHAN(3, 6, 0, 0xFF), /*!< Memory to IC Encoder PreProcessing to Memory */ - MEM_ROT_ENC_MEM = _MAKE_CHAN(4, 10, 8, 0xFF), /*!< Memory to IC Encoder Rotation to Memory */ - - CSI_PRP_VF_MEM = _MAKE_CHAN(5, 0xFF, 1, 0xFF), /*!< CSI to IC Viewfinder PreProcessing to Memory */ - CSI_PRP_VF_ADC = _MAKE_CHAN(6, 0xFF, 1, 0xFF), /*!< CSI to IC Viewfinder PreProcessing to ADC */ - MEM_PRP_VF_MEM = _MAKE_CHAN(7, 6, 1, 3), /*!< Memory to IC Viewfinder PreProcessing to Memory */ - MEM_PRP_VF_ADC = _MAKE_CHAN(8, 6, 1, 3), /*!< Memory to IC Viewfinder PreProcessing to ADC */ - MEM_ROT_VF_MEM = _MAKE_CHAN(9, 11, 9, 0xFF), /*!< Memory to IC Viewfinder Rotation to Memory */ - - MEM_PP_MEM = _MAKE_CHAN(10, 5, 2, 4), /*!< Memory to IC PostProcessing to Memory */ - MEM_ROT_PP_MEM = _MAKE_CHAN(11, 13, 12, 0xFF), /*!< Memory to IC PostProcessing Rotation to Memory */ - MEM_PP_ADC = _MAKE_CHAN(12, 5, 2, 4), /*!< Memory to IC PostProcessing to ADC */ - - MEM_SDC_BG = _MAKE_CHAN(14, 14, 0xFF, 0xFF), /*!< Memory to SDC Background plane */ - MEM_SDC_FG = _MAKE_CHAN(15, 15, 0xFF, 0xFF), /*!< Memory to SDC Foreground plane */ - MEM_SDC_MASK = _MAKE_CHAN(16, 16, 0xFF, 0xFF), /*!< Memory to SDC Mask */ - - MEM_BG_SYNC = MEM_SDC_BG, - MEM_FG_SYNC = MEM_SDC_FG, - - ADC_SYS1 = _MAKE_CHAN(17, 18, 22, 20), /*!< Memory to ADC System Channel 1 */ - ADC_SYS2 = _MAKE_CHAN(18, 19, 23, 21), /*!< Memory to ADC System Channel 2 */ - - MEM_PF_Y_MEM = _MAKE_CHAN(19, 26, 29, 24), /*!< Y and PF Memory to Post-filter to Y Memory */ - MEM_PF_U_MEM = _MAKE_CHAN(20, 27, 30, 25), /*!< U and PF Memory to Post-filter to U Memory */ - MEM_PF_V_MEM = _MAKE_CHAN(21, 28, 31, 0xFF), /*!< V Memory to Post-filter to V Memory */ - - MEM_DC_SYNC = CHAN_NONE, - DIRECT_ASYNC0 = CHAN_NONE, - DIRECT_ASYNC1 = CHAN_NONE, - MEM_VDI_PRP_VF_MEM_P = CHAN_NONE, - MEM_VDI_PRP_VF_MEM = CHAN_NONE, - MEM_VDI_PRP_VF_MEM_N = CHAN_NONE, -#else - MEM_ROT_ENC_MEM = _MAKE_CHAN(1, 45, NO_DMA, NO_DMA, 48), - MEM_ROT_VF_MEM = _MAKE_CHAN(2, 46, NO_DMA, NO_DMA, 49), - MEM_ROT_PP_MEM = _MAKE_CHAN(3, 47, NO_DMA, NO_DMA, 50), - - MEM_PRP_ENC_MEM = _MAKE_CHAN(4, 12, 14, 17, 20), - MEM_PRP_VF_MEM = _MAKE_CHAN(5, 12, 14, 17, 21), - MEM_PP_MEM = _MAKE_CHAN(6, 11, 15, 18, 22), - - MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA), - MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA), - MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA), - MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA), - - MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA), - MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA), - MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0), - MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0), - - DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA), - DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA), - - CSI_MEM0 = _MAKE_CHAN(15, NO_DMA, NO_DMA, NO_DMA, 0), - CSI_MEM1 = _MAKE_CHAN(16, NO_DMA, NO_DMA, NO_DMA, 1), - CSI_MEM2 = _MAKE_CHAN(17, NO_DMA, NO_DMA, NO_DMA, 2), - CSI_MEM3 = _MAKE_CHAN(18, NO_DMA, NO_DMA, NO_DMA, 3), - - CSI_MEM = CSI_MEM0, - - CSI_PRP_ENC_MEM = _MAKE_CHAN(19, NO_DMA, NO_DMA, NO_DMA, 20), - CSI_PRP_VF_MEM = _MAKE_CHAN(20, NO_DMA, NO_DMA, NO_DMA, 21), - - MEM_VDI_PRP_VF_MEM_P = _MAKE_CHAN(21, 8, 14, 17, 21), - MEM_VDI_PRP_VF_MEM = _MAKE_CHAN(22, 9, 14, 17, 21), - MEM_VDI_PRP_VF_MEM_N = _MAKE_CHAN(23, 10, 14, 17, 21), - - MEM_PP_ADC = CHAN_NONE, - ADC_SYS2 = CHAN_NONE, -#endif - -} ipu_channel_t; - -/*! - * Enumeration of types of buffers for a logical channel. - */ -typedef enum { - IPU_OUTPUT_BUFFER = 0, /*!< Buffer for output from IPU */ - IPU_ALPHA_IN_BUFFER = 1, /*!< Buffer for input to IPU */ - IPU_GRAPH_IN_BUFFER = 2, /*!< Buffer for input to IPU */ - IPU_VIDEO_IN_BUFFER = 3, /*!< Buffer for input to IPU */ - IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER, - IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER, -} ipu_buffer_t; - -#define IPU_PANEL_SERIAL 1 -#define IPU_PANEL_PARALLEL 2 - -/*! - * Enumeration of DI ports for ADC. - */ -typedef enum { - DISP0, - DISP1, - DISP2, - DISP3 -} display_port_t; - -/*! - * Enumeration of ADC channel operation mode. - */ -typedef enum { - Disable, - WriteTemplateNonSeq, - ReadTemplateNonSeq, - WriteTemplateUnCon, - ReadTemplateUnCon, - WriteDataWithRS, - WriteDataWoRS, - WriteCmd -} mcu_mode_t; - -/*! - * Enumeration of ADC channel addressing mode. - */ -typedef enum { - FullWoBE, - FullWithBE, - XY -} display_addressing_t; - -/*! - * Union of initialization parameters for a logical channel. - */ -typedef union { - struct { - uint32_t csi; - uint32_t mipi_id; - bool mipi_en; - bool interlaced; - } csi_mem; - struct { - uint32_t in_width; - uint32_t in_height; - uint32_t in_pixel_fmt; - uint32_t out_width; - uint32_t out_height; - uint32_t out_pixel_fmt; - uint32_t csi; - } csi_prp_enc_mem; - struct { - uint32_t in_width; - uint32_t in_height; - uint32_t in_pixel_fmt; - uint32_t out_width; - uint32_t out_height; - uint32_t out_pixel_fmt; - uint32_t outh_resize_ratio; - uint32_t outv_resize_ratio; - } mem_prp_enc_mem; - struct { - uint32_t in_width; - uint32_t in_height; - uint32_t in_pixel_fmt; - uint32_t out_width; - uint32_t out_height; - uint32_t out_pixel_fmt; - } mem_rot_enc_mem; - struct { - uint32_t in_width; - uint32_t in_height; - uint32_t in_pixel_fmt; - uint32_t out_width; - uint32_t out_height; - uint32_t out_pixel_fmt; - bool graphics_combine_en; - bool global_alpha_en; - bool key_color_en; - uint32_t csi; - } csi_prp_vf_mem; - struct { - uint32_t in_width; - uint32_t in_height; - uint32_t in_pixel_fmt; - uint32_t out_width; - uint32_t out_height; - uint32_t out_pixel_fmt; - bool graphics_combine_en; - bool global_alpha_en; - bool key_color_en; - display_port_t disp; - uint32_t out_left; - uint32_t out_top; - } csi_prp_vf_adc; - struct { - uint32_t in_width; - uint32_t in_height; - uint32_t in_pixel_fmt; - uint32_t out_width; - uint32_t out_height; - uint32_t out_pixel_fmt; - uint32_t outh_resize_ratio; - uint32_t outv_resize_ratio; - bool graphics_combine_en; - bool global_alpha_en; - bool key_color_en; - uint32_t in_g_pixel_fmt; - uint8_t alpha; - uint32_t key_color; - bool alpha_chan_en; - ipu_motion_sel motion_sel; - enum v4l2_field field_fmt; - } mem_prp_vf_mem; - struct { - uint32_t temp; - } mem_prp_vf_adc; - struct { - uint32_t temp; - } mem_rot_vf_mem; - struct { - uint32_t in_width; - uint32_t in_height; - uint32_t in_pixel_fmt; - uint32_t out_width; - uint32_t out_height; - uint32_t out_pixel_fmt; - uint32_t outh_resize_ratio; - uint32_t outv_resize_ratio; - bool graphics_combine_en; - bool global_alpha_en; - bool key_color_en; - uint32_t in_g_pixel_fmt; - uint8_t alpha; - uint32_t key_color; - bool alpha_chan_en; - } mem_pp_mem; - struct { - uint32_t temp; - } mem_rot_mem; - struct { - uint32_t in_width; - uint32_t in_height; - uint32_t in_pixel_fmt; - uint32_t out_width; - uint32_t out_height; - uint32_t out_pixel_fmt; - bool graphics_combine_en; - bool global_alpha_en; - bool key_color_en; - display_port_t disp; - uint32_t out_left; - uint32_t out_top; - } mem_pp_adc; - struct { - pf_operation_t operation; - } mem_pf_mem; - struct { - uint32_t di; - bool interlaced; - uint32_t in_pixel_fmt; - uint32_t out_pixel_fmt; - } mem_dc_sync; - struct { - uint32_t temp; - } mem_sdc_fg; - struct { - uint32_t di; - bool interlaced; - uint32_t in_pixel_fmt; - uint32_t out_pixel_fmt; - bool alpha_chan_en; - } mem_dp_bg_sync; - struct { - uint32_t temp; - } mem_sdc_bg; - struct { - uint32_t di; - bool interlaced; - uint32_t in_pixel_fmt; - uint32_t out_pixel_fmt; - bool alpha_chan_en; - } mem_dp_fg_sync; - struct { - uint32_t di; - } direct_async; - struct { - display_port_t disp; - mcu_mode_t ch_mode; - uint32_t out_left; - uint32_t out_top; - } adc_sys1; - struct { - display_port_t disp; - mcu_mode_t ch_mode; - uint32_t out_left; - uint32_t out_top; - } adc_sys2; -} ipu_channel_params_t; - -/*! - * Enumeration of IPU interrupt sources. - */ -enum ipu_irq_line { -#ifdef CONFIG_MXC_IPU_V1 - IPU_IRQ_DC_FC_1 = -1, - - IPU_IRQ_PRP_ENC_OUT_EOF = 0, - IPU_IRQ_PRP_VF_OUT_EOF = 1, - IPU_IRQ_PP_OUT_EOF = 2, - IPU_IRQ_PRP_GRAPH_IN_EOF = 3, - IPU_IRQ_PP_GRAPH_IN_EOF = 4, - IPU_IRQ_PP_IN_EOF = 5, - IPU_IRQ_PRP_IN_EOF = 6, - IPU_IRQ_SENSOR_OUT_EOF = 7, - IPU_IRQ_CSI0_OUT_EOF = IPU_IRQ_SENSOR_OUT_EOF, - IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 8, - IPU_IRQ_PRP_VF_ROT_OUT_EOF = 9, - IPU_IRQ_PRP_ENC_ROT_IN_EOF = 10, - IPU_IRQ_PRP_VF_ROT_IN_EOF = 11, - IPU_IRQ_PP_ROT_OUT_EOF = 12, - IPU_IRQ_PP_ROT_IN_EOF = 13, - IPU_IRQ_BG_SYNC_EOF = 14, - IPU_IRQ_SDC_BG_EOF = IPU_IRQ_BG_SYNC_EOF, - IPU_IRQ_FG_SYNC_EOF = 15, - IPU_IRQ_SDC_FG_EOF = IPU_IRQ_FG_SYNC_EOF, - IPU_IRQ_SDC_MASK_EOF = 16, - IPU_IRQ_SDC_BG_PART_EOF = 17, - IPU_IRQ_ADC_SYS1_WR_EOF = 18, - IPU_IRQ_ADC_SYS2_WR_EOF = 19, - IPU_IRQ_ADC_SYS1_CMD_EOF = 20, - IPU_IRQ_ADC_SYS2_CMD_EOF = 21, - IPU_IRQ_ADC_SYS1_RD_EOF = 22, - IPU_IRQ_ADC_SYS2_RD_EOF = 23, - IPU_IRQ_PF_QP_IN_EOF = 24, - IPU_IRQ_PF_BSP_IN_EOF = 25, - IPU_IRQ_PF_Y_IN_EOF = 26, - IPU_IRQ_PF_U_IN_EOF = 27, - IPU_IRQ_PF_V_IN_EOF = 28, - IPU_IRQ_PF_Y_OUT_EOF = 29, - IPU_IRQ_PF_U_OUT_EOF = 30, - IPU_IRQ_PF_V_OUT_EOF = 31, - - IPU_IRQ_PRP_ENC_OUT_NF = 32, - IPU_IRQ_PRP_VF_OUT_NF = 33, - IPU_IRQ_PP_OUT_NF = 34, - IPU_IRQ_PRP_GRAPH_IN_NF = 35, - IPU_IRQ_PP_GRAPH_IN_NF = 36, - IPU_IRQ_PP_IN_NF = 37, - IPU_IRQ_PRP_IN_NF = 38, - IPU_IRQ_SENSOR_OUT_NF = 39, - IPU_IRQ_PRP_ENC_ROT_OUT_NF = 40, - IPU_IRQ_PRP_VF_ROT_OUT_NF = 41, - IPU_IRQ_PRP_ENC_ROT_IN_NF = 42, - IPU_IRQ_PRP_VF_ROT_IN_NF = 43, - IPU_IRQ_PP_ROT_OUT_NF = 44, - IPU_IRQ_PP_ROT_IN_NF = 45, - IPU_IRQ_SDC_FG_NF = 46, - IPU_IRQ_SDC_BG_NF = 47, - IPU_IRQ_SDC_MASK_NF = 48, - IPU_IRQ_SDC_BG_PART_NF = 49, - IPU_IRQ_ADC_SYS1_WR_NF = 50, - IPU_IRQ_ADC_SYS2_WR_NF = 51, - IPU_IRQ_ADC_SYS1_CMD_NF = 52, - IPU_IRQ_ADC_SYS2_CMD_NF = 53, - IPU_IRQ_ADC_SYS1_RD_NF = 54, - IPU_IRQ_ADC_SYS2_RD_NF = 55, - IPU_IRQ_PF_QP_IN_NF = 56, - IPU_IRQ_PF_BSP_IN_NF = 57, - IPU_IRQ_PF_Y_IN_NF = 58, - IPU_IRQ_PF_U_IN_NF = 59, - IPU_IRQ_PF_V_IN_NF = 60, - IPU_IRQ_PF_Y_OUT_NF = 61, - IPU_IRQ_PF_U_OUT_NF = 62, - IPU_IRQ_PF_V_OUT_NF = 63, - - IPU_IRQ_BREAKRQ = 64, - IPU_IRQ_SDC_BG_OUT_EOF = 65, - IPU_IRQ_BG_SF_END = IPU_IRQ_SDC_BG_OUT_EOF, - IPU_IRQ_SDC_FG_OUT_EOF = 66, - IPU_IRQ_SDC_MASK_OUT_EOF = 67, - IPU_IRQ_ADC_SERIAL_DATA_OUT = 68, - IPU_IRQ_SENSOR_NF = 69, - IPU_IRQ_SENSOR_EOF = 70, - IPU_IRQ_SDC_DISP3_VSYNC = 80, - IPU_IRQ_ADC_DISP0_VSYNC = 81, - IPU_IRQ_ADC_DISP12_VSYNC = 82, - IPU_IRQ_ADC_PRP_EOF = 83, - IPU_IRQ_ADC_PP_EOF = 84, - IPU_IRQ_ADC_SYS1_EOF = 85, - IPU_IRQ_ADC_SYS2_EOF = 86, - - IPU_IRQ_PRP_ENC_OUT_NFB4EOF_ERR = 96, - IPU_IRQ_PRP_VF_OUT_NFB4EOF_ERR = 97, - IPU_IRQ_PP_OUT_NFB4EOF_ERR = 98, - IPU_IRQ_PRP_GRAPH_IN_NFB4EOF_ERR = 99, - IPU_IRQ_PP_GRAPH_IN_NFB4EOF_ERR = 100, - IPU_IRQ_PP_IN_NFB4EOF_ERR = 101, - IPU_IRQ_PRP_IN_NFB4EOF_ERR = 102, - IPU_IRQ_SENSOR_OUT_NFB4EOF_ERR = 103, - IPU_IRQ_PRP_ENC_ROT_OUT_NFB4EOF_ERR = 104, - IPU_IRQ_PRP_VF_ROT_OUT_NFB4EOF_ERR = 105, - IPU_IRQ_PRP_ENC_ROT_IN_NFB4EOF_ERR = 106, - IPU_IRQ_PRP_VF_ROT_IN_NFB4EOF_ERR = 107, - IPU_IRQ_PP_ROT_OUT_NFB4EOF_ERR = 108, - IPU_IRQ_PP_ROT_IN_NFB4EOF_ERR = 109, - IPU_IRQ_SDC_FG_NFB4EOF_ERR = 110, - IPU_IRQ_SDC_BG_NFB4EOF_ERR = 111, - IPU_IRQ_SDC_MASK_NFB4EOF_ERR = 112, - IPU_IRQ_SDC_BG_PART_NFB4EOF_ERR = 113, - IPU_IRQ_ADC_SYS1_WR_NFB4EOF_ERR = 114, - IPU_IRQ_ADC_SYS2_WR_NFB4EOF_ERR = 115, - IPU_IRQ_ADC_SYS1_CMD_NFB4EOF_ERR = 116, - IPU_IRQ_ADC_SYS2_CMD_NFB4EOF_ERR = 117, - IPU_IRQ_ADC_SYS1_RD_NFB4EOF_ERR = 118, - IPU_IRQ_ADC_SYS2_RD_NFB4EOF_ERR = 119, - IPU_IRQ_PF_QP_IN_NFB4EOF_ERR = 120, - IPU_IRQ_PF_BSP_IN_NFB4EOF_ERR = 121, - IPU_IRQ_PF_Y_IN_NFB4EOF_ERR = 122, - IPU_IRQ_PF_U_IN_NFB4EOF_ERR = 123, - IPU_IRQ_PF_V_IN_NFB4EOF_ERR = 124, - IPU_IRQ_PF_Y_OUT_NFB4EOF_ERR = 125, - IPU_IRQ_PF_U_OUT_NFB4EOF_ERR = 126, - IPU_IRQ_PF_V_OUT_NFB4EOF_ERR = 127, - - IPU_IRQ_BAYER_BUFOVF_ERR = 128, - IPU_IRQ_ENC_BUFOVF_ERR = 129, - IPU_IRQ_VF_BUFOVF_ERR = 130, - IPU_IRQ_ADC_PP_TEAR_ERR = 131, - IPU_IRQ_ADC_SYS1_TEAR_ERR = 132, - IPU_IRQ_ADC_SYS2_TEAR_ERR = 133, - IPU_IRQ_SDC_BGD_ERR = 134, - IPU_IRQ_SDC_FGD_ERR = 135, - IPU_IRQ_SDC_MASKD_ERR = 136, - IPU_IRQ_BAYER_FRM_LOST_ERR = 137, - IPU_IRQ_ENC_FRM_LOST_ERR = 138, - IPU_IRQ_VF_FRM_LOST_ERR = 139, - IPU_IRQ_ADC_LOCK_ERR = 140, - IPU_IRQ_DI_LLA_LOCK_ERR = 141, - IPU_IRQ_AHB_M1_ERR = 142, - IPU_IRQ_AHB_M12_ERR = 143, -#else - IPU_IRQ_CSI0_OUT_EOF = 0, - IPU_IRQ_CSI1_OUT_EOF = 1, - IPU_IRQ_CSI2_OUT_EOF = 2, - IPU_IRQ_CSI3_OUT_EOF = 3, - IPU_IRQ_VDI_P_IN_EOF = 8, - IPU_IRQ_VDI_C_IN_EOF = 9, - IPU_IRQ_VDI_N_IN_EOF = 10, - IPU_IRQ_PP_IN_EOF = 11, - IPU_IRQ_PRP_IN_EOF = 12, - IPU_IRQ_PRP_GRAPH_IN_EOF = 14, - IPU_IRQ_PP_GRAPH_IN_EOF = 15, - IPU_IRQ_PRP_ALPHA_IN_EOF = 17, - IPU_IRQ_PP_ALPHA_IN_EOF = 18, - IPU_IRQ_PRP_ENC_OUT_EOF = 20, - IPU_IRQ_PRP_VF_OUT_EOF = 21, - IPU_IRQ_PP_OUT_EOF = 22, - IPU_IRQ_BG_SYNC_EOF = 23, - IPU_IRQ_BG_ASYNC_EOF = 24, - IPU_IRQ_FG_SYNC_EOF = 27, - IPU_IRQ_DC_SYNC_EOF = 28, - IPU_IRQ_FG_ASYNC_EOF = 29, - IPU_IRQ_FG_ALPHA_SYNC_EOF = 31, - - IPU_IRQ_FG_ALPHA_ASYNC_EOF = 33, - IPU_IRQ_DC_READ_EOF = 40, - IPU_IRQ_DC_ASYNC_EOF = 41, - IPU_IRQ_DC_CMD1_EOF = 42, - IPU_IRQ_DC_CMD2_EOF = 43, - IPU_IRQ_DC_MASK_EOF = 44, - IPU_IRQ_PRP_ENC_ROT_IN_EOF = 45, - IPU_IRQ_PRP_VF_ROT_IN_EOF = 46, - IPU_IRQ_PP_ROT_IN_EOF = 47, - IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 48, - IPU_IRQ_PRP_VF_ROT_OUT_EOF = 49, - IPU_IRQ_PP_ROT_OUT_EOF = 50, - IPU_IRQ_BG_ALPHA_SYNC_EOF = 51, - IPU_IRQ_BG_ALPHA_ASYNC_EOF = 52, - - IPU_IRQ_DP_SF_START = 448 + 2, - IPU_IRQ_DP_SF_END = 448 + 3, - IPU_IRQ_BG_SF_END = IPU_IRQ_DP_SF_END, - IPU_IRQ_DC_FC_0 = 448 + 8, - IPU_IRQ_DC_FC_1 = 448 + 9, - IPU_IRQ_DC_FC_2 = 448 + 10, - IPU_IRQ_DC_FC_3 = 448 + 11, - IPU_IRQ_DC_FC_4 = 448 + 12, - IPU_IRQ_DC_FC_6 = 448 + 13, - IPU_IRQ_VSYNC_PRE_0 = 448 + 14, - IPU_IRQ_VSYNC_PRE_1 = 448 + 15, -#endif - - IPU_IRQ_COUNT -}; - -/*! - * Bitfield of Display Interface signal polarities. - */ -typedef struct { - unsigned datamask_en:1; - unsigned int_clk:1; - unsigned interlaced:1; - unsigned odd_field_first:1; - unsigned clksel_en:1; - unsigned clkidle_en:1; - unsigned data_pol:1; /* true = inverted */ - unsigned clk_pol:1; /* true = rising edge */ - unsigned enable_pol:1; - unsigned Hsync_pol:1; /* true = active high */ - unsigned Vsync_pol:1; -} ipu_di_signal_cfg_t; - -/*! - * Bitfield of CSI signal polarities and modes. - */ - -typedef struct { - unsigned data_width:4; - unsigned clk_mode:3; - unsigned ext_vsync:1; - unsigned Vsync_pol:1; - unsigned Hsync_pol:1; - unsigned pixclk_pol:1; - unsigned data_pol:1; - unsigned sens_clksrc:1; - unsigned pack_tight:1; - unsigned force_eof:1; - unsigned data_en_pol:1; - unsigned data_fmt; - unsigned csi; - unsigned mclk; -} ipu_csi_signal_cfg_t; - -/*! - * Enumeration of CSI data bus widths. - */ -enum { - IPU_CSI_DATA_WIDTH_4, - IPU_CSI_DATA_WIDTH_8, - IPU_CSI_DATA_WIDTH_10, - IPU_CSI_DATA_WIDTH_16, -}; - -/*! - * Enumeration of CSI clock modes. - */ -enum { - IPU_CSI_CLK_MODE_GATED_CLK, - IPU_CSI_CLK_MODE_NONGATED_CLK, - IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE, - IPU_CSI_CLK_MODE_CCIR656_INTERLACED, - IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR, - IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR, - IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR, - IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR, -}; - -enum { - IPU_CSI_MIPI_DI0, - IPU_CSI_MIPI_DI1, - IPU_CSI_MIPI_DI2, - IPU_CSI_MIPI_DI3, -}; - -typedef enum { - RGB, - YCbCr, - YUV -} ipu_color_space_t; - -/*! - * Enumeration of ADC vertical sync mode. - */ -typedef enum { - VsyncNone, - VsyncInternal, - VsyncCSI, - VsyncExternal -} vsync_t; - -typedef enum { - DAT, - CMD -} cmddata_t; - -/*! - * Enumeration of ADC display update mode. - */ -typedef enum { - IPU_ADC_REFRESH_NONE, - IPU_ADC_AUTO_REFRESH, - IPU_ADC_AUTO_REFRESH_SNOOP, - IPU_ADC_SNOOPING, -} ipu_adc_update_mode_t; - -/*! - * Enumeration of ADC display interface types (serial or parallel). - */ -enum { - IPU_ADC_IFC_MODE_SYS80_TYPE1, - IPU_ADC_IFC_MODE_SYS80_TYPE2, - IPU_ADC_IFC_MODE_SYS68K_TYPE1, - IPU_ADC_IFC_MODE_SYS68K_TYPE2, - IPU_ADC_IFC_MODE_3WIRE_SERIAL, - IPU_ADC_IFC_MODE_4WIRE_SERIAL, - IPU_ADC_IFC_MODE_5WIRE_SERIAL_CLK, - IPU_ADC_IFC_MODE_5WIRE_SERIAL_CS, -}; - -enum { - IPU_ADC_IFC_WIDTH_8, - IPU_ADC_IFC_WIDTH_16, -}; - -/*! - * Enumeration of ADC display interface burst mode. - */ -enum { - IPU_ADC_BURST_WCS, - IPU_ADC_BURST_WBLCK, - IPU_ADC_BURST_NONE, - IPU_ADC_BURST_SERIAL, -}; - -/*! - * Enumeration of ADC display interface RW signal timing modes. - */ -enum { - IPU_ADC_SER_NO_RW, - IPU_ADC_SER_RW_BEFORE_RS, - IPU_ADC_SER_RW_AFTER_RS, -}; - -/*! - * Bitfield of ADC signal polarities and modes. - */ -typedef struct { - unsigned data_pol:1; - unsigned clk_pol:1; - unsigned cs_pol:1; - unsigned rs_pol:1; - unsigned addr_pol:1; - unsigned read_pol:1; - unsigned write_pol:1; - unsigned Vsync_pol:1; - unsigned burst_pol:1; - unsigned burst_mode:2; - unsigned ifc_mode:3; - unsigned ifc_width:5; - unsigned ser_preamble_len:4; - unsigned ser_preamble:8; - unsigned ser_rw_mode:2; -} ipu_adc_sig_cfg_t; - -/*! - * Enumeration of ADC template commands. - */ -enum { - RD_DATA, - RD_ACK, - RD_WAIT, - WR_XADDR, - WR_YADDR, - WR_ADDR, - WR_CMND, - WR_DATA, -}; - -/*! - * Enumeration of ADC template command flow control. - */ -enum { - SINGLE_STEP, - PAUSE, - STOP, -}; - - -/*Define template constants*/ -#define ATM_ADDR_RANGE 0x20 /*offset address of DISP */ -#define TEMPLATE_BUF_SIZE 0x20 /*size of template */ - -/*! - * Define to create ADC template command entry. - */ -#define ipu_adc_template_gen(oc, rs, fc, dat) (((rs) << 29) | ((fc) << 27) | \ - ((oc) << 24) | (dat)) - -typedef struct { - u32 reg; - u32 value; -} ipu_lpmc_reg_t; - -#define IPU_LPMC_REG_READ 0x80000000L - -#define CSI_MCLK_VF 1 -#define CSI_MCLK_ENC 2 -#define CSI_MCLK_RAW 4 -#define CSI_MCLK_I2C 8 - -struct ipu_soc; -/* Common IPU API */ -struct ipu_soc *ipu_get_soc(int id); -int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params); -void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel); - -static inline bool ipu_can_rotate_in_place(ipu_rotate_mode_t rot) -{ -#ifdef CONFIG_MXC_IPU_V3D - return (rot < IPU_ROTATE_HORIZ_FLIP); -#else - return (rot < IPU_ROTATE_90_RIGHT); -#endif -} - -int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, - uint32_t pixel_fmt, - uint16_t width, uint16_t height, - uint32_t stride, - ipu_rotate_mode_t rot_mode, - dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, - dma_addr_t phyaddr_2, - uint32_t u_offset, uint32_t v_offset); - -int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, - uint32_t bufNum, dma_addr_t phyaddr); - -int32_t ipu_update_channel_offset(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, - uint32_t pixel_fmt, - uint16_t width, uint16_t height, - uint32_t stride, - uint32_t u, uint32_t v, - uint32_t vertical_offset, uint32_t horizontal_offset); - -int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel, - ipu_buffer_t type, uint32_t bufNum); -int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum); - -int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch); -int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch); - -int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel); -int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, - uint32_t bufNum); -void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, - uint32_t bufNum); -uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type); -int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel); -int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop); -int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch); - -int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi); -int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi); - -int ipu_lowpwr_display_enable(void); -int ipu_lowpwr_display_disable(void); - -void ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq); -void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq); -void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq); -int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq, - irqreturn_t(*handler) (int, void *), - uint32_t irq_flags, const char *devname, void *dev_id); -void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id); -bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq); -void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]); - -/* two stripe calculations */ -struct stripe_param{ - unsigned int input_width; /* width of the input stripe */ - unsigned int output_width; /* width of the output stripe */ - unsigned int input_column; /* the first column on the input stripe */ - unsigned int output_column; /* the first column on the output stripe */ - unsigned int idr; - /* inverse downisizing ratio parameter; expressed as a power of 2 */ - unsigned int irr; - /* inverse resizing ratio parameter; expressed as a multiple of 2^-13 */ -}; -int ipu_calc_stripes_sizes(const unsigned int input_frame_width, - unsigned int output_frame_width, - const unsigned int maximal_stripe_width, - const unsigned long long cirr, - const unsigned int equal_stripes, - u32 input_pixelformat, - u32 output_pixelformat, - struct stripe_param *left, - struct stripe_param *right); - -/* SDC API */ -int32_t ipu_sdc_init_panel(ipu_panel_t panel, - uint32_t pixel_clk, - uint16_t width, uint16_t height, - uint32_t pixel_fmt, - uint16_t hStartWidth, uint16_t hSyncWidth, - uint16_t hEndWidth, uint16_t vStartWidth, - uint16_t vSyncWidth, uint16_t vEndWidth, - ipu_di_signal_cfg_t sig); - -int32_t ipu_sdc_set_global_alpha(bool enable, uint8_t alpha); -int32_t ipu_sdc_set_color_key(ipu_channel_t channel, bool enable, - uint32_t colorKey); -int32_t ipu_sdc_set_brightness(uint8_t value); - -int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp, - uint32_t pixel_clk, - uint16_t width, uint16_t height, - uint32_t pixel_fmt, - uint16_t h_start_width, uint16_t h_sync_width, - uint16_t h_end_width, uint16_t v_start_width, - uint16_t v_sync_width, uint16_t v_end_width, - uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig); - -void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp); - -int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t x_pos, - int16_t y_pos); -int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t *x_pos, - int16_t *y_pos); -int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, - uint8_t alpha); -int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, - uint32_t colorKey); -int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, - int constk[], int slopek[]); - -int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time, - uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig); -void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset); -void ipu_reset_disp_panel(struct ipu_soc *ipu); - -/* ADC API */ -int32_t ipu_adc_write_template(display_port_t disp, uint32_t *pCmd, - bool write); - -int32_t ipu_adc_set_update_mode(ipu_channel_t channel, - ipu_adc_update_mode_t mode, - uint32_t refresh_rate, unsigned long addr, - uint32_t *size); - -int32_t ipu_adc_get_snooping_status(uint32_t *statl, uint32_t *stath); - -int32_t ipu_adc_write_cmd(display_port_t disp, cmddata_t type, - uint32_t cmd, const uint32_t *params, - uint16_t numParams); - -int32_t ipu_adc_init_panel(display_port_t disp, - uint16_t width, uint16_t height, - uint32_t pixel_fmt, - uint32_t stride, - ipu_adc_sig_cfg_t sig, - display_addressing_t addr, - uint32_t vsync_width, vsync_t mode); - -int32_t ipu_adc_init_ifc_timing(display_port_t disp, bool read, - uint32_t cycle_time, - uint32_t up_time, - uint32_t down_time, - uint32_t read_latch_time, uint32_t pixel_clk); - -/* CMOS Sensor Interface API */ -int32_t ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height, - uint32_t pixel_fmt, ipu_csi_signal_cfg_t sig); - -int32_t ipu_csi_get_sensor_protocol(struct ipu_soc *ipu, uint32_t csi); - -int32_t ipu_csi_enable_mclk(struct ipu_soc *ipu, int src, bool flag, bool wait); - -static inline int32_t ipu_csi_enable_mclk_if(struct ipu_soc *ipu, int src, uint32_t csi, - bool flag, bool wait) -{ -#ifdef CONFIG_MXC_IPU_V1 - return ipu_csi_enable_mclk(ipu, src, flag, wait); -#else - return ipu_csi_enable_mclk(ipu, csi, flag, wait); -#endif -} - -int ipu_csi_read_mclk_flag(void); - -void ipu_csi_flash_strobe(bool flag); - -void ipu_csi_get_window_size(struct ipu_soc *ipu, uint32_t *width, uint32_t *height, uint32_t csi); - -void ipu_csi_set_window_size(struct ipu_soc *ipu, uint32_t width, uint32_t height, uint32_t csi); - -void ipu_csi_set_window_pos(struct ipu_soc *ipu, uint32_t left, uint32_t top, uint32_t csi); - -/* Post Filter functions */ -int32_t ipu_pf_set_pause_row(uint32_t pause_row); - -uint32_t bytes_per_pixel(uint32_t fmt); - /* IPU device */ struct ipu_pos { u32 x; -- cgit v1.2.3 From 433dcab893a40595c0a70a5180fd2c97c6b2fb63 Mon Sep 17 00:00:00 2001 From: Jason Chen Date: Thu, 29 Sep 2011 09:22:07 +0800 Subject: ENGR00158456-1 ipuv3 dev: return error for split mode with rotation Currently we do not support split mode with rotation. Signed-off-by: Jason Chen --- include/linux/ipu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux') diff --git a/include/linux/ipu.h b/include/linux/ipu.h index d6c1588b82c..17638ab1512 100644 --- a/include/linux/ipu.h +++ b/include/linux/ipu.h @@ -237,6 +237,7 @@ enum { IPU_CHECK_ERR_SPLIT_INPUTH_OVER, IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER, IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER, + IPU_CHECK_ERR_SPLIT_WITH_ROT, }; /* IOCTL commands */ -- cgit v1.2.3 From dc6e4d2285bb2e4757f004c9beceb04b3e98fde2 Mon Sep 17 00:00:00 2001 From: Jason Chen Date: Thu, 27 Oct 2011 09:32:41 +0800 Subject: ENGR00160875-1 ipuv3 dev: low performance if enable rotation 1. no dma alloc for rot buf every time which will cost time. 2. fix split mode condition. 3. export some functions. This patch for common head file. Signed-off-by: Jason Chen --- include/linux/ipu.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'include/linux') diff --git a/include/linux/ipu.h b/include/linux/ipu.h index 17638ab1512..05162485455 100644 --- a/include/linux/ipu.h +++ b/include/linux/ipu.h @@ -138,6 +138,12 @@ typedef enum { /*! @} */ /* IPU device */ +typedef enum { + RGB_CS, + YUV_CS, + NULL_CS +} cs_t; + struct ipu_pos { u32 x; u32 y; @@ -246,4 +252,14 @@ enum { #define IPU_ALLOC _IOWR('I', 0x3, int) #define IPU_FREE _IOW('I', 0x4, int) +/* export functions */ +#ifdef __KERNEL__ +unsigned int fmt_to_bpp(unsigned int pixelformat); +cs_t colorspaceofpixel(int fmt); +int need_csc(int ifmt, int ofmt); + +int ipu_queue_task(struct ipu_task *task); +int ipu_check_task(struct ipu_task *task); +#endif + #endif -- cgit v1.2.3 From 378757ab3d41b492ac85f7d93c82b5b0d8347ed2 Mon Sep 17 00:00:00 2001 From: Jason Chen Date: Thu, 27 Oct 2011 10:31:51 +0800 Subject: ENGR00160878-1 mxc v4l2 output: new mxc v4l2 output driver based on videobuf This new v4l2 output driver is based on videobuf, using dma contig alloc method. It creates video dev node for each display framebuffer begin from /dev/video16 by default. If need post-processing, this driver will do it by ipu pp driver which support: - resizing - CSC - rotate - deinterlacing If no need post-processing, the IPU IC will be bypassed as old driver, the buf will be set to fb buffer directly by crack fb smem_start. The user should do setting before streamon like below: 1. set output crop 2. set ctrl like rotate/vflip/hflip/deinterlacing motion 3. set fmt 4. reqbuf The new features compare to old driver: - support multi-instance - support user point buffer - runtime suspend/resume For suspend/resume, still has chance to meet issue on mx6q, will fix later. This patch for head file. Signed-off-by: Jason Chen --- include/linux/mxc_v4l2.h | 23 +---------------------- 1 file changed, 1 insertion(+), 22 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mxc_v4l2.h b/include/linux/mxc_v4l2.h index e83e5923c2a..95e8d9e64c7 100644 --- a/include/linux/mxc_v4l2.h +++ b/include/linux/mxc_v4l2.h @@ -22,27 +22,6 @@ #ifndef __ASM_ARCH_MXC_V4L2_H__ #define __ASM_ARCH_MXC_V4L2_H__ -/* - * For IPUv1 and IPUv3, V4L2_CID_MXC_ROT means encoder ioctl ID. - * And V4L2_CID_MXC_VF_ROT is viewfinder ioctl ID only for IPUv1 and IPUv3. - */ -#define V4L2_CID_MXC_ROT (V4L2_CID_PRIVATE_BASE + 0) -#define V4L2_CID_MXC_FLASH (V4L2_CID_PRIVATE_BASE + 1) -#define V4L2_CID_MXC_VF_ROT (V4L2_CID_PRIVATE_BASE + 2) -#define V4L2_CID_MXC_MOTION (V4L2_CID_PRIVATE_BASE + 3) - -#define V4L2_MXC_ROTATE_NONE 0 -#define V4L2_MXC_ROTATE_VERT_FLIP 1 -#define V4L2_MXC_ROTATE_HORIZ_FLIP 2 -#define V4L2_MXC_ROTATE_180 3 -#define V4L2_MXC_ROTATE_90_RIGHT 4 -#define V4L2_MXC_ROTATE_90_RIGHT_VFLIP 5 -#define V4L2_MXC_ROTATE_90_RIGHT_HFLIP 6 -#define V4L2_MXC_ROTATE_90_LEFT 7 - -struct v4l2_mxc_offset { - uint32_t u_offset; - uint32_t v_offset; -}; +#define V4L2_CID_MXC_MOTION (V4L2_CID_PRIVATE_BASE + 0) #endif -- cgit v1.2.3