path: root/arch/sparc64/kernel/mdesc.c
AgeCommit message (Collapse)Author
2007-09-16[SPARC64]: Warn user if cpu is ignored.David S. Miller
When NR_CPUS is smaller than the cpu probed, let the user know that the cpu won't be used. Suggested by Al Viro. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-15[SPARC64]: Allow userspace to get at the machine description.David S. Miller
Like the OF device tree, it's useful to let userland get at the machine description so it can pretty print the graph etc. The implementation is a simple MISC device with a read method. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-07[SPARC]: Centralize find_in_proplist() instead of duplicating N times.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-20[SPARC64]: fix section mismatch warning in mdesc.cSam Ravnborg
Fix following warning: WARNING: vmlinux.o(.text+0x35264): Section mismatch: reference to .init.text:__alloc_bootmem (between 'mdesc_bootmem_alloc' and 'mdesc_bootmem_free') Rename mdesc_mem_ops to *_ops so modpost ignores __init references and declare mdesc_bootmem_alloc __init since it is only used during __init context. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-19[SPARC64]: Fix handling of multiple vdc-port nodes.David S. Miller
The "id" property in vdc-port nodes are not unique, they are all zero. Therefore assign ID's using the parent's "cfg-handle" property which will be unique. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-18[SPARC64]: Add basic infrastructure for MD add/remove notification.David S. Miller
And add dummy handlers for the VIO device layer. These will be filled in with real code after the vdc, vnet, and ds drivers are reworked to have simpler dependencies on the VIO device tree. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-16[SPARC64]: Fix race between MD update and dr-cpu add.David S. Miller
We need to make sure the MD update occurs before we try to process dr-cpu configure requests. MD update and dr-cpu were being processed by seperate threads so that did not happen occaisionally. Fix this by executing all domain services data packets from a single thread, in order. This will help simplify some other things as well. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-16[SPARC64]: mdesc.c needs linux/mm.hDavid S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-16[SPARC64]: Initial LDOM cpu hotplug support.David S. Miller
Only adding cpus is supports at the moment, removal will come next. When new cpus are configured, the machine description is updated. When we get the configure request we pass in a cpu mask of to-be-added cpus to the mdesc CPU node parser so it only fetches information for those cpus. That code also proceeds to update the SMT/multi-core scheduling bitmaps. cpu_up() does all the work and we return the status back over the DS channel. CPUs via dr-cpu need to be booted straight out of the hypervisor, and this requires: 1) A new trampoline mechanism. CPUs are booted straight out of the hypervisor with MMU disabled and running in physical addresses with no mappings installed in the TLB. The new hvtramp.S code sets up the critical cpu state, installs the locked TLB mappings for the kernel, and turns the MMU on. It then proceeds to follow the logic of the existing trampoline.S SMP cpu bringup code. 2) All calls into OBP have to be disallowed when domaining is enabled. Since cpus boot straight into the kernel from the hypervisor, OBP has no state about that cpu and therefore cannot handle being invoked on that cpu. Luckily it's only a handful of interfaces which can be called after the OBP device tree is obtained. For example, rebooting, halting, powering-off, and setting options node variables. CPU removal support will require some infrastructure changes here. Namely we'll have to process the requests via a true kernel thread instead of in a workqueue. workqueues run on a per-cpu thread, but when unconfiguring we might need to force the thread to execute on another cpu if the current cpu is the one being removed. Removal of a cpu also causes the kernel to destroy that cpu's workqueue running thread. Another issue on removal is that we may have interrupts still pointing to the cpu-to-be-removed. So new code will be needed to walk the active INO list and retarget those cpus as-needed. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-16[SPARC64]: Abstract out mdesc accesses for better MD update handling.David S. Miller
Since we have to be able to handle MD updates, having an in-tree set of data structures representing the MD objects actually makes things more painful. The MD itself is easy to parse, and we can implement the existing interfaces using direct parsing of the MD binary image. The MD is now reference counted, so accesses have to now take the form: handle = mdesc_grab(); ... operations on MD ... mdesc_release(handle); The only remaining issue are cases where code holds on to references to MD property values. mdesc_get_property() returns a direct pointer to the property value, most cases just pull in the information they need and discard the pointer, but there are few that use the pointer directly over a long lifetime. Those will be fixed up in a subsequent changeset. A preliminary handler for MD update events from domain services is there, it is rudimentry but it works and handles all of the reference counting. It does not check the generation number of the MDs, and it does not generate a "add/delete" list for notification to interesting parties about MD changes but that will be forthcoming. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-06-04[SPARC64]: Fix {mc,smt}_capable().David S. Miller
It's not just sun4v hypervisor platforms that should return true for this, sun4u with UltraSPARC-IV should return true too. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-06-04[SPARC64]: Proper multi-core scheduling support.David S. Miller
The scheduling domain hierarchy is: all cpus --> cpus that share an instruction cache --> cpus that share an integer execution unit Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-29[SPARC64]: Use machine description and OBP properly for cpu probing.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>