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Add flexcan support.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Add support for ASRC driver in MX6 sabre-lite
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
(cherry picked from commit 6fc9c1edb695b2743464efe4375f9ab659a9f6fc)
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In MX6 gpu2d core clock setting, gpu3d core clock field is misued
to set 2d core clock rate. Correct it to use the right clock field
Signed-off-by: Larry Li <b20787@freescale.com>
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The ASRC mem to mem mode does not work without this patch.
Bacause 1.5Mhz clock rate is not available which will cause
clock setting fail, change to 7.5Mhz (the mininum one) to make
ASRC work properly.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Need to decline SOC LDO domain voltage to make 800M ARM2 board work,
we can set the SOC power domain to be same as ARM core power domain.
Tested on both 1G rework board and 800M origin board.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Previous setting for ARM core is 1V during suspend, it
is working for 800MHz cpu freq, but not enough for
1G cpu freq, actually, we didn't need to change ARM core
LDO's setting during suspend, hardware will auto change it.
Signed-off-by: Anson Huang <b20788@freescale.com>
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- An well-behavior class driver should disable their endpoints
after being notified disconnect with host, we use all endpoints
are stopped (ep->stopped) to indicates the class
driver will not visit device driver any more.
the ep-stopped will be initialized as 1 for non-control endpoint
it will be 0 after fsl_ep_enable, and be 1 after fsl_ep_disable.
Where is a non-sleep wait routine at disconnect event for waiting all
endpoints are stopped
- Some controller's (like i.mx6q) DP will change from J
to SE0 slowly after the cable disconnects with host, in that case there
will be a wakeup interrupt after driver enables the wakeup interrupt.
For i.mx6q, there is a discharge routine for DP after the disconnection.
- Should not wait vbus to low during first otg switch, as the wait will
be timeout when the usb cable is connecting to host.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Set the ARM LDO voltage to 1.225V to run the part at 1GHz.
Also updated the rest of the voltages based on the latest
available working points.
The boards will need to be modified for this change to work
correctly. Please ensure that the VDDARM_IN is set to 1.38V
(using the potentiometer on the ARM2 board or choosing the correct
resistors on the sabrelite boards).
Also added command line option (arm_freq=800) to set the max ARM freq.
Add:
arm_freq=1000 -> to set the max ARM freq to 1GHz
arm_freq=800 -> to set the max ARM freq to 800MHz.
Default max ARM freq is 1GHz. No other values are currently
supported. If your board is not modified, please add the command
line "arm_freq=800' to avoid failures.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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fix pin conflict between sd vselect and canbus enable pin.
add 'canbus' to the cmdline will enable canbus driver.
if canbus driver is enabled, sd 3.0 card will not work
Signed-off-by: Tony Lin <tony.lin@freescale.com>
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This reverts commit 564e25cb10cd827ea3fa5cda2487fd978f08bbd7.
Sourcing ARM_CLK from PLL2_PFD_400M is causing issues when setting
the ARM_PODF. So for now source arm_clk from PLL1_SYS_MAIN only.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add basic bluetooth support to mx6q platform:
1) Enable bluetooth driver by default
2) Configure uart2 which is used by bluetooth
Signed-off-by: Lionel Xu <Lionel.Xu@freescale.com>
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These two irqs can't be masked together, otherwise, system
will crash when only booting up one core, and NFS can only
work with 4 cores running. Need hardware team to help find
the root cause, this is only a temp work around.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Relocking of PLL sometimes takes longer than 1msec when PLL is
enabled after a power down. The kernel panics if the PLL is not locked
in 1ms. Max time expected by HW is only 500us.
Workaround is to disable the output of the PLL and set it in bypass
mode when its output is not being used.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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OpenVG can not work with latest kernel
this is caused by some gpu2d clock changes.
Signed-off-by: Wu Guoxing <b39297@freescale.com>
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This can fix the following issue:
root@freescale ~$ ./ip link set can1 up type can bitrate 125000
flexcan imx6q-flexcan.1: writing ctrl=0x0e312005
------------[ cut here ]------------
WARNING: at drivers/gpio/gpiolib.c:1593 __gpio_set_value+0x64/0x74()
Modules linked in:
[<8005499c>] (unwind_backtrace+0x0/0x108) from [<804db0e8>] (dump_stack+0x20/0x24)
[<804db0e8>] (dump_stack+0x20/0x24) from [<80079ac0>] (warn_slowpath_common+0x5c/0x74)
[<80079ac0>] (warn_slowpath_common+0x5c/0x74) from [<80079b04>] (warn_slowpath_null+0x2c/0x34)
[<80079b04>] (warn_slowpath_null+0x2c/0x34) from [<80297d50>] (__gpio_set_value+0x64/0x74)
[<80297d50>] (__gpio_set_value+0x64/0x74) from [<80064630>] (mx6q_flexcan1_switch+0x50/0x54)
[<80064630>] (mx6q_flexcan1_switch+0x50/0x54) from [<80324bf0>] (flexcan_chip_start+0x2dc/0x378)
[<80324bf0>] (flexcan_chip_start+0x2dc/0x378) from [<80324d0c>] (flexcan_open+0x80/0xe8)
[<80324d0c>] (flexcan_open+0x80/0xe8) from [<8041b7a8>] (__dev_open+0xac/0xf8)
[<8041b7a8>] (__dev_open+0xac/0xf8) from [<80418848>] (__dev_change_flags+0x90/0x148)
[<80418848>] (__dev_change_flags+0x90/0x148) from [<8041b6c4>] (dev_change_flags+0x20/0x58)
[<8041b6c4>] (dev_change_flags+0x20/0x58) from [<804292d8>] (do_setlink+0x1a0/0x7b4)
[<804292d8>] (do_setlink+0x1a0/0x7b4) from [<8042a734>] (rtnl_newlink+0x438/0x488)
[<8042a734>] (rtnl_newlink+0x438/0x488) from [<8042a2d4>] (rtnetlink_rcv_msg+0x200/0x228)
[<8042a2d4>] (rtnetlink_rcv_msg+0x200/0x228) from [<80434e88>] (netlink_rcv_skb+0xcc/0xe8)
[<80434e88>] (netlink_rcv_skb+0xcc/0xe8) from [<8042a0cc>] (rtnetlink_rcv+0x2c/0x34)
[<8042a0cc>] (rtnetlink_rcv+0x2c/0x34) from [<80434aac>] (netlink_unicast+0x2c0/0x328)
[<80434aac>] (netlink_unicast+0x2c0/0x328) from [<804354a0>] (netlink_sendmsg+0x22c/0x350)
[<804354a0>] (netlink_sendmsg+0x22c/0x350) from [<80406e24>] (sock_sendmsg+0xa4/0xc4)
[<80406e24>] (sock_sendmsg+0xa4/0xc4) from [<804073a4>] (sys_sendmsg+0x140/0x270)
[<804073a4>] (sys_sendmsg+0x140/0x270) from [<8004dc40>] (ret_fast_syscall+0x0/0x30)
---[ end trace 4612d184c78ddab8 ]---
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Acked-by: Lily Zhang
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Align the implementation, eventually this should go to a common place
across MX6 platforms
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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- Fix the building warning:
common.h:75: warning: 'struct fec_platform_data' declared
inside parameter list
Signed-off-by: Fugang Duan <B38611@freescale.com>
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- The clock formula has error, fix the get clock rate
for FEC module.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Update the PAD settings to lower pull-up resistor as this was
causing WP to not be detected.
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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Add config USB OC setting code for mx6q, and make the OC default off.
After adding it, fixing the loop less code during kernel boot in mx6qLite.
Signed-off-by: make shi <b15407@freescale.com>
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- FEC get the default MAC address from OCOTP.
- If the MAC address is all zero, get the random address.
- But, if add para "fec_mac=xx:xx:xx:xx:xx:xx" in uboot,
FEC will get the last MAC address from uboot para.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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1. Config MIPI CSI2 driver as a default build in driver
2. Change ov5640 mipi sensor as a module
Signed-off-by: Even Xu <b21019@freescale.com>
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- IEEE 1588 use 40MHz divided from pll3 480MHz. And use 480M ddr
init script. So, cannot disable pll3 in clock.c file.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Dynamically checking whether enable spdif or flexcan via a boot
param 'spdif'.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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64k is too small for uboot.
So enlarge the partition to 256K.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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[MX6] OTG load fail when remove all usb module
Signed-off-by: make shi <b15407@freescale.com>
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arch/arm/mach-mx6/cpu.c:39: warning:
'arm_base' defined but not used.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add support to access SST SPI-NOR on MX6 Sabre-lite
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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When WAIT mode is not enabled, execute cpu_do_idle() code.
Currently WAIT mode requires the code to be run from IRAM with caches disabled.
No L2 cache access should be done for a specified period after the system exits
WAIT mode. This delay and running code from IRAM adversely affects the
SDHC performance.
Hardware team is looking into the extended delay that is required.
Till its root caused, default should be to execute cpu_do_idle() and
disable entry into WAIT mode.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add support for HDMI audio on MX6 Sabre-lite
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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fix section mismatch warning
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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- Set Phy AR8031 to saving power mode while no cable connect.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Initialize MIPI CSI2 platform data
Signed-off-by: Even Xu <b21019@freescale.com>
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Enable OTG driver on mx6q board
Signed-off-by: make shi <b15407@freescale.com>
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MSL part
Add HSIC support for Host2 and Host3, for HSIC mode, there
is not usb phy needed, the usb device is always at the board
- Validation hardware: iMX6Q Validation Port Card and Re-worked
Rev X3 board, for hardware rework detail, contact Ken Sun (b03826)
- Validation device: HSIC interface SMSC HUB(USB4640) and Host 3.
Host 2 is coding finishes, but not verified due to hardware limitation.
- Pin Conflict with Ethernet, order to use HSIC, the user need
disable ethernet function at both u-boot and linux kernel.
For u-boot: please undefine CONFIG_MXC_FEC at your board config file
For kernel: please define CONFIG_USB_EHCI_ARC_HSIC, the entry is:
Device Drivers---> USB support---> Support HSIC Host controller
for Freescale SoC
- Suspend/resume and wakeup are not supported due to IC issues,
these IC issues will be fixed at TO1.1 for i.mx6, software will
add these support after receiving TO1.1 chip.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Both S/PDIF in and I2C3 SDA use GPIO_16, so only one can be enabled
at a time.
Add early param "spdif_in" to enable S/PDIF in. Default is to
enable I2C3 and leave S/PDIF in disabled.
Signed-off-by: Alan Tull <alan.tull@freescale.com>
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Add flexcan support.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Current warm reset is not working with MMDC_CH1 bypass
bit set, now we disable warm reset to workaround it for
the coming release. Then, wdog reset will be cold reset.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add clock enable code to arch.
OCOTP driver missed code to enable clock in driver.
Thus if ocotp clock is not enabled in clock.c, ocotp will not work.
We will remove ocotp clock enable code in board file and leave this
operation to driver.
Signed-off-by: Terry Lv <r65388@freescale.com>
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add pwm-backlight driver on mx6q arm2 board
Signed-off-by: Gary Zhang <b13634@freescale.com>
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Add dummy regulators for MMC and SD drivers.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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Add dummy regulators for CS42888 CODEC.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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MX6 MIPI DSI: Add MIPI DSI driver and support for TRULY WVGA LCD panel
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Add dummy regulators for MMC and SD drivers.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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Add support for the PWM module under MX6. Sabre-lite uses
this for controlling the LVDS backlight
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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Add support for the MX6 Sabre-lite board
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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Move the codec regulator registration code to the board
specific file
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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1.modify config
2.add board level support ecspi
3.add ecspi pad configure
Signed-off-by: Robin Gong <B38343@freescale.com>
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Machine layer patch.
Sabreauto is an inaccurate name for the Armadillo2 board that
this code is actually meant for. So, renamed "sabreauto" board file,
configs, and code to "arm2". Created a new machine id for
ARM2 board.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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1. Add Anatop regulator support.
2. Add some dummy regulators support for audio codec.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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