| Age | Commit message (Collapse) | Author |
|---|
|
Preserve bad block indication of NAND
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
MX23: Fix CPU frequency can not be changed after LCD is off if mDDR is used.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
|
|
Disabling PLL3 was causing failure to boot from MMC slot0.
Move SDHC clocks to be sourced from PLL2 instead of PLL3.
Signed-off-by: Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com>
|
|
Fixed long-term video playback issue due to incorrect increment of
clock usecount.
Fixed various bugs associated with system entering LP-APM mode.
Fixed incorrect enabling of PLL3 that was not allowing system to enter
LP-APM mode if TVE was built in.
EMI_GARB clock needs to be enabled when certain clock dividers are changed.
Signed-off-by: Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com>
|
|
Use the DMA mode in normal, and revert to PIO mode when
there are small data transmissions.
Signed-off-by: Richard Zhu <r65037@freescale.com>
|
|
Change mmc clock setting to fit new clock driver
Signed-off-by: Jeremy Yao <r65161@freescale.com>
|
|
Unset SPS bit, allow normal parity check
Signed-off-by: Jeremy Yao <r65161@freescale.com>
|
|
- add set_rate functionality for x_clk.
Added the x_set_rate and x_round_rate functions. A lower
x_clk rate will be used for the lowest power 24Mhz state.
This implementation to be added later into cpufreq but
going ahead and providing the necessary clock driver
functionality now.
- add enable/disable functionality to ref clocks
Assigned the enable and disable function pointers
of each of the *_ref_clk tables to the mx23 enable
and disable functions.
- change lcd clock (default) parent to ref_pix
Self explanatory. Previously this was incorrectly
assigned directly to the PLL which would cause
ref_pix clock to never be gated when not being
used which causes very small but unnecessary
additional power usage to occur when the LCD is disabled.
- add hbus autoslow function to be used by cpufreq
Added this function for eventual used by cpufreq driver.
- fix pll_enable() delay
This delay was changed to match delay requirements given
in the mx23 reference manual from the definition of the
PLLCTRL0 POWER bitfield.
- revise emi_set_rate
emi_set_rate had several small issues.
The amount of iram it was asking for was set to an
arbitrary amount instead of being assigned to the
size of the assembly code. Instead, assigning it
to the size of the assembly code.
When no changes in emiclk speed were being made, we didn't
need to spend the time allocating iram, disabling fiqs/irqs,
and jumping to the assembly routines Added checks to
minimize the time spent in emi_set_rate if then new
clock divisors were the same as the old.
Added functionality for switching the parent between
ref_emi_clk and ref_xtal_clk source based on the clock
speed.
- added "set_sys_dependent_parent" functionality to allow
the reduction some of the peripheral clocks (mainly SSP
and GPMI) during the lowest power 24MHz cpu_clk state
was needed to allow the PLL to turn off and achieve
minimum power usage for that state. The
"set_sys_dependent_parent" functionality implements this
functionality by checking the cpu speed and changing the
parent as needed (but only when the ref count is zero).
- other minor cleanup
In a couple of locations, I saw the following syntax being used:
> -val &= ~(BM_CLKCTRL_FRAC_CPUFRAC << BP_CLKCTRL_FRAC_CPUFRAC);
> -val |= clkctrl_frac;
This was incorrect because the BM_ definition is already
shifted to the correct bitfield location of the register.
Shifting it over further by BP_ is a bug. This bug
didn't cause problems in these cases because the BP_
value happended to be zero, but needed cleaning up anyway.
The mx23_raw_enable was being called without any delays
to ensure the clock was ready for use. Added a call
to check the clock busy bit to ensure the clock is ready
before being used.
- Added clock_busy_wait function which replaced all the
individual busy_wait handling and properly accounts for
clocks with xtal source (which use a separate xtal
sourced busy bit).
- Cleaned up xtal and rtc clocks/sources functionality.
- Added functionality to SSP and GPMI set_rate function
to allow changing the parent clock to the xtal if the
rate is a factor of 24MHz.
Signed-off-by: Robert Lee <robert.lee@freescale.com>
|
|
MX53 NAND defconfig support
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
MX53 NAND driver support
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
MX53 NAND mach support
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
Get resources from platform data
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
MX28:Dual ENET mach support
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
MX28 has two MAC,but External PHY can only be configed by MAC0
which means PHY1 should be configed by MAC0 according to IC spec.
This patch enable dual ENET support. If want to test rootfs from
eth1, can add ip=:::::eth1:dhcp in the command line
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Rob Herring <r.herring@freescale.com>
|
|
Add FEC phy interface mode platform data for platforms using RMII.
Signed-off-by: Rob Herring <r.herring@freescale.com>
|
|
This fixes RMII support which was broken by phylib support.
Signed-off-by: Rob Herring <r.herring@freescale.com>
|
|
operation
BugLink: http://bugs.launchpad.net/bugs/546649
BugLink: http://bugs.launchpad.net/bugs/457878
After introducing phylib supporting, users experienced performace drop. That is
because of the mdio polling operation of phylib. Use msleep to replace the busy
waiting cpu_relax() and remove the warning message.
Signed-off-by: Bryan Wu <bryan.wu@canonical.com>
Acked-by: Andy Whitcroft <apw@canonical.com>
Signed-off-by: Andy Whitcroft <apw@canonical.com>
|
|
BugLink: http://bugs.launchpad.net/bugs/546649
BugLink: http://bugs.launchpad.net/bugs/457878
- remove duplicated phy_speed caculation
- fix the phy_speed caculation according to the DataSheet
Signed-off-by: Bryan Wu <bryan.wu@canonical.com>
Acked-by: Andy Whitcroft <apw@canonical.com>
Signed-off-by: Andy Whitcroft <apw@canonical.com>
|
|
BugLink: http://bugs.launchpad.net/bugs/457878
Missed to set .ndo_do_ioctl as fec_enet_ioctl, so will generate a compiling
warning due to nobody uses fec_enet_ioctl. This patch fixed that.
Signed-off-by: Bryan Wu <bryan.wu@canonical.com>
Acked-by: Amit Kucheria <amit.kucheria@canonical.com>
Acked-by: Colin King <colin.king@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
|
|
netdev/fec.c: add phylib supporting to enable carrier detection
BugLink: http://bugs.launchpad.net/bugs/457878
- removed old MII phy control code
- add phylib supporting
- add ethtool interface to make user space NetworkManager works
This patch is ready for upstream, it will be pushed to upstream for merge
Signed-off-by: Bryan Wu <bryan.wu@canonical.com>
Acked-by: Amit Kucheria <amit.kucheria@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
|
|
Deleted the old drivers.
Broke the driver into separate files, for readability and to isolate
hardware dependencies.
Fixed bad block problems in the boot area for the i.MX23.
At this writing, UBI can't handle MTDs larger than 2GiB. If the
general use partition is larger than 2GiB, the driver will create
sub-partitions, none of which are larger than 2GiB.
Updated the default configs for the i.MX23 and i.MX28.
Other, miscellaneous changes.
Signed-off-by: Patrick Turley <patrick.turley@freescale.com>
|
|
Enable IDMAC WM enable bit when enable corresponding
DMFC channel's watermark.
Signed-off-by: Liu Ying <b17645@freescale.com>
|
|
Fix build error debug options selected for power driver
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
|
|
IDMAC's EBA/UBO/VBO/ILO are 8-byte aligned.
This patch will check the values for EBA/UBO/VBO/ILO 8-byte aligned.
If not, the driver will give out warning information.
Signed-off-by: Liu Ying <b17645@freescale.com>
|
|
Add keypad memory resource in MX31 3-stack platform
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
Add Keypad mem resource in MX25 platform
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
1. Get mem from platform resource in mxc keypad driver
2. Remove unnecessory header file
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
MX23: CPU frequency can not be changed to 64 MHz.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
|
|
MX23 w/ mDDR: EMI clock change code causes crashes with 24MHz state transitions.
Signed-off-by: Robert Lee <robert.lee@freescale.com>
|
|
Firmware will be copied to the /lib/firmware/ath6k/AR6102 directory
so change the path in the driver.
Signed-off-by: Alan Tull <r80115@freescale.com>
|
|
The max packet length bit mask used for isochronous endpoints should
be 0x7FF instead of 0x8FF. 0x8FF will actually clear higher-order bits
in the max packet length field.
Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
|
|
1. Remove iomux warning in boot
2. Put I2C PIN configurations into table
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
Fixed cpufreq-set can not work when fb0 is blank.
Fixed incorrect clock dividers
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
|
|
Add SPI NOR support in MX53 EVK
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
Add support for MLB by adding MLB MSL codes.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
|
|
Set correct stride for non-interleave fmt, if not, will cause v4l output
play uncorrectly for ic_bypass mode.
Signed-off-by: Jason Chen <b02280@freescale.com>
|
|
mx28: build broken after commit a5421893d5.
Signed-off-by: Robert Lee <robert.lee@freescale.com>
|
|
Changes such that DAC Mux will only affect whether the headphone
output gets connected to the DAC or Line in.
The previous implementation of the DAC Mux allowed the dapm power
level of the sgtl5000 to be affected whether audio was playing or
not. It also controlled the an internal osc which had no effect
since it didn't affect whether mclk was turned on.
Signed-off-by: Alan Tull <r80115@freescale.com>
|
|
Add functionality of using OTP key for crypto into dcp driver
Signed-off-by: Anish Trivedi <anish@freescale.com>
|
|
clock ref wrong set to __s8
Signed-off-by: Frank Li <Frank.Li@freescale.com>
|
|
iMX53 was not in list of parts that include VDI, iMX53 was add.
Signed-off-by: Ran Ferderber r53561@freescale.com
|
|
The WP bit is set in the 4Bytes wifi write operations
accidentally.
That would cause the INT wouldn't be generated.
There is no such kind issue in SD/MMC write operations.
Since that the BUS load on wifi maybe much lighter than
that when SD/MMC is used.
Remove the 100K pull up pad configuration on the eSDHC1
WP pin can solve this issue.
Or
Remove the SION configuration can fix this issue too.
In the end, the second method is used.
Unify the platform data configurations, and enable the registers
dump when there are errors in the execution of esdhc driver.
Signed-off-by: Richard Zhu <r65037@freescale.com>
|
|
This driver unifies the i.MX23 and i.MX28 NAND Flash drivers into a single
driver that supports both SoC's.
Signed-off-by: Patrick Turley <patrick.turley@freescale.com>
|
|
The current method of changing the cpu FRAC and integer
dividers can cause short-term unexpectedly high frequencies.
Also, h_clk temporarily runs higher than expected as well.
Signed-off-by: Robert Lee <robert.lee@freescale.com>
|
|
Enable TVOUT of mxs.
Signed-off-by: Frank Li <frank.li@freescale.com>
|
|
Add original stmp378x tvenc.c
Signed-off-by: Frank Li <Frank.Li@freescale.com>
|
|
Fix SDIO INTR
Signed-off-by: Jeremy Yao <r65161@freescale.com>
|
|
Users may confuse old imx23 kernel default configration, so delete them
Signed-off-by: Peter Chen <b29397@freescale.com>
|
|
Add imx23evk updater default configration without nand support
Signed-off-by: Peter Chen <b29397@freescale.com>
|
|
Pass memory and irq information via resources in MX5 platforms
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
