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-rw-r--r--include/acpi/acmacros.h6
-rw-r--r--include/acpi/platform/acgcc.h2
-rw-r--r--include/asm-arm/plat-s3c/debug-macro.S75
-rw-r--r--include/asm-arm/plat-s3c/map.h40
-rw-r--r--include/asm-arm/plat-s3c/regs-adc.h60
-rw-r--r--include/asm-arm/plat-s3c/regs-serial.h232
-rw-r--r--include/asm-arm/plat-s3c/regs-timer.h115
-rw-r--r--include/asm-arm/plat-s3c/uncompress.h155
-rw-r--r--include/asm-arm/plat-s3c24xx/clock.h64
-rw-r--r--include/asm-arm/plat-s3c24xx/common-smdk.h15
-rw-r--r--include/asm-arm/plat-s3c24xx/cpu.h54
-rw-r--r--include/asm-arm/plat-s3c24xx/devs.h49
-rw-r--r--include/asm-arm/plat-s3c24xx/dma.h82
-rw-r--r--include/asm-arm/plat-s3c24xx/irq.h109
-rw-r--r--include/asm-arm/plat-s3c24xx/pm.h73
-rw-r--r--include/asm-arm/plat-s3c24xx/s3c2400.h31
-rw-r--r--include/asm-arm/plat-s3c24xx/s3c2410.h31
-rw-r--r--include/asm-arm/plat-s3c24xx/s3c2412.h29
-rw-r--r--include/asm-arm/plat-s3c24xx/s3c2440.h17
-rw-r--r--include/asm-arm/plat-s3c24xx/s3c2442.h17
-rw-r--r--include/asm-arm/plat-s3c24xx/s3c2443.h32
-rw-r--r--include/asm-cris/a.out.h26
-rw-r--r--include/asm-cris/elf.h2
-rw-r--r--include/asm-cris/thread_info.h2
-rw-r--r--include/asm-frv/elf.h2
-rw-r--r--include/asm-frv/ide.h10
-rw-r--r--include/asm-frv/unaligned.h2
-rw-r--r--include/asm-generic/bug.h4
-rw-r--r--include/asm-generic/gpio.h18
-rw-r--r--include/asm-generic/rtc.h24
-rw-r--r--include/asm-generic/siginfo.h2
-rw-r--r--include/asm-generic/statfs.h65
-rw-r--r--include/asm-generic/vmlinux.lds.h25
-rw-r--r--include/asm-h8300/timer.h25
-rw-r--r--include/asm-m32r/a.out.h20
-rw-r--r--include/asm-m32r/elf.h2
-rw-r--r--include/asm-m68k/atarihw.h1
-rw-r--r--include/asm-m68k/dma-mapping.h16
-rw-r--r--include/asm-m68k/dma.h4
-rw-r--r--include/asm-m68k/elf.h2
-rw-r--r--include/asm-m68k/entry.h2
-rw-r--r--include/asm-m68k/ide.h9
-rw-r--r--include/asm-m68k/io.h66
-rw-r--r--include/asm-m68k/pci.h47
-rw-r--r--include/asm-m68k/thread_info.h1
-rw-r--r--include/asm-m68k/virtconvert.h6
-rw-r--r--include/asm-mips/Kbuild3
-rw-r--r--include/asm-mips/a.out.h35
-rw-r--r--include/asm-mips/abi.h25
-rw-r--r--include/asm-mips/addrspace.h154
-rw-r--r--include/asm-mips/asm.h409
-rw-r--r--include/asm-mips/asmmacro-32.h158
-rw-r--r--include/asm-mips/asmmacro-64.h139
-rw-r--r--include/asm-mips/asmmacro.h82
-rw-r--r--include/asm-mips/atomic.h801
-rw-r--r--include/asm-mips/auxvec.h4
-rw-r--r--include/asm-mips/barrier.h155
-rw-r--r--include/asm-mips/bcache.h60
-rw-r--r--include/asm-mips/bitops.h672
-rw-r--r--include/asm-mips/bootinfo.h110
-rw-r--r--include/asm-mips/branch.h38
-rw-r--r--include/asm-mips/break.h34
-rw-r--r--include/asm-mips/bug.h33
-rw-r--r--include/asm-mips/bugs.h53
-rw-r--r--include/asm-mips/byteorder.h76
-rw-r--r--include/asm-mips/cache.h20
-rw-r--r--include/asm-mips/cachectl.h26
-rw-r--r--include/asm-mips/cacheflush.h116
-rw-r--r--include/asm-mips/cacheops.h85
-rw-r--r--include/asm-mips/cevt-r4k.h46
-rw-r--r--include/asm-mips/checksum.h260
-rw-r--r--include/asm-mips/cmp.h18
-rw-r--r--include/asm-mips/cmpxchg.h124
-rw-r--r--include/asm-mips/compat-signal.h119
-rw-r--r--include/asm-mips/compat.h221
-rw-r--r--include/asm-mips/compiler.h19
-rw-r--r--include/asm-mips/cpu-features.h219
-rw-r--r--include/asm-mips/cpu-info.h84
-rw-r--r--include/asm-mips/cpu.h267
-rw-r--r--include/asm-mips/cputime.h6
-rw-r--r--include/asm-mips/current.h23
-rw-r--r--include/asm-mips/debug.h48
-rw-r--r--include/asm-mips/dec/ecc.h55
-rw-r--r--include/asm-mips/dec/interrupts.h126
-rw-r--r--include/asm-mips/dec/ioasic.h38
-rw-r--r--include/asm-mips/dec/ioasic_addrs.h152
-rw-r--r--include/asm-mips/dec/ioasic_ints.h74
-rw-r--r--include/asm-mips/dec/kn01.h90
-rw-r--r--include/asm-mips/dec/kn02.h91
-rw-r--r--include/asm-mips/dec/kn02ba.h67
-rw-r--r--include/asm-mips/dec/kn02ca.h79
-rw-r--r--include/asm-mips/dec/kn02xa.h84
-rw-r--r--include/asm-mips/dec/kn03.h74
-rw-r--r--include/asm-mips/dec/kn05.h76
-rw-r--r--include/asm-mips/dec/kn230.h26
-rw-r--r--include/asm-mips/dec/machtype.h27
-rw-r--r--include/asm-mips/dec/prom.h174
-rw-r--r--include/asm-mips/dec/system.h19
-rw-r--r--include/asm-mips/delay.h112
-rw-r--r--include/asm-mips/device.h7
-rw-r--r--include/asm-mips/div64.h110
-rw-r--r--include/asm-mips/dma-mapping.h81
-rw-r--r--include/asm-mips/dma.h315
-rw-r--r--include/asm-mips/ds1286.h15
-rw-r--r--include/asm-mips/ds1287.h27
-rw-r--r--include/asm-mips/dsp.h85
-rw-r--r--include/asm-mips/edac.h34
-rw-r--r--include/asm-mips/elf.h371
-rw-r--r--include/asm-mips/emergency-restart.h6
-rw-r--r--include/asm-mips/emma2rh/emma2rh.h333
-rw-r--r--include/asm-mips/emma2rh/markeins.h75
-rw-r--r--include/asm-mips/errno.h131
-rw-r--r--include/asm-mips/fb.h19
-rw-r--r--include/asm-mips/fcntl.h61
-rw-r--r--include/asm-mips/fixmap.h118
-rw-r--r--include/asm-mips/floppy.h56
-rw-r--r--include/asm-mips/fpregdef.h99
-rw-r--r--include/asm-mips/fpu.h153
-rw-r--r--include/asm-mips/fpu_emulator.h37
-rw-r--r--include/asm-mips/futex.h203
-rw-r--r--include/asm-mips/fw/arc/hinv.h175
-rw-r--r--include/asm-mips/fw/arc/types.h86
-rw-r--r--include/asm-mips/fw/cfe/cfe_api.h122
-rw-r--r--include/asm-mips/fw/cfe/cfe_error.h80
-rw-r--r--include/asm-mips/gcmpregs.h117
-rw-r--r--include/asm-mips/gic.h487
-rw-r--r--include/asm-mips/gpio.h6
-rw-r--r--include/asm-mips/gt64120.h580
-rw-r--r--include/asm-mips/hardirq.h24
-rw-r--r--include/asm-mips/hazards.h271
-rw-r--r--include/asm-mips/highmem.h67
-rw-r--r--include/asm-mips/hw_irq.h20
-rw-r--r--include/asm-mips/i8253.h21
-rw-r--r--include/asm-mips/i8259.h86
-rw-r--r--include/asm-mips/ide.h13
-rw-r--r--include/asm-mips/inst.h394
-rw-r--r--include/asm-mips/io.h589
-rw-r--r--include/asm-mips/ioctl.h94
-rw-r--r--include/asm-mips/ioctls.h109
-rw-r--r--include/asm-mips/ip32/crime.h158
-rw-r--r--include/asm-mips/ip32/ip32_ints.h114
-rw-r--r--include/asm-mips/ip32/mace.h365
-rw-r--r--include/asm-mips/ipcbuf.h28
-rw-r--r--include/asm-mips/irq.h163
-rw-r--r--include/asm-mips/irq_cpu.h20
-rw-r--r--include/asm-mips/irq_gt641xx.h60
-rw-r--r--include/asm-mips/irq_regs.h21
-rw-r--r--include/asm-mips/irqflags.h283
-rw-r--r--include/asm-mips/isadep.h34
-rw-r--r--include/asm-mips/jazz.h310
-rw-r--r--include/asm-mips/jazzdma.h95
-rw-r--r--include/asm-mips/kdebug.h13
-rw-r--r--include/asm-mips/kexec.h30
-rw-r--r--include/asm-mips/kgdb.h44
-rw-r--r--include/asm-mips/kmap_types.h30
-rw-r--r--include/asm-mips/kspd.h36
-rw-r--r--include/asm-mips/lasat/ds1603.h18
-rw-r--r--include/asm-mips/lasat/eeprom.h17
-rw-r--r--include/asm-mips/lasat/head.h22
-rw-r--r--include/asm-mips/lasat/lasat.h258
-rw-r--r--include/asm-mips/lasat/lasatint.h14
-rw-r--r--include/asm-mips/lasat/picvue.h15
-rw-r--r--include/asm-mips/lasat/serial.h13
-rw-r--r--include/asm-mips/linkage.h10
-rw-r--r--include/asm-mips/local.h221
-rw-r--r--include/asm-mips/m48t35.h27
-rw-r--r--include/asm-mips/m48t37.h35
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h1772
-rw-r--r--include/asm-mips/mach-au1x00/au1000_dma.h458
-rw-r--r--include/asm-mips/mach-au1x00/au1000_gpio.h56
-rw-r--r--include/asm-mips/mach-au1x00/au1100_mmc.h208
-rw-r--r--include/asm-mips/mach-au1x00/au1550_spi.h15
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx.h43
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_dbdma.h386
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_ide.h194
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_psc.h505
-rw-r--r--include/asm-mips/mach-au1x00/gpio.h69
-rw-r--r--include/asm-mips/mach-au1x00/ioremap.h42
-rw-r--r--include/asm-mips/mach-au1x00/prom.h13
-rw-r--r--include/asm-mips/mach-au1x00/war.h25
-rw-r--r--include/asm-mips/mach-bcm47xx/bcm47xx.h25
-rw-r--r--include/asm-mips/mach-bcm47xx/gpio.h59
-rw-r--r--include/asm-mips/mach-bcm47xx/war.h25
-rw-r--r--include/asm-mips/mach-cobalt/cobalt.h22
-rw-r--r--include/asm-mips/mach-cobalt/cpu-feature-overrides.h56
-rw-r--r--include/asm-mips/mach-cobalt/irq.h57
-rw-r--r--include/asm-mips/mach-cobalt/mach-gt64120.h27
-rw-r--r--include/asm-mips/mach-cobalt/war.h25
-rw-r--r--include/asm-mips/mach-db1x00/db1200.h230
-rw-r--r--include/asm-mips/mach-db1x00/db1x00.h179
-rw-r--r--include/asm-mips/mach-dec/mc146818rtc.h43
-rw-r--r--include/asm-mips/mach-dec/war.h25
-rw-r--r--include/asm-mips/mach-emma2rh/irq.h15
-rw-r--r--include/asm-mips/mach-emma2rh/war.h25
-rw-r--r--include/asm-mips/mach-excite/cpu-feature-overrides.h48
-rw-r--r--include/asm-mips/mach-excite/excite.h154
-rw-r--r--include/asm-mips/mach-excite/excite_fpga.h80
-rw-r--r--include/asm-mips/mach-excite/excite_nandflash.h7
-rw-r--r--include/asm-mips/mach-excite/rm9k_eth.h23
-rw-r--r--include/asm-mips/mach-excite/rm9k_wdt.h12
-rw-r--r--include/asm-mips/mach-excite/rm9k_xicap.h16
-rw-r--r--include/asm-mips/mach-excite/war.h25
-rw-r--r--include/asm-mips/mach-generic/cpu-feature-overrides.h13
-rw-r--r--include/asm-mips/mach-generic/dma-coherence.h45
-rw-r--r--include/asm-mips/mach-generic/floppy.h139
-rw-r--r--include/asm-mips/mach-generic/gpio.h21
-rw-r--r--include/asm-mips/mach-generic/ide.h167
-rw-r--r--include/asm-mips/mach-generic/ioremap.h34
-rw-r--r--include/asm-mips/mach-generic/irq.h45
-rw-r--r--include/asm-mips/mach-generic/kernel-entry-init.h25
-rw-r--r--include/asm-mips/mach-generic/kmalloc.h13
-rw-r--r--include/asm-mips/mach-generic/mangle-port.h52
-rw-r--r--include/asm-mips/mach-generic/mc146818rtc.h36
-rw-r--r--include/asm-mips/mach-generic/spaces.h85
-rw-r--r--include/asm-mips/mach-generic/topology.h1
-rw-r--r--include/asm-mips/mach-ip22/cpu-feature-overrides.h44
-rw-r--r--include/asm-mips/mach-ip22/ds1286.h18
-rw-r--r--include/asm-mips/mach-ip22/spaces.h27
-rw-r--r--include/asm-mips/mach-ip22/war.h29
-rw-r--r--include/asm-mips/mach-ip27/cpu-feature-overrides.h54
-rw-r--r--include/asm-mips/mach-ip27/dma-coherence.h50
-rw-r--r--include/asm-mips/mach-ip27/irq.h22
-rw-r--r--include/asm-mips/mach-ip27/kernel-entry-init.h59
-rw-r--r--include/asm-mips/mach-ip27/kmalloc.h8
-rw-r--r--include/asm-mips/mach-ip27/mangle-port.h25
-rw-r--r--include/asm-mips/mach-ip27/mmzone.h36
-rw-r--r--include/asm-mips/mach-ip27/spaces.h30
-rw-r--r--include/asm-mips/mach-ip27/topology.h59
-rw-r--r--include/asm-mips/mach-ip27/war.h25
-rw-r--r--include/asm-mips/mach-ip28/cpu-feature-overrides.h50
-rw-r--r--include/asm-mips/mach-ip28/ds1286.h4
-rw-r--r--include/asm-mips/mach-ip28/spaces.h22
-rw-r--r--include/asm-mips/mach-ip28/war.h25
-rw-r--r--include/asm-mips/mach-ip32/cpu-feature-overrides.h50
-rw-r--r--include/asm-mips/mach-ip32/dma-coherence.h72
-rw-r--r--include/asm-mips/mach-ip32/kmalloc.h11
-rw-r--r--include/asm-mips/mach-ip32/mangle-port.h26
-rw-r--r--include/asm-mips/mach-ip32/mc146818rtc.h36
-rw-r--r--include/asm-mips/mach-ip32/war.h25
-rw-r--r--include/asm-mips/mach-jazz/dma-coherence.h40
-rw-r--r--include/asm-mips/mach-jazz/floppy.h135
-rw-r--r--include/asm-mips/mach-jazz/mc146818rtc.h38
-rw-r--r--include/asm-mips/mach-jazz/war.h25
-rw-r--r--include/asm-mips/mach-lasat/irq.h13
-rw-r--r--include/asm-mips/mach-lasat/mach-gt64120.h27
-rw-r--r--include/asm-mips/mach-lasat/war.h25
-rw-r--r--include/asm-mips/mach-lemote/dma-coherence.h42
-rw-r--r--include/asm-mips/mach-lemote/mc146818rtc.h36
-rw-r--r--include/asm-mips/mach-lemote/war.h25
-rw-r--r--include/asm-mips/mach-malta/cpu-feature-overrides.h72
-rw-r--r--include/asm-mips/mach-malta/irq.h9
-rw-r--r--include/asm-mips/mach-malta/kernel-entry-init.h52
-rw-r--r--include/asm-mips/mach-malta/mach-gt64120.h19
-rw-r--r--include/asm-mips/mach-malta/mc146818rtc.h48
-rw-r--r--include/asm-mips/mach-malta/war.h25
-rw-r--r--include/asm-mips/mach-mipssim/cpu-feature-overrides.h65
-rw-r--r--include/asm-mips/mach-mipssim/war.h25
-rw-r--r--include/asm-mips/mach-pb1x00/mc146818rtc.h34
-rw-r--r--include/asm-mips/mach-pb1x00/pb1000.h87
-rw-r--r--include/asm-mips/mach-pb1x00/pb1100.h85
-rw-r--r--include/asm-mips/mach-pb1x00/pb1200.h259
-rw-r--r--include/asm-mips/mach-pb1x00/pb1500.h49
-rw-r--r--include/asm-mips/mach-pb1x00/pb1550.h177
-rw-r--r--include/asm-mips/mach-pnx8550/cm.h43
-rw-r--r--include/asm-mips/mach-pnx8550/glb.h86
-rw-r--r--include/asm-mips/mach-pnx8550/int.h140
-rw-r--r--include/asm-mips/mach-pnx8550/kernel-entry-init.h262
-rw-r--r--include/asm-mips/mach-pnx8550/nand.h121
-rw-r--r--include/asm-mips/mach-pnx8550/pci.h185
-rw-r--r--include/asm-mips/mach-pnx8550/uart.h30
-rw-r--r--include/asm-mips/mach-pnx8550/usb.h32
-rw-r--r--include/asm-mips/mach-pnx8550/war.h25
-rw-r--r--include/asm-mips/mach-rc32434/cpu-feature-overrides.h81
-rw-r--r--include/asm-mips/mach-rc32434/ddr.h141
-rw-r--r--include/asm-mips/mach-rc32434/dma.h103
-rw-r--r--include/asm-mips/mach-rc32434/dma_v.h52
-rw-r--r--include/asm-mips/mach-rc32434/eth.h220
-rw-r--r--include/asm-mips/mach-rc32434/gpio.h126
-rw-r--r--include/asm-mips/mach-rc32434/integ.h59
-rw-r--r--include/asm-mips/mach-rc32434/irq.h8
-rw-r--r--include/asm-mips/mach-rc32434/pci.h481
-rw-r--r--include/asm-mips/mach-rc32434/prom.h44
-rw-r--r--include/asm-mips/mach-rc32434/rb.h81
-rw-r--r--include/asm-mips/mach-rc32434/rc32434.h61
-rw-r--r--include/asm-mips/mach-rc32434/timer.h65
-rw-r--r--include/asm-mips/mach-rc32434/war.h25
-rw-r--r--include/asm-mips/mach-rm/cpu-feature-overrides.h43
-rw-r--r--include/asm-mips/mach-rm/mc146818rtc.h21
-rw-r--r--include/asm-mips/mach-rm/war.h29
-rw-r--r--include/asm-mips/mach-sibyte/cpu-feature-overrides.h47
-rw-r--r--include/asm-mips/mach-sibyte/war.h37
-rw-r--r--include/asm-mips/mach-tx39xx/ioremap.h38
-rw-r--r--include/asm-mips/mach-tx39xx/mangle-port.h23
-rw-r--r--include/asm-mips/mach-tx39xx/war.h25
-rw-r--r--include/asm-mips/mach-tx49xx/cpu-feature-overrides.h23
-rw-r--r--include/asm-mips/mach-tx49xx/ioremap.h43
-rw-r--r--include/asm-mips/mach-tx49xx/kmalloc.h8
-rw-r--r--include/asm-mips/mach-tx49xx/war.h25
-rw-r--r--include/asm-mips/mach-vr41xx/irq.h8
-rw-r--r--include/asm-mips/mach-vr41xx/war.h25
-rw-r--r--include/asm-mips/mach-wrppmc/mach-gt64120.h83
-rw-r--r--include/asm-mips/mach-wrppmc/war.h25
-rw-r--r--include/asm-mips/mach-yosemite/cpu-feature-overrides.h47
-rw-r--r--include/asm-mips/mach-yosemite/war.h25
-rw-r--r--include/asm-mips/mc146818-time.h119
-rw-r--r--include/asm-mips/mc146818rtc.h16
-rw-r--r--include/asm-mips/mips-boards/bonito64.h436
-rw-r--r--include/asm-mips/mips-boards/generic.h104
-rw-r--r--include/asm-mips/mips-boards/launch.h35
-rw-r--r--include/asm-mips/mips-boards/malta.h102
-rw-r--r--include/asm-mips/mips-boards/maltaint.h110
-rw-r--r--include/asm-mips/mips-boards/msc01_pci.h258
-rw-r--r--include/asm-mips/mips-boards/piix4.h80
-rw-r--r--include/asm-mips/mips-boards/prom.h47
-rw-r--r--include/asm-mips/mips-boards/sim.h40
-rw-r--r--include/asm-mips/mips-boards/simint.h31
-rw-r--r--include/asm-mips/mips_mt.h26
-rw-r--r--include/asm-mips/mipsmtregs.h395
-rw-r--r--include/asm-mips/mipsprom.h76
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-rw-r--r--include/net/phonet/pep.h160
-rw-r--r--include/net/phonet/phonet.h112
-rw-r--r--include/net/phonet/pn_dev.h50
-rw-r--r--include/net/pkt_sched.h5
-rw-r--r--include/net/route.h11
-rw-r--r--include/net/sch_generic.h1
-rw-r--r--include/net/sctp/constants.h4
-rw-r--r--include/net/sctp/sctp.h12
-rw-r--r--include/net/sctp/structs.h34
-rw-r--r--include/net/sctp/tsnmap.h53
-rw-r--r--include/net/sock.h19
-rw-r--r--include/net/tc_act/tc_skbedit.h34
-rw-r--r--include/net/tcp.h52
-rw-r--r--include/net/udp.h21
-rw-r--r--include/net/wireless.h65
-rw-r--r--include/net/xfrm.h104
-rw-r--r--include/pcmcia/ciscode.h2
-rw-r--r--include/pcmcia/cistpl.h38
-rw-r--r--include/pcmcia/cs.h165
-rw-r--r--include/pcmcia/cs_types.h8
-rw-r--r--include/pcmcia/device_id.h18
-rw-r--r--include/pcmcia/ds.h411
-rw-r--r--include/pcmcia/ss.h202
-rw-r--r--include/scsi/iscsi_if.h2
-rw-r--r--include/scsi/libiscsi.h15
-rw-r--r--include/scsi/scsi.h6
-rw-r--r--include/scsi/scsi_device.h10
-rw-r--r--include/scsi/scsi_transport_fc.h8
-rw-r--r--include/scsi/scsi_transport_iscsi.h5
-rw-r--r--include/sound/ad1848.h218
-rw-r--r--include/sound/asound.h52
-rw-r--r--include/sound/asoundef.h89
-rw-r--r--include/sound/core.h35
-rw-r--r--include/sound/cs4231.h175
-rw-r--r--include/sound/jack.h75
-rw-r--r--include/sound/memalloc.h18
-rw-r--r--include/sound/minors.h2
-rw-r--r--include/sound/pcm.h39
-rw-r--r--include/sound/pxa2xx-lib.h45
-rw-r--r--include/sound/sb.h5
-rw-r--r--include/sound/snd_wavefront.h1
-rw-r--r--include/sound/soc-dapm.h1
-rw-r--r--include/sound/soc-of-simple.h25
-rw-r--r--include/sound/soc.h74
-rw-r--r--include/sound/tea575x-tuner.h1
-rw-r--r--include/sound/version.h2
-rw-r--r--include/sound/vx_core.h9
-rw-r--r--include/sound/wss.h235
-rw-r--r--include/trace/sched.h56
-rw-r--r--include/video/atmel_lcdc.h1
-rw-r--r--include/video/cyblafb.h2
-rw-r--r--include/video/metronomefb.h31
-rw-r--r--include/video/neomagic.h1
-rw-r--r--include/video/radeon.h23
-rw-r--r--include/video/s1d13xxxfb.h3
-rw-r--r--include/video/sh_mobile_lcdc.h78
-rw-r--r--include/xen/balloon.h61
-rw-r--r--include/xen/events.h2
1115 files changed, 17765 insertions, 78647 deletions
diff --git a/include/acpi/acmacros.h b/include/acpi/acmacros.h
index 57ab9e9d759..74a9617776a 100644
--- a/include/acpi/acmacros.h
+++ b/include/acpi/acmacros.h
@@ -467,7 +467,7 @@ struct acpi_integer_overlay {
/*
* If ACPI_GET_FUNCTION_NAME was not defined in the compiler-dependent header,
* define it now. This is the case where there the compiler does not support
- * a __FUNCTION__ macro or equivalent.
+ * a __func__ macro or equivalent.
*/
#ifndef ACPI_GET_FUNCTION_NAME
#define ACPI_GET_FUNCTION_NAME _acpi_function_name
@@ -475,12 +475,12 @@ struct acpi_integer_overlay {
* The Name parameter should be the procedure name as a quoted string.
* The function name is also used by the function exit macros below.
* Note: (const char) is used to be compatible with the debug interfaces
- * and macros such as __FUNCTION__.
+ * and macros such as __func__.
*/
#define ACPI_FUNCTION_NAME(name) static const char _acpi_function_name[] = #name;
#else
-/* Compiler supports __FUNCTION__ (or equivalent) -- Ignore this macro */
+/* Compiler supports __func__ (or equivalent) -- Ignore this macro */
#define ACPI_FUNCTION_NAME(name)
#endif
diff --git a/include/acpi/platform/acgcc.h b/include/acpi/platform/acgcc.h
index 8996dba90cd..8e2cdc57b19 100644
--- a/include/acpi/platform/acgcc.h
+++ b/include/acpi/platform/acgcc.h
@@ -46,7 +46,7 @@
/* Function name is used for debug output. Non-ANSI, compiler-dependent */
-#define ACPI_GET_FUNCTION_NAME __FUNCTION__
+#define ACPI_GET_FUNCTION_NAME __func__
/*
* This macro is used to tag functions as "printf-like" because
diff --git a/include/asm-arm/plat-s3c/debug-macro.S b/include/asm-arm/plat-s3c/debug-macro.S
deleted file mode 100644
index 84c40b847da..00000000000
--- a/include/asm-arm/plat-s3c/debug-macro.S
+++ /dev/null
@@ -1,75 +0,0 @@
-/* linux/include/asm-arm/plat-s3c/debug-macro.S
- *
- * Copyright 2005, 2007 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <asm/plat-s3c/regs-serial.h>
-
-/* The S3C2440 implementations are used by default as they are the
- * most widely re-used */
-
- .macro fifo_level_s3c2440 rd, rx
- ldr \rd, [ \rx, # S3C2410_UFSTAT ]
- and \rd, \rd, #S3C2440_UFSTAT_TXMASK
- .endm
-
-#ifndef fifo_level
-#define fifo_level fifo_level_s3c2410
-#endif
-
- .macro fifo_full_s3c2440 rd, rx
- ldr \rd, [ \rx, # S3C2410_UFSTAT ]
- tst \rd, #S3C2440_UFSTAT_TXFULL
- .endm
-
-#ifndef fifo_full
-#define fifo_full fifo_full_s3c2440
-#endif
-
- .macro senduart,rd,rx
- strb \rd, [\rx, # S3C2410_UTXH ]
- .endm
-
- .macro busyuart, rd, rx
- ldr \rd, [ \rx, # S3C2410_UFCON ]
- tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
- beq 1001f @
- @ FIFO enabled...
-1003:
- fifo_full \rd, \rx
- bne 1003b
- b 1002f
-
-1001:
- @ busy waiting for non fifo
- ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
- tst \rd, #S3C2410_UTRSTAT_TXFE
- beq 1001b
-
-1002: @ exit busyuart
- .endm
-
- .macro waituart,rd,rx
- ldr \rd, [ \rx, # S3C2410_UFCON ]
- tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
- beq 1001f @
- @ FIFO enabled...
-1003:
- fifo_level \rd, \rx
- teq \rd, #0
- bne 1003b
- b 1002f
-1001:
- @ idle waiting for non fifo
- ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
- tst \rd, #S3C2410_UTRSTAT_TXFE
- beq 1001b
-
-1002: @ exit busyuart
- .endm
diff --git a/include/asm-arm/plat-s3c/map.h b/include/asm-arm/plat-s3c/map.h
deleted file mode 100644
index b84289d32a5..00000000000
--- a/include/asm-arm/plat-s3c/map.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/include/asm-arm/plat-s3c/map.h
- *
- * Copyright 2003, 2007 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C - Memory map definitions (virtual addresses)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_MAP_H
-#define __ASM_PLAT_MAP_H __FILE__
-
-/* Fit all our registers in at 0xF4000000 upwards, trying to use as
- * little of the VA space as possible so vmalloc and friends have a
- * better chance of getting memory.
- *
- * we try to ensure stuff like the IRQ registers are available for
- * an single MOVS instruction (ie, only 8 bits of set data)
- */
-
-#define S3C_ADDR_BASE (0xF4000000)
-
-#ifndef __ASSEMBLY__
-#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x))
-#else
-#define S3C_ADDR(x) (S3C_ADDR_BASE + (x))
-#endif
-
-#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */
-#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */
-#define S3C_VA_MEM S3C_ADDR(0x00200000) /* system control */
-#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */
-#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */
-#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */
-
-#endif /* __ASM_PLAT_MAP_H */
diff --git a/include/asm-arm/plat-s3c/regs-adc.h b/include/asm-arm/plat-s3c/regs-adc.h
deleted file mode 100644
index 4323cccc86c..00000000000
--- a/include/asm-arm/plat-s3c/regs-adc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-adc.h
- *
- * Copyright (c) 2004 Shannon Holland <holland@loser.net>
- *
- * This program is free software; yosu can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 ADC registers
-*/
-
-#ifndef __ASM_ARCH_REGS_ADC_H
-#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
-
-#define S3C2410_ADCREG(x) (x)
-
-#define S3C2410_ADCCON S3C2410_ADCREG(0x00)
-#define S3C2410_ADCTSC S3C2410_ADCREG(0x04)
-#define S3C2410_ADCDLY S3C2410_ADCREG(0x08)
-#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C)
-#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
-
-
-/* ADCCON Register Bits */
-#define S3C2410_ADCCON_ECFLG (1<<15)
-#define S3C2410_ADCCON_PRSCEN (1<<14)
-#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6)
-#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6)
-#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3)
-#define S3C2410_ADCCON_MUXMASK (0x7<<3)
-#define S3C2410_ADCCON_STDBM (1<<2)
-#define S3C2410_ADCCON_READ_START (1<<1)
-#define S3C2410_ADCCON_ENABLE_START (1<<0)
-#define S3C2410_ADCCON_STARTMASK (0x3<<0)
-
-
-/* ADCTSC Register Bits */
-#define S3C2410_ADCTSC_YM_SEN (1<<7)
-#define S3C2410_ADCTSC_YP_SEN (1<<6)
-#define S3C2410_ADCTSC_XM_SEN (1<<5)
-#define S3C2410_ADCTSC_XP_SEN (1<<4)
-#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3)
-#define S3C2410_ADCTSC_AUTO_PST (1<<2)
-#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0)
-
-/* ADCDAT0 Bits */
-#define S3C2410_ADCDAT0_UPDOWN (1<<15)
-#define S3C2410_ADCDAT0_AUTO_PST (1<<14)
-#define S3C2410_ADCDAT0_XY_PST (0x3<<12)
-#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF)
-
-/* ADCDAT1 Bits */
-#define S3C2410_ADCDAT1_UPDOWN (1<<15)
-#define S3C2410_ADCDAT1_AUTO_PST (1<<14)
-#define S3C2410_ADCDAT1_XY_PST (0x3<<12)
-#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF)
-
-#endif /* __ASM_ARCH_REGS_ADC_H */
-
-
diff --git a/include/asm-arm/plat-s3c/regs-serial.h b/include/asm-arm/plat-s3c/regs-serial.h
deleted file mode 100644
index a0daa647b92..00000000000
--- a/include/asm-arm/plat-s3c/regs-serial.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-serial.h
- *
- * From linux/include/asm-arm/hardware/serial_s3c2410.h
- *
- * Internal header file for Samsung S3C2410 serial ports (UART0-2)
- *
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *
- * Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
- *
- * Adapted from:
- *
- * Internal header file for MX1ADS serial ports (UART1 & 2)
- *
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#ifndef __ASM_ARM_REGS_SERIAL_H
-#define __ASM_ARM_REGS_SERIAL_H
-
-#define S3C24XX_VA_UART0 (S3C_VA_UART)
-#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
-#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
-#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )
-
-#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
-#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
-#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
-#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
-
-#define S3C2410_URXH (0x24)
-#define S3C2410_UTXH (0x20)
-#define S3C2410_ULCON (0x00)
-#define S3C2410_UCON (0x04)
-#define S3C2410_UFCON (0x08)
-#define S3C2410_UMCON (0x0C)
-#define S3C2410_UBRDIV (0x28)
-#define S3C2410_UTRSTAT (0x10)
-#define S3C2410_UERSTAT (0x14)
-#define S3C2410_UFSTAT (0x18)
-#define S3C2410_UMSTAT (0x1C)
-
-#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
-
-#define S3C2410_LCON_CS5 (0x0)
-#define S3C2410_LCON_CS6 (0x1)
-#define S3C2410_LCON_CS7 (0x2)
-#define S3C2410_LCON_CS8 (0x3)
-#define S3C2410_LCON_CSMASK (0x3)
-
-#define S3C2410_LCON_PNONE (0x0)
-#define S3C2410_LCON_PEVEN (0x5 << 3)
-#define S3C2410_LCON_PODD (0x4 << 3)
-#define S3C2410_LCON_PMASK (0x7 << 3)
-
-#define S3C2410_LCON_STOPB (1<<2)
-#define S3C2410_LCON_IRM (1<<6)
-
-#define S3C2440_UCON_CLKMASK (3<<10)
-#define S3C2440_UCON_PCLK (0<<10)
-#define S3C2440_UCON_UCLK (1<<10)
-#define S3C2440_UCON_PCLK2 (2<<10)
-#define S3C2440_UCON_FCLK (3<<10)
-#define S3C2443_UCON_EPLL (3<<10)
-
-#define S3C2440_UCON2_FCLK_EN (1<<15)
-#define S3C2440_UCON0_DIVMASK (15 << 12)
-#define S3C2440_UCON1_DIVMASK (15 << 12)
-#define S3C2440_UCON2_DIVMASK (7 << 12)
-#define S3C2440_UCON_DIVSHIFT (12)
-
-#define S3C2412_UCON_CLKMASK (3<<10)
-#define S3C2412_UCON_UCLK (1<<10)
-#define S3C2412_UCON_USYSCLK (3<<10)
-#define S3C2412_UCON_PCLK (0<<10)
-#define S3C2412_UCON_PCLK2 (2<<10)
-
-#define S3C2410_UCON_UCLK (1<<10)
-#define S3C2410_UCON_SBREAK (1<<4)
-
-#define S3C2410_UCON_TXILEVEL (1<<9)
-#define S3C2410_UCON_RXILEVEL (1<<8)
-#define S3C2410_UCON_TXIRQMODE (1<<2)
-#define S3C2410_UCON_RXIRQMODE (1<<0)
-#define S3C2410_UCON_RXFIFO_TOI (1<<7)
-#define S3C2443_UCON_RXERR_IRQEN (1<<6)
-#define S3C2443_UCON_LOOPBACK (1<<5)
-
-#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
- S3C2410_UCON_RXILEVEL | \
- S3C2410_UCON_TXIRQMODE | \
- S3C2410_UCON_RXIRQMODE | \
- S3C2410_UCON_RXFIFO_TOI)
-
-#define S3C2410_UFCON_FIFOMODE (1<<0)
-#define S3C2410_UFCON_TXTRIG0 (0<<6)
-#define S3C2410_UFCON_RXTRIG8 (1<<4)
-#define S3C2410_UFCON_RXTRIG12 (2<<4)
-
-/* S3C2440 FIFO trigger levels */
-#define S3C2440_UFCON_RXTRIG1 (0<<4)
-#define S3C2440_UFCON_RXTRIG8 (1<<4)
-#define S3C2440_UFCON_RXTRIG16 (2<<4)
-#define S3C2440_UFCON_RXTRIG32 (3<<4)
-
-#define S3C2440_UFCON_TXTRIG0 (0<<6)
-#define S3C2440_UFCON_TXTRIG16 (1<<6)
-#define S3C2440_UFCON_TXTRIG32 (2<<6)
-#define S3C2440_UFCON_TXTRIG48 (3<<6)
-
-#define S3C2410_UFCON_RESETBOTH (3<<1)
-#define S3C2410_UFCON_RESETTX (1<<2)
-#define S3C2410_UFCON_RESETRX (1<<1)
-
-#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
- S3C2410_UFCON_TXTRIG0 | \
- S3C2410_UFCON_RXTRIG8 )
-
-#define S3C2410_UMCOM_AFC (1<<4)
-#define S3C2410_UMCOM_RTS_LOW (1<<0)
-
-#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
-#define S3C2412_UMCON_AFC_56 (1<<5)
-#define S3C2412_UMCON_AFC_48 (2<<5)
-#define S3C2412_UMCON_AFC_40 (3<<5)
-#define S3C2412_UMCON_AFC_32 (4<<5)
-#define S3C2412_UMCON_AFC_24 (5<<5)
-#define S3C2412_UMCON_AFC_16 (6<<5)
-#define S3C2412_UMCON_AFC_8 (7<<5)
-
-#define S3C2410_UFSTAT_TXFULL (1<<9)
-#define S3C2410_UFSTAT_RXFULL (1<<8)
-#define S3C2410_UFSTAT_TXMASK (15<<4)
-#define S3C2410_UFSTAT_TXSHIFT (4)
-#define S3C2410_UFSTAT_RXMASK (15<<0)
-#define S3C2410_UFSTAT_RXSHIFT (0)
-
-/* UFSTAT S3C2443 same as S3C2440 */
-#define S3C2440_UFSTAT_TXFULL (1<<14)
-#define S3C2440_UFSTAT_RXFULL (1<<6)
-#define S3C2440_UFSTAT_TXSHIFT (8)
-#define S3C2440_UFSTAT_RXSHIFT (0)
-#define S3C2440_UFSTAT_TXMASK (63<<8)
-#define S3C2440_UFSTAT_RXMASK (63)
-
-#define S3C2410_UTRSTAT_TXE (1<<2)
-#define S3C2410_UTRSTAT_TXFE (1<<1)
-#define S3C2410_UTRSTAT_RXDR (1<<0)
-
-#define S3C2410_UERSTAT_OVERRUN (1<<0)
-#define S3C2410_UERSTAT_FRAME (1<<2)
-#define S3C2410_UERSTAT_BREAK (1<<3)
-#define S3C2443_UERSTAT_PARITY (1<<1)
-
-#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
- S3C2410_UERSTAT_FRAME | \
- S3C2410_UERSTAT_BREAK)
-
-#define S3C2410_UMSTAT_CTS (1<<0)
-#define S3C2410_UMSTAT_DeltaCTS (1<<2)
-
-#define S3C2443_DIVSLOT (0x2C)
-
-#ifndef __ASSEMBLY__
-
-/* struct s3c24xx_uart_clksrc
- *
- * this structure defines a named clock source that can be used for the
- * uart, so that the best clock can be selected for the requested baud
- * rate.
- *
- * min_baud and max_baud define the range of baud-rates this clock is
- * acceptable for, if they are both zero, it is assumed any baud rate that
- * can be generated from this clock will be used.
- *
- * divisor gives the divisor from the clock to the one seen by the uart
-*/
-
-struct s3c24xx_uart_clksrc {
- const char *name;
- unsigned int divisor;
- unsigned int min_baud;
- unsigned int max_baud;
-};
-
-/* configuration structure for per-machine configurations for the
- * serial port
- *
- * the pointer is setup by the machine specific initialisation from the
- * arch/arm/mach-s3c2410/ directory.
-*/
-
-struct s3c2410_uartcfg {
- unsigned char hwport; /* hardware port number */
- unsigned char unused;
- unsigned short flags;
- upf_t uart_flags; /* default uart flags */
-
- unsigned long ucon; /* value of ucon for port */
- unsigned long ulcon; /* value of ulcon for port */
- unsigned long ufcon; /* value of ufcon for port */
-
- struct s3c24xx_uart_clksrc *clocks;
- unsigned int clocks_size;
-};
-
-/* s3c24xx_uart_devs
- *
- * this is exported from the core as we cannot use driver_register(),
- * or platform_add_device() before the console_initcall()
-*/
-
-extern struct platform_device *s3c24xx_uart_devs[3];
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASM_ARM_REGS_SERIAL_H */
-
diff --git a/include/asm-arm/plat-s3c/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h
deleted file mode 100644
index cc0eedd53e3..00000000000
--- a/include/asm-arm/plat-s3c/regs-timer.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-timer.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- * http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Timer configuration
-*/
-
-
-#ifndef __ASM_ARCH_REGS_TIMER_H
-#define __ASM_ARCH_REGS_TIMER_H
-
-#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
-#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
-
-#define S3C2410_TCFG0 S3C_TIMERREG(0x00)
-#define S3C2410_TCFG1 S3C_TIMERREG(0x04)
-#define S3C2410_TCON S3C_TIMERREG(0x08)
-
-#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
-#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
-#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
-#define S3C2410_TCFG_DEADZONE_MASK (255<<16)
-#define S3C2410_TCFG_DEADZONE_SHIFT (16)
-
-#define S3C2410_TCFG1_MUX4_DIV2 (0<<16)
-#define S3C2410_TCFG1_MUX4_DIV4 (1<<16)
-#define S3C2410_TCFG1_MUX4_DIV8 (2<<16)
-#define S3C2410_TCFG1_MUX4_DIV16 (3<<16)
-#define S3C2410_TCFG1_MUX4_TCLK1 (4<<16)
-#define S3C2410_TCFG1_MUX4_MASK (15<<16)
-#define S3C2410_TCFG1_MUX4_SHIFT (16)
-
-#define S3C2410_TCFG1_MUX3_DIV2 (0<<12)
-#define S3C2410_TCFG1_MUX3_DIV4 (1<<12)
-#define S3C2410_TCFG1_MUX3_DIV8 (2<<12)
-#define S3C2410_TCFG1_MUX3_DIV16 (3<<12)
-#define S3C2410_TCFG1_MUX3_TCLK1 (4<<12)
-#define S3C2410_TCFG1_MUX3_MASK (15<<12)
-
-
-#define S3C2410_TCFG1_MUX2_DIV2 (0<<8)
-#define S3C2410_TCFG1_MUX2_DIV4 (1<<8)
-#define S3C2410_TCFG1_MUX2_DIV8 (2<<8)
-#define S3C2410_TCFG1_MUX2_DIV16 (3<<8)
-#define S3C2410_TCFG1_MUX2_TCLK1 (4<<8)
-#define S3C2410_TCFG1_MUX2_MASK (15<<8)
-
-
-#define S3C2410_TCFG1_MUX1_DIV2 (0<<4)
-#define S3C2410_TCFG1_MUX1_DIV4 (1<<4)
-#define S3C2410_TCFG1_MUX1_DIV8 (2<<4)
-#define S3C2410_TCFG1_MUX1_DIV16 (3<<4)
-#define S3C2410_TCFG1_MUX1_TCLK0 (4<<4)
-#define S3C2410_TCFG1_MUX1_MASK (15<<4)
-
-#define S3C2410_TCFG1_MUX0_DIV2 (0<<0)
-#define S3C2410_TCFG1_MUX0_DIV4 (1<<0)
-#define S3C2410_TCFG1_MUX0_DIV8 (2<<0)
-#define S3C2410_TCFG1_MUX0_DIV16 (3<<0)
-#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0)
-#define S3C2410_TCFG1_MUX0_MASK (15<<0)
-
-#define S3C2410_TCFG1_MUX_DIV2 (0<<0)
-#define S3C2410_TCFG1_MUX_DIV4 (1<<0)
-#define S3C2410_TCFG1_MUX_DIV8 (2<<0)
-#define S3C2410_TCFG1_MUX_DIV16 (3<<0)
-#define S3C2410_TCFG1_MUX_TCLK (4<<0)
-#define S3C2410_TCFG1_MUX_MASK (15<<0)
-
-#define S3C2410_TCFG1_SHIFT(x) ((x) * 4)
-
-/* for each timer, we have an count buffer, an compare buffer and
- * an observation buffer
-*/
-
-/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
-
-#define S3C2410_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00)
-#define S3C2410_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04)
-#define S3C2410_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
-
-#define S3C2410_TCON_T4RELOAD (1<<22)
-#define S3C2410_TCON_T4MANUALUPD (1<<21)
-#define S3C2410_TCON_T4START (1<<20)
-
-#define S3C2410_TCON_T3RELOAD (1<<19)
-#define S3C2410_TCON_T3INVERT (1<<18)
-#define S3C2410_TCON_T3MANUALUPD (1<<17)
-#define S3C2410_TCON_T3START (1<<16)
-
-#define S3C2410_TCON_T2RELOAD (1<<15)
-#define S3C2410_TCON_T2INVERT (1<<14)
-#define S3C2410_TCON_T2MANUALUPD (1<<13)
-#define S3C2410_TCON_T2START (1<<12)
-
-#define S3C2410_TCON_T1RELOAD (1<<11)
-#define S3C2410_TCON_T1INVERT (1<<10)
-#define S3C2410_TCON_T1MANUALUPD (1<<9)
-#define S3C2410_TCON_T1START (1<<8)
-
-#define S3C2410_TCON_T0DEADZONE (1<<4)
-#define S3C2410_TCON_T0RELOAD (1<<3)
-#define S3C2410_TCON_T0INVERT (1<<2)
-#define S3C2410_TCON_T0MANUALUPD (1<<1)
-#define S3C2410_TCON_T0START (1<<0)
-
-#endif /* __ASM_ARCH_REGS_TIMER_H */
-
-
-
diff --git a/include/asm-arm/plat-s3c/uncompress.h b/include/asm-arm/plat-s3c/uncompress.h
deleted file mode 100644
index 19b9eda3948..00000000000
--- a/include/asm-arm/plat-s3c/uncompress.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* linux/include/asm-arm/plat-s3c/uncompress.h
- *
- * Copyright 2003, 2007 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_UNCOMPRESS_H
-#define __ASM_PLAT_UNCOMPRESS_H
-
-typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
-
-/* uart setup */
-
-static unsigned int fifo_mask;
-static unsigned int fifo_max;
-
-/* forward declerations */
-
-static void arch_detect_cpu(void);
-
-/* defines for UART registers */
-
-#include <asm/plat-s3c/regs-serial.h>
-#include <asm/plat-s3c/regs-watchdog.h>
-
-/* working in physical space... */
-#undef S3C2410_WDOGREG
-#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
-
-/* how many bytes we allow into the FIFO at a time in FIFO mode */
-#define FIFO_MAX (14)
-
-#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
-
-static __inline__ void
-uart_wr(unsigned int reg, unsigned int val)
-{
- volatile unsigned int *ptr;
-
- ptr = (volatile unsigned int *)(reg + uart_base);
- *ptr = val;
-}
-
-static __inline__ unsigned int
-uart_rd(unsigned int reg)
-{
- volatile unsigned int *ptr;
-
- ptr = (volatile unsigned int *)(reg + uart_base);
- return *ptr;
-}
-
-/* we can deal with the case the UARTs are being run
- * in FIFO mode, so that we don't hold up our execution
- * waiting for tx to happen...
-*/
-
-static void putc(int ch)
-{
- if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
- int level;
-
- while (1) {
- level = uart_rd(S3C2410_UFSTAT);
- level &= fifo_mask;
-
- if (level < fifo_max)
- break;
- }
-
- } else {
- /* not using fifos */
-
- while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
- barrier();
- }
-
- /* write byte to transmission register */
- uart_wr(S3C2410_UTXH, ch);
-}
-
-static inline void flush(void)
-{
-}
-
-#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
-
-/* CONFIG_S3C_BOOT_WATCHDOG
- *
- * Simple boot-time watchdog setup, to reboot the system if there is
- * any problem with the boot process
-*/
-
-#ifdef CONFIG_S3C_BOOT_WATCHDOG
-
-#define WDOG_COUNT (0xff00)
-
-static inline void arch_decomp_wdog(void)
-{
- __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-}
-
-static void arch_decomp_wdog_start(void)
-{
- __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
- __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
- __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
-}
-
-#else
-#define arch_decomp_wdog_start()
-#define arch_decomp_wdog()
-#endif
-
-#ifdef CONFIG_S3C_BOOT_ERROR_RESET
-
-static void arch_decomp_error(const char *x)
-{
- putstr("\n\n");
- putstr(x);
- putstr("\n\n -- System resetting\n");
-
- __raw_writel(0x4000, S3C2410_WTDAT);
- __raw_writel(0x4000, S3C2410_WTCNT);
- __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
-
- while(1);
-}
-
-#define arch_error arch_decomp_error
-#endif
-
-static void error(char *err);
-
-static void
-arch_decomp_setup(void)
-{
- /* we may need to setup the uart(s) here if we are not running
- * on an BAST... the BAST will have left the uarts configured
- * after calling linux.
- */
-
- arch_detect_cpu();
- arch_decomp_wdog_start();
-}
-
-
-#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/include/asm-arm/plat-s3c24xx/clock.h b/include/asm-arm/plat-s3c24xx/clock.h
deleted file mode 100644
index 235b753cd87..00000000000
--- a/include/asm-arm/plat-s3c24xx/clock.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/clock.h
- * linux/arch/arm/mach-s3c2410/clock.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- * http://www.simtec.co.uk/products/SWLINUX/
- * Written by Ben Dooks, <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct clk {
- struct list_head list;
- struct module *owner;
- struct clk *parent;
- const char *name;
- int id;
- int usage;
- unsigned long rate;
- unsigned long ctrlbit;
-
- int (*enable)(struct clk *, int enable);
- int (*set_rate)(struct clk *c, unsigned long rate);
- unsigned long (*get_rate)(struct clk *c);
- unsigned long (*round_rate)(struct clk *c, unsigned long rate);
- int (*set_parent)(struct clk *c, struct clk *parent);
-};
-
-/* other clocks which may be registered by board support */
-
-extern struct clk s3c24xx_dclk0;
-extern struct clk s3c24xx_dclk1;
-extern struct clk s3c24xx_clkout0;
-extern struct clk s3c24xx_clkout1;
-extern struct clk s3c24xx_uclk;
-
-extern struct clk clk_usb_bus;
-
-/* core clock support */
-
-extern struct clk clk_f;
-extern struct clk clk_h;
-extern struct clk clk_p;
-extern struct clk clk_mpll;
-extern struct clk clk_upll;
-extern struct clk clk_xtal;
-
-/* exports for arch/arm/mach-s3c2410
- *
- * Please DO NOT use these outside of arch/arm/mach-s3c2410
-*/
-
-extern struct mutex clocks_mutex;
-
-extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
-
-extern int s3c24xx_register_clock(struct clk *clk);
-extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
-
-extern int s3c24xx_setup_clocks(unsigned long xtal,
- unsigned long fclk,
- unsigned long hclk,
- unsigned long pclk);
diff --git a/include/asm-arm/plat-s3c24xx/common-smdk.h b/include/asm-arm/plat-s3c24xx/common-smdk.h
deleted file mode 100644
index 58d9094c935..00000000000
--- a/include/asm-arm/plat-s3c24xx/common-smdk.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/common-smdk.h
- *
- * Copyright (c) 2006 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Common code for SMDK2410 and SMDK2440 boards
- *
- * http://www.fluff.org/ben/smdk2440/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-extern void smdk_machine_init(void);
diff --git a/include/asm-arm/plat-s3c24xx/cpu.h b/include/asm-arm/plat-s3c24xx/cpu.h
deleted file mode 100644
index 23e420e8bd5..00000000000
--- a/include/asm-arm/plat-s3c24xx/cpu.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/cpu.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C24XX CPU support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* todo - fix when rmk changes iodescs to use `void __iomem *` */
-
-#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
-
-#ifndef MHZ
-#define MHZ (1000*1000)
-#endif
-
-#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000)
-
-/* forward declaration */
-struct s3c24xx_uart_resources;
-struct platform_device;
-struct s3c2410_uartcfg;
-struct map_desc;
-
-/* core initialisation functions */
-
-extern void s3c24xx_init_irq(void);
-
-extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
-
-extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c24xx_init_clocks(int xtal);
-
-extern void s3c24xx_init_uartdevs(char *name,
- struct s3c24xx_uart_resources *res,
- struct s3c2410_uartcfg *cfg, int no);
-
-/* timer for 2410/2440 */
-
-struct sys_timer;
-extern struct sys_timer s3c24xx_timer;
-
-/* system device classes */
-
-extern struct sysdev_class s3c2410_sysclass;
-extern struct sysdev_class s3c2412_sysclass;
-extern struct sysdev_class s3c2440_sysclass;
-extern struct sysdev_class s3c2442_sysclass;
-extern struct sysdev_class s3c2443_sysclass;
diff --git a/include/asm-arm/plat-s3c24xx/devs.h b/include/asm-arm/plat-s3c24xx/devs.h
deleted file mode 100644
index badaac9d64a..00000000000
--- a/include/asm-arm/plat-s3c24xx/devs.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/devs.h
- *
- * Copyright (c) 2004 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2410 standard platform devices
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/platform_device.h>
-
-struct s3c24xx_uart_resources {
- struct resource *resources;
- unsigned long nr_resources;
-};
-
-extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
-
-extern struct platform_device *s3c24xx_uart_devs[];
-extern struct platform_device *s3c24xx_uart_src[];
-
-extern struct platform_device s3c_device_timer[];
-
-extern struct platform_device s3c_device_usb;
-extern struct platform_device s3c_device_lcd;
-extern struct platform_device s3c_device_wdt;
-extern struct platform_device s3c_device_i2c;
-extern struct platform_device s3c_device_iis;
-extern struct platform_device s3c_device_rtc;
-extern struct platform_device s3c_device_adc;
-extern struct platform_device s3c_device_sdi;
-extern struct platform_device s3c_device_hsmmc;
-
-extern struct platform_device s3c_device_spi0;
-extern struct platform_device s3c_device_spi1;
-
-extern struct platform_device s3c_device_nand;
-
-extern struct platform_device s3c_device_usbgadget;
-
-/* s3c2440 specific devices */
-
-#ifdef CONFIG_CPU_S3C2440
-
-extern struct platform_device s3c_device_camif;
-
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/dma.h b/include/asm-arm/plat-s3c24xx/dma.h
deleted file mode 100644
index c78efe316fc..00000000000
--- a/include/asm-arm/plat-s3c24xx/dma.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/dma.h
- *
- * Copyright (C) 2006 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Samsung S3C24XX DMA support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-extern struct sysdev_class dma_sysclass;
-extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
-
-#define DMA_CH_VALID (1<<31)
-#define DMA_CH_NEVER (1<<30)
-
-struct s3c24xx_dma_addr {
- unsigned long from;
- unsigned long to;
-};
-
-/* struct s3c24xx_dma_map
- *
- * this holds the mapping information for the channel selected
- * to be connected to the specified device
-*/
-
-struct s3c24xx_dma_map {
- const char *name;
- struct s3c24xx_dma_addr hw_addr;
-
- unsigned long channels[S3C2410_DMA_CHANNELS];
- unsigned long channels_rx[S3C2410_DMA_CHANNELS];
-};
-
-struct s3c24xx_dma_selection {
- struct s3c24xx_dma_map *map;
- unsigned long map_size;
- unsigned long dcon_mask;
-
- void (*select)(struct s3c2410_dma_chan *chan,
- struct s3c24xx_dma_map *map);
-
- void (*direction)(struct s3c2410_dma_chan *chan,
- struct s3c24xx_dma_map *map,
- enum s3c2410_dmasrc dir);
-};
-
-extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
-
-/* struct s3c24xx_dma_order_ch
- *
- * channel map for one of the `enum dma_ch` dma channels. the list
- * entry contains a set of low-level channel numbers, orred with
- * DMA_CH_VALID, which are checked in the order in the array.
-*/
-
-struct s3c24xx_dma_order_ch {
- unsigned int list[S3C2410_DMA_CHANNELS]; /* list of channels */
- unsigned int flags; /* flags */
-};
-
-/* struct s3c24xx_dma_order
- *
- * information provided by either the core or the board to give the
- * dma system a hint on how to allocate channels
-*/
-
-struct s3c24xx_dma_order {
- struct s3c24xx_dma_order_ch channels[DMACH_MAX];
-};
-
-extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
-
-/* DMA init code, called from the cpu support code */
-
-extern int s3c2410_dma_init(void);
-
-extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq,
- unsigned int stride);
diff --git a/include/asm-arm/plat-s3c24xx/irq.h b/include/asm-arm/plat-s3c24xx/irq.h
deleted file mode 100644
index 45746a99534..00000000000
--- a/include/asm-arm/plat-s3c24xx/irq.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/irq.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C24XX CPU IRQ support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define irqdbf(x...)
-#define irqdbf2(x...)
-
-#define EXTINT_OFF (IRQ_EINT4 - 4)
-
-/* these are exported for arch/arm/mach-* usage */
-extern struct irq_chip s3c_irq_level_chip;
-extern struct irq_chip s3c_irq_chip;
-
-static inline void
-s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
- int subcheck)
-{
- unsigned long mask;
- unsigned long submask;
-
- submask = __raw_readl(S3C2410_INTSUBMSK);
- mask = __raw_readl(S3C2410_INTMSK);
-
- submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
-
- /* check to see if we need to mask the parent IRQ */
-
- if ((submask & subcheck) == subcheck) {
- __raw_writel(mask | parentbit, S3C2410_INTMSK);
- }
-
- /* write back masks */
- __raw_writel(submask, S3C2410_INTSUBMSK);
-
-}
-
-static inline void
-s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
-{
- unsigned long mask;
- unsigned long submask;
-
- submask = __raw_readl(S3C2410_INTSUBMSK);
- mask = __raw_readl(S3C2410_INTMSK);
-
- submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
- mask &= ~parentbit;
-
- /* write back masks */
- __raw_writel(submask, S3C2410_INTSUBMSK);
- __raw_writel(mask, S3C2410_INTMSK);
-}
-
-
-static inline void
-s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
-{
- unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
-
- s3c_irqsub_mask(irqno, parentmask, group);
-
- __raw_writel(bit, S3C2410_SUBSRCPND);
-
- /* only ack parent if we've got all the irqs (seems we must
- * ack, all and hope that the irq system retriggers ok when
- * the interrupt goes off again)
- */
-
- if (1) {
- __raw_writel(parentmask, S3C2410_SRCPND);
- __raw_writel(parentmask, S3C2410_INTPND);
- }
-}
-
-static inline void
-s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
-{
- unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
-
- __raw_writel(bit, S3C2410_SUBSRCPND);
-
- /* only ack parent if we've got all the irqs (seems we must
- * ack, all and hope that the irq system retriggers ok when
- * the interrupt goes off again)
- */
-
- if (1) {
- __raw_writel(parentmask, S3C2410_SRCPND);
- __raw_writel(parentmask, S3C2410_INTPND);
- }
-}
-
-/* exported for use in arch/arm/mach-s3c2410 */
-
-#ifdef CONFIG_PM
-extern int s3c_irq_wake(unsigned int irqno, unsigned int state);
-#else
-#define s3c_irq_wake NULL
-#endif
-
-extern int s3c_irqext_type(unsigned int irq, unsigned int type);
diff --git a/include/asm-arm/plat-s3c24xx/pm.h b/include/asm-arm/plat-s3c24xx/pm.h
deleted file mode 100644
index cc623667e48..00000000000
--- a/include/asm-arm/plat-s3c24xx/pm.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/pm.h
- *
- * Copyright (c) 2004 Simtec Electronics
- * Written by Ben Dooks, <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* s3c2410_pm_init
- *
- * called from board at initialisation time to setup the power
- * management
-*/
-
-#ifdef CONFIG_PM
-
-extern __init int s3c2410_pm_init(void);
-
-#else
-
-static inline int s3c2410_pm_init(void)
-{
- return 0;
-}
-#endif
-
-/* configuration for the IRQ mask over sleep */
-extern unsigned long s3c_irqwake_intmask;
-extern unsigned long s3c_irqwake_eintmask;
-
-/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
-extern unsigned long s3c_irqwake_intallow;
-extern unsigned long s3c_irqwake_eintallow;
-
-/* per-cpu sleep functions */
-
-extern void (*pm_cpu_prep)(void);
-extern void (*pm_cpu_sleep)(void);
-
-/* Flags for PM Control */
-
-extern unsigned long s3c_pm_flags;
-
-/* from sleep.S */
-
-extern int s3c2410_cpu_save(unsigned long *saveblk);
-extern void s3c2410_cpu_suspend(void);
-extern void s3c2410_cpu_resume(void);
-
-extern unsigned long s3c2410_sleep_save_phys;
-
-/* sleep save info */
-
-struct sleep_save {
- void __iomem *reg;
- unsigned long val;
-};
-
-#define SAVE_ITEM(x) \
- { .reg = (x) }
-
-extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count);
-extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count);
-
-#ifdef CONFIG_PM
-extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
-extern int s3c24xx_irq_resume(struct sys_device *dev);
-#else
-#define s3c24xx_irq_suspend NULL
-#define s3c24xx_irq_resume NULL
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2400.h b/include/asm-arm/plat-s3c24xx/s3c2400.h
deleted file mode 100644
index 3a5a16821af..00000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2400.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2400.h
- *
- * Copyright (c) 2004 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C2400 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Modifications:
- * 09-Fev-2006 LCVR First version, based on s3c2410.h
-*/
-
-#ifdef CONFIG_CPU_S3C2400
-
-extern int s3c2400_init(void);
-
-extern void s3c2400_map_io(struct map_desc *mach_desc, int size);
-
-extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2400_init_clocks(int xtal);
-
-#else
-#define s3c2400_init_clocks NULL
-#define s3c2400_init_uarts NULL
-#define s3c2400_map_io NULL
-#define s3c2400_init NULL
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2410.h b/include/asm-arm/plat-s3c24xx/s3c2410.h
deleted file mode 100644
index 3cd1ec677b3..00000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2410.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2410.h
- *
- * Copyright (c) 2004 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2410 machine directory
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#ifdef CONFIG_CPU_S3C2410
-
-extern int s3c2410_init(void);
-
-extern void s3c2410_map_io(struct map_desc *mach_desc, int size);
-
-extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2410_init_clocks(int xtal);
-
-#else
-#define s3c2410_init_clocks NULL
-#define s3c2410_init_uarts NULL
-#define s3c2410_map_io NULL
-#define s3c2410_init NULL
-#endif
-
-extern int s3c2410_baseclk_add(void);
diff --git a/include/asm-arm/plat-s3c24xx/s3c2412.h b/include/asm-arm/plat-s3c24xx/s3c2412.h
deleted file mode 100644
index 3ec97685e78..00000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2412.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2412.h
- *
- * Copyright (c) 2006 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2412 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2412
-
-extern int s3c2412_init(void);
-
-extern void s3c2412_map_io(struct map_desc *mach_desc, int size);
-
-extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2412_init_clocks(int xtal);
-
-extern int s3c2412_baseclk_add(void);
-#else
-#define s3c2412_init_clocks NULL
-#define s3c2412_init_uarts NULL
-#define s3c2412_map_io NULL
-#define s3c2412_init NULL
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2440.h b/include/asm-arm/plat-s3c24xx/s3c2440.h
deleted file mode 100644
index 107853bf948..00000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2440.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2440.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2440 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2440
-extern int s3c2440_init(void);
-#else
-#define s3c2440_init NULL
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2442.h b/include/asm-arm/plat-s3c24xx/s3c2442.h
deleted file mode 100644
index 451a23a2092..00000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2442.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2442.h
- *
- * Copyright (c) 2006 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2442 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2442
-extern int s3c2442_init(void);
-#else
-#define s3c2442_init NULL
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2443.h b/include/asm-arm/plat-s3c24xx/s3c2443.h
deleted file mode 100644
index 11d83b5c84e..00000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2443.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2443 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2443
-
-struct s3c2410_uartcfg;
-
-extern int s3c2443_init(void);
-
-extern void s3c2443_map_io(struct map_desc *mach_desc, int size);
-
-extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2443_init_clocks(int xtal);
-
-extern int s3c2443_baseclk_add(void);
-
-#else
-#define s3c2443_init_clocks NULL
-#define s3c2443_init_uarts NULL
-#define s3c2443_map_io NULL
-#define s3c2443_init NULL
-#endif
diff --git a/include/asm-cris/a.out.h b/include/asm-cris/a.out.h
deleted file mode 100644
index c82e9f9b75f..00000000000
--- a/include/asm-cris/a.out.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef __CRIS_A_OUT_H__
-#define __CRIS_A_OUT_H__
-
-/* we don't support a.out binaries on Linux/CRIS anyway, so this is
- * not really used but still needed because binfmt_elf.c for some reason
- * wants to know about a.out even if there is no interpreter available...
- */
-
-struct exec
-{
- unsigned long a_info; /* Use macros N_MAGIC, etc for access */
- unsigned a_text; /* length of text, in bytes */
- unsigned a_data; /* length of data, in bytes */
- unsigned a_bss; /* length of uninitialized data area for file, in bytes */
- unsigned a_syms; /* length of symbol table data in file, in bytes */
- unsigned a_entry; /* start address */
- unsigned a_trsize; /* length of relocation info for text, in bytes */
- unsigned a_drsize; /* length of relocation info for data, in bytes */
-};
-
-
-#define N_TRSIZE(a) ((a).a_trsize)
-#define N_DRSIZE(a) ((a).a_drsize)
-#define N_SYMSIZE(a) ((a).a_syms)
-
-#endif
diff --git a/include/asm-cris/elf.h b/include/asm-cris/elf.h
index 001f64ad11e..f0d17fbc81b 100644
--- a/include/asm-cris/elf.h
+++ b/include/asm-cris/elf.h
@@ -88,6 +88,6 @@ typedef unsigned long elf_fpregset_t;
#define ELF_PLATFORM (NULL)
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
#endif
diff --git a/include/asm-cris/thread_info.h b/include/asm-cris/thread_info.h
index 7efe1000f99..cee97f14af3 100644
--- a/include/asm-cris/thread_info.h
+++ b/include/asm-cris/thread_info.h
@@ -88,6 +88,7 @@ struct thread_info {
#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */
#define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */
#define TIF_MEMDIE 17
+#define TIF_FREEZE 18 /* is freezing for suspend */
#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
@@ -95,6 +96,7 @@ struct thread_info {
#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
+#define _TIF_FREEZE (1<<TIF_FREEZE)
#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
#define _TIF_ALLWORK_MASK 0x0000FFFF /* work to do on any return to u-space */
diff --git a/include/asm-frv/elf.h b/include/asm-frv/elf.h
index 9fb946bb7dc..7279ec07d62 100644
--- a/include/asm-frv/elf.h
+++ b/include/asm-frv/elf.h
@@ -137,6 +137,6 @@ do { \
#define ELF_PLATFORM (NULL)
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
#endif
diff --git a/include/asm-frv/ide.h b/include/asm-frv/ide.h
index 7ebcc56a222..36107661185 100644
--- a/include/asm-frv/ide.h
+++ b/include/asm-frv/ide.h
@@ -18,15 +18,7 @@
#include <asm/io.h>
#include <asm/irq.h>
-/****************************************************************************/
-/*
- * some bits needed for parts of the IDE subsystem to compile
- */
-#define __ide_mm_insw(port, addr, n) insw((unsigned long) (port), addr, n)
-#define __ide_mm_insl(port, addr, n) insl((unsigned long) (port), addr, n)
-#define __ide_mm_outsw(port, addr, n) outsw((unsigned long) (port), addr, n)
-#define __ide_mm_outsl(port, addr, n) outsl((unsigned long) (port), addr, n)
-
+#include <asm-generic/ide_iops.h>
#endif /* __KERNEL__ */
#endif /* _ASM_IDE_H */
diff --git a/include/asm-frv/unaligned.h b/include/asm-frv/unaligned.h
index 839a2fbffa0..6c61c05b2e0 100644
--- a/include/asm-frv/unaligned.h
+++ b/include/asm-frv/unaligned.h
@@ -13,7 +13,7 @@
#define _ASM_UNALIGNED_H
#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/be_struct.h>
#include <linux/unaligned/generic.h>
#define get_unaligned __get_unaligned_be
diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index edc6ba82e09..12c07c1866b 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
@@ -22,7 +22,7 @@ struct bug_entry {
#ifndef HAVE_ARCH_BUG
#define BUG() do { \
- printk("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
+ printk("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
panic("BUG!"); \
} while (0)
#endif
@@ -41,7 +41,7 @@ extern void warn_slowpath(const char *file, const int line,
#define __WARN() warn_on_slowpath(__FILE__, __LINE__)
#define __WARN_printf(arg...) warn_slowpath(__FILE__, __LINE__, arg)
#else
-#define __WARN_printf(arg...) __WARN()
+#define __WARN_printf(arg...) do { printk(arg); __WARN(); } while (0)
#endif
#ifndef WARN_ON
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 0f99ad38b01..81797ec9ab2 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -35,11 +35,17 @@ struct module;
* @label: for diagnostics
* @dev: optional device providing the GPIOs
* @owner: helps prevent removal of modules exporting active GPIOs
+ * @request: optional hook for chip-specific activation, such as
+ * enabling module power and clock; may sleep
+ * @free: optional hook for chip-specific deactivation, such as
+ * disabling module power and clock; may sleep
* @direction_input: configures signal "offset" as input, or returns error
* @get: returns value for signal "offset"; for output signals this
* returns either the value actually sensed, or zero
* @direction_output: configures signal "offset" as output, or returns error
* @set: assigns output value for signal "offset"
+ * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
+ * implementation may not sleep
* @dbg_show: optional routine to show contents in debugfs; default code
* will be used when this is omitted, but custom code can show extra
* state (such as pullup/pulldown configuration).
@@ -61,10 +67,15 @@ struct module;
* is calculated by subtracting @base from the gpio number.
*/
struct gpio_chip {
- char *label;
+ const char *label;
struct device *dev;
struct module *owner;
+ int (*request)(struct gpio_chip *chip,
+ unsigned offset);
+ void (*free)(struct gpio_chip *chip,
+ unsigned offset);
+
int (*direction_input)(struct gpio_chip *chip,
unsigned offset);
int (*get)(struct gpio_chip *chip,
@@ -73,6 +84,10 @@ struct gpio_chip {
unsigned offset, int value);
void (*set)(struct gpio_chip *chip,
unsigned offset, int value);
+
+ int (*to_irq)(struct gpio_chip *chip,
+ unsigned offset);
+
void (*dbg_show)(struct seq_file *s,
struct gpio_chip *chip);
int base;
@@ -112,6 +127,7 @@ extern void __gpio_set_value(unsigned gpio, int value);
extern int __gpio_cansleep(unsigned gpio);
+extern int __gpio_to_irq(unsigned gpio);
#ifdef CONFIG_GPIO_SYSFS
diff --git a/include/asm-generic/rtc.h b/include/asm-generic/rtc.h
index 71ef3f0b968..89061c1a67d 100644
--- a/include/asm-generic/rtc.h
+++ b/include/asm-generic/rtc.h
@@ -84,12 +84,12 @@ static inline unsigned int get_rtc_time(struct rtc_time *time)
if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
{
- BCD_TO_BIN(time->tm_sec);
- BCD_TO_BIN(time->tm_min);
- BCD_TO_BIN(time->tm_hour);
- BCD_TO_BIN(time->tm_mday);
- BCD_TO_BIN(time->tm_mon);
- BCD_TO_BIN(time->tm_year);
+ time->tm_sec = bcd2bin(time->tm_sec);
+ time->tm_min = bcd2bin(time->tm_min);
+ time->tm_hour = bcd2bin(time->tm_hour);
+ time->tm_mday = bcd2bin(time->tm_mday);
+ time->tm_mon = bcd2bin(time->tm_mon);
+ time->tm_year = bcd2bin(time->tm_year);
}
#ifdef CONFIG_MACH_DECSTATION
@@ -159,12 +159,12 @@ static inline int set_rtc_time(struct rtc_time *time)
if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY)
|| RTC_ALWAYS_BCD) {
- BIN_TO_BCD(sec);
- BIN_TO_BCD(min);
- BIN_TO_BCD(hrs);
- BIN_TO_BCD(day);
- BIN_TO_BCD(mon);
- BIN_TO_BCD(yrs);
+ sec = bin2bcd(sec);
+ min = bin2bcd(min);
+ hrs = bin2bcd(hrs);
+ day = bin2bcd(day);
+ mon = bin2bcd(mon);
+ yrs = bin2bcd(yrs);
}
save_control = CMOS_READ(RTC_CONTROL);
diff --git a/include/asm-generic/siginfo.h b/include/asm-generic/siginfo.h
index 8786e01e0db..969570167e9 100644
--- a/include/asm-generic/siginfo.h
+++ b/include/asm-generic/siginfo.h
@@ -199,6 +199,8 @@ typedef struct siginfo {
*/
#define TRAP_BRKPT (__SI_FAULT|1) /* process breakpoint */
#define TRAP_TRACE (__SI_FAULT|2) /* process trace trap */
+#define TRAP_BRANCH (__SI_FAULT|3) /* process taken branch trap */
+#define TRAP_HWBKPT (__SI_FAULT|4) /* hardware breakpoint/watchpoint */
#define NSIGTRAP 2
/*
diff --git a/include/asm-generic/statfs.h b/include/asm-generic/statfs.h
index 1d01043e797..6129d680214 100644
--- a/include/asm-generic/statfs.h
+++ b/include/asm-generic/statfs.h
@@ -6,33 +6,64 @@
typedef __kernel_fsid_t fsid_t;
#endif
+/*
+ * Most 64-bit platforms use 'long', while most 32-bit platforms use '__u32'.
+ * Yes, they differ in signedness as well as size.
+ * Special cases can override it for themselves -- except for S390x, which
+ * is just a little too special for us. And MIPS, which I'm not touching
+ * with a 10' pole.
+ */
+#ifndef __statfs_word
+#if BITS_PER_LONG == 64
+#define __statfs_word long
+#else
+#define __statfs_word __u32
+#endif
+#endif
+
struct statfs {
- __u32 f_type;
- __u32 f_bsize;
- __u32 f_blocks;
- __u32 f_bfree;
- __u32 f_bavail;
- __u32 f_files;
- __u32 f_ffree;
+ __statfs_word f_type;
+ __statfs_word f_bsize;
+ __statfs_word f_blocks;
+ __statfs_word f_bfree;
+ __statfs_word f_bavail;
+ __statfs_word f_files;
+ __statfs_word f_ffree;
__kernel_fsid_t f_fsid;
- __u32 f_namelen;
- __u32 f_frsize;
- __u32 f_spare[5];
+ __statfs_word f_namelen;
+ __statfs_word f_frsize;
+ __statfs_word f_spare[5];
};
+/*
+ * ARM needs to avoid the 32-bit padding at the end, for consistency
+ * between EABI and OABI
+ */
+#ifndef ARCH_PACK_STATFS64
+#define ARCH_PACK_STATFS64
+#endif
+
struct statfs64 {
- __u32 f_type;
- __u32 f_bsize;
+ __statfs_word f_type;
+ __statfs_word f_bsize;
__u64 f_blocks;
__u64 f_bfree;
__u64 f_bavail;
__u64 f_files;
__u64 f_ffree;
__kernel_fsid_t f_fsid;
- __u32 f_namelen;
- __u32 f_frsize;
- __u32 f_spare[5];
-};
+ __statfs_word f_namelen;
+ __statfs_word f_frsize;
+ __statfs_word f_spare[5];
+} ARCH_PACK_STATFS64;
+
+/*
+ * IA64 and x86_64 need to avoid the 32-bit padding at the end,
+ * to be compatible with the i386 ABI
+ */
+#ifndef ARCH_PACK_COMPAT_STATFS64
+#define ARCH_PACK_COMPAT_STATFS64
+#endif
struct compat_statfs64 {
__u32 f_type;
@@ -46,6 +77,6 @@ struct compat_statfs64 {
__u32 f_namelen;
__u32 f_frsize;
__u32 f_spare[5];
-};
+} ARCH_PACK_COMPAT_STATFS64;
#endif
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index cb752ba7246..80744606bad 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -37,6 +37,13 @@
#define MEM_DISCARD(sec) *(.mem##sec)
#endif
+#ifdef CONFIG_FTRACE_MCOUNT_RECORD
+#define MCOUNT_REC() VMLINUX_SYMBOL(__start_mcount_loc) = .; \
+ *(__mcount_loc) \
+ VMLINUX_SYMBOL(__stop_mcount_loc) = .;
+#else
+#define MCOUNT_REC()
+#endif
/* .data section */
#define DATA_DATA \
@@ -52,7 +59,10 @@
. = ALIGN(8); \
VMLINUX_SYMBOL(__start___markers) = .; \
*(__markers) \
- VMLINUX_SYMBOL(__stop___markers) = .;
+ VMLINUX_SYMBOL(__stop___markers) = .; \
+ VMLINUX_SYMBOL(__start___tracepoints) = .; \
+ *(__tracepoints) \
+ VMLINUX_SYMBOL(__stop___tracepoints) = .;
#define RO_DATA(align) \
. = ALIGN((align)); \
@@ -61,6 +71,7 @@
*(.rodata) *(.rodata.*) \
*(__vermagic) /* Kernel version magic */ \
*(__markers_strings) /* Markers: strings */ \
+ *(__tracepoints_strings)/* Tracepoints: strings */ \
} \
\
.rodata1 : AT(ADDR(.rodata1) - LOAD_OFFSET) { \
@@ -188,6 +199,7 @@
/* __*init sections */ \
__init_rodata : AT(ADDR(__init_rodata) - LOAD_OFFSET) { \
*(.ref.rodata) \
+ MCOUNT_REC() \
DEV_KEEP(init.rodata) \
DEV_KEEP(exit.rodata) \
CPU_KEEP(init.rodata) \
@@ -268,7 +280,15 @@
CPU_DISCARD(init.data) \
CPU_DISCARD(init.rodata) \
MEM_DISCARD(init.data) \
- MEM_DISCARD(init.rodata)
+ MEM_DISCARD(init.rodata) \
+ /* implement dynamic printk debug */ \
+ VMLINUX_SYMBOL(__start___verbose_strings) = .; \
+ *(__verbose_strings) \
+ VMLINUX_SYMBOL(__stop___verbose_strings) = .; \
+ . = ALIGN(8); \
+ VMLINUX_SYMBOL(__start___verbose) = .; \
+ *(__verbose) \
+ VMLINUX_SYMBOL(__stop___verbose) = .;
#define INIT_TEXT \
*(.init.text) \
@@ -385,6 +405,7 @@
. = ALIGN(align); \
VMLINUX_SYMBOL(__per_cpu_start) = .; \
.data.percpu : AT(ADDR(.data.percpu) - LOAD_OFFSET) { \
+ *(.data.percpu.page_aligned) \
*(.data.percpu) \
*(.data.percpu.shared_aligned) \
} \
diff --git a/include/asm-h8300/timer.h b/include/asm-h8300/timer.h
new file mode 100644
index 00000000000..def80464d38
--- /dev/null
+++ b/include/asm-h8300/timer.h
@@ -0,0 +1,25 @@
+#ifndef __H8300_TIMER_H
+#define __H8300_TIMER_H
+
+void h8300_timer_tick(void);
+void h8300_timer_setup(void);
+void h8300_gettod(unsigned int *year, unsigned int *mon, unsigned int *day,
+ unsigned int *hour, unsigned int *min, unsigned int *sec);
+
+#define TIMER_FREQ (CONFIG_CPU_CLOCK*10000) /* Timer input freq. */
+
+#define calc_param(cnt, div, rate, limit) \
+do { \
+ cnt = TIMER_FREQ / HZ; \
+ for (div = 0; div < ARRAY_SIZE(divide_rate); div++) { \
+ if (rate[div] == 0) \
+ continue; \
+ if ((cnt / rate[div]) > limit) \
+ break; \
+ } \
+ if (div == ARRAY_SIZE(divide_rate)) \
+ panic("Timer counter overflow"); \
+ cnt /= divide_rate[div]; \
+} while(0)
+
+#endif
diff --git a/include/asm-m32r/a.out.h b/include/asm-m32r/a.out.h
deleted file mode 100644
index ab150f5c166..00000000000
--- a/include/asm-m32r/a.out.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _ASM_M32R_A_OUT_H
-#define _ASM_M32R_A_OUT_H
-
-struct exec
-{
- unsigned long a_info; /* Use macros N_MAGIC, etc for access */
- unsigned a_text; /* length of text, in bytes */
- unsigned a_data; /* length of data, in bytes */
- unsigned a_bss; /* length of uninitialized data area for file, in bytes */
- unsigned a_syms; /* length of symbol table data in file, in bytes */
- unsigned a_entry; /* start address */
- unsigned a_trsize; /* length of relocation info for text, in bytes */
- unsigned a_drsize; /* length of relocation info for data, in bytes */
-};
-
-#define N_TRSIZE(a) ((a).a_trsize)
-#define N_DRSIZE(a) ((a).a_drsize)
-#define N_SYMSIZE(a) ((a).a_syms)
-
-#endif /* _ASM_M32R_A_OUT_H */
diff --git a/include/asm-m32r/elf.h b/include/asm-m32r/elf.h
index 67bcd77494a..0cc34c94bf2 100644
--- a/include/asm-m32r/elf.h
+++ b/include/asm-m32r/elf.h
@@ -129,6 +129,6 @@ typedef elf_fpreg_t elf_fpregset_t;
intent than poking at uname or /proc/cpuinfo. */
#define ELF_PLATFORM (NULL)
-#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
#endif /* _ASM_M32R__ELF_H */
diff --git a/include/asm-m68k/atarihw.h b/include/asm-m68k/atarihw.h
index ecf007df774..1412b4ab202 100644
--- a/include/asm-m68k/atarihw.h
+++ b/include/asm-m68k/atarihw.h
@@ -39,7 +39,6 @@ extern int atari_dont_touch_floppy_select;
#define MACH_IS_TT ((atari_mch_cookie >> 16) == ATARI_MCH_TT)
#define MACH_IS_FALCON ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON)
#define MACH_IS_MEDUSA (atari_mch_type == ATARI_MACH_MEDUSA)
-#define MACH_IS_HADES (atari_mch_type == ATARI_MACH_HADES)
#define MACH_IS_AB40 (atari_mch_type == ATARI_MACH_AB40)
/* values for atari_switches */
diff --git a/include/asm-m68k/dma-mapping.h b/include/asm-m68k/dma-mapping.h
index 91f7944333d..26f505488c1 100644
--- a/include/asm-m68k/dma-mapping.h
+++ b/include/asm-m68k/dma-mapping.h
@@ -74,6 +74,14 @@ extern void dma_sync_single_for_device(struct device *, dma_addr_t, size_t,
extern void dma_sync_sg_for_device(struct device *, struct scatterlist *, int,
enum dma_data_direction);
+static inline void dma_sync_single_range_for_device(struct device *dev,
+ dma_addr_t dma_handle, unsigned long offset, size_t size,
+ enum dma_data_direction direction)
+{
+ /* just sync everything for now */
+ dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
+}
+
static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle,
size_t size, enum dma_data_direction dir)
{
@@ -84,6 +92,14 @@ static inline void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *s
{
}
+static inline void dma_sync_single_range_for_cpu(struct device *dev,
+ dma_addr_t dma_handle, unsigned long offset, size_t size,
+ enum dma_data_direction direction)
+{
+ /* just sync everything for now */
+ dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
+}
+
static inline int dma_mapping_error(struct device *dev, dma_addr_t handle)
{
return 0;
diff --git a/include/asm-m68k/dma.h b/include/asm-m68k/dma.h
index d0c9e61e57b..4240fbc946f 100644
--- a/include/asm-m68k/dma.h
+++ b/include/asm-m68k/dma.h
@@ -11,10 +11,6 @@
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
extern void free_dma(unsigned int dmanr); /* release it again */
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
#define isa_dma_bridge_buggy (0)
-#endif
#endif /* _M68K_DMA_H */
diff --git a/include/asm-m68k/elf.h b/include/asm-m68k/elf.h
index 14ea42152b9..0b0f49eb876 100644
--- a/include/asm-m68k/elf.h
+++ b/include/asm-m68k/elf.h
@@ -114,6 +114,6 @@ typedef struct user_m68kfp_struct elf_fpregset_t;
#define ELF_PLATFORM (NULL)
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
#endif
diff --git a/include/asm-m68k/entry.h b/include/asm-m68k/entry.h
index f8f6b185d79..5202f5a5b42 100644
--- a/include/asm-m68k/entry.h
+++ b/include/asm-m68k/entry.h
@@ -31,7 +31,7 @@
*/
/* the following macro is used when enabling interrupts */
-#if defined(MACH_ATARI_ONLY) && !defined(CONFIG_HADES)
+#if defined(MACH_ATARI_ONLY)
/* block out HSYNC on the atari */
#define ALLOWINT (~0x400)
#define MAX_NOINT_IPL 3
diff --git a/include/asm-m68k/ide.h b/include/asm-m68k/ide.h
index 1daf6cbdd9f..b996a3c8cff 100644
--- a/include/asm-m68k/ide.h
+++ b/include/asm-m68k/ide.h
@@ -92,15 +92,6 @@
#define outsw_swapw(port, addr, n) raw_outsw_swapw((u16 *)port, addr, n)
#endif
-
-/* Q40 and Atari have byteswapped IDE busses and since many interesting
- * values in the identification string are text, chars and words they
- * happened to be almost correct without swapping.. However *_capacity
- * is needed for drives over 8 GB. RZ */
-#if defined(CONFIG_Q40) || defined(CONFIG_ATARI)
-#define M68K_IDE_SWAPW (MACH_IS_Q40 || MACH_IS_ATARI)
-#endif
-
#ifdef CONFIG_BLK_DEV_FALCON_IDE
#define IDE_ARCH_LOCK
diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h
index 657187f0c7c..9e673e3bd43 100644
--- a/include/asm-m68k/io.h
+++ b/include/asm-m68k/io.h
@@ -7,15 +7,12 @@
* - added skeleton for GG-II and Amiga PCMCIA
* 2/3/01 RZ: - moved a few more defs into raw_io.h
*
- * inX/outX/readX/writeX should not be used by any driver unless it does
- * ISA or PCI access. Other drivers should use function defined in raw_io.h
+ * inX/outX should not be used by any driver unless it does
+ * ISA access. Other drivers should use function defined in raw_io.h
* or define its own macros on top of these.
*
- * inX(),outX() are for PCI and ISA I/O
- * readX(),writeX() are for PCI memory
+ * inX(),outX() are for ISA I/O
* isa_readX(),isa_writeX() are for ISA memory
- *
- * moved mem{cpy,set}_*io inside CONFIG_PCI
*/
#ifndef _IO_H
@@ -256,10 +253,7 @@ static inline void isa_delay(void)
(ISA_SEX ? raw_outsl(isa_itl(port), (u32 *)(buf), (nr)) : \
raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))
-#endif /* CONFIG_ISA */
-
-#if defined(CONFIG_ISA) && !defined(CONFIG_PCI)
#define inb isa_inb
#define inb_p isa_inb_p
#define outb isa_outb
@@ -282,55 +276,9 @@ static inline void isa_delay(void)
#define readw isa_readw
#define writeb isa_writeb
#define writew isa_writew
-#endif /* CONFIG_ISA */
-
-#if defined(CONFIG_PCI)
-
-#define readl(addr) in_le32(addr)
-#define writel(val,addr) out_le32((addr),(val))
-
-/* those can be defined for both ISA and PCI - it won't work though */
-#define readb(addr) in_8(addr)
-#define readw(addr) in_le16(addr)
-#define writeb(val,addr) out_8((addr),(val))
-#define writew(val,addr) out_le16((addr),(val))
-#define readb_relaxed(addr) readb(addr)
-#define readw_relaxed(addr) readw(addr)
-#define readl_relaxed(addr) readl(addr)
+#else /* CONFIG_ISA */
-#ifndef CONFIG_ISA
-#define inb(port) in_8(port)
-#define outb(val,port) out_8((port),(val))
-#define inw(port) in_le16(port)
-#define outw(val,port) out_le16((port),(val))
-#define inl(port) in_le32(port)
-#define outl(val,port) out_le32((port),(val))
-
-#else
-/*
- * kernel with both ISA and PCI compiled in, those have
- * conflicting defs for in/out. Simply consider port < 1024
- * ISA and everything else PCI. read,write not defined
- * in this case
- */
-#define inb(port) ((port)<1024 ? isa_inb(port) : in_8(port))
-#define inb_p(port) ((port)<1024 ? isa_inb_p(port) : in_8(port))
-#define inw(port) ((port)<1024 ? isa_inw(port) : in_le16(port))
-#define inw_p(port) ((port)<1024 ? isa_inw_p(port) : in_le16(port))
-#define inl(port) ((port)<1024 ? isa_inl(port) : in_le32(port))
-#define inl_p(port) ((port)<1024 ? isa_inl_p(port) : in_le32(port))
-
-#define outb(val,port) ((port)<1024 ? isa_outb((val),(port)) : out_8((port),(val)))
-#define outb_p(val,port) ((port)<1024 ? isa_outb_p((val),(port)) : out_8((port),(val)))
-#define outw(val,port) ((port)<1024 ? isa_outw((val),(port)) : out_le16((port),(val)))
-#define outw_p(val,port) ((port)<1024 ? isa_outw_p((val),(port)) : out_le16((port),(val)))
-#define outl(val,port) ((port)<1024 ? isa_outl((val),(port)) : out_le32((port),(val)))
-#define outl_p(val,port) ((port)<1024 ? isa_outl_p((val),(port)) : out_le32((port),(val)))
-#endif
-#endif /* CONFIG_PCI */
-
-#if !defined(CONFIG_ISA) && !defined(CONFIG_PCI)
/*
* We need to define dummy functions for GENERIC_IOMAP support.
*/
@@ -357,11 +305,11 @@ static inline void isa_delay(void)
#define writeb(val,addr) out_8((addr),(val))
#define readw(addr) in_le16(addr)
#define writew(val,addr) out_le16((addr),(val))
-#endif
-#if !defined(CONFIG_PCI)
+
+#endif /* CONFIG_ISA */
+
#define readl(addr) in_le32(addr)
#define writel(val,addr) out_le32((addr),(val))
-#endif
#define mmiowb()
diff --git a/include/asm-m68k/pci.h b/include/asm-m68k/pci.h
index 678cb0b5231..4ad0aea48ab 100644
--- a/include/asm-m68k/pci.h
+++ b/include/asm-m68k/pci.h
@@ -1,52 +1,7 @@
#ifndef _ASM_M68K_PCI_H
#define _ASM_M68K_PCI_H
-/*
- * asm-m68k/pci_m68k.h - m68k specific PCI declarations.
- *
- * Written by Wout Klaren.
- */
-
-#include <asm/scatterlist.h>
-
-struct pci_ops;
-
-/*
- * Structure with hardware dependent information and functions of the
- * PCI bus.
- */
-
-struct pci_bus_info
-{
- /*
- * Resources of the PCI bus.
- */
-
- struct resource mem_space;
- struct resource io_space;
-
- /*
- * System dependent functions.
- */
-
- struct pci_ops *m68k_pci_ops;
-
- void (*fixup)(int pci_modify);
- void (*conf_device)(struct pci_dev *dev);
-};
-
-#define pcibios_assign_all_busses() 0
-#define pcibios_scan_all_fns(a, b) 0
-
-static inline void pcibios_set_master(struct pci_dev *dev)
-{
- /* No special bus mastering setup handling */
-}
-
-static inline void pcibios_penalize_isa_irq(int irq, int active)
-{
- /* We don't do dynamic PCI IRQ allocation */
-}
+#include <asm-generic/pci-dma-compat.h>
/* The PCI address space does equal the physical memory
* address space. The networking and block device layers use
diff --git a/include/asm-m68k/thread_info.h b/include/asm-m68k/thread_info.h
index abc002798a2..af0fda46e94 100644
--- a/include/asm-m68k/thread_info.h
+++ b/include/asm-m68k/thread_info.h
@@ -52,5 +52,6 @@ struct thread_info {
#define TIF_DELAYED_TRACE 14 /* single step a syscall */
#define TIF_SYSCALL_TRACE 15 /* syscall trace active */
#define TIF_MEMDIE 16
+#define TIF_FREEZE 17 /* thread is freezing for suspend */
#endif /* _ASM_M68K_THREAD_INFO_H */
diff --git a/include/asm-m68k/virtconvert.h b/include/asm-m68k/virtconvert.h
index dea32fbc7e5..22ab05c9c52 100644
--- a/include/asm-m68k/virtconvert.h
+++ b/include/asm-m68k/virtconvert.h
@@ -40,15 +40,9 @@ static inline void *phys_to_virt(unsigned long address)
/*
* IO bus memory addresses are 1:1 with the physical address,
- * except on the PCI bus of the Hades.
*/
-#ifdef CONFIG_HADES
-#define virt_to_bus(a) (virt_to_phys(a) + (MACH_IS_HADES ? 0x80000000 : 0))
-#define bus_to_virt(a) (phys_to_virt((a) - (MACH_IS_HADES ? 0x80000000 : 0)))
-#else
#define virt_to_bus virt_to_phys
#define bus_to_virt phys_to_virt
-#endif
#endif
#endif
diff --git a/include/asm-mips/Kbuild b/include/asm-mips/Kbuild
deleted file mode 100644
index 7897f05e316..00000000000
--- a/include/asm-mips/Kbuild
+++ /dev/null
@@ -1,3 +0,0 @@
-include include/asm-generic/Kbuild.asm
-
-header-y += cachectl.h sgidefs.h sysmips.h
diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h
deleted file mode 100644
index cad8371422a..00000000000
--- a/include/asm-mips/a.out.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 - 1999, 2003 by Ralf Baechle
- */
-#ifndef _ASM_A_OUT_H
-#define _ASM_A_OUT_H
-
-#ifdef __KERNEL__
-
-
-#endif
-
-struct exec
-{
- unsigned long a_info; /* Use macros N_MAGIC, etc for access */
- unsigned a_text; /* length of text, in bytes */
- unsigned a_data; /* length of data, in bytes */
- unsigned a_bss; /* length of uninitialized data area for
- file, in bytes */
- unsigned a_syms; /* length of symbol table data in file,
- in bytes */
- unsigned a_entry; /* start address */
- unsigned a_trsize; /* length of relocation info for text, in
- bytes */
- unsigned a_drsize; /* length of relocation info for data, in bytes */
-};
-
-#define N_TRSIZE(a) ((a).a_trsize)
-#define N_DRSIZE(a) ((a).a_drsize)
-#define N_SYMSIZE(a) ((a).a_syms)
-
-#endif /* _ASM_A_OUT_H */
diff --git a/include/asm-mips/abi.h b/include/asm-mips/abi.h
deleted file mode 100644
index 1dd74fbdc09..00000000000
--- a/include/asm-mips/abi.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2005, 06 by Ralf Baechle (ralf@linux-mips.org)
- * Copyright (C) 2005 MIPS Technologies, Inc.
- */
-#ifndef _ASM_ABI_H
-#define _ASM_ABI_H
-
-#include <asm/signal.h>
-#include <asm/siginfo.h>
-
-struct mips_abi {
- int (* const setup_frame)(struct k_sigaction * ka,
- struct pt_regs *regs, int signr,
- sigset_t *set);
- int (* const setup_rt_frame)(struct k_sigaction * ka,
- struct pt_regs *regs, int signr,
- sigset_t *set, siginfo_t *info);
- const unsigned long restart;
-};
-
-#endif /* _ASM_ABI_H */
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
deleted file mode 100644
index 569f80aacbd..00000000000
--- a/include/asm-mips/addrspace.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 99 Ralf Baechle
- * Copyright (C) 2000, 2002 Maciej W. Rozycki
- * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
- */
-#ifndef _ASM_ADDRSPACE_H
-#define _ASM_ADDRSPACE_H
-
-#include <spaces.h>
-
-/*
- * Configure language
- */
-#ifdef __ASSEMBLY__
-#define _ATYPE_
-#define _ATYPE32_
-#define _ATYPE64_
-#define _CONST64_(x) x
-#else
-#define _ATYPE_ __PTRDIFF_TYPE__
-#define _ATYPE32_ int
-#define _ATYPE64_ __s64
-#ifdef CONFIG_64BIT
-#define _CONST64_(x) x ## L
-#else
-#define _CONST64_(x) x ## LL
-#endif
-#endif
-
-/*
- * 32-bit MIPS address spaces
- */
-#ifdef __ASSEMBLY__
-#define _ACAST32_
-#define _ACAST64_
-#else
-#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
-#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
-#endif
-
-/*
- * Returns the kernel segment base of a given address
- */
-#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000)
-
-/*
- * Returns the physical address of a CKSEGx / XKPHYS address
- */
-#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
-#define XPHYSADDR(a) ((_ACAST64_(a)) & \
- _CONST64_(0x000000ffffffffff))
-
-#ifdef CONFIG_64BIT
-
-/*
- * Memory segments (64bit kernel mode addresses)
- * The compatibility segments use the full 64-bit sign extended value. Note
- * the R8000 doesn't have them so don't reference these in generic MIPS code.
- */
-#define XKUSEG _CONST64_(0x0000000000000000)
-#define XKSSEG _CONST64_(0x4000000000000000)
-#define XKPHYS _CONST64_(0x8000000000000000)
-#define XKSEG _CONST64_(0xc000000000000000)
-#define CKSEG0 _CONST64_(0xffffffff80000000)
-#define CKSEG1 _CONST64_(0xffffffffa0000000)
-#define CKSSEG _CONST64_(0xffffffffc0000000)
-#define CKSEG3 _CONST64_(0xffffffffe0000000)
-
-#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
-#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
-#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2)
-#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3)
-
-#else
-
-#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
-#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
-#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
-#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
-
-/*
- * Map an address to a certain kernel segment
- */
-#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
-#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
-#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
-#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
-
-/*
- * Memory segments (32bit kernel mode addresses)
- * These are the traditional names used in the 32-bit universe.
- */
-#define KUSEG 0x00000000
-#define KSEG0 0x80000000
-#define KSEG1 0xa0000000
-#define KSEG2 0xc0000000
-#define KSEG3 0xe0000000
-
-#define CKUSEG 0x00000000
-#define CKSEG0 0x80000000
-#define CKSEG1 0xa0000000
-#define CKSEG2 0xc0000000
-#define CKSEG3 0xe0000000
-
-#endif
-
-/*
- * Cache modes for XKPHYS address conversion macros
- */
-#define K_CALG_COH_EXCL1_NOL2 0
-#define K_CALG_COH_SHRL1_NOL2 1
-#define K_CALG_UNCACHED 2
-#define K_CALG_NONCOHERENT 3
-#define K_CALG_COH_EXCL 4
-#define K_CALG_COH_SHAREABLE 5
-#define K_CALG_NOTUSED 6
-#define K_CALG_UNCACHED_ACCEL 7
-
-/*
- * 64-bit address conversions
- */
-#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
-#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
-#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
-#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \
- (_CONST64_(cm) << 59) | (a))
-
-/*
- * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
- * the region, 3 bits for the CCA mode. This leaves 59 bits of which the
- * R8000 implements most with its 48-bit physical address space.
- */
-#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
-
-#ifndef CONFIG_CPU_R8000
-
-/*
- * The R8000 doesn't have the 32-bit compat spaces so we don't define them
- * in order to catch bugs in the source code.
- */
-
-#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
-#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
-
-#endif
-
-#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
-#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
-
-#endif /* _ASM_ADDRSPACE_H */
diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h
deleted file mode 100644
index 608cfcfbb3e..00000000000
--- a/include/asm-mips/asm.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
- * Copyright (C) 1999 by Silicon Graphics, Inc.
- * Copyright (C) 2001 MIPS Technologies, Inc.
- * Copyright (C) 2002 Maciej W. Rozycki
- *
- * Some useful macros for MIPS assembler code
- *
- * Some of the routines below contain useless nops that will be optimized
- * away by gas in -O mode. These nops are however required to fill delay
- * slots in noreorder mode.
- */
-#ifndef __ASM_ASM_H
-#define __ASM_ASM_H
-
-#include <asm/sgidefs.h>
-
-#ifndef CAT
-#ifdef __STDC__
-#define __CAT(str1, str2) str1##str2
-#else
-#define __CAT(str1, str2) str1/**/str2
-#endif
-#define CAT(str1, str2) __CAT(str1, str2)
-#endif
-
-/*
- * PIC specific declarations
- * Not used for the kernel but here seems to be the right place.
- */
-#ifdef __PIC__
-#define CPRESTORE(register) \
- .cprestore register
-#define CPADD(register) \
- .cpadd register
-#define CPLOAD(register) \
- .cpload register
-#else
-#define CPRESTORE(register)
-#define CPADD(register)
-#define CPLOAD(register)
-#endif
-
-/*
- * LEAF - declare leaf routine
- */
-#define LEAF(symbol) \
- .globl symbol; \
- .align 2; \
- .type symbol, @function; \
- .ent symbol, 0; \
-symbol: .frame sp, 0, ra
-
-/*
- * NESTED - declare nested routine entry point
- */
-#define NESTED(symbol, framesize, rpc) \
- .globl symbol; \
- .align 2; \
- .type symbol, @function; \
- .ent symbol, 0; \
-symbol: .frame sp, framesize, rpc
-
-/*
- * END - mark end of function
- */
-#define END(function) \
- .end function; \
- .size function, .-function
-
-/*
- * EXPORT - export definition of symbol
- */
-#define EXPORT(symbol) \
- .globl symbol; \
-symbol:
-
-/*
- * FEXPORT - export definition of a function symbol
- */
-#define FEXPORT(symbol) \
- .globl symbol; \
- .type symbol, @function; \
-symbol:
-
-/*
- * ABS - export absolute symbol
- */
-#define ABS(symbol,value) \
- .globl symbol; \
-symbol = value
-
-#define PANIC(msg) \
- .set push; \
- .set reorder; \
- PTR_LA a0, 8f; \
- jal panic; \
-9: b 9b; \
- .set pop; \
- TEXT(msg)
-
-/*
- * Print formatted string
- */
-#ifdef CONFIG_PRINTK
-#define PRINT(string) \
- .set push; \
- .set reorder; \
- PTR_LA a0, 8f; \
- jal printk; \
- .set pop; \
- TEXT(string)
-#else
-#define PRINT(string)
-#endif
-
-#define TEXT(msg) \
- .pushsection .data; \
-8: .asciiz msg; \
- .popsection;
-
-/*
- * Build text tables
- */
-#define TTABLE(string) \
- .pushsection .text; \
- .word 1f; \
- .popsection \
- .pushsection .data; \
-1: .asciiz string; \
- .popsection
-
-/*
- * MIPS IV pref instruction.
- * Use with .set noreorder only!
- *
- * MIPS IV implementations are free to treat this as a nop. The R5000
- * is one of them. So we should have an option not to use this instruction.
- */
-#ifdef CONFIG_CPU_HAS_PREFETCH
-
-#define PREF(hint,addr) \
- .set push; \
- .set mips4; \
- pref hint, addr; \
- .set pop
-
-#define PREFX(hint,addr) \
- .set push; \
- .set mips4; \
- prefx hint, addr; \
- .set pop
-
-#else /* !CONFIG_CPU_HAS_PREFETCH */
-
-#define PREF(hint, addr)
-#define PREFX(hint, addr)
-
-#endif /* !CONFIG_CPU_HAS_PREFETCH */
-
-/*
- * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
- */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
-#define MOVN(rd, rs, rt) \
- .set push; \
- .set reorder; \
- beqz rt, 9f; \
- move rd, rs; \
- .set pop; \
-9:
-#define MOVZ(rd, rs, rt) \
- .set push; \
- .set reorder; \
- bnez rt, 9f; \
- move rd, rs; \
- .set pop; \
-9:
-#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
-#define MOVN(rd, rs, rt) \
- .set push; \
- .set noreorder; \
- bnezl rt, 9f; \
- move rd, rs; \
- .set pop; \
-9:
-#define MOVZ(rd, rs, rt) \
- .set push; \
- .set noreorder; \
- beqzl rt, 9f; \
- move rd, rs; \
- .set pop; \
-9:
-#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
- (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
-#define MOVN(rd, rs, rt) \
- movn rd, rs, rt
-#define MOVZ(rd, rs, rt) \
- movz rd, rs, rt
-#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
-
-/*
- * Stack alignment
- */
-#if (_MIPS_SIM == _MIPS_SIM_ABI32)
-#define ALSZ 7
-#define ALMASK ~7
-#endif
-#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
-#define ALSZ 15
-#define ALMASK ~15
-#endif
-
-/*
- * Macros to handle different pointer/register sizes for 32/64-bit code
- */
-
-/*
- * Size of a register
- */
-#ifdef __mips64
-#define SZREG 8
-#else
-#define SZREG 4
-#endif
-
-/*
- * Use the following macros in assemblercode to load/store registers,
- * pointers etc.
- */
-#if (_MIPS_SIM == _MIPS_SIM_ABI32)
-#define REG_S sw
-#define REG_L lw
-#define REG_SUBU subu
-#define REG_ADDU addu
-#endif
-#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
-#define REG_S sd
-#define REG_L ld
-#define REG_SUBU dsubu
-#define REG_ADDU daddu
-#endif
-
-/*
- * How to add/sub/load/store/shift C int variables.
- */
-#if (_MIPS_SZINT == 32)
-#define INT_ADD add
-#define INT_ADDU addu
-#define INT_ADDI addi
-#define INT_ADDIU addiu
-#define INT_SUB sub
-#define INT_SUBU subu
-#define INT_L lw
-#define INT_S sw
-#define INT_SLL sll
-#define INT_SLLV sllv
-#define INT_SRL srl
-#define INT_SRLV srlv
-#define INT_SRA sra
-#define INT_SRAV srav
-#endif
-
-#if (_MIPS_SZINT == 64)
-#define INT_ADD dadd
-#define INT_ADDU daddu
-#define INT_ADDI daddi
-#define INT_ADDIU daddiu
-#define INT_SUB dsub
-#define INT_SUBU dsubu
-#define INT_L ld
-#define INT_S sd
-#define INT_SLL dsll
-#define INT_SLLV dsllv
-#define INT_SRL dsrl
-#define INT_SRLV dsrlv
-#define INT_SRA dsra
-#define INT_SRAV dsrav
-#endif
-
-/*
- * How to add/sub/load/store/shift C long variables.
- */
-#if (_MIPS_SZLONG == 32)
-#define LONG_ADD add
-#define LONG_ADDU addu
-#define LONG_ADDI addi
-#define LONG_ADDIU addiu
-#define LONG_SUB sub
-#define LONG_SUBU subu
-#define LONG_L lw
-#define LONG_S sw
-#define LONG_SLL sll
-#define LONG_SLLV sllv
-#define LONG_SRL srl
-#define LONG_SRLV srlv
-#define LONG_SRA sra
-#define LONG_SRAV srav
-
-#define LONG .word
-#define LONGSIZE 4
-#define LONGMASK 3
-#define LONGLOG 2
-#endif
-
-#if (_MIPS_SZLONG == 64)
-#define LONG_ADD dadd
-#define LONG_ADDU daddu
-#define LONG_ADDI daddi
-#define LONG_ADDIU daddiu
-#define LONG_SUB dsub
-#define LONG_SUBU dsubu
-#define LONG_L ld
-#define LONG_S sd
-#define LONG_SLL dsll
-#define LONG_SLLV dsllv
-#define LONG_SRL dsrl
-#define LONG_SRLV dsrlv
-#define LONG_SRA dsra
-#define LONG_SRAV dsrav
-
-#define LONG .dword
-#define LONGSIZE 8
-#define LONGMASK 7
-#define LONGLOG 3
-#endif
-
-/*
- * How to add/sub/load/store/shift pointers.
- */
-#if (_MIPS_SZPTR == 32)
-#define PTR_ADD add
-#define PTR_ADDU addu
-#define PTR_ADDI addi
-#define PTR_ADDIU addiu
-#define PTR_SUB sub
-#define PTR_SUBU subu
-#define PTR_L lw
-#define PTR_S sw
-#define PTR_LA la
-#define PTR_LI li
-#define PTR_SLL sll
-#define PTR_SLLV sllv
-#define PTR_SRL srl
-#define PTR_SRLV srlv
-#define PTR_SRA sra
-#define PTR_SRAV srav
-
-#define PTR_SCALESHIFT 2
-
-#define PTR .word
-#define PTRSIZE 4
-#define PTRLOG 2
-#endif
-
-#if (_MIPS_SZPTR == 64)
-#define PTR_ADD dadd
-#define PTR_ADDU daddu
-#define PTR_ADDI daddi
-#define PTR_ADDIU daddiu
-#define PTR_SUB dsub
-#define PTR_SUBU dsubu
-#define PTR_L ld
-#define PTR_S sd
-#define PTR_LA dla
-#define PTR_LI dli
-#define PTR_SLL dsll
-#define PTR_SLLV dsllv
-#define PTR_SRL dsrl
-#define PTR_SRLV dsrlv
-#define PTR_SRA dsra
-#define PTR_SRAV dsrav
-
-#define PTR_SCALESHIFT 3
-
-#define PTR .dword
-#define PTRSIZE 8
-#define PTRLOG 3
-#endif
-
-/*
- * Some cp0 registers were extended to 64bit for MIPS III.
- */
-#if (_MIPS_SIM == _MIPS_SIM_ABI32)
-#define MFC0 mfc0
-#define MTC0 mtc0
-#endif
-#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
-#define MFC0 dmfc0
-#define MTC0 dmtc0
-#endif
-
-#define SSNOP sll zero, zero, 1
-
-#ifdef CONFIG_SGI_IP28
-/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
-#include <asm/cacheops.h>
-#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
-#else
-#define R10KCBARRIER(addr)
-#endif
-
-#endif /* __ASM_ASM_H */
diff --git a/include/asm-mips/asmmacro-32.h b/include/asm-mips/asmmacro-32.h
deleted file mode 100644
index 5de3963f511..00000000000
--- a/include/asm-mips/asmmacro-32.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * asmmacro.h: Assembler macros to make things easier to read.
- *
- * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- * Copyright (C) 1998, 1999, 2003 Ralf Baechle
- */
-#ifndef _ASM_ASMMACRO_32_H
-#define _ASM_ASMMACRO_32_H
-
-#include <asm/asm-offsets.h>
-#include <asm/regdef.h>
-#include <asm/fpregdef.h>
-#include <asm/mipsregs.h>
-
- .macro fpu_save_double thread status tmp1=t0
- cfc1 \tmp1, fcr31
- sdc1 $f0, THREAD_FPR0(\thread)
- sdc1 $f2, THREAD_FPR2(\thread)
- sdc1 $f4, THREAD_FPR4(\thread)
- sdc1 $f6, THREAD_FPR6(\thread)
- sdc1 $f8, THREAD_FPR8(\thread)
- sdc1 $f10, THREAD_FPR10(\thread)
- sdc1 $f12, THREAD_FPR12(\thread)
- sdc1 $f14, THREAD_FPR14(\thread)
- sdc1 $f16, THREAD_FPR16(\thread)
- sdc1 $f18, THREAD_FPR18(\thread)
- sdc1 $f20, THREAD_FPR20(\thread)
- sdc1 $f22, THREAD_FPR22(\thread)
- sdc1 $f24, THREAD_FPR24(\thread)
- sdc1 $f26, THREAD_FPR26(\thread)
- sdc1 $f28, THREAD_FPR28(\thread)
- sdc1 $f30, THREAD_FPR30(\thread)
- sw \tmp1, THREAD_FCR31(\thread)
- .endm
-
- .macro fpu_save_single thread tmp=t0
- cfc1 \tmp, fcr31
- swc1 $f0, THREAD_FPR0(\thread)
- swc1 $f1, THREAD_FPR1(\thread)
- swc1 $f2, THREAD_FPR2(\thread)
- swc1 $f3, THREAD_FPR3(\thread)
- swc1 $f4, THREAD_FPR4(\thread)
- swc1 $f5, THREAD_FPR5(\thread)
- swc1 $f6, THREAD_FPR6(\thread)
- swc1 $f7, THREAD_FPR7(\thread)
- swc1 $f8, THREAD_FPR8(\thread)
- swc1 $f9, THREAD_FPR9(\thread)
- swc1 $f10, THREAD_FPR10(\thread)
- swc1 $f11, THREAD_FPR11(\thread)
- swc1 $f12, THREAD_FPR12(\thread)
- swc1 $f13, THREAD_FPR13(\thread)
- swc1 $f14, THREAD_FPR14(\thread)
- swc1 $f15, THREAD_FPR15(\thread)
- swc1 $f16, THREAD_FPR16(\thread)
- swc1 $f17, THREAD_FPR17(\thread)
- swc1 $f18, THREAD_FPR18(\thread)
- swc1 $f19, THREAD_FPR19(\thread)
- swc1 $f20, THREAD_FPR20(\thread)
- swc1 $f21, THREAD_FPR21(\thread)
- swc1 $f22, THREAD_FPR22(\thread)
- swc1 $f23, THREAD_FPR23(\thread)
- swc1 $f24, THREAD_FPR24(\thread)
- swc1 $f25, THREAD_FPR25(\thread)
- swc1 $f26, THREAD_FPR26(\thread)
- swc1 $f27, THREAD_FPR27(\thread)
- swc1 $f28, THREAD_FPR28(\thread)
- swc1 $f29, THREAD_FPR29(\thread)
- swc1 $f30, THREAD_FPR30(\thread)
- swc1 $f31, THREAD_FPR31(\thread)
- sw \tmp, THREAD_FCR31(\thread)
- .endm
-
- .macro fpu_restore_double thread status tmp=t0
- lw \tmp, THREAD_FCR31(\thread)
- ldc1 $f0, THREAD_FPR0(\thread)
- ldc1 $f2, THREAD_FPR2(\thread)
- ldc1 $f4, THREAD_FPR4(\thread)
- ldc1 $f6, THREAD_FPR6(\thread)
- ldc1 $f8, THREAD_FPR8(\thread)
- ldc1 $f10, THREAD_FPR10(\thread)
- ldc1 $f12, THREAD_FPR12(\thread)
- ldc1 $f14, THREAD_FPR14(\thread)
- ldc1 $f16, THREAD_FPR16(\thread)
- ldc1 $f18, THREAD_FPR18(\thread)
- ldc1 $f20, THREAD_FPR20(\thread)
- ldc1 $f22, THREAD_FPR22(\thread)
- ldc1 $f24, THREAD_FPR24(\thread)
- ldc1 $f26, THREAD_FPR26(\thread)
- ldc1 $f28, THREAD_FPR28(\thread)
- ldc1 $f30, THREAD_FPR30(\thread)
- ctc1 \tmp, fcr31
- .endm
-
- .macro fpu_restore_single thread tmp=t0
- lw \tmp, THREAD_FCR31(\thread)
- lwc1 $f0, THREAD_FPR0(\thread)
- lwc1 $f1, THREAD_FPR1(\thread)
- lwc1 $f2, THREAD_FPR2(\thread)
- lwc1 $f3, THREAD_FPR3(\thread)
- lwc1 $f4, THREAD_FPR4(\thread)
- lwc1 $f5, THREAD_FPR5(\thread)
- lwc1 $f6, THREAD_FPR6(\thread)
- lwc1 $f7, THREAD_FPR7(\thread)
- lwc1 $f8, THREAD_FPR8(\thread)
- lwc1 $f9, THREAD_FPR9(\thread)
- lwc1 $f10, THREAD_FPR10(\thread)
- lwc1 $f11, THREAD_FPR11(\thread)
- lwc1 $f12, THREAD_FPR12(\thread)
- lwc1 $f13, THREAD_FPR13(\thread)
- lwc1 $f14, THREAD_FPR14(\thread)
- lwc1 $f15, THREAD_FPR15(\thread)
- lwc1 $f16, THREAD_FPR16(\thread)
- lwc1 $f17, THREAD_FPR17(\thread)
- lwc1 $f18, THREAD_FPR18(\thread)
- lwc1 $f19, THREAD_FPR19(\thread)
- lwc1 $f20, THREAD_FPR20(\thread)
- lwc1 $f21, THREAD_FPR21(\thread)
- lwc1 $f22, THREAD_FPR22(\thread)
- lwc1 $f23, THREAD_FPR23(\thread)
- lwc1 $f24, THREAD_FPR24(\thread)
- lwc1 $f25, THREAD_FPR25(\thread)
- lwc1 $f26, THREAD_FPR26(\thread)
- lwc1 $f27, THREAD_FPR27(\thread)
- lwc1 $f28, THREAD_FPR28(\thread)
- lwc1 $f29, THREAD_FPR29(\thread)
- lwc1 $f30, THREAD_FPR30(\thread)
- lwc1 $f31, THREAD_FPR31(\thread)
- ctc1 \tmp, fcr31
- .endm
-
- .macro cpu_save_nonscratch thread
- LONG_S s0, THREAD_REG16(\thread)
- LONG_S s1, THREAD_REG17(\thread)
- LONG_S s2, THREAD_REG18(\thread)
- LONG_S s3, THREAD_REG19(\thread)
- LONG_S s4, THREAD_REG20(\thread)
- LONG_S s5, THREAD_REG21(\thread)
- LONG_S s6, THREAD_REG22(\thread)
- LONG_S s7, THREAD_REG23(\thread)
- LONG_S sp, THREAD_REG29(\thread)
- LONG_S fp, THREAD_REG30(\thread)
- .endm
-
- .macro cpu_restore_nonscratch thread
- LONG_L s0, THREAD_REG16(\thread)
- LONG_L s1, THREAD_REG17(\thread)
- LONG_L s2, THREAD_REG18(\thread)
- LONG_L s3, THREAD_REG19(\thread)
- LONG_L s4, THREAD_REG20(\thread)
- LONG_L s5, THREAD_REG21(\thread)
- LONG_L s6, THREAD_REG22(\thread)
- LONG_L s7, THREAD_REG23(\thread)
- LONG_L sp, THREAD_REG29(\thread)
- LONG_L fp, THREAD_REG30(\thread)
- LONG_L ra, THREAD_REG31(\thread)
- .endm
-
-#endif /* _ASM_ASMMACRO_32_H */
diff --git a/include/asm-mips/asmmacro-64.h b/include/asm-mips/asmmacro-64.h
deleted file mode 100644
index 225feefcb25..00000000000
--- a/include/asm-mips/asmmacro-64.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * asmmacro.h: Assembler macros to make things easier to read.
- *
- * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- * Copyright (C) 1998, 1999 Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_ASMMACRO_64_H
-#define _ASM_ASMMACRO_64_H
-
-#include <asm/asm-offsets.h>
-#include <asm/regdef.h>
-#include <asm/fpregdef.h>
-#include <asm/mipsregs.h>
-
- .macro fpu_save_16even thread tmp=t0
- cfc1 \tmp, fcr31
- sdc1 $f0, THREAD_FPR0(\thread)
- sdc1 $f2, THREAD_FPR2(\thread)
- sdc1 $f4, THREAD_FPR4(\thread)
- sdc1 $f6, THREAD_FPR6(\thread)
- sdc1 $f8, THREAD_FPR8(\thread)
- sdc1 $f10, THREAD_FPR10(\thread)
- sdc1 $f12, THREAD_FPR12(\thread)
- sdc1 $f14, THREAD_FPR14(\thread)
- sdc1 $f16, THREAD_FPR16(\thread)
- sdc1 $f18, THREAD_FPR18(\thread)
- sdc1 $f20, THREAD_FPR20(\thread)
- sdc1 $f22, THREAD_FPR22(\thread)
- sdc1 $f24, THREAD_FPR24(\thread)
- sdc1 $f26, THREAD_FPR26(\thread)
- sdc1 $f28, THREAD_FPR28(\thread)
- sdc1 $f30, THREAD_FPR30(\thread)
- sw \tmp, THREAD_FCR31(\thread)
- .endm
-
- .macro fpu_save_16odd thread
- sdc1 $f1, THREAD_FPR1(\thread)
- sdc1 $f3, THREAD_FPR3(\thread)
- sdc1 $f5, THREAD_FPR5(\thread)
- sdc1 $f7, THREAD_FPR7(\thread)
- sdc1 $f9, THREAD_FPR9(\thread)
- sdc1 $f11, THREAD_FPR11(\thread)
- sdc1 $f13, THREAD_FPR13(\thread)
- sdc1 $f15, THREAD_FPR15(\thread)
- sdc1 $f17, THREAD_FPR17(\thread)
- sdc1 $f19, THREAD_FPR19(\thread)
- sdc1 $f21, THREAD_FPR21(\thread)
- sdc1 $f23, THREAD_FPR23(\thread)
- sdc1 $f25, THREAD_FPR25(\thread)
- sdc1 $f27, THREAD_FPR27(\thread)
- sdc1 $f29, THREAD_FPR29(\thread)
- sdc1 $f31, THREAD_FPR31(\thread)
- .endm
-
- .macro fpu_save_double thread status tmp
- sll \tmp, \status, 5
- bgez \tmp, 2f
- fpu_save_16odd \thread
-2:
- fpu_save_16even \thread \tmp
- .endm
-
- .macro fpu_restore_16even thread tmp=t0
- lw \tmp, THREAD_FCR31(\thread)
- ldc1 $f0, THREAD_FPR0(\thread)
- ldc1 $f2, THREAD_FPR2(\thread)
- ldc1 $f4, THREAD_FPR4(\thread)
- ldc1 $f6, THREAD_FPR6(\thread)
- ldc1 $f8, THREAD_FPR8(\thread)
- ldc1 $f10, THREAD_FPR10(\thread)
- ldc1 $f12, THREAD_FPR12(\thread)
- ldc1 $f14, THREAD_FPR14(\thread)
- ldc1 $f16, THREAD_FPR16(\thread)
- ldc1 $f18, THREAD_FPR18(\thread)
- ldc1 $f20, THREAD_FPR20(\thread)
- ldc1 $f22, THREAD_FPR22(\thread)
- ldc1 $f24, THREAD_FPR24(\thread)
- ldc1 $f26, THREAD_FPR26(\thread)
- ldc1 $f28, THREAD_FPR28(\thread)
- ldc1 $f30, THREAD_FPR30(\thread)
- ctc1 \tmp, fcr31
- .endm
-
- .macro fpu_restore_16odd thread
- ldc1 $f1, THREAD_FPR1(\thread)
- ldc1 $f3, THREAD_FPR3(\thread)
- ldc1 $f5, THREAD_FPR5(\thread)
- ldc1 $f7, THREAD_FPR7(\thread)
- ldc1 $f9, THREAD_FPR9(\thread)
- ldc1 $f11, THREAD_FPR11(\thread)
- ldc1 $f13, THREAD_FPR13(\thread)
- ldc1 $f15, THREAD_FPR15(\thread)
- ldc1 $f17, THREAD_FPR17(\thread)
- ldc1 $f19, THREAD_FPR19(\thread)
- ldc1 $f21, THREAD_FPR21(\thread)
- ldc1 $f23, THREAD_FPR23(\thread)
- ldc1 $f25, THREAD_FPR25(\thread)
- ldc1 $f27, THREAD_FPR27(\thread)
- ldc1 $f29, THREAD_FPR29(\thread)
- ldc1 $f31, THREAD_FPR31(\thread)
- .endm
-
- .macro fpu_restore_double thread status tmp
- sll \tmp, \status, 5
- bgez \tmp, 1f # 16 register mode?
-
- fpu_restore_16odd \thread
-1: fpu_restore_16even \thread \tmp
- .endm
-
- .macro cpu_save_nonscratch thread
- LONG_S s0, THREAD_REG16(\thread)
- LONG_S s1, THREAD_REG17(\thread)
- LONG_S s2, THREAD_REG18(\thread)
- LONG_S s3, THREAD_REG19(\thread)
- LONG_S s4, THREAD_REG20(\thread)
- LONG_S s5, THREAD_REG21(\thread)
- LONG_S s6, THREAD_REG22(\thread)
- LONG_S s7, THREAD_REG23(\thread)
- LONG_S sp, THREAD_REG29(\thread)
- LONG_S fp, THREAD_REG30(\thread)
- .endm
-
- .macro cpu_restore_nonscratch thread
- LONG_L s0, THREAD_REG16(\thread)
- LONG_L s1, THREAD_REG17(\thread)
- LONG_L s2, THREAD_REG18(\thread)
- LONG_L s3, THREAD_REG19(\thread)
- LONG_L s4, THREAD_REG20(\thread)
- LONG_L s5, THREAD_REG21(\thread)
- LONG_L s6, THREAD_REG22(\thread)
- LONG_L s7, THREAD_REG23(\thread)
- LONG_L sp, THREAD_REG29(\thread)
- LONG_L fp, THREAD_REG30(\thread)
- LONG_L ra, THREAD_REG31(\thread)
- .endm
-
-#endif /* _ASM_ASMMACRO_64_H */
diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h
deleted file mode 100644
index 7a881755800..00000000000
--- a/include/asm-mips/asmmacro.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003 Ralf Baechle
- */
-#ifndef _ASM_ASMMACRO_H
-#define _ASM_ASMMACRO_H
-
-#include <asm/hazards.h>
-
-#ifdef CONFIG_32BIT
-#include <asm/asmmacro-32.h>
-#endif
-#ifdef CONFIG_64BIT
-#include <asm/asmmacro-64.h>
-#endif
-#ifdef CONFIG_MIPS_MT_SMTC
-#include <asm/mipsmtregs.h>
-#endif
-
-#ifdef CONFIG_MIPS_MT_SMTC
- .macro local_irq_enable reg=t0
- mfc0 \reg, CP0_TCSTATUS
- ori \reg, \reg, TCSTATUS_IXMT
- xori \reg, \reg, TCSTATUS_IXMT
- mtc0 \reg, CP0_TCSTATUS
- _ehb
- .endm
-
- .macro local_irq_disable reg=t0
- mfc0 \reg, CP0_TCSTATUS
- ori \reg, \reg, TCSTATUS_IXMT
- mtc0 \reg, CP0_TCSTATUS
- _ehb
- .endm
-#else
- .macro local_irq_enable reg=t0
- mfc0 \reg, CP0_STATUS
- ori \reg, \reg, 1
- mtc0 \reg, CP0_STATUS
- irq_enable_hazard
- .endm
-
- .macro local_irq_disable reg=t0
- mfc0 \reg, CP0_STATUS
- ori \reg, \reg, 1
- xori \reg, \reg, 1
- mtc0 \reg, CP0_STATUS
- irq_disable_hazard
- .endm
-#endif /* CONFIG_MIPS_MT_SMTC */
-
-/*
- * Temporary until all gas have MT ASE support
- */
- .macro DMT reg=0
- .word 0x41600bc1 | (\reg << 16)
- .endm
-
- .macro EMT reg=0
- .word 0x41600be1 | (\reg << 16)
- .endm
-
- .macro DVPE reg=0
- .word 0x41600001 | (\reg << 16)
- .endm
-
- .macro EVPE reg=0
- .word 0x41600021 | (\reg << 16)
- .endm
-
- .macro MFTR rt=0, rd=0, u=0, sel=0
- .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
- .endm
-
- .macro MTTR rt=0, rd=0, u=0, sel=0
- .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
- .endm
-
-#endif /* _ASM_ASMMACRO_H */
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
deleted file mode 100644
index 1232be3885b..00000000000
--- a/include/asm-mips/atomic.h
+++ /dev/null
@@ -1,801 +0,0 @@
-/*
- * Atomic operations that C can't guarantee us. Useful for
- * resource counting etc..
- *
- * But use these as seldom as possible since they are much more slower
- * than regular operations.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle
- */
-#ifndef _ASM_ATOMIC_H
-#define _ASM_ATOMIC_H
-
-#include <linux/irqflags.h>
-#include <asm/barrier.h>
-#include <asm/cpu-features.h>
-#include <asm/war.h>
-#include <asm/system.h>
-
-typedef struct { volatile int counter; } atomic_t;
-
-#define ATOMIC_INIT(i) { (i) }
-
-/*
- * atomic_read - read atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically reads the value of @v.
- */
-#define atomic_read(v) ((v)->counter)
-
-/*
- * atomic_set - set atomic variable
- * @v: pointer of type atomic_t
- * @i: required value
- *
- * Atomically sets the value of @v to @i.
- */
-#define atomic_set(v, i) ((v)->counter = (i))
-
-/*
- * atomic_add - add integer to atomic variable
- * @i: integer value to add
- * @v: pointer of type atomic_t
- *
- * Atomically adds @i to @v.
- */
-static __inline__ void atomic_add(int i, atomic_t * v)
-{
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %0, %1 # atomic_add \n"
- " addu %0, %2 \n"
- " sc %0, %1 \n"
- " beqzl %0, 1b \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
- } else if (cpu_has_llsc) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %0, %1 # atomic_add \n"
- " addu %0, %2 \n"
- " sc %0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
- } else {
- unsigned long flags;
-
- raw_local_irq_save(flags);
- v->counter += i;
- raw_local_irq_restore(flags);
- }
-}
-
-/*
- * atomic_sub - subtract the atomic variable
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v.
- */
-static __inline__ void atomic_sub(int i, atomic_t * v)
-{
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %0, %1 # atomic_sub \n"
- " subu %0, %2 \n"
- " sc %0, %1 \n"
- " beqzl %0, 1b \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
- } else if (cpu_has_llsc) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %0, %1 # atomic_sub \n"
- " subu %0, %2 \n"
- " sc %0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
- } else {
- unsigned long flags;
-
- raw_local_irq_save(flags);
- v->counter -= i;
- raw_local_irq_restore(flags);
- }
-}
-
-/*
- * Same as above, but return the result value
- */
-static __inline__ int atomic_add_return(int i, atomic_t * v)
-{
- unsigned long result;
-
- smp_llsc_mb();
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %1, %2 # atomic_add_return \n"
- " addu %0, %1, %3 \n"
- " sc %0, %2 \n"
- " beqzl %0, 1b \n"
- " addu %0, %1, %3 \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
- } else if (cpu_has_llsc) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %1, %2 # atomic_add_return \n"
- " addu %0, %1, %3 \n"
- " sc %0, %2 \n"
- " beqz %0, 2f \n"
- " addu %0, %1, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
- } else {
- unsigned long flags;
-
- raw_local_irq_save(flags);
- result = v->counter;
- result += i;
- v->counter = result;
- raw_local_irq_restore(flags);
- }
-
- smp_llsc_mb();
-
- return result;
-}
-
-static __inline__ int atomic_sub_return(int i, atomic_t * v)
-{
- unsigned long result;
-
- smp_llsc_mb();
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %1, %2 # atomic_sub_return \n"
- " subu %0, %1, %3 \n"
- " sc %0, %2 \n"
- " beqzl %0, 1b \n"
- " subu %0, %1, %3 \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
- } else if (cpu_has_llsc) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %1, %2 # atomic_sub_return \n"
- " subu %0, %1, %3 \n"
- " sc %0, %2 \n"
- " beqz %0, 2f \n"
- " subu %0, %1, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
- } else {
- unsigned long flags;
-
- raw_local_irq_save(flags);
- result = v->counter;
- result -= i;
- v->counter = result;
- raw_local_irq_restore(flags);
- }
-
- smp_llsc_mb();
-
- return result;
-}
-
-/*
- * atomic_sub_if_positive - conditionally subtract integer from atomic variable
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically test @v and subtract @i if @v is greater or equal than @i.
- * The function returns the old value of @v minus @i.
- */
-static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
-{
- unsigned long result;
-
- smp_llsc_mb();
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %1, %2 # atomic_sub_if_positive\n"
- " subu %0, %1, %3 \n"
- " bltz %0, 1f \n"
- " sc %0, %2 \n"
- " .set noreorder \n"
- " beqzl %0, 1b \n"
- " subu %0, %1, %3 \n"
- " .set reorder \n"
- "1: \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
- } else if (cpu_has_llsc) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %1, %2 # atomic_sub_if_positive\n"
- " subu %0, %1, %3 \n"
- " bltz %0, 1f \n"
- " sc %0, %2 \n"
- " .set noreorder \n"
- " beqz %0, 2f \n"
- " subu %0, %1, %3 \n"
- " .set reorder \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- "1: \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
- } else {
- unsigned long flags;
-
- raw_local_irq_save(flags);
- result = v->counter;
- result -= i;
- if (result >= 0)
- v->counter = result;
- raw_local_irq_restore(flags);
- }
-
- smp_llsc_mb();
-
- return result;
-}
-
-#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), (new)))
-
-/**
- * atomic_add_unless - add unless the number is a given value
- * @v: pointer of type atomic_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns non-zero if @v was not @u, and zero otherwise.
- */
-static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
-{
- int c, old;
- c = atomic_read(v);
- for (;;) {
- if (unlikely(c == (u)))
- break;
- old = atomic_cmpxchg((v), c, c + (a));
- if (likely(old == c))
- break;
- c = old;
- }
- return c != (u);
-}
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-#define atomic_dec_return(v) atomic_sub_return(1, (v))
-#define atomic_inc_return(v) atomic_add_return(1, (v))
-
-/*
- * atomic_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
-
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-/*
- * atomic_dec_and_test - decrement by 1 and test
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1 and
- * returns true if the result is 0, or false for all other
- * cases.
- */
-#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
-
-/*
- * atomic_dec_if_positive - decrement by 1 if old value positive
- * @v: pointer of type atomic_t
- */
-#define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v)
-
-/*
- * atomic_inc - increment atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1.
- */
-#define atomic_inc(v) atomic_add(1, (v))
-
-/*
- * atomic_dec - decrement and test
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1.
- */
-#define atomic_dec(v) atomic_sub(1, (v))
-
-/*
- * atomic_add_negative - add and test if negative
- * @v: pointer of type atomic_t
- * @i: integer value to add
- *
- * Atomically adds @i to @v and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-#define atomic_add_negative(i, v) (atomic_add_return(i, (v)) < 0)
-
-#ifdef CONFIG_64BIT
-
-typedef struct { volatile long counter; } atomic64_t;
-
-#define ATOMIC64_INIT(i) { (i) }
-
-/*
- * atomic64_read - read atomic variable
- * @v: pointer of type atomic64_t
- *
- */
-#define atomic64_read(v) ((v)->counter)
-
-/*
- * atomic64_set - set atomic variable
- * @v: pointer of type atomic64_t
- * @i: required value
- */
-#define atomic64_set(v, i) ((v)->counter = (i))
-
-/*
- * atomic64_add - add integer to atomic variable
- * @i: integer value to add
- * @v: pointer of type atomic64_t
- *
- * Atomically adds @i to @v.
- */
-static __inline__ void atomic64_add(long i, atomic64_t * v)
-{
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %0, %1 # atomic64_add \n"
- " addu %0, %2 \n"
- " scd %0, %1 \n"
- " beqzl %0, 1b \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
- } else if (cpu_has_llsc) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %0, %1 # atomic64_add \n"
- " addu %0, %2 \n"
- " scd %0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
- } else {
- unsigned long flags;
-
- raw_local_irq_save(flags);
- v->counter += i;
- raw_local_irq_restore(flags);
- }
-}
-
-/*
- * atomic64_sub - subtract the atomic variable
- * @i: integer value to subtract
- * @v: pointer of type atomic64_t
- *
- * Atomically subtracts @i from @v.
- */
-static __inline__ void atomic64_sub(long i, atomic64_t * v)
-{
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %0, %1 # atomic64_sub \n"
- " subu %0, %2 \n"
- " scd %0, %1 \n"
- " beqzl %0, 1b \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
- } else if (cpu_has_llsc) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %0, %1 # atomic64_sub \n"
- " subu %0, %2 \n"
- " scd %0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
- } else {
- unsigned long flags;
-
- raw_local_irq_save(flags);
- v->counter -= i;
- raw_local_irq_restore(flags);
- }
-}
-
-/*
- * Same as above, but return the result value
- */
-static __inline__ long atomic64_add_return(long i, atomic64_t * v)
-{
- unsigned long result;
-
- smp_llsc_mb();
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %1, %2 # atomic64_add_return \n"
- " addu %0, %1, %3 \n"
- " scd %0, %2 \n"
- " beqzl %0, 1b \n"
- " addu %0, %1, %3 \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
- } else if (cpu_has_llsc) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %1, %2 # atomic64_add_return \n"
- " addu %0, %1, %3 \n"
- " scd %0, %2 \n"
- " beqz %0, 2f \n"
- " addu %0, %1, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
- } else {
- unsigned long flags;
-
- raw_local_irq_save(flags);
- result = v->counter;
- result += i;
- v->counter = result;
- raw_local_irq_restore(flags);
- }
-
- smp_llsc_mb();
-
- return result;
-}
-
-static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
-{
- unsigned long result;
-
- smp_llsc_mb();
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %1, %2 # atomic64_sub_return \n"
- " subu %0, %1, %3 \n"
- " scd %0, %2 \n"
- " beqzl %0, 1b \n"
- " subu %0, %1, %3 \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
- } else if (cpu_has_llsc) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %1, %2 # atomic64_sub_return \n"
- " subu %0, %1, %3 \n"
- " scd %0, %2 \n"
- " beqz %0, 2f \n"
- " subu %0, %1, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
- } else {
- unsigned long flags;
-
- raw_local_irq_save(flags);
- result = v->counter;
- result -= i;
- v->counter = result;
- raw_local_irq_restore(flags);
- }
-
- smp_llsc_mb();
-
- return result;
-}
-
-/*
- * atomic64_sub_if_positive - conditionally subtract integer from atomic variable
- * @i: integer value to subtract
- * @v: pointer of type atomic64_t
- *
- * Atomically test @v and subtract @i if @v is greater or equal than @i.
- * The function returns the old value of @v minus @i.
- */
-static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
-{
- unsigned long result;
-
- smp_llsc_mb();
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %1, %2 # atomic64_sub_if_positive\n"
- " dsubu %0, %1, %3 \n"
- " bltz %0, 1f \n"
- " scd %0, %2 \n"
- " .set noreorder \n"
- " beqzl %0, 1b \n"
- " dsubu %0, %1, %3 \n"
- " .set reorder \n"
- "1: \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
- } else if (cpu_has_llsc) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %1, %2 # atomic64_sub_if_positive\n"
- " dsubu %0, %1, %3 \n"
- " bltz %0, 1f \n"
- " scd %0, %2 \n"
- " .set noreorder \n"
- " beqz %0, 2f \n"
- " dsubu %0, %1, %3 \n"
- " .set reorder \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- "1: \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
- } else {
- unsigned long flags;
-
- raw_local_irq_save(flags);
- result = v->counter;
- result -= i;
- if (result >= 0)
- v->counter = result;
- raw_local_irq_restore(flags);
- }
-
- smp_llsc_mb();
-
- return result;
-}
-
-#define atomic64_cmpxchg(v, o, n) \
- ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
-#define atomic64_xchg(v, new) (xchg(&((v)->counter), (new)))
-
-/**
- * atomic64_add_unless - add unless the number is a given value
- * @v: pointer of type atomic64_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns non-zero if @v was not @u, and zero otherwise.
- */
-static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
-{
- long c, old;
- c = atomic64_read(v);
- for (;;) {
- if (unlikely(c == (u)))
- break;
- old = atomic64_cmpxchg((v), c, c + (a));
- if (likely(old == c))
- break;
- c = old;
- }
- return c != (u);
-}
-
-#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
-
-#define atomic64_dec_return(v) atomic64_sub_return(1, (v))
-#define atomic64_inc_return(v) atomic64_add_return(1, (v))
-
-/*
- * atomic64_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @v: pointer of type atomic64_t
- *
- * Atomically subtracts @i from @v and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0)
-
-/*
- * atomic64_inc_and_test - increment and test
- * @v: pointer of type atomic64_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
-
-/*
- * atomic64_dec_and_test - decrement by 1 and test
- * @v: pointer of type atomic64_t
- *
- * Atomically decrements @v by 1 and
- * returns true if the result is 0, or false for all other
- * cases.
- */
-#define atomic64_dec_and_test(v) (atomic64_sub_return(1, (v)) == 0)
-
-/*
- * atomic64_dec_if_positive - decrement by 1 if old value positive
- * @v: pointer of type atomic64_t
- */
-#define atomic64_dec_if_positive(v) atomic64_sub_if_positive(1, v)
-
-/*
- * atomic64_inc - increment atomic variable
- * @v: pointer of type atomic64_t
- *
- * Atomically increments @v by 1.
- */
-#define atomic64_inc(v) atomic64_add(1, (v))
-
-/*
- * atomic64_dec - decrement and test
- * @v: pointer of type atomic64_t
- *
- * Atomically decrements @v by 1.
- */
-#define atomic64_dec(v) atomic64_sub(1, (v))
-
-/*
- * atomic64_add_negative - add and test if negative
- * @v: pointer of type atomic64_t
- * @i: integer value to add
- *
- * Atomically adds @i to @v and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-#define atomic64_add_negative(i, v) (atomic64_add_return(i, (v)) < 0)
-
-#endif /* CONFIG_64BIT */
-
-/*
- * atomic*_return operations are serializing but not the non-*_return
- * versions.
- */
-#define smp_mb__before_atomic_dec() smp_llsc_mb()
-#define smp_mb__after_atomic_dec() smp_llsc_mb()
-#define smp_mb__before_atomic_inc() smp_llsc_mb()
-#define smp_mb__after_atomic_inc() smp_llsc_mb()
-
-#include <asm-generic/atomic.h>
-
-#endif /* _ASM_ATOMIC_H */
diff --git a/include/asm-mips/auxvec.h b/include/asm-mips/auxvec.h
deleted file mode 100644
index 7cf7f2d2194..00000000000
--- a/include/asm-mips/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _ASM_AUXVEC_H
-#define _ASM_AUXVEC_H
-
-#endif /* _ASM_AUXVEC_H */
diff --git a/include/asm-mips/barrier.h b/include/asm-mips/barrier.h
deleted file mode 100644
index 8e9ac313ca3..00000000000
--- a/include/asm-mips/barrier.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_BARRIER_H
-#define __ASM_BARRIER_H
-
-/*
- * read_barrier_depends - Flush all pending reads that subsequents reads
- * depend on.
- *
- * No data-dependent reads from memory-like regions are ever reordered
- * over this barrier. All reads preceding this primitive are guaranteed
- * to access memory (but not necessarily other CPUs' caches) before any
- * reads following this primitive that depend on the data return by
- * any of the preceding reads. This primitive is much lighter weight than
- * rmb() on most CPUs, and is never heavier weight than is
- * rmb().
- *
- * These ordering constraints are respected by both the local CPU
- * and the compiler.
- *
- * Ordering is not guaranteed by anything other than these primitives,
- * not even by data dependencies. See the documentation for
- * memory_barrier() for examples and URLs to more information.
- *
- * For example, the following code would force ordering (the initial
- * value of "a" is zero, "b" is one, and "p" is "&a"):
- *
- * <programlisting>
- * CPU 0 CPU 1
- *
- * b = 2;
- * memory_barrier();
- * p = &b; q = p;
- * read_barrier_depends();
- * d = *q;
- * </programlisting>
- *
- * because the read of "*q" depends on the read of "p" and these
- * two reads are separated by a read_barrier_depends(). However,
- * the following code, with the same initial values for "a" and "b":
- *
- * <programlisting>
- * CPU 0 CPU 1
- *
- * a = 2;
- * memory_barrier();
- * b = 3; y = b;
- * read_barrier_depends();
- * x = a;
- * </programlisting>
- *
- * does not enforce ordering, since there is no data dependency between
- * the read of "a" and the read of "b". Therefore, on some CPUs, such
- * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
- * in cases like this where there are no data dependencies.
- */
-
-#define read_barrier_depends() do { } while(0)
-#define smp_read_barrier_depends() do { } while(0)
-
-#ifdef CONFIG_CPU_HAS_SYNC
-#define __sync() \
- __asm__ __volatile__( \
- ".set push\n\t" \
- ".set noreorder\n\t" \
- ".set mips2\n\t" \
- "sync\n\t" \
- ".set pop" \
- : /* no output */ \
- : /* no input */ \
- : "memory")
-#else
-#define __sync() do { } while(0)
-#endif
-
-#define __fast_iob() \
- __asm__ __volatile__( \
- ".set push\n\t" \
- ".set noreorder\n\t" \
- "lw $0,%0\n\t" \
- "nop\n\t" \
- ".set pop" \
- : /* no output */ \
- : "m" (*(int *)CKSEG1) \
- : "memory")
-
-#define fast_wmb() __sync()
-#define fast_rmb() __sync()
-#define fast_mb() __sync()
-#ifdef CONFIG_SGI_IP28
-#define fast_iob() \
- __asm__ __volatile__( \
- ".set push\n\t" \
- ".set noreorder\n\t" \
- "lw $0,%0\n\t" \
- "sync\n\t" \
- "lw $0,%0\n\t" \
- ".set pop" \
- : /* no output */ \
- : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
- : "memory")
-#else
-#define fast_iob() \
- do { \
- __sync(); \
- __fast_iob(); \
- } while (0)
-#endif
-
-#ifdef CONFIG_CPU_HAS_WB
-
-#include <asm/wbflush.h>
-
-#define wmb() fast_wmb()
-#define rmb() fast_rmb()
-#define mb() wbflush()
-#define iob() wbflush()
-
-#else /* !CONFIG_CPU_HAS_WB */
-
-#define wmb() fast_wmb()
-#define rmb() fast_rmb()
-#define mb() fast_mb()
-#define iob() fast_iob()
-
-#endif /* !CONFIG_CPU_HAS_WB */
-
-#if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP)
-#define __WEAK_ORDERING_MB " sync \n"
-#else
-#define __WEAK_ORDERING_MB " \n"
-#endif
-#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
-#define __WEAK_LLSC_MB " sync \n"
-#else
-#define __WEAK_LLSC_MB " \n"
-#endif
-
-#define smp_mb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
-#define smp_rmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
-#define smp_wmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
-
-#define set_mb(var, value) \
- do { var = value; smp_mb(); } while (0)
-
-#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
-#define smp_llsc_rmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
-#define smp_llsc_wmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
-
-#endif /* __ASM_BARRIER_H */
diff --git a/include/asm-mips/bcache.h b/include/asm-mips/bcache.h
deleted file mode 100644
index 0ba9d6ef76a..00000000000
--- a/include/asm-mips/bcache.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 1997, 1999 by Ralf Baechle
- * Copyright (c) 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_BCACHE_H
-#define _ASM_BCACHE_H
-
-
-/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
- chipset implemented caches. On machines with other CPUs the CPU does the
- cache thing itself. */
-struct bcache_ops {
- void (*bc_enable)(void);
- void (*bc_disable)(void);
- void (*bc_wback_inv)(unsigned long page, unsigned long size);
- void (*bc_inv)(unsigned long page, unsigned long size);
-};
-
-extern void indy_sc_init(void);
-
-#ifdef CONFIG_BOARD_SCACHE
-
-extern struct bcache_ops *bcops;
-
-static inline void bc_enable(void)
-{
- bcops->bc_enable();
-}
-
-static inline void bc_disable(void)
-{
- bcops->bc_disable();
-}
-
-static inline void bc_wback_inv(unsigned long page, unsigned long size)
-{
- bcops->bc_wback_inv(page, size);
-}
-
-static inline void bc_inv(unsigned long page, unsigned long size)
-{
- bcops->bc_inv(page, size);
-}
-
-#else /* !defined(CONFIG_BOARD_SCACHE) */
-
-/* Not R4000 / R4400 / R4600 / R5000. */
-
-#define bc_enable() do { } while (0)
-#define bc_disable() do { } while (0)
-#define bc_wback_inv(page, size) do { } while (0)
-#define bc_inv(page, size) do { } while (0)
-
-#endif /* !defined(CONFIG_BOARD_SCACHE) */
-
-#endif /* _ASM_BCACHE_H */
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
deleted file mode 100644
index 49df8c4c9d2..00000000000
--- a/include/asm-mips/bitops.h
+++ /dev/null
@@ -1,672 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 1994 - 1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
- * Copyright (c) 1999, 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_BITOPS_H
-#define _ASM_BITOPS_H
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <linux/compiler.h>
-#include <linux/irqflags.h>
-#include <linux/types.h>
-#include <asm/barrier.h>
-#include <asm/bug.h>
-#include <asm/byteorder.h> /* sigh ... */
-#include <asm/cpu-features.h>
-#include <asm/sgidefs.h>
-#include <asm/war.h>
-
-#if _MIPS_SZLONG == 32
-#define SZLONG_LOG 5
-#define SZLONG_MASK 31UL
-#define __LL "ll "
-#define __SC "sc "
-#define __INS "ins "
-#define __EXT "ext "
-#elif _MIPS_SZLONG == 64
-#define SZLONG_LOG 6
-#define SZLONG_MASK 63UL
-#define __LL "lld "
-#define __SC "scd "
-#define __INS "dins "
-#define __EXT "dext "
-#endif
-
-/*
- * clear_bit() doesn't provide any barrier for the compiler.
- */
-#define smp_mb__before_clear_bit() smp_llsc_mb()
-#define smp_mb__after_clear_bit() smp_llsc_mb()
-
-/*
- * set_bit - Atomically set a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * This function is atomic and may not be reordered. See __set_bit()
- * if you do not require the atomic guarantees.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
-{
- unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned short bit = nr & SZLONG_MASK;
- unsigned long temp;
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: " __LL "%0, %1 # set_bit \n"
- " or %0, %2 \n"
- " " __SC "%0, %1 \n"
- " beqzl %0, 1b \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << bit), "m" (*m));
-#ifdef CONFIG_CPU_MIPSR2
- } else if (__builtin_constant_p(bit)) {
- __asm__ __volatile__(
- "1: " __LL "%0, %1 # set_bit \n"
- " " __INS "%0, %4, %2, 1 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (bit), "m" (*m), "r" (~0));
-#endif /* CONFIG_CPU_MIPSR2 */
- } else if (cpu_has_llsc) {
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: " __LL "%0, %1 # set_bit \n"
- " or %0, %2 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << bit), "m" (*m));
- } else {
- volatile unsigned long *a = addr;
- unsigned long mask;
- unsigned long flags;
-
- a += nr >> SZLONG_LOG;
- mask = 1UL << bit;
- raw_local_irq_save(flags);
- *a |= mask;
- raw_local_irq_restore(flags);
- }
-}
-
-/*
- * clear_bit - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * clear_bit() is atomic and may not be reordered. However, it does
- * not contain a memory barrier, so if it is used for locking purposes,
- * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
- * in order to ensure changes are visible on other processors.
- */
-static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
-{
- unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned short bit = nr & SZLONG_MASK;
- unsigned long temp;
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: " __LL "%0, %1 # clear_bit \n"
- " and %0, %2 \n"
- " " __SC "%0, %1 \n"
- " beqzl %0, 1b \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (~(1UL << bit)), "m" (*m));
-#ifdef CONFIG_CPU_MIPSR2
- } else if (__builtin_constant_p(bit)) {
- __asm__ __volatile__(
- "1: " __LL "%0, %1 # clear_bit \n"
- " " __INS "%0, $0, %2, 1 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (bit), "m" (*m));
-#endif /* CONFIG_CPU_MIPSR2 */
- } else if (cpu_has_llsc) {
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: " __LL "%0, %1 # clear_bit \n"
- " and %0, %2 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (~(1UL << bit)), "m" (*m));
- } else {
- volatile unsigned long *a = addr;
- unsigned long mask;
- unsigned long flags;
-
- a += nr >> SZLONG_LOG;
- mask = 1UL << bit;
- raw_local_irq_save(flags);
- *a &= ~mask;
- raw_local_irq_restore(flags);
- }
-}
-
-/*
- * clear_bit_unlock - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * clear_bit() is atomic and implies release semantics before the memory
- * operation. It can be used for an unlock.
- */
-static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
-{
- smp_mb__before_clear_bit();
- clear_bit(nr, addr);
-}
-
-/*
- * change_bit - Toggle a bit in memory
- * @nr: Bit to change
- * @addr: Address to start counting from
- *
- * change_bit() is atomic and may not be reordered.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
-{
- unsigned short bit = nr & SZLONG_MASK;
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: " __LL "%0, %1 # change_bit \n"
- " xor %0, %2 \n"
- " " __SC "%0, %1 \n"
- " beqzl %0, 1b \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << bit), "m" (*m));
- } else if (cpu_has_llsc) {
- unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: " __LL "%0, %1 # change_bit \n"
- " xor %0, %2 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << bit), "m" (*m));
- } else {
- volatile unsigned long *a = addr;
- unsigned long mask;
- unsigned long flags;
-
- a += nr >> SZLONG_LOG;
- mask = 1UL << bit;
- raw_local_irq_save(flags);
- *a ^= mask;
- raw_local_irq_restore(flags);
- }
-}
-
-/*
- * test_and_set_bit - Set a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int test_and_set_bit(unsigned long nr,
- volatile unsigned long *addr)
-{
- unsigned short bit = nr & SZLONG_MASK;
- unsigned long res;
-
- smp_llsc_mb();
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_set_bit \n"
- " or %2, %0, %3 \n"
- " " __SC "%2, %1 \n"
- " beqzl %2, 1b \n"
- " and %2, %0, %3 \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
- : "memory");
- } else if (cpu_has_llsc) {
- unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set push \n"
- " .set noreorder \n"
- " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_set_bit \n"
- " or %2, %0, %3 \n"
- " " __SC "%2, %1 \n"
- " beqz %2, 2f \n"
- " and %2, %0, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " nop \n"
- " .previous \n"
- " .set pop \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
- : "memory");
- } else {
- volatile unsigned long *a = addr;
- unsigned long mask;
- unsigned long flags;
-
- a += nr >> SZLONG_LOG;
- mask = 1UL << bit;
- raw_local_irq_save(flags);
- res = (mask & *a);
- *a |= mask;
- raw_local_irq_restore(flags);
- }
-
- smp_llsc_mb();
-
- return res != 0;
-}
-
-/*
- * test_and_set_bit_lock - Set a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and implies acquire ordering semantics
- * after the memory operation.
- */
-static inline int test_and_set_bit_lock(unsigned long nr,
- volatile unsigned long *addr)
-{
- unsigned short bit = nr & SZLONG_MASK;
- unsigned long res;
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_set_bit \n"
- " or %2, %0, %3 \n"
- " " __SC "%2, %1 \n"
- " beqzl %2, 1b \n"
- " and %2, %0, %3 \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
- : "memory");
- } else if (cpu_has_llsc) {
- unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set push \n"
- " .set noreorder \n"
- " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_set_bit \n"
- " or %2, %0, %3 \n"
- " " __SC "%2, %1 \n"
- " beqz %2, 2f \n"
- " and %2, %0, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " nop \n"
- " .previous \n"
- " .set pop \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
- : "memory");
- } else {
- volatile unsigned long *a = addr;
- unsigned long mask;
- unsigned long flags;
-
- a += nr >> SZLONG_LOG;
- mask = 1UL << bit;
- raw_local_irq_save(flags);
- res = (mask & *a);
- *a |= mask;
- raw_local_irq_restore(flags);
- }
-
- smp_llsc_mb();
-
- return res != 0;
-}
-/*
- * test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to clear
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int test_and_clear_bit(unsigned long nr,
- volatile unsigned long *addr)
-{
- unsigned short bit = nr & SZLONG_MASK;
- unsigned long res;
-
- smp_llsc_mb();
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_clear_bit \n"
- " or %2, %0, %3 \n"
- " xor %2, %3 \n"
- " " __SC "%2, %1 \n"
- " beqzl %2, 1b \n"
- " and %2, %0, %3 \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
- : "memory");
-#ifdef CONFIG_CPU_MIPSR2
- } else if (__builtin_constant_p(nr)) {
- unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp;
-
- __asm__ __volatile__(
- "1: " __LL "%0, %1 # test_and_clear_bit \n"
- " " __EXT "%2, %0, %3, 1 \n"
- " " __INS "%0, $0, %3, 1 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "ir" (bit), "m" (*m)
- : "memory");
-#endif
- } else if (cpu_has_llsc) {
- unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set push \n"
- " .set noreorder \n"
- " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_clear_bit \n"
- " or %2, %0, %3 \n"
- " xor %2, %3 \n"
- " " __SC "%2, %1 \n"
- " beqz %2, 2f \n"
- " and %2, %0, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " nop \n"
- " .previous \n"
- " .set pop \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
- : "memory");
- } else {
- volatile unsigned long *a = addr;
- unsigned long mask;
- unsigned long flags;
-
- a += nr >> SZLONG_LOG;
- mask = 1UL << bit;
- raw_local_irq_save(flags);
- res = (mask & *a);
- *a &= ~mask;
- raw_local_irq_restore(flags);
- }
-
- smp_llsc_mb();
-
- return res != 0;
-}
-
-/*
- * test_and_change_bit - Change a bit and return its old value
- * @nr: Bit to change
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int test_and_change_bit(unsigned long nr,
- volatile unsigned long *addr)
-{
- unsigned short bit = nr & SZLONG_MASK;
- unsigned long res;
-
- smp_llsc_mb();
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_change_bit \n"
- " xor %2, %0, %3 \n"
- " " __SC "%2, %1 \n"
- " beqzl %2, 1b \n"
- " and %2, %0, %3 \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
- : "memory");
- } else if (cpu_has_llsc) {
- unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set push \n"
- " .set noreorder \n"
- " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_change_bit \n"
- " xor %2, %0, %3 \n"
- " " __SC "\t%2, %1 \n"
- " beqz %2, 2f \n"
- " and %2, %0, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " nop \n"
- " .previous \n"
- " .set pop \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
- : "memory");
- } else {
- volatile unsigned long *a = addr;
- unsigned long mask;
- unsigned long flags;
-
- a += nr >> SZLONG_LOG;
- mask = 1UL << bit;
- raw_local_irq_save(flags);
- res = (mask & *a);
- *a ^= mask;
- raw_local_irq_restore(flags);
- }
-
- smp_llsc_mb();
-
- return res != 0;
-}
-
-#include <asm-generic/bitops/non-atomic.h>
-
-/*
- * __clear_bit_unlock - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * __clear_bit() is non-atomic and implies release semantics before the memory
- * operation. It can be used for an unlock if no other CPUs can concurrently
- * modify other bits in the word.
- */
-static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
-{
- smp_mb();
- __clear_bit(nr, addr);
-}
-
-#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
-
-/*
- * Return the bit position (0..63) of the most significant 1 bit in a word
- * Returns -1 if no 1 bit exists
- */
-static inline unsigned long __fls(unsigned long x)
-{
- int lz;
-
- if (sizeof(x) == 4) {
- __asm__(
- " .set push \n"
- " .set mips32 \n"
- " clz %0, %1 \n"
- " .set pop \n"
- : "=r" (lz)
- : "r" (x));
-
- return 31 - lz;
- }
-
- BUG_ON(sizeof(x) != 8);
-
- __asm__(
- " .set push \n"
- " .set mips64 \n"
- " dclz %0, %1 \n"
- " .set pop \n"
- : "=r" (lz)
- : "r" (x));
-
- return 63 - lz;
-}
-
-/*
- * __ffs - find first bit in word.
- * @word: The word to search
- *
- * Returns 0..SZLONG-1
- * Undefined if no bit exists, so code should check against 0 first.
- */
-static inline unsigned long __ffs(unsigned long word)
-{
- return __fls(word & -word);
-}
-
-/*
- * fls - find last bit set.
- * @word: The word to search
- *
- * This is defined the same way as ffs.
- * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
- */
-static inline int fls(int word)
-{
- __asm__("clz %0, %1" : "=r" (word) : "r" (word));
-
- return 32 - word;
-}
-
-#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64)
-static inline int fls64(__u64 word)
-{
- __asm__("dclz %0, %1" : "=r" (word) : "r" (word));
-
- return 64 - word;
-}
-#else
-#include <asm-generic/bitops/fls64.h>
-#endif
-
-/*
- * ffs - find first bit set.
- * @word: The word to search
- *
- * This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-static inline int ffs(int word)
-{
- if (!word)
- return 0;
-
- return fls(word & -word);
-}
-
-#else
-
-#include <asm-generic/bitops/__ffs.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/ffs.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/fls64.h>
-
-#endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */
-
-#include <asm-generic/bitops/ffz.h>
-#include <asm-generic/bitops/find.h>
-
-#ifdef __KERNEL__
-
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/ext2-non-atomic.h>
-#include <asm-generic/bitops/ext2-atomic.h>
-#include <asm-generic/bitops/minix.h>
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_BITOPS_H */
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
deleted file mode 100644
index 610fe3af7a0..00000000000
--- a/include/asm-mips/bootinfo.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 1996, 2003 by Ralf Baechle
- * Copyright (C) 1995, 1996 Andreas Busse
- * Copyright (C) 1995, 1996 Stoned Elipot
- * Copyright (C) 1995, 1996 Paul M. Antoine.
- */
-#ifndef _ASM_BOOTINFO_H
-#define _ASM_BOOTINFO_H
-
-#include <linux/types.h>
-#include <asm/setup.h>
-
-/*
- * The MACH_ IDs are sort of equivalent to PCI product IDs. As such the
- * numbers do not necessarily reflect technical relations or similarities
- * between systems.
- */
-
-/*
- * Valid machtype values for group unknown
- */
-#define MACH_UNKNOWN 0 /* whatever... */
-
-/*
- * Valid machtype for group DEC
- */
-#define MACH_DSUNKNOWN 0
-#define MACH_DS23100 1 /* DECstation 2100 or 3100 */
-#define MACH_DS5100 2 /* DECsystem 5100 */
-#define MACH_DS5000_200 3 /* DECstation 5000/200 */
-#define MACH_DS5000_1XX 4 /* DECstation 5000/120, 125, 133, 150 */
-#define MACH_DS5000_XX 5 /* DECstation 5000/20, 25, 33, 50 */
-#define MACH_DS5000_2X0 6 /* DECstation 5000/240, 260 */
-#define MACH_DS5400 7 /* DECsystem 5400 */
-#define MACH_DS5500 8 /* DECsystem 5500 */
-#define MACH_DS5800 9 /* DECsystem 5800 */
-#define MACH_DS5900 10 /* DECsystem 5900 */
-
-/*
- * Valid machtype for group PMC-MSP
- */
-#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */
-#define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */
-#define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */
-#define MACH_MSP7120_EVAL 3 /* PMC-Sierra MSP7120 Evaluation */
-#define MACH_MSP7120_GW 4 /* PMC-Sierra MSP7120 Residential GW */
-#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
-#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
-
-/*
- * Valid machtype for group Mikrotik
- */
-#define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */
-#define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */
-
-#define CL_SIZE COMMAND_LINE_SIZE
-
-extern char *system_type;
-const char *get_system_type(void);
-
-extern unsigned long mips_machtype;
-
-#define BOOT_MEM_MAP_MAX 32
-#define BOOT_MEM_RAM 1
-#define BOOT_MEM_ROM_DATA 2
-#define BOOT_MEM_RESERVED 3
-
-/*
- * A memory map that's built upon what was determined
- * or specified on the command line.
- */
-struct boot_mem_map {
- int nr_map;
- struct boot_mem_map_entry {
- phys_t addr; /* start of memory segment */
- phys_t size; /* size of memory segment */
- long type; /* type of memory segment */
- } map[BOOT_MEM_MAP_MAX];
-};
-
-extern struct boot_mem_map boot_mem_map;
-
-extern void add_memory_region(phys_t start, phys_t size, long type);
-
-extern void prom_init(void);
-extern void prom_free_prom_memory(void);
-
-extern void free_init_pages(const char *what,
- unsigned long begin, unsigned long end);
-
-/*
- * Initial kernel command line, usually setup by prom_init()
- */
-extern char arcs_cmdline[CL_SIZE];
-
-/*
- * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware
- */
-extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
-
-/*
- * Platform memory detection hook called by setup_arch
- */
-extern void plat_mem_setup(void);
-
-#endif /* _ASM_BOOTINFO_H */
diff --git a/include/asm-mips/branch.h b/include/asm-mips/branch.h
deleted file mode 100644
index 37c6857c8d4..00000000000
--- a/include/asm-mips/branch.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
- */
-#ifndef _ASM_BRANCH_H
-#define _ASM_BRANCH_H
-
-#include <asm/ptrace.h>
-
-static inline int delay_slot(struct pt_regs *regs)
-{
- return regs->cp0_cause & CAUSEF_BD;
-}
-
-static inline unsigned long exception_epc(struct pt_regs *regs)
-{
- if (!delay_slot(regs))
- return regs->cp0_epc;
-
- return regs->cp0_epc + 4;
-}
-
-extern int __compute_return_epc(struct pt_regs *regs);
-
-static inline int compute_return_epc(struct pt_regs *regs)
-{
- if (!delay_slot(regs)) {
- regs->cp0_epc += 4;
- return 0;
- }
-
- return __compute_return_epc(regs);
-}
-
-#endif /* _ASM_BRANCH_H */
diff --git a/include/asm-mips/break.h b/include/asm-mips/break.h
deleted file mode 100644
index 25b980c91e7..00000000000
--- a/include/asm-mips/break.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 2003 by Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-#ifndef __ASM_BREAK_H
-#define __ASM_BREAK_H
-
-/*
- * The following break codes are or were in use for specific purposes in
- * other MIPS operating systems. Linux/MIPS doesn't use all of them. The
- * unused ones are here as placeholders; we might encounter them in
- * non-Linux/MIPS object files or make use of them in the future.
- */
-#define BRK_USERBP 0 /* User bp (used by debuggers) */
-#define BRK_KERNELBP 1 /* Break in the kernel */
-#define BRK_ABORT 2 /* Sometimes used by abort(3) to SIGIOT */
-#define BRK_BD_TAKEN 3 /* For bd slot emulation - not implemented */
-#define BRK_BD_NOTTAKEN 4 /* For bd slot emulation - not implemented */
-#define BRK_SSTEPBP 5 /* User bp (used by debuggers) */
-#define BRK_OVERFLOW 6 /* Overflow check */
-#define BRK_DIVZERO 7 /* Divide by zero check */
-#define BRK_RANGE 8 /* Range error check */
-#define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */
-#define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */
-#define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */
-#define BRK_BUG 512 /* Used by BUG() */
-#define BRK_KDB 513 /* Used in KDB_ENTER() */
-#define BRK_MULOVF 1023 /* Multiply overflow */
-
-#endif /* __ASM_BREAK_H */
diff --git a/include/asm-mips/bug.h b/include/asm-mips/bug.h
deleted file mode 100644
index 7eb63de808b..00000000000
--- a/include/asm-mips/bug.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef __ASM_BUG_H
-#define __ASM_BUG_H
-
-#include <asm/sgidefs.h>
-
-#ifdef CONFIG_BUG
-
-#include <asm/break.h>
-
-#define BUG() \
-do { \
- __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); \
-} while (0)
-
-#define HAVE_ARCH_BUG
-
-#if (_MIPS_ISA > _MIPS_ISA_MIPS1)
-
-#define BUG_ON(condition) \
-do { \
- __asm__ __volatile__("tne $0, %0, %1" \
- : : "r" (condition), "i" (BRK_BUG)); \
-} while (0)
-
-#define HAVE_ARCH_BUG_ON
-
-#endif /* _MIPS_ISA > _MIPS_ISA_MIPS1 */
-
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif /* __ASM_BUG_H */
diff --git a/include/asm-mips/bugs.h b/include/asm-mips/bugs.h
deleted file mode 100644
index 9dc10df3207..00000000000
--- a/include/asm-mips/bugs.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This is included by init/main.c to check for architecture-dependent bugs.
- *
- * Copyright (C) 2007 Maciej W. Rozycki
- *
- * Needs:
- * void check_bugs(void);
- */
-#ifndef _ASM_BUGS_H
-#define _ASM_BUGS_H
-
-#include <linux/bug.h>
-#include <linux/delay.h>
-
-#include <asm/cpu.h>
-#include <asm/cpu-info.h>
-
-extern int daddiu_bug;
-
-extern void check_bugs64_early(void);
-
-extern void check_bugs32(void);
-extern void check_bugs64(void);
-
-static inline void check_bugs_early(void)
-{
-#ifdef CONFIG_64BIT
- check_bugs64_early();
-#endif
-}
-
-static inline void check_bugs(void)
-{
- unsigned int cpu = smp_processor_id();
-
- cpu_data[cpu].udelay_val = loops_per_jiffy;
- check_bugs32();
-#ifdef CONFIG_64BIT
- check_bugs64();
-#endif
-}
-
-static inline int r4k_daddiu_bug(void)
-{
-#ifdef CONFIG_64BIT
- WARN_ON(daddiu_bug < 0);
- return daddiu_bug != 0;
-#else
- return 0;
-#endif
-}
-
-#endif /* _ASM_BUGS_H */
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h
deleted file mode 100644
index fe7dc2d59b6..00000000000
--- a/include/asm-mips/byteorder.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 99, 2003 by Ralf Baechle
- */
-#ifndef _ASM_BYTEORDER_H
-#define _ASM_BYTEORDER_H
-
-#include <linux/compiler.h>
-#include <asm/types.h>
-
-#ifdef __GNUC__
-
-#ifdef CONFIG_CPU_MIPSR2
-
-static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
-{
- __asm__(
- " wsbh %0, %1 \n"
- : "=r" (x)
- : "r" (x));
-
- return x;
-}
-#define __arch__swab16(x) ___arch__swab16(x)
-
-static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
-{
- __asm__(
- " wsbh %0, %1 \n"
- " rotr %0, %0, 16 \n"
- : "=r" (x)
- : "r" (x));
-
- return x;
-}
-#define __arch__swab32(x) ___arch__swab32(x)
-
-#ifdef CONFIG_CPU_MIPS64_R2
-
-static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
-{
- __asm__(
- " dsbh %0, %1 \n"
- " dshd %0, %0 \n"
- " drotr %0, %0, 32 \n"
- : "=r" (x)
- : "r" (x));
-
- return x;
-}
-
-#define __arch__swab64(x) ___arch__swab64(x)
-
-#endif /* CONFIG_CPU_MIPS64_R2 */
-
-#endif /* CONFIG_CPU_MIPSR2 */
-
-#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-# define __BYTEORDER_HAS_U64__
-# define __SWAB_64_THRU_32__
-#endif
-
-#endif /* __GNUC__ */
-
-#if defined(__MIPSEB__)
-# include <linux/byteorder/big_endian.h>
-#elif defined(__MIPSEL__)
-# include <linux/byteorder/little_endian.h>
-#else
-# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
-#endif
-
-#endif /* _ASM_BYTEORDER_H */
diff --git a/include/asm-mips/cache.h b/include/asm-mips/cache.h
deleted file mode 100644
index 37f175c42bb..00000000000
--- a/include/asm-mips/cache.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1997, 98, 99, 2000, 2003 Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_CACHE_H
-#define _ASM_CACHE_H
-
-#include <kmalloc.h>
-
-#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-
-#define SMP_CACHE_SHIFT L1_CACHE_SHIFT
-#define SMP_CACHE_BYTES L1_CACHE_BYTES
-
-#endif /* _ASM_CACHE_H */
diff --git a/include/asm-mips/cachectl.h b/include/asm-mips/cachectl.h
deleted file mode 100644
index f3ce721861d..00000000000
--- a/include/asm-mips/cachectl.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
- */
-#ifndef _ASM_CACHECTL
-#define _ASM_CACHECTL
-
-/*
- * Options for cacheflush system call
- */
-#define ICACHE (1<<0) /* flush instruction cache */
-#define DCACHE (1<<1) /* writeback and flush data cache */
-#define BCACHE (ICACHE|DCACHE) /* flush both caches */
-
-/*
- * Caching modes for the cachectl(2) call
- *
- * cachectl(2) is currently not supported and returns ENOSYS.
- */
-#define CACHEABLE 0 /* make pages cacheable */
-#define UNCACHEABLE 1 /* make pages uncacheable */
-
-#endif /* _ASM_CACHECTL */
diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h
deleted file mode 100644
index 03b1d69b142..00000000000
--- a/include/asm-mips/cacheflush.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
- * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
- */
-#ifndef _ASM_CACHEFLUSH_H
-#define _ASM_CACHEFLUSH_H
-
-/* Keep includes the same across arches. */
-#include <linux/mm.h>
-#include <asm/cpu-features.h>
-
-/* Cache flushing:
- *
- * - flush_cache_all() flushes entire cache
- * - flush_cache_mm(mm) flushes the specified mm context's cache lines
- * - flush_cache_dup mm(mm) handles cache flushing when forking
- * - flush_cache_page(mm, vmaddr, pfn) flushes a single page
- * - flush_cache_range(vma, start, end) flushes a range of pages
- * - flush_icache_range(start, end) flush a range of instructions
- * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
- *
- * MIPS specific flush operations:
- *
- * - flush_cache_sigtramp() flush signal trampoline
- * - flush_icache_all() flush the entire instruction cache
- * - flush_data_cache_page() flushes a page from the data cache
- */
-extern void (*flush_cache_all)(void);
-extern void (*__flush_cache_all)(void);
-extern void (*flush_cache_mm)(struct mm_struct *mm);
-#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0)
-extern void (*flush_cache_range)(struct vm_area_struct *vma,
- unsigned long start, unsigned long end);
-extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
-extern void __flush_dcache_page(struct page *page);
-
-static inline void flush_dcache_page(struct page *page)
-{
- if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
- __flush_dcache_page(page);
-
-}
-
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-
-#define ARCH_HAS_FLUSH_ANON_PAGE
-extern void __flush_anon_page(struct page *, unsigned long);
-static inline void flush_anon_page(struct vm_area_struct *vma,
- struct page *page, unsigned long vmaddr)
-{
- if (cpu_has_dc_aliases && PageAnon(page))
- __flush_anon_page(page, vmaddr);
-}
-
-static inline void flush_icache_page(struct vm_area_struct *vma,
- struct page *page)
-{
-}
-
-extern void (*flush_icache_range)(unsigned long start, unsigned long end);
-extern void (*local_flush_icache_range)(unsigned long start, unsigned long end);
-
-extern void (*__flush_cache_vmap)(void);
-
-static inline void flush_cache_vmap(unsigned long start, unsigned long end)
-{
- if (cpu_has_dc_aliases)
- __flush_cache_vmap();
-}
-
-extern void (*__flush_cache_vunmap)(void);
-
-static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
-{
- if (cpu_has_dc_aliases)
- __flush_cache_vunmap();
-}
-
-extern void copy_to_user_page(struct vm_area_struct *vma,
- struct page *page, unsigned long vaddr, void *dst, const void *src,
- unsigned long len);
-
-extern void copy_from_user_page(struct vm_area_struct *vma,
- struct page *page, unsigned long vaddr, void *dst, const void *src,
- unsigned long len);
-
-extern void (*flush_cache_sigtramp)(unsigned long addr);
-extern void (*flush_icache_all)(void);
-extern void (*local_flush_data_cache_page)(void * addr);
-extern void (*flush_data_cache_page)(unsigned long addr);
-
-/*
- * This flag is used to indicate that the page pointed to by a pte
- * is dirty and requires cleaning before returning it to the user.
- */
-#define PG_dcache_dirty PG_arch_1
-
-#define Page_dcache_dirty(page) \
- test_bit(PG_dcache_dirty, &(page)->flags)
-#define SetPageDcacheDirty(page) \
- set_bit(PG_dcache_dirty, &(page)->flags)
-#define ClearPageDcacheDirty(page) \
- clear_bit(PG_dcache_dirty, &(page)->flags)
-
-/* Run kernel code uncached, useful for cache probing functions. */
-unsigned long run_uncached(void *func);
-
-extern void *kmap_coherent(struct page *page, unsigned long addr);
-extern void kunmap_coherent(void);
-
-#endif /* _ASM_CACHEFLUSH_H */
diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h
deleted file mode 100644
index 256ad2cc6eb..00000000000
--- a/include/asm-mips/cacheops.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Cache operations for the cache instruction.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
- * (C) Copyright 1999 Silicon Graphics, Inc.
- */
-#ifndef __ASM_CACHEOPS_H
-#define __ASM_CACHEOPS_H
-
-/*
- * Cache Operations available on all MIPS processors with R4000-style caches
- */
-#define Index_Invalidate_I 0x00
-#define Index_Writeback_Inv_D 0x01
-#define Index_Load_Tag_I 0x04
-#define Index_Load_Tag_D 0x05
-#define Index_Store_Tag_I 0x08
-#define Index_Store_Tag_D 0x09
-#if defined(CONFIG_CPU_LOONGSON2)
-#define Hit_Invalidate_I 0x00
-#else
-#define Hit_Invalidate_I 0x10
-#endif
-#define Hit_Invalidate_D 0x11
-#define Hit_Writeback_Inv_D 0x15
-
-/*
- * R4000-specific cacheops
- */
-#define Create_Dirty_Excl_D 0x0d
-#define Fill 0x14
-#define Hit_Writeback_I 0x18
-#define Hit_Writeback_D 0x19
-
-/*
- * R4000SC and R4400SC-specific cacheops
- */
-#define Index_Invalidate_SI 0x02
-#define Index_Writeback_Inv_SD 0x03
-#define Index_Load_Tag_SI 0x06
-#define Index_Load_Tag_SD 0x07
-#define Index_Store_Tag_SI 0x0A
-#define Index_Store_Tag_SD 0x0B
-#define Create_Dirty_Excl_SD 0x0f
-#define Hit_Invalidate_SI 0x12
-#define Hit_Invalidate_SD 0x13
-#define Hit_Writeback_Inv_SD 0x17
-#define Hit_Writeback_SD 0x1b
-#define Hit_Set_Virtual_SI 0x1e
-#define Hit_Set_Virtual_SD 0x1f
-
-/*
- * R5000-specific cacheops
- */
-#define R5K_Page_Invalidate_S 0x17
-
-/*
- * RM7000-specific cacheops
- */
-#define Page_Invalidate_T 0x16
-
-/*
- * R10000-specific cacheops
- *
- * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
- * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
- */
-#define Index_Writeback_Inv_S 0x03
-#define Index_Load_Tag_S 0x07
-#define Index_Store_Tag_S 0x0B
-#define Hit_Invalidate_S 0x13
-#define Cache_Barrier 0x14
-#define Hit_Writeback_Inv_S 0x17
-#define Index_Load_Data_I 0x18
-#define Index_Load_Data_D 0x19
-#define Index_Load_Data_S 0x1b
-#define Index_Store_Data_I 0x1c
-#define Index_Store_Data_D 0x1d
-#define Index_Store_Data_S 0x1f
-
-#endif /* __ASM_CACHEOPS_H */
diff --git a/include/asm-mips/cevt-r4k.h b/include/asm-mips/cevt-r4k.h
deleted file mode 100644
index fa4328f9124..00000000000
--- a/include/asm-mips/cevt-r4k.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2008 Kevin D. Kissell
- */
-
-/*
- * Definitions used for common event timer implementation
- * for MIPS 4K-type processors and their MIPS MT variants.
- * Avoids unsightly extern declarations in C files.
- */
-#ifndef __ASM_CEVT_R4K_H
-#define __ASM_CEVT_R4K_H
-
-DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
-
-void mips_event_handler(struct clock_event_device *dev);
-int c0_compare_int_usable(void);
-void mips_set_clock_mode(enum clock_event_mode, struct clock_event_device *);
-irqreturn_t c0_compare_interrupt(int, void *);
-
-extern struct irqaction c0_compare_irqaction;
-extern int cp0_timer_irq_installed;
-
-/*
- * Possibly handle a performance counter interrupt.
- * Return true if the timer interrupt should not be checked
- */
-
-static inline int handle_perf_irq(int r2)
-{
- /*
- * The performance counter overflow interrupt may be shared with the
- * timer interrupt (cp0_perfcount_irq < 0). If it is and a
- * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
- * and we can't reliably determine if a counter interrupt has also
- * happened (!r2) then don't check for a timer interrupt.
- */
- return (cp0_perfcount_irq < 0) &&
- perf_irq() == IRQ_HANDLED &&
- !r2;
-}
-
-#endif /* __ASM_CEVT_R4K_H */
diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h
deleted file mode 100644
index 290485ac540..00000000000
--- a/include/asm-mips/checksum.h
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 96, 97, 98, 99, 2001 by Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Copyright (C) 2001 Thiemo Seufer.
- * Copyright (C) 2002 Maciej W. Rozycki
- */
-#ifndef _ASM_CHECKSUM_H
-#define _ASM_CHECKSUM_H
-
-#include <linux/in6.h>
-
-#include <asm/uaccess.h>
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum sum);
-
-__wsum __csum_partial_copy_user(const void *src, void *dst,
- int len, __wsum sum, int *err_ptr);
-
-/*
- * this is a new version of the above that records errors it finds in *errp,
- * but continues and zeros the rest of the buffer.
- */
-static inline
-__wsum csum_partial_copy_from_user(const void __user *src, void *dst, int len,
- __wsum sum, int *err_ptr)
-{
- might_sleep();
- return __csum_partial_copy_user((__force void *)src, dst,
- len, sum, err_ptr);
-}
-
-/*
- * Copy and checksum to user
- */
-#define HAVE_CSUM_COPY_USER
-static inline
-__wsum csum_and_copy_to_user(const void *src, void __user *dst, int len,
- __wsum sum, int *err_ptr)
-{
- might_sleep();
- if (access_ok(VERIFY_WRITE, dst, len))
- return __csum_partial_copy_user(src, (__force void *)dst,
- len, sum, err_ptr);
- if (len)
- *err_ptr = -EFAULT;
-
- return (__force __wsum)-1; /* invalid checksum */
-}
-
-/*
- * the same as csum_partial, but copies from user space (but on MIPS
- * we have just one address space, so this is identical to the above)
- */
-__wsum csum_partial_copy_nocheck(const void *src, void *dst,
- int len, __wsum sum);
-
-/*
- * Fold a partial checksum without adding pseudo headers
- */
-static inline __sum16 csum_fold(__wsum sum)
-{
- __asm__(
- " .set push # csum_fold\n"
- " .set noat \n"
- " sll $1, %0, 16 \n"
- " addu %0, $1 \n"
- " sltu $1, %0, $1 \n"
- " srl %0, %0, 16 \n"
- " addu %0, $1 \n"
- " xori %0, 0xffff \n"
- " .set pop"
- : "=r" (sum)
- : "0" (sum));
-
- return (__force __sum16)sum;
-}
-
-/*
- * This is a version of ip_compute_csum() optimized for IP headers,
- * which always checksum on 4 octet boundaries.
- *
- * By Jorge Cwik <jorge@laser.satlink.net>, adapted for linux by
- * Arnt Gulbrandsen.
- */
-static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
-{
- const unsigned int *word = iph;
- const unsigned int *stop = word + ihl;
- unsigned int csum;
- int carry;
-
- csum = word[0];
- csum += word[1];
- carry = (csum < word[1]);
- csum += carry;
-
- csum += word[2];
- carry = (csum < word[2]);
- csum += carry;
-
- csum += word[3];
- carry = (csum < word[3]);
- csum += carry;
-
- word += 4;
- do {
- csum += *word;
- carry = (csum < *word);
- csum += carry;
- word++;
- } while (word != stop);
-
- return csum_fold(csum);
-}
-
-static inline __wsum csum_tcpudp_nofold(__be32 saddr,
- __be32 daddr, unsigned short len, unsigned short proto,
- __wsum sum)
-{
- __asm__(
- " .set push # csum_tcpudp_nofold\n"
- " .set noat \n"
-#ifdef CONFIG_32BIT
- " addu %0, %2 \n"
- " sltu $1, %0, %2 \n"
- " addu %0, $1 \n"
-
- " addu %0, %3 \n"
- " sltu $1, %0, %3 \n"
- " addu %0, $1 \n"
-
- " addu %0, %4 \n"
- " sltu $1, %0, %4 \n"
- " addu %0, $1 \n"
-#endif
-#ifdef CONFIG_64BIT
- " daddu %0, %2 \n"
- " daddu %0, %3 \n"
- " daddu %0, %4 \n"
- " dsll32 $1, %0, 0 \n"
- " daddu %0, $1 \n"
- " dsra32 %0, %0, 0 \n"
-#endif
- " .set pop"
- : "=r" (sum)
- : "0" ((__force unsigned long)daddr),
- "r" ((__force unsigned long)saddr),
-#ifdef __MIPSEL__
- "r" ((proto + len) << 8),
-#else
- "r" (proto + len),
-#endif
- "r" ((__force unsigned long)sum));
-
- return sum;
-}
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
- unsigned short len,
- unsigned short proto,
- __wsum sum)
-{
- return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-static inline __sum16 ip_compute_csum(const void *buff, int len)
-{
- return csum_fold(csum_partial(buff, len, 0));
-}
-
-#define _HAVE_ARCH_IPV6_CSUM
-static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
- const struct in6_addr *daddr,
- __u32 len, unsigned short proto,
- __wsum sum)
-{
- __asm__(
- " .set push # csum_ipv6_magic\n"
- " .set noreorder \n"
- " .set noat \n"
- " addu %0, %5 # proto (long in network byte order)\n"
- " sltu $1, %0, %5 \n"
- " addu %0, $1 \n"
-
- " addu %0, %6 # csum\n"
- " sltu $1, %0, %6 \n"
- " lw %1, 0(%2) # four words source address\n"
- " addu %0, $1 \n"
- " addu %0, %1 \n"
- " sltu $1, %0, %1 \n"
-
- " lw %1, 4(%2) \n"
- " addu %0, $1 \n"
- " addu %0, %1 \n"
- " sltu $1, %0, %1 \n"
-
- " lw %1, 8(%2) \n"
- " addu %0, $1 \n"
- " addu %0, %1 \n"
- " sltu $1, %0, %1 \n"
-
- " lw %1, 12(%2) \n"
- " addu %0, $1 \n"
- " addu %0, %1 \n"
- " sltu $1, %0, %1 \n"
-
- " lw %1, 0(%3) \n"
- " addu %0, $1 \n"
- " addu %0, %1 \n"
- " sltu $1, %0, %1 \n"
-
- " lw %1, 4(%3) \n"
- " addu %0, $1 \n"
- " addu %0, %1 \n"
- " sltu $1, %0, %1 \n"
-
- " lw %1, 8(%3) \n"
- " addu %0, $1 \n"
- " addu %0, %1 \n"
- " sltu $1, %0, %1 \n"
-
- " lw %1, 12(%3) \n"
- " addu %0, $1 \n"
- " addu %0, %1 \n"
- " sltu $1, %0, %1 \n"
-
- " addu %0, $1 # Add final carry\n"
- " .set pop"
- : "=r" (sum), "=r" (proto)
- : "r" (saddr), "r" (daddr),
- "0" (htonl(len)), "1" (htonl(proto)), "r" (sum));
-
- return csum_fold(sum);
-}
-
-#endif /* _ASM_CHECKSUM_H */
diff --git a/include/asm-mips/cmp.h b/include/asm-mips/cmp.h
deleted file mode 100644
index 89a73fb93ae..00000000000
--- a/include/asm-mips/cmp.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef _ASM_CMP_H
-#define _ASM_CMP_H
-
-/*
- * Definitions for CMP multitasking on MIPS cores
- */
-struct task_struct;
-
-extern void cmp_smp_setup(void);
-extern void cmp_smp_finish(void);
-extern void cmp_boot_secondary(int cpu, struct task_struct *t);
-extern void cmp_init_secondary(void);
-extern void cmp_cpus_done(void);
-extern void cmp_prepare_cpus(unsigned int max_cpus);
-
-/* This is platform specific */
-extern void cmp_send_ipi(int cpu, unsigned int action);
-#endif /* _ASM_CMP_H */
diff --git a/include/asm-mips/cmpxchg.h b/include/asm-mips/cmpxchg.h
deleted file mode 100644
index 4a812c3ceb9..00000000000
--- a/include/asm-mips/cmpxchg.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_CMPXCHG_H
-#define __ASM_CMPXCHG_H
-
-#include <linux/irqflags.h>
-
-#define __HAVE_ARCH_CMPXCHG 1
-
-#define __cmpxchg_asm(ld, st, m, old, new) \
-({ \
- __typeof(*(m)) __ret; \
- \
- if (cpu_has_llsc && R10000_LLSC_WAR) { \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " .set mips3 \n" \
- "1: " ld " %0, %2 # __cmpxchg_asm \n" \
- " bne %0, %z3, 2f \n" \
- " .set mips0 \n" \
- " move $1, %z4 \n" \
- " .set mips3 \n" \
- " " st " $1, %1 \n" \
- " beqzl $1, 1b \n" \
- "2: \n" \
- " .set pop \n" \
- : "=&r" (__ret), "=R" (*m) \
- : "R" (*m), "Jr" (old), "Jr" (new) \
- : "memory"); \
- } else if (cpu_has_llsc) { \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " .set mips3 \n" \
- "1: " ld " %0, %2 # __cmpxchg_asm \n" \
- " bne %0, %z3, 2f \n" \
- " .set mips0 \n" \
- " move $1, %z4 \n" \
- " .set mips3 \n" \
- " " st " $1, %1 \n" \
- " beqz $1, 3f \n" \
- "2: \n" \
- " .subsection 2 \n" \
- "3: b 1b \n" \
- " .previous \n" \
- " .set pop \n" \
- : "=&r" (__ret), "=R" (*m) \
- : "R" (*m), "Jr" (old), "Jr" (new) \
- : "memory"); \
- } else { \
- unsigned long __flags; \
- \
- raw_local_irq_save(__flags); \
- __ret = *m; \
- if (__ret == old) \
- *m = new; \
- raw_local_irq_restore(__flags); \
- } \
- \
- __ret; \
-})
-
-/*
- * This function doesn't exist, so you'll get a linker error
- * if something tries to do an invalid cmpxchg().
- */
-extern void __cmpxchg_called_with_bad_pointer(void);
-
-#define __cmpxchg(ptr, old, new, barrier) \
-({ \
- __typeof__(ptr) __ptr = (ptr); \
- __typeof__(*(ptr)) __old = (old); \
- __typeof__(*(ptr)) __new = (new); \
- __typeof__(*(ptr)) __res = 0; \
- \
- barrier; \
- \
- switch (sizeof(*(__ptr))) { \
- case 4: \
- __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); \
- break; \
- case 8: \
- if (sizeof(long) == 8) { \
- __res = __cmpxchg_asm("lld", "scd", __ptr, \
- __old, __new); \
- break; \
- } \
- default: \
- __cmpxchg_called_with_bad_pointer(); \
- break; \
- } \
- \
- barrier; \
- \
- __res; \
-})
-
-#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb())
-#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, )
-
-#define cmpxchg64(ptr, o, n) \
- ({ \
- BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
- cmpxchg((ptr), (o), (n)); \
- })
-
-#ifdef CONFIG_64BIT
-#define cmpxchg64_local(ptr, o, n) \
- ({ \
- BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
- cmpxchg_local((ptr), (o), (n)); \
- })
-#else
-#include <asm-generic/cmpxchg-local.h>
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-#endif
-
-#endif /* __ASM_CMPXCHG_H */
diff --git a/include/asm-mips/compat-signal.h b/include/asm-mips/compat-signal.h
deleted file mode 100644
index 368a99e5c3e..00000000000
--- a/include/asm-mips/compat-signal.h
+++ /dev/null
@@ -1,119 +0,0 @@
-#ifndef __ASM_COMPAT_SIGNAL_H
-#define __ASM_COMPAT_SIGNAL_H
-
-#include <linux/bug.h>
-#include <linux/compat.h>
-#include <linux/compiler.h>
-
-#include <asm/signal.h>
-#include <asm/siginfo.h>
-
-#include <asm/uaccess.h>
-
-#define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3)
-
-typedef struct compat_siginfo {
- int si_signo;
- int si_code;
- int si_errno;
-
- union {
- int _pad[SI_PAD_SIZE32];
-
- /* kill() */
- struct {
- compat_pid_t _pid; /* sender's pid */
- compat_uid_t _uid; /* sender's uid */
- } _kill;
-
- /* SIGCHLD */
- struct {
- compat_pid_t _pid; /* which child */
- compat_uid_t _uid; /* sender's uid */
- int _status; /* exit code */
- compat_clock_t _utime;
- compat_clock_t _stime;
- } _sigchld;
-
- /* IRIX SIGCHLD */
- struct {
- compat_pid_t _pid; /* which child */
- compat_clock_t _utime;
- int _status; /* exit code */
- compat_clock_t _stime;
- } _irix_sigchld;
-
- /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
- struct {
- s32 _addr; /* faulting insn/memory ref. */
- } _sigfault;
-
- /* SIGPOLL, SIGXFSZ (To do ...) */
- struct {
- int _band; /* POLL_IN, POLL_OUT, POLL_MSG */
- int _fd;
- } _sigpoll;
-
- /* POSIX.1b timers */
- struct {
- timer_t _tid; /* timer id */
- int _overrun; /* overrun count */
- compat_sigval_t _sigval;/* same as below */
- int _sys_private; /* not to be passed to user */
- } _timer;
-
- /* POSIX.1b signals */
- struct {
- compat_pid_t _pid; /* sender's pid */
- compat_uid_t _uid; /* sender's uid */
- compat_sigval_t _sigval;
- } _rt;
-
- } _sifields;
-} compat_siginfo_t;
-
-static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d,
- const sigset_t *s)
-{
- int err;
-
- BUG_ON(sizeof(*d) != sizeof(*s));
- BUG_ON(_NSIG_WORDS != 2);
-
- err = __put_user(s->sig[0], &d->sig[0]);
- err |= __put_user(s->sig[0] >> 32, &d->sig[1]);
- err |= __put_user(s->sig[1], &d->sig[2]);
- err |= __put_user(s->sig[1] >> 32, &d->sig[3]);
-
- return err;
-}
-
-static inline int __copy_conv_sigset_from_user(sigset_t *d,
- const compat_sigset_t __user *s)
-{
- int err;
- union sigset_u {
- sigset_t s;
- compat_sigset_t c;
- } *u = (union sigset_u *) d;
-
- BUG_ON(sizeof(*d) != sizeof(*s));
- BUG_ON(_NSIG_WORDS != 2);
-
-#ifdef CONFIG_CPU_BIG_ENDIAN
- err = __get_user(u->c.sig[1], &s->sig[0]);
- err |= __get_user(u->c.sig[0], &s->sig[1]);
- err |= __get_user(u->c.sig[3], &s->sig[2]);
- err |= __get_user(u->c.sig[2], &s->sig[3]);
-#endif
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
- err = __get_user(u->c.sig[0], &s->sig[0]);
- err |= __get_user(u->c.sig[1], &s->sig[1]);
- err |= __get_user(u->c.sig[2], &s->sig[2]);
- err |= __get_user(u->c.sig[3], &s->sig[3]);
-#endif
-
- return err;
-}
-
-#endif /* __ASM_COMPAT_SIGNAL_H */
diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h
deleted file mode 100644
index ac5d541368e..00000000000
--- a/include/asm-mips/compat.h
+++ /dev/null
@@ -1,221 +0,0 @@
-#ifndef _ASM_COMPAT_H
-#define _ASM_COMPAT_H
-/*
- * Architecture specific compatibility types
- */
-#include <linux/types.h>
-#include <asm/page.h>
-#include <asm/ptrace.h>
-
-#define COMPAT_USER_HZ 100
-
-typedef u32 compat_size_t;
-typedef s32 compat_ssize_t;
-typedef s32 compat_time_t;
-typedef s32 compat_clock_t;
-typedef s32 compat_suseconds_t;
-
-typedef s32 compat_pid_t;
-typedef s32 __compat_uid_t;
-typedef s32 __compat_gid_t;
-typedef __compat_uid_t __compat_uid32_t;
-typedef __compat_gid_t __compat_gid32_t;
-typedef u32 compat_mode_t;
-typedef u32 compat_ino_t;
-typedef u32 compat_dev_t;
-typedef s32 compat_off_t;
-typedef s64 compat_loff_t;
-typedef u32 compat_nlink_t;
-typedef s32 compat_ipc_pid_t;
-typedef s32 compat_daddr_t;
-typedef s32 compat_caddr_t;
-typedef struct {
- s32 val[2];
-} compat_fsid_t;
-typedef s32 compat_timer_t;
-typedef s32 compat_key_t;
-
-typedef s32 compat_int_t;
-typedef s32 compat_long_t;
-typedef s64 compat_s64;
-typedef u32 compat_uint_t;
-typedef u32 compat_ulong_t;
-typedef u64 compat_u64;
-
-struct compat_timespec {
- compat_time_t tv_sec;
- s32 tv_nsec;
-};
-
-struct compat_timeval {
- compat_time_t tv_sec;
- s32 tv_usec;
-};
-
-struct compat_stat {
- compat_dev_t st_dev;
- s32 st_pad1[3];
- compat_ino_t st_ino;
- compat_mode_t st_mode;
- compat_nlink_t st_nlink;
- __compat_uid_t st_uid;
- __compat_gid_t st_gid;
- compat_dev_t st_rdev;
- s32 st_pad2[2];
- compat_off_t st_size;
- s32 st_pad3;
- compat_time_t st_atime;
- s32 st_atime_nsec;
- compat_time_t st_mtime;
- s32 st_mtime_nsec;
- compat_time_t st_ctime;
- s32 st_ctime_nsec;
- s32 st_blksize;
- s32 st_blocks;
- s32 st_pad4[14];
-};
-
-struct compat_flock {
- short l_type;
- short l_whence;
- compat_off_t l_start;
- compat_off_t l_len;
- s32 l_sysid;
- compat_pid_t l_pid;
- short __unused;
- s32 pad[4];
-};
-
-#define F_GETLK64 33
-#define F_SETLK64 34
-#define F_SETLKW64 35
-
-struct compat_flock64 {
- short l_type;
- short l_whence;
- compat_loff_t l_start;
- compat_loff_t l_len;
- compat_pid_t l_pid;
-};
-
-struct compat_statfs {
- int f_type;
- int f_bsize;
- int f_frsize;
- int f_blocks;
- int f_bfree;
- int f_files;
- int f_ffree;
- int f_bavail;
- compat_fsid_t f_fsid;
- int f_namelen;
- int f_spare[6];
-};
-
-#define COMPAT_RLIM_INFINITY 0x7fffffffUL
-
-typedef u32 compat_old_sigset_t; /* at least 32 bits */
-
-#define _COMPAT_NSIG 128 /* Don't ask !$@#% ... */
-#define _COMPAT_NSIG_BPW 32
-
-typedef u32 compat_sigset_word;
-
-#define COMPAT_OFF_T_MAX 0x7fffffff
-#define COMPAT_LOFF_T_MAX 0x7fffffffffffffffL
-
-/*
- * A pointer passed in from user mode. This should not
- * be used for syscall parameters, just declare them
- * as pointers because the syscall entry code will have
- * appropriately converted them already.
- */
-typedef u32 compat_uptr_t;
-
-static inline void __user *compat_ptr(compat_uptr_t uptr)
-{
- /* cast to a __user pointer via "unsigned long" makes sparse happy */
- return (void __user *)(unsigned long)(long)uptr;
-}
-
-static inline compat_uptr_t ptr_to_compat(void __user *uptr)
-{
- return (u32)(unsigned long)uptr;
-}
-
-static inline void __user *compat_alloc_user_space(long len)
-{
- struct pt_regs *regs = (struct pt_regs *)
- ((unsigned long) current_thread_info() + THREAD_SIZE - 32) - 1;
-
- return (void __user *) (regs->regs[29] - len);
-}
-
-struct compat_ipc64_perm {
- compat_key_t key;
- __compat_uid32_t uid;
- __compat_gid32_t gid;
- __compat_uid32_t cuid;
- __compat_gid32_t cgid;
- compat_mode_t mode;
- unsigned short seq;
- unsigned short __pad2;
- compat_ulong_t __unused1;
- compat_ulong_t __unused2;
-};
-
-struct compat_semid64_ds {
- struct compat_ipc64_perm sem_perm;
- compat_time_t sem_otime;
- compat_time_t sem_ctime;
- compat_ulong_t sem_nsems;
- compat_ulong_t __unused1;
- compat_ulong_t __unused2;
-};
-
-struct compat_msqid64_ds {
- struct compat_ipc64_perm msg_perm;
-#ifndef CONFIG_CPU_LITTLE_ENDIAN
- compat_ulong_t __unused1;
-#endif
- compat_time_t msg_stime;
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
- compat_ulong_t __unused1;
-#endif
-#ifndef CONFIG_CPU_LITTLE_ENDIAN
- compat_ulong_t __unused2;
-#endif
- compat_time_t msg_rtime;
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
- compat_ulong_t __unused2;
-#endif
-#ifndef CONFIG_CPU_LITTLE_ENDIAN
- compat_ulong_t __unused3;
-#endif
- compat_time_t msg_ctime;
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
- compat_ulong_t __unused3;
-#endif
- compat_ulong_t msg_cbytes;
- compat_ulong_t msg_qnum;
- compat_ulong_t msg_qbytes;
- compat_pid_t msg_lspid;
- compat_pid_t msg_lrpid;
- compat_ulong_t __unused4;
- compat_ulong_t __unused5;
-};
-
-struct compat_shmid64_ds {
- struct compat_ipc64_perm shm_perm;
- compat_size_t shm_segsz;
- compat_time_t shm_atime;
- compat_time_t shm_dtime;
- compat_time_t shm_ctime;
- compat_pid_t shm_cpid;
- compat_pid_t shm_lpid;
- compat_ulong_t shm_nattch;
- compat_ulong_t __unused1;
- compat_ulong_t __unused2;
-};
-
-#endif /* _ASM_COMPAT_H */
diff --git a/include/asm-mips/compiler.h b/include/asm-mips/compiler.h
deleted file mode 100644
index 71f5c5cfc58..00000000000
--- a/include/asm-mips/compiler.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2004, 2007 Maciej W. Rozycki
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef _ASM_COMPILER_H
-#define _ASM_COMPILER_H
-
-#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
-#define GCC_IMM_ASM() "n"
-#define GCC_REG_ACCUM "$0"
-#else
-#define GCC_IMM_ASM() "rn"
-#define GCC_REG_ACCUM "accum"
-#endif
-
-#endif /* _ASM_COMPILER_H */
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
deleted file mode 100644
index 5ea701fc342..00000000000
--- a/include/asm-mips/cpu-features.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 2004 Ralf Baechle
- * Copyright (C) 2004 Maciej W. Rozycki
- */
-#ifndef __ASM_CPU_FEATURES_H
-#define __ASM_CPU_FEATURES_H
-
-#include <asm/cpu.h>
-#include <asm/cpu-info.h>
-#include <cpu-feature-overrides.h>
-
-#ifndef current_cpu_type
-#define current_cpu_type() current_cpu_data.cputype
-#endif
-
-/*
- * SMP assumption: Options of CPU 0 are a superset of all processors.
- * This is true for all known MIPS systems.
- */
-#ifndef cpu_has_tlb
-#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
-#endif
-#ifndef cpu_has_4kex
-#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
-#endif
-#ifndef cpu_has_3k_cache
-#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
-#endif
-#define cpu_has_6k_cache 0
-#define cpu_has_8k_cache 0
-#ifndef cpu_has_4k_cache
-#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
-#endif
-#ifndef cpu_has_tx39_cache
-#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
-#endif
-#ifndef cpu_has_fpu
-#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
-#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
-#else
-#define raw_cpu_has_fpu cpu_has_fpu
-#endif
-#ifndef cpu_has_32fpr
-#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
-#endif
-#ifndef cpu_has_counter
-#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
-#endif
-#ifndef cpu_has_watch
-#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
-#endif
-#ifndef cpu_has_divec
-#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
-#endif
-#ifndef cpu_has_vce
-#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
-#endif
-#ifndef cpu_has_cache_cdex_p
-#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
-#endif
-#ifndef cpu_has_cache_cdex_s
-#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
-#endif
-#ifndef cpu_has_prefetch
-#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
-#endif
-#ifndef cpu_has_mcheck
-#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
-#endif
-#ifndef cpu_has_ejtag
-#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
-#endif
-#ifndef cpu_has_llsc
-#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
-#endif
-#ifndef cpu_has_mips16
-#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
-#endif
-#ifndef cpu_has_mdmx
-#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
-#endif
-#ifndef cpu_has_mips3d
-#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
-#endif
-#ifndef cpu_has_smartmips
-#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
-#endif
-#ifndef cpu_has_vtag_icache
-#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
-#endif
-#ifndef cpu_has_dc_aliases
-#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
-#endif
-#ifndef cpu_has_ic_fills_f_dc
-#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
-#endif
-#ifndef cpu_has_pindexed_dcache
-#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
-#endif
-
-/*
- * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
- * such as the R10000 have I-Caches that snoop local stores; the embedded ones
- * don't. For maintaining I-cache coherency this means we need to flush the
- * D-cache all the way back to whever the I-cache does refills from, so the
- * I-cache has a chance to see the new data at all. Then we have to flush the
- * I-cache also.
- * Note we may have been rescheduled and may no longer be running on the CPU
- * that did the store so we can't optimize this into only doing the flush on
- * the local CPU.
- */
-#ifndef cpu_icache_snoops_remote_store
-#ifdef CONFIG_SMP
-#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
-#else
-#define cpu_icache_snoops_remote_store 1
-#endif
-#endif
-
-# ifndef cpu_has_mips32r1
-# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
-# endif
-# ifndef cpu_has_mips32r2
-# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
-# endif
-# ifndef cpu_has_mips64r1
-# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
-# endif
-# ifndef cpu_has_mips64r2
-# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
-# endif
-
-/*
- * Shortcuts ...
- */
-#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
-#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
-#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
-#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
-
-#ifndef cpu_has_dsp
-#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
-#endif
-
-#ifndef cpu_has_mipsmt
-#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
-#endif
-
-#ifndef cpu_has_userlocal
-#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
-#endif
-
-#ifdef CONFIG_32BIT
-# ifndef cpu_has_nofpuex
-# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
-# endif
-# ifndef cpu_has_64bits
-# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
-# endif
-# ifndef cpu_has_64bit_zero_reg
-# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
-# endif
-# ifndef cpu_has_64bit_gp_regs
-# define cpu_has_64bit_gp_regs 0
-# endif
-# ifndef cpu_has_64bit_addresses
-# define cpu_has_64bit_addresses 0
-# endif
-#endif
-
-#ifdef CONFIG_64BIT
-# ifndef cpu_has_nofpuex
-# define cpu_has_nofpuex 0
-# endif
-# ifndef cpu_has_64bits
-# define cpu_has_64bits 1
-# endif
-# ifndef cpu_has_64bit_zero_reg
-# define cpu_has_64bit_zero_reg 1
-# endif
-# ifndef cpu_has_64bit_gp_regs
-# define cpu_has_64bit_gp_regs 1
-# endif
-# ifndef cpu_has_64bit_addresses
-# define cpu_has_64bit_addresses 1
-# endif
-#endif
-
-#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
-# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
-#elif !defined(cpu_has_vint)
-# define cpu_has_vint 0
-#endif
-
-#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
-# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
-#elif !defined(cpu_has_veic)
-# define cpu_has_veic 0
-#endif
-
-#ifndef cpu_has_inclusive_pcaches
-#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
-#endif
-
-#ifndef cpu_dcache_line_size
-#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
-#endif
-#ifndef cpu_icache_line_size
-#define cpu_icache_line_size() cpu_data[0].icache.linesz
-#endif
-#ifndef cpu_scache_line_size
-#define cpu_scache_line_size() cpu_data[0].scache.linesz
-#endif
-
-#endif /* __ASM_CPU_FEATURES_H */
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
deleted file mode 100644
index 2de73dbb2e9..00000000000
--- a/include/asm-mips/cpu-info.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 Waldorf GMBH
- * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
- * Copyright (C) 1996 Paul M. Antoine
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2004 Maciej W. Rozycki
- */
-#ifndef __ASM_CPU_INFO_H
-#define __ASM_CPU_INFO_H
-
-#include <asm/cache.h>
-
-/*
- * Descriptor for a cache
- */
-struct cache_desc {
- unsigned int waysize; /* Bytes per way */
- unsigned short sets; /* Number of lines per set */
- unsigned char ways; /* Number of ways */
- unsigned char linesz; /* Size of line in bytes */
- unsigned char waybit; /* Bits to select in a cache set */
- unsigned char flags; /* Flags describing cache properties */
-};
-
-/*
- * Flag definitions
- */
-#define MIPS_CACHE_NOT_PRESENT 0x00000001
-#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
-#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
-#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
-#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
-#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
-
-struct cpuinfo_mips {
- unsigned long udelay_val;
- unsigned long asid_cache;
-
- /*
- * Capability and feature descriptor structure for MIPS CPU
- */
- unsigned long options;
- unsigned long ases;
- unsigned int processor_id;
- unsigned int fpu_id;
- unsigned int cputype;
- int isa_level;
- int tlbsize;
- struct cache_desc icache; /* Primary I-cache */
- struct cache_desc dcache; /* Primary D or combined I/D cache */
- struct cache_desc scache; /* Secondary cache */
- struct cache_desc tcache; /* Tertiary/split secondary cache */
- int srsets; /* Shadow register sets */
- int core; /* physical core number */
-#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
- /*
- * In the MIPS MT "SMTC" model, each TC is considered
- * to be a "CPU" for the purposes of scheduling, but
- * exception resources, ASID spaces, etc, are common
- * to all TCs within the same VPE.
- */
- int vpe_id; /* Virtual Processor number */
-#endif
-#ifdef CONFIG_MIPS_MT_SMTC
- int tc_id; /* Thread Context number */
-#endif
- void *data; /* Additional data */
-} __attribute__((aligned(SMP_CACHE_BYTES)));
-
-extern struct cpuinfo_mips cpu_data[];
-#define current_cpu_data cpu_data[smp_processor_id()]
-#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
-
-extern void cpu_probe(void);
-extern void cpu_report(void);
-
-extern const char *__cpu_name[];
-#define cpu_name_string() __cpu_name[smp_processor_id()]
-
-#endif /* __ASM_CPU_INFO_H */
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
deleted file mode 100644
index 229a786101d..00000000000
--- a/include/asm-mips/cpu.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * cpu.h: Values of the PRId register used to match up
- * various MIPS cpu types.
- *
- * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- * Copyright (C) 2004 Maciej W. Rozycki
- */
-#ifndef _ASM_CPU_H
-#define _ASM_CPU_H
-
-/* Assigned Company values for bits 23:16 of the PRId Register
- (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from
- MTI, the PRId register is defined in this (backwards compatible)
- way:
-
- +----------------+----------------+----------------+----------------+
- | Company Options| Company ID | Processor ID | Revision |
- +----------------+----------------+----------------+----------------+
- 31 24 23 16 15 8 7
-
- I don't have docs for all the previous processors, but my impression is
- that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
- spec.
-*/
-
-#define PRID_COMP_LEGACY 0x000000
-#define PRID_COMP_MIPS 0x010000
-#define PRID_COMP_BROADCOM 0x020000
-#define PRID_COMP_ALCHEMY 0x030000
-#define PRID_COMP_SIBYTE 0x040000
-#define PRID_COMP_SANDCRAFT 0x050000
-#define PRID_COMP_NXP 0x060000
-#define PRID_COMP_TOSHIBA 0x070000
-#define PRID_COMP_LSI 0x080000
-#define PRID_COMP_LEXRA 0x0b0000
-
-
-/*
- * Assigned values for the product ID register. In order to detect a
- * certain CPU type exactly eventually additional registers may need to
- * be examined. These are valid when 23:16 == PRID_COMP_LEGACY
- */
-#define PRID_IMP_R2000 0x0100
-#define PRID_IMP_AU1_REV1 0x0100
-#define PRID_IMP_AU1_REV2 0x0200
-#define PRID_IMP_R3000 0x0200 /* Same as R2000A */
-#define PRID_IMP_R6000 0x0300 /* Same as R3000A */
-#define PRID_IMP_R4000 0x0400
-#define PRID_IMP_R6000A 0x0600
-#define PRID_IMP_R10000 0x0900
-#define PRID_IMP_R4300 0x0b00
-#define PRID_IMP_VR41XX 0x0c00
-#define PRID_IMP_R12000 0x0e00
-#define PRID_IMP_R14000 0x0f00
-#define PRID_IMP_R8000 0x1000
-#define PRID_IMP_PR4450 0x1200
-#define PRID_IMP_R4600 0x2000
-#define PRID_IMP_R4700 0x2100
-#define PRID_IMP_TX39 0x2200
-#define PRID_IMP_R4640 0x2200
-#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
-#define PRID_IMP_R5000 0x2300
-#define PRID_IMP_TX49 0x2d00
-#define PRID_IMP_SONIC 0x2400
-#define PRID_IMP_MAGIC 0x2500
-#define PRID_IMP_RM7000 0x2700
-#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
-#define PRID_IMP_RM9000 0x3400
-#define PRID_IMP_LOONGSON1 0x4200
-#define PRID_IMP_R5432 0x5400
-#define PRID_IMP_R5500 0x5500
-#define PRID_IMP_LOONGSON2 0x6300
-
-#define PRID_IMP_UNKNOWN 0xff00
-
-/*
- * These are the PRID's for when 23:16 == PRID_COMP_MIPS
- */
-
-#define PRID_IMP_4KC 0x8000
-#define PRID_IMP_5KC 0x8100
-#define PRID_IMP_20KC 0x8200
-#define PRID_IMP_4KEC 0x8400
-#define PRID_IMP_4KSC 0x8600
-#define PRID_IMP_25KF 0x8800
-#define PRID_IMP_5KE 0x8900
-#define PRID_IMP_4KECR2 0x9000
-#define PRID_IMP_4KEMPR2 0x9100
-#define PRID_IMP_4KSD 0x9200
-#define PRID_IMP_24K 0x9300
-#define PRID_IMP_34K 0x9500
-#define PRID_IMP_24KE 0x9600
-#define PRID_IMP_74K 0x9700
-#define PRID_IMP_1004K 0x9900
-
-/*
- * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
- */
-
-#define PRID_IMP_SB1 0x0100
-#define PRID_IMP_SB1A 0x1100
-
-/*
- * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
- */
-
-#define PRID_IMP_SR71000 0x0400
-
-/*
- * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
- */
-
-#define PRID_IMP_BCM4710 0x4000
-#define PRID_IMP_BCM3302 0x9000
-
-/*
- * Definitions for 7:0 on legacy processors
- */
-
-#define PRID_REV_MASK 0x00ff
-
-#define PRID_REV_TX4927 0x0022
-#define PRID_REV_TX4937 0x0030
-#define PRID_REV_R4400 0x0040
-#define PRID_REV_R3000A 0x0030
-#define PRID_REV_R3000 0x0020
-#define PRID_REV_R2000A 0x0010
-#define PRID_REV_TX3912 0x0010
-#define PRID_REV_TX3922 0x0030
-#define PRID_REV_TX3927 0x0040
-#define PRID_REV_VR4111 0x0050
-#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
-#define PRID_REV_VR4121 0x0060
-#define PRID_REV_VR4122 0x0070
-#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
-#define PRID_REV_VR4130 0x0080
-#define PRID_REV_34K_V1_0_2 0x0022
-
-/*
- * Older processors used to encode processor version and revision in two
- * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
- * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
- * the patch number. *ARGH*
- */
-#define PRID_REV_ENCODE_44(ver, rev) \
- ((ver) << 4 | (rev))
-#define PRID_REV_ENCODE_332(ver, rev, patch) \
- ((ver) << 5 | (rev) << 2 | (patch))
-
-/*
- * FPU implementation/revision register (CP1 control register 0).
- *
- * +---------------------------------+----------------+----------------+
- * | 0 | Implementation | Revision |
- * +---------------------------------+----------------+----------------+
- * 31 16 15 8 7 0
- */
-
-#define FPIR_IMP_NONE 0x0000
-
-enum cpu_type_enum {
- CPU_UNKNOWN,
-
- /*
- * R2000 class processors
- */
- CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
- CPU_R3081, CPU_R3081E,
-
- /*
- * R6000 class processors
- */
- CPU_R6000, CPU_R6000A,
-
- /*
- * R4000 class processors
- */
- CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
- CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
- CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432,
- CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
- CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
- CPU_SR71000, CPU_RM9000, CPU_TX49XX,
-
- /*
- * R8000 class processors
- */
- CPU_R8000,
-
- /*
- * TX3900 class processors
- */
- CPU_TX3912, CPU_TX3922, CPU_TX3927,
-
- /*
- * MIPS32 class processors
- */
- CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
- CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500,
- CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
-
- /*
- * MIPS64 class processors
- */
- CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
-
- CPU_LAST
-};
-
-
-/*
- * ISA Level encodings
- *
- */
-#define MIPS_CPU_ISA_I 0x00000001
-#define MIPS_CPU_ISA_II 0x00000002
-#define MIPS_CPU_ISA_III 0x00000004
-#define MIPS_CPU_ISA_IV 0x00000008
-#define MIPS_CPU_ISA_V 0x00000010
-#define MIPS_CPU_ISA_M32R1 0x00000020
-#define MIPS_CPU_ISA_M32R2 0x00000040
-#define MIPS_CPU_ISA_M64R1 0x00000080
-#define MIPS_CPU_ISA_M64R2 0x00000100
-
-#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
- MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
-#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
- MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
-
-/*
- * CPU Option encodings
- */
-#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
-#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */
-#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */
-#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */
-#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */
-#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */
-#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */
-#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */
-#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */
-#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
-#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
-#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
-#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */
-#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */
-#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */
-#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */
-#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
-#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */
-#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
-#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
-#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
-#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
-
-/*
- * CPU ASE encodings
- */
-#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
-#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
-#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
-#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
-#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
-#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
-
-
-#endif /* _ASM_CPU_H */
diff --git a/include/asm-mips/cputime.h b/include/asm-mips/cputime.h
deleted file mode 100644
index c00eacbdd97..00000000000
--- a/include/asm-mips/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __MIPS_CPUTIME_H
-#define __MIPS_CPUTIME_H
-
-#include <asm-generic/cputime.h>
-
-#endif /* __MIPS_CPUTIME_H */
diff --git a/include/asm-mips/current.h b/include/asm-mips/current.h
deleted file mode 100644
index 559db66b979..00000000000
--- a/include/asm-mips/current.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998, 2002 Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_CURRENT_H
-#define _ASM_CURRENT_H
-
-#include <linux/thread_info.h>
-
-struct task_struct;
-
-static inline struct task_struct * get_current(void)
-{
- return current_thread_info()->task;
-}
-
-#define current get_current()
-
-#endif /* _ASM_CURRENT_H */
diff --git a/include/asm-mips/debug.h b/include/asm-mips/debug.h
deleted file mode 100644
index 1fd5a2b3944..00000000000
--- a/include/asm-mips/debug.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Debug macros for run-time debugging.
- * Turned on/off with CONFIG_RUNTIME_DEBUG option.
- *
- * Copyright (C) 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifndef _ASM_DEBUG_H
-#define _ASM_DEBUG_H
-
-
-/*
- * run-time macros for catching spurious errors. Eable CONFIG_RUNTIME_DEBUG in
- * kernel hacking config menu to use them.
- *
- * Use them as run-time debugging aid. NEVER USE THEM AS ERROR HANDLING CODE!!!
- */
-
-#ifdef CONFIG_RUNTIME_DEBUG
-
-#include <linux/kernel.h>
-
-#define db_assert(x) if (!(x)) { \
- panic("assertion failed at %s:%d: %s", __FILE__, __LINE__, #x); }
-#define db_warn(x) if (!(x)) { \
- printk(KERN_WARNING "warning at %s:%d: %s", __FILE__, __LINE__, #x); }
-#define db_verify(x, y) db_assert(x y)
-#define db_verify_warn(x, y) db_warn(x y)
-#define db_run(x) do { x; } while (0)
-
-#else
-
-#define db_assert(x)
-#define db_warn(x)
-#define db_verify(x, y) x
-#define db_verify_warn(x, y) x
-#define db_run(x)
-
-#endif
-
-#endif /* _ASM_DEBUG_H */
diff --git a/include/asm-mips/dec/ecc.h b/include/asm-mips/dec/ecc.h
deleted file mode 100644
index 707ffdbc9ad..00000000000
--- a/include/asm-mips/dec/ecc.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * include/asm-mips/dec/ecc.h
- *
- * ECC handling logic definitions common to DECstation/DECsystem
- * 5000/200 (KN02), 5000/240 (KN03), 5000/260 (KN05) and
- * DECsystem 5900 (KN03), 5900/260 (KN05) systems.
- *
- * Copyright (C) 2003 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_MIPS_DEC_ECC_H
-#define __ASM_MIPS_DEC_ECC_H
-
-/*
- * Error Address Register bits.
- * The register is r/wc -- any write clears it.
- */
-#define KN0X_EAR_VALID (1<<31) /* error data valid, bus IRQ */
-#define KN0X_EAR_CPU (1<<30) /* CPU/DMA transaction */
-#define KN0X_EAR_WRITE (1<<29) /* write/read transaction */
-#define KN0X_EAR_ECCERR (1<<28) /* ECC/timeout or overrun */
-#define KN0X_EAR_RES_27 (1<<27) /* unused */
-#define KN0X_EAR_ADDRESS (0x7ffffff<<0) /* address involved */
-
-/*
- * Error Syndrome Register bits.
- * The register is frozen when EAR.VALID is set, otherwise it records bits
- * from the last memory read. The register is r/wc -- any write clears it.
- */
-#define KN0X_ESR_VLDHI (1<<31) /* error data valid hi word */
-#define KN0X_ESR_CHKHI (0x7f<<24) /* check bits read from mem */
-#define KN0X_ESR_SNGHI (1<<23) /* single/double bit error */
-#define KN0X_ESR_SYNHI (0x7f<<16) /* syndrome from ECC logic */
-#define KN0X_ESR_VLDLO (1<<15) /* error data valid lo word */
-#define KN0X_ESR_CHKLO (0x7f<<8) /* check bits read from mem */
-#define KN0X_ESR_SNGLO (1<<7) /* single/double bit error */
-#define KN0X_ESR_SYNLO (0x7f<<0) /* syndrome from ECC logic */
-
-
-#ifndef __ASSEMBLY__
-
-#include <linux/interrupt.h>
-
-struct pt_regs;
-
-extern void dec_ecc_be_init(void);
-extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup);
-extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id);
-#endif
-
-#endif /* __ASM_MIPS_DEC_ECC_H */
diff --git a/include/asm-mips/dec/interrupts.h b/include/asm-mips/dec/interrupts.h
deleted file mode 100644
index e10d341067c..00000000000
--- a/include/asm-mips/dec/interrupts.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Miscellaneous definitions used to initialise the interrupt vector table
- * with the machine-specific interrupt routines.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1997 by Paul M. Antoine.
- * reworked 1998 by Harald Koerfgen.
- * Copyright (C) 2001, 2002, 2003 Maciej W. Rozycki
- */
-
-#ifndef __ASM_DEC_INTERRUPTS_H
-#define __ASM_DEC_INTERRUPTS_H
-
-#include <irq.h>
-#include <asm/mipsregs.h>
-
-
-/*
- * The list of possible system devices which provide an
- * interrupt. Not all devices exist on a given system.
- */
-#define DEC_IRQ_CASCADE 0 /* cascade from CSR or I/O ASIC */
-
-/* Ordinary interrupts */
-#define DEC_IRQ_AB_RECV 1 /* ACCESS.bus receive */
-#define DEC_IRQ_AB_XMIT 2 /* ACCESS.bus transmit */
-#define DEC_IRQ_DZ11 3 /* DZ11 (DC7085) serial */
-#define DEC_IRQ_ASC 4 /* ASC (NCR53C94) SCSI */
-#define DEC_IRQ_FLOPPY 5 /* 82077 FDC */
-#define DEC_IRQ_FPU 6 /* R3k FPU */
-#define DEC_IRQ_HALT 7 /* HALT button or from ACCESS.Bus */
-#define DEC_IRQ_ISDN 8 /* Am79C30A ISDN */
-#define DEC_IRQ_LANCE 9 /* LANCE (Am7990) Ethernet */
-#define DEC_IRQ_BUS 10 /* memory, I/O bus read/write errors */
-#define DEC_IRQ_PSU 11 /* power supply unit warning */
-#define DEC_IRQ_RTC 12 /* DS1287 RTC */
-#define DEC_IRQ_SCC0 13 /* SCC (Z85C30) serial #0 */
-#define DEC_IRQ_SCC1 14 /* SCC (Z85C30) serial #1 */
-#define DEC_IRQ_SII 15 /* SII (DC7061) SCSI */
-#define DEC_IRQ_TC0 16 /* TURBOchannel slot #0 */
-#define DEC_IRQ_TC1 17 /* TURBOchannel slot #1 */
-#define DEC_IRQ_TC2 18 /* TURBOchannel slot #2 */
-#define DEC_IRQ_TIMER 19 /* ARC periodic timer */
-#define DEC_IRQ_VIDEO 20 /* framebuffer */
-
-/* I/O ASIC DMA interrupts */
-#define DEC_IRQ_ASC_MERR 21 /* ASC memory read error */
-#define DEC_IRQ_ASC_ERR 22 /* ASC page overrun */
-#define DEC_IRQ_ASC_DMA 23 /* ASC buffer pointer loaded */
-#define DEC_IRQ_FLOPPY_ERR 24 /* FDC error */
-#define DEC_IRQ_ISDN_ERR 25 /* ISDN memory read/overrun error */
-#define DEC_IRQ_ISDN_RXDMA 26 /* ISDN recv buffer pointer loaded */
-#define DEC_IRQ_ISDN_TXDMA 27 /* ISDN xmit buffer pointer loaded */
-#define DEC_IRQ_LANCE_MERR 28 /* LANCE memory read error */
-#define DEC_IRQ_SCC0A_RXERR 29 /* SCC0A (printer) receive overrun */
-#define DEC_IRQ_SCC0A_RXDMA 30 /* SCC0A receive half page */
-#define DEC_IRQ_SCC0A_TXERR 31 /* SCC0A xmit memory read/overrun */
-#define DEC_IRQ_SCC0A_TXDMA 32 /* SCC0A transmit page end */
-#define DEC_IRQ_AB_RXERR 33 /* ACCESS.bus receive overrun */
-#define DEC_IRQ_AB_RXDMA 34 /* ACCESS.bus receive half page */
-#define DEC_IRQ_AB_TXERR 35 /* ACCESS.bus xmit memory read/ovrn */
-#define DEC_IRQ_AB_TXDMA 36 /* ACCESS.bus transmit page end */
-#define DEC_IRQ_SCC1A_RXERR 37 /* SCC1A (modem) receive overrun */
-#define DEC_IRQ_SCC1A_RXDMA 38 /* SCC1A receive half page */
-#define DEC_IRQ_SCC1A_TXERR 39 /* SCC1A xmit memory read/overrun */
-#define DEC_IRQ_SCC1A_TXDMA 40 /* SCC1A transmit page end */
-
-/* TC5 & TC6 are virtual slots for KN02's onboard devices */
-#define DEC_IRQ_TC5 DEC_IRQ_ASC /* virtual PMAZ-AA */
-#define DEC_IRQ_TC6 DEC_IRQ_LANCE /* virtual PMAD-AA */
-
-#define DEC_NR_INTS 41
-
-
-/* Largest of cpu mask_nr tables. */
-#define DEC_MAX_CPU_INTS 6
-/* Largest of asic mask_nr tables. */
-#define DEC_MAX_ASIC_INTS 9
-
-
-/*
- * CPU interrupt bits common to all systems.
- */
-#define DEC_CPU_INR_FPU 7 /* R3k FPU */
-#define DEC_CPU_INR_SW1 1 /* software #1 */
-#define DEC_CPU_INR_SW0 0 /* software #0 */
-
-#define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */
-
-#define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE)
-#define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP))
-#define DEC_CPU_IRQ_ALL (0xff << CAUSEB_IP)
-
-
-#ifndef __ASSEMBLY__
-
-/*
- * Interrupt table structures to hide differences between systems.
- */
-typedef union { int i; void *p; } int_ptr;
-extern int dec_interrupt[DEC_NR_INTS];
-extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2];
-extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2];
-extern int cpu_fpu_mask;
-
-
-/*
- * Common interrupt routine prototypes for all DECStations
- */
-extern void kn02_io_int(void);
-extern void kn02xa_io_int(void);
-extern void kn03_io_int(void);
-extern void asic_dma_int(void);
-extern void asic_all_int(void);
-extern void kn02_all_int(void);
-extern void cpu_all_int(void);
-
-extern void dec_intr_unimplemented(void);
-extern void asic_intr_unimplemented(void);
-
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/include/asm-mips/dec/ioasic.h b/include/asm-mips/dec/ioasic.h
deleted file mode 100644
index 98badd6bf22..00000000000
--- a/include/asm-mips/dec/ioasic.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * include/asm-mips/dec/ioasic.h
- *
- * DEC I/O ASIC access operations.
- *
- * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef __ASM_DEC_IOASIC_H
-#define __ASM_DEC_IOASIC_H
-
-#include <linux/spinlock.h>
-#include <linux/types.h>
-
-extern spinlock_t ioasic_ssr_lock;
-
-extern volatile u32 *ioasic_base;
-
-static inline void ioasic_write(unsigned int reg, u32 v)
-{
- ioasic_base[reg / 4] = v;
-}
-
-static inline u32 ioasic_read(unsigned int reg)
-{
- return ioasic_base[reg / 4];
-}
-
-extern void init_ioasic_irqs(int base);
-
-extern void dec_ioasic_clocksource_init(void);
-
-#endif /* __ASM_DEC_IOASIC_H */
diff --git a/include/asm-mips/dec/ioasic_addrs.h b/include/asm-mips/dec/ioasic_addrs.h
deleted file mode 100644
index 4cbc1f8a112..00000000000
--- a/include/asm-mips/dec/ioasic_addrs.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Definitions for the address map in the JUNKIO Asic
- *
- * Created with Information from:
- *
- * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
- *
- * and the Mach Sources
- *
- * Copyright (C) 199x the Anonymous
- * Copyright (C) 2002, 2003 Maciej W. Rozycki
- */
-
-#ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H
-#define __ASM_MIPS_DEC_IOASIC_ADDRS_H
-
-#define IOASIC_SLOT_SIZE 0x00040000
-
-/*
- * Address ranges decoded by the I/O ASIC for onboard devices.
- */
-#define IOASIC_SYS_ROM (0*IOASIC_SLOT_SIZE) /* system board ROM */
-#define IOASIC_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */
-#define IOASIC_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
-#define IOASIC_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
-#define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE) /* SCC #0 */
-#define IOASIC_VDAC_HI (5*IOASIC_SLOT_SIZE) /* VDAC (maxine) */
-#define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE) /* SCC #1 (3min, 3max+) */
-#define IOASIC_VDAC_LO (7*IOASIC_SLOT_SIZE) /* VDAC (maxine) */
-#define IOASIC_TOY (8*IOASIC_SLOT_SIZE) /* RTC */
-#define IOASIC_ISDN (9*IOASIC_SLOT_SIZE) /* ISDN (maxine) */
-#define IOASIC_ERRADDR (9*IOASIC_SLOT_SIZE) /* bus error address (3max+) */
-#define IOASIC_CHKSYN (10*IOASIC_SLOT_SIZE) /* ECC syndrome (3max+) */
-#define IOASIC_ACC_BUS (10*IOASIC_SLOT_SIZE) /* ACCESS.bus (maxine) */
-#define IOASIC_MCR (11*IOASIC_SLOT_SIZE) /* memory control (3max+) */
-#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */
-#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
-#define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */
-#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */
-#define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */
-
-
-/*
- * Offsets for I/O ASIC registers
- * (relative to (dec_kn_slot_base + IOASIC_IOCTL)).
- */
- /* all systems */
-#define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */
-#define IO_REG_SCSI_DMA_BP 0x10 /* SCSI DMA Buffer Pointer */
-#define IO_REG_LANCE_DMA_P 0x20 /* LANCE DMA Pointer */
-#define IO_REG_SCC0A_T_DMA_P 0x30 /* SCC0A Transmit DMA Pointer */
-#define IO_REG_SCC0A_R_DMA_P 0x40 /* SCC0A Receive DMA Pointer */
-
- /* except Maxine */
-#define IO_REG_SCC1A_T_DMA_P 0x50 /* SCC1A Transmit DMA Pointer */
-#define IO_REG_SCC1A_R_DMA_P 0x60 /* SCC1A Receive DMA Pointer */
-
- /* Maxine */
-#define IO_REG_AB_T_DMA_P 0x50 /* ACCESS.bus Transmit DMA Pointer */
-#define IO_REG_AB_R_DMA_P 0x60 /* ACCESS.bus Receive DMA Pointer */
-#define IO_REG_FLOPPY_DMA_P 0x70 /* Floppy DMA Pointer */
-#define IO_REG_ISDN_T_DMA_P 0x80 /* ISDN Transmit DMA Pointer */
-#define IO_REG_ISDN_T_DMA_BP 0x90 /* ISDN Transmit DMA Buffer Pointer */
-#define IO_REG_ISDN_R_DMA_P 0xa0 /* ISDN Receive DMA Pointer */
-#define IO_REG_ISDN_R_DMA_BP 0xb0 /* ISDN Receive DMA Buffer Pointer */
-
- /* all systems */
-#define IO_REG_DATA_0 0xc0 /* System Data Buffer 0 */
-#define IO_REG_DATA_1 0xd0 /* System Data Buffer 1 */
-#define IO_REG_DATA_2 0xe0 /* System Data Buffer 2 */
-#define IO_REG_DATA_3 0xf0 /* System Data Buffer 3 */
-
- /* all systems */
-#define IO_REG_SSR 0x100 /* System Support Register */
-#define IO_REG_SIR 0x110 /* System Interrupt Register */
-#define IO_REG_SIMR 0x120 /* System Interrupt Mask Reg. */
-#define IO_REG_SAR 0x130 /* System Address Register */
-
- /* Maxine */
-#define IO_REG_ISDN_T_DATA 0x140 /* ISDN Xmit Data Register */
-#define IO_REG_ISDN_R_DATA 0x150 /* ISDN Receive Data Register */
-
- /* all systems */
-#define IO_REG_LANCE_SLOT 0x160 /* LANCE I/O Slot Register */
-#define IO_REG_SCSI_SLOT 0x170 /* SCSI Slot Register */
-#define IO_REG_SCC0A_SLOT 0x180 /* SCC0A DMA Slot Register */
-
- /* except Maxine */
-#define IO_REG_SCC1A_SLOT 0x190 /* SCC1A DMA Slot Register */
-
- /* Maxine */
-#define IO_REG_AB_SLOT 0x190 /* ACCESS.bus DMA Slot Register */
-#define IO_REG_FLOPPY_SLOT 0x1a0 /* Floppy Slot Register */
-
- /* all systems */
-#define IO_REG_SCSI_SCR 0x1b0 /* SCSI Partial-Word DMA Control */
-#define IO_REG_SCSI_SDR0 0x1c0 /* SCSI DMA Partial Word 0 */
-#define IO_REG_SCSI_SDR1 0x1d0 /* SCSI DMA Partial Word 1 */
-#define IO_REG_FCTR 0x1e0 /* Free-Running Counter */
-#define IO_REG_RES_31 0x1f0 /* unused */
-
-
-/*
- * The upper 16 bits of the System Support Register are a part of the
- * I/O ASIC's internal DMA engine and thus are common to all I/O ASIC
- * machines. The exception is the Maxine, which makes use of the
- * FLOPPY and ISDN bits (otherwise unused) and has a different SCC
- * wiring.
- */
- /* all systems */
-#define IO_SSR_SCC0A_TX_DMA_EN (1<<31) /* SCC0A transmit DMA enable */
-#define IO_SSR_SCC0A_RX_DMA_EN (1<<30) /* SCC0A receive DMA enable */
-#define IO_SSR_RES_27 (1<<27) /* unused */
-#define IO_SSR_RES_26 (1<<26) /* unused */
-#define IO_SSR_RES_25 (1<<25) /* unused */
-#define IO_SSR_RES_24 (1<<24) /* unused */
-#define IO_SSR_RES_23 (1<<23) /* unused */
-#define IO_SSR_SCSI_DMA_DIR (1<<18) /* SCSI DMA direction */
-#define IO_SSR_SCSI_DMA_EN (1<<17) /* SCSI DMA enable */
-#define IO_SSR_LANCE_DMA_EN (1<<16) /* LANCE DMA enable */
-
- /* except Maxine */
-#define IO_SSR_SCC1A_TX_DMA_EN (1<<29) /* SCC1A transmit DMA enable */
-#define IO_SSR_SCC1A_RX_DMA_EN (1<<28) /* SCC1A receive DMA enable */
-#define IO_SSR_RES_22 (1<<22) /* unused */
-#define IO_SSR_RES_21 (1<<21) /* unused */
-#define IO_SSR_RES_20 (1<<20) /* unused */
-#define IO_SSR_RES_19 (1<<19) /* unused */
-
- /* Maxine */
-#define IO_SSR_AB_TX_DMA_EN (1<<29) /* ACCESS.bus xmit DMA enable */
-#define IO_SSR_AB_RX_DMA_EN (1<<28) /* ACCESS.bus recv DMA enable */
-#define IO_SSR_FLOPPY_DMA_DIR (1<<22) /* Floppy DMA direction */
-#define IO_SSR_FLOPPY_DMA_EN (1<<21) /* Floppy DMA enable */
-#define IO_SSR_ISDN_TX_DMA_EN (1<<20) /* ISDN transmit DMA enable */
-#define IO_SSR_ISDN_RX_DMA_EN (1<<19) /* ISDN receive DMA enable */
-
-/*
- * The lower 16 bits are system-specific. Bits 15,11:8 are common and
- * defined here. The rest is defined in system-specific headers.
- */
-#define KN0X_IO_SSR_DIAGDN (1<<15) /* diagnostic jumper */
-#define KN0X_IO_SSR_SCC_RST (1<<11) /* ~SCC0,1 (Z85C30) reset */
-#define KN0X_IO_SSR_RTC_RST (1<<10) /* ~RTC (DS1287) reset */
-#define KN0X_IO_SSR_ASC_RST (1<<9) /* ~ASC (NCR53C94) reset */
-#define KN0X_IO_SSR_LANCE_RST (1<<8) /* ~LANCE (Am7990) reset */
-
-#endif /* __ASM_MIPS_DEC_IOASIC_ADDRS_H */
diff --git a/include/asm-mips/dec/ioasic_ints.h b/include/asm-mips/dec/ioasic_ints.h
deleted file mode 100644
index 9aaa9869615..00000000000
--- a/include/asm-mips/dec/ioasic_ints.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Definitions for the interrupt related bits in the I/O ASIC
- * interrupt status register (and the interrupt mask register, of course)
- *
- * Created with Information from:
- *
- * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
- *
- * and the Mach Sources
- *
- * Copyright (C) 199x the Anonymous
- * Copyright (C) 2002 Maciej W. Rozycki
- */
-
-#ifndef __ASM_DEC_IOASIC_INTS_H
-#define __ASM_DEC_IOASIC_INTS_H
-
-/*
- * The upper 16 bits are a part of the I/O ASIC's internal DMA engine
- * and thus are common to all I/O ASIC machines. The exception is
- * the Maxine, which makes use of the FLOPPY and ISDN bits (otherwise
- * unused) and has a different SCC wiring.
- */
- /* all systems */
-#define IO_INR_SCC0A_TXDMA 31 /* SCC0A transmit page end */
-#define IO_INR_SCC0A_TXERR 30 /* SCC0A transmit memory read error */
-#define IO_INR_SCC0A_RXDMA 29 /* SCC0A receive half page */
-#define IO_INR_SCC0A_RXERR 28 /* SCC0A receive overrun */
-#define IO_INR_ASC_DMA 19 /* ASC buffer pointer loaded */
-#define IO_INR_ASC_ERR 18 /* ASC page overrun */
-#define IO_INR_ASC_MERR 17 /* ASC memory read error */
-#define IO_INR_LANCE_MERR 16 /* LANCE memory read error */
-
- /* except Maxine */
-#define IO_INR_SCC1A_TXDMA 27 /* SCC1A transmit page end */
-#define IO_INR_SCC1A_TXERR 26 /* SCC1A transmit memory read error */
-#define IO_INR_SCC1A_RXDMA 25 /* SCC1A receive half page */
-#define IO_INR_SCC1A_RXERR 24 /* SCC1A receive overrun */
-#define IO_INR_RES_23 23 /* unused */
-#define IO_INR_RES_22 22 /* unused */
-#define IO_INR_RES_21 21 /* unused */
-#define IO_INR_RES_20 20 /* unused */
-
- /* Maxine */
-#define IO_INR_AB_TXDMA 27 /* ACCESS.bus transmit page end */
-#define IO_INR_AB_TXERR 26 /* ACCESS.bus xmit memory read error */
-#define IO_INR_AB_RXDMA 25 /* ACCESS.bus receive half page */
-#define IO_INR_AB_RXERR 24 /* ACCESS.bus receive overrun */
-#define IO_INR_FLOPPY_ERR 23 /* FDC error */
-#define IO_INR_ISDN_TXDMA 22 /* ISDN xmit buffer pointer loaded */
-#define IO_INR_ISDN_RXDMA 21 /* ISDN recv buffer pointer loaded */
-#define IO_INR_ISDN_ERR 20 /* ISDN memory read/overrun error */
-
-#define IO_INR_DMA 16 /* first DMA IRQ */
-
-/*
- * The lower 16 bits are system-specific and thus defined in
- * system-specific headers.
- */
-
-
-#define IO_IRQ_BASE 8 /* first IRQ assigned to I/O ASIC */
-#define IO_IRQ_LINES 32 /* number of I/O ASIC interrupts */
-
-#define IO_IRQ_NR(n) ((n) + IO_IRQ_BASE)
-#define IO_IRQ_MASK(n) (1 << (n))
-#define IO_IRQ_ALL 0x0000ffff
-#define IO_IRQ_DMA 0xffff0000
-
-#endif /* __ASM_DEC_IOASIC_INTS_H */
diff --git a/include/asm-mips/dec/kn01.h b/include/asm-mips/dec/kn01.h
deleted file mode 100644
index 28fa717ac42..00000000000
--- a/include/asm-mips/dec/kn01.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Hardware info about DECstation DS2100/3100 systems (otherwise known as
- * pmin/pmax or KN01).
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
- * are by courtesy of Chris Fraser.
- * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
- */
-#ifndef __ASM_MIPS_DEC_KN01_H
-#define __ASM_MIPS_DEC_KN01_H
-
-#define KN01_SLOT_BASE 0x10000000
-#define KN01_SLOT_SIZE 0x01000000
-
-/*
- * Address ranges for devices.
- */
-#define KN01_PMASK (0*KN01_SLOT_SIZE) /* color plane mask */
-#define KN01_PCC (1*KN01_SLOT_SIZE) /* PCC (DC503) cursor */
-#define KN01_VDAC (2*KN01_SLOT_SIZE) /* color map */
-#define KN01_RES_3 (3*KN01_SLOT_SIZE) /* unused */
-#define KN01_RES_4 (4*KN01_SLOT_SIZE) /* unused */
-#define KN01_RES_5 (5*KN01_SLOT_SIZE) /* unused */
-#define KN01_RES_6 (6*KN01_SLOT_SIZE) /* unused */
-#define KN01_ERRADDR (7*KN01_SLOT_SIZE) /* write error address */
-#define KN01_LANCE (8*KN01_SLOT_SIZE) /* LANCE (Am7990) Ethernet */
-#define KN01_LANCE_MEM (9*KN01_SLOT_SIZE) /* LANCE buffer memory */
-#define KN01_SII (10*KN01_SLOT_SIZE) /* SII (DC7061) SCSI */
-#define KN01_SII_MEM (11*KN01_SLOT_SIZE) /* SII buffer memory */
-#define KN01_DZ11 (12*KN01_SLOT_SIZE) /* DZ11 (DC7085) serial */
-#define KN01_RTC (13*KN01_SLOT_SIZE) /* DS1287 RTC (bytes #0) */
-#define KN01_ESAR (13*KN01_SLOT_SIZE) /* MAC address (bytes #1) */
-#define KN01_CSR (14*KN01_SLOT_SIZE) /* system ctrl & status reg */
-#define KN01_SYS_ROM (15*KN01_SLOT_SIZE) /* system board ROM */
-
-
-/*
- * Frame buffer memory address.
- */
-#define KN01_VFB_MEM 0x0fc00000
-
-/*
- * CPU interrupt bits.
- */
-#define KN01_CPU_INR_BUS 6 /* memory, I/O bus read/write errors */
-#define KN01_CPU_INR_VIDEO 6 /* PCC area detect #2 */
-#define KN01_CPU_INR_RTC 5 /* DS1287 RTC */
-#define KN01_CPU_INR_DZ11 4 /* DZ11 (DC7085) serial */
-#define KN01_CPU_INR_LANCE 3 /* LANCE (Am7990) Ethernet */
-#define KN01_CPU_INR_SII 2 /* SII (DC7061) SCSI */
-
-
-/*
- * System Control & Status Register bits.
- */
-#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */
-#define KN01_CSR_STATUS (1<<14) /* self-test result status output */
-#define KN01_CSR_PARDIS (1<<13) /* parity error disable */
-#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */
-#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */
-#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/
-#define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */
-#define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */
-#define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */
-#define KN01_CSR_VRGTRG (1<<1) /* red DAC voltage over green (r/o) */
-#define KN01_CSR_VRGTRB (1<<0) /* red DAC voltage over blue (r/o) */
-#define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
-
-
-#ifndef __ASSEMBLY__
-
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/types.h>
-
-struct pt_regs;
-
-extern u16 cached_kn01_csr;
-extern spinlock_t kn01_lock;
-
-extern void dec_kn01_be_init(void);
-extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
-extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id);
-#endif
-
-#endif /* __ASM_MIPS_DEC_KN01_H */
diff --git a/include/asm-mips/dec/kn02.h b/include/asm-mips/dec/kn02.h
deleted file mode 100644
index 93430b5f472..00000000000
--- a/include/asm-mips/dec/kn02.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Hardware info about DECstation 5000/200 systems (otherwise known as
- * 3max or KN02).
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
- * are by courtesy of Chris Fraser.
- * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
- */
-#ifndef __ASM_MIPS_DEC_KN02_H
-#define __ASM_MIPS_DEC_KN02_H
-
-#define KN02_SLOT_BASE 0x1fc00000
-#define KN02_SLOT_SIZE 0x00080000
-
-/*
- * Address ranges decoded by the "system slot" logic for onboard devices.
- */
-#define KN02_SYS_ROM (0*KN02_SLOT_SIZE) /* system board ROM */
-#define KN02_RES_1 (1*KN02_SLOT_SIZE) /* unused */
-#define KN02_CHKSYN (2*KN02_SLOT_SIZE) /* ECC syndrome */
-#define KN02_ERRADDR (3*KN02_SLOT_SIZE) /* bus error address */
-#define KN02_DZ11 (4*KN02_SLOT_SIZE) /* DZ11 (DC7085) serial */
-#define KN02_RTC (5*KN02_SLOT_SIZE) /* DS1287 RTC */
-#define KN02_CSR (6*KN02_SLOT_SIZE) /* system ctrl & status reg */
-#define KN02_SYS_ROM_7 (7*KN02_SLOT_SIZE) /* system board ROM (alias) */
-
-
-/*
- * System Control & Status Register bits.
- */
-#define KN02_CSR_RES_28 (0xf<<28) /* unused */
-#define KN02_CSR_PSU (1<<27) /* power supply unit warning */
-#define KN02_CSR_NVRAM (1<<26) /* ~NVRAM clear jumper */
-#define KN02_CSR_REFEVEN (1<<25) /* mem refresh bank toggle */
-#define KN02_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */
-#define KN02_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */
-#define KN02_CSR_DIAGCHK (1<<15) /* diagn/norml ECC reads */
-#define KN02_CSR_DIAGGEN (1<<14) /* diagn/norml ECC writes */
-#define KN02_CSR_CORRECT (1<<13) /* ECC correct/check */
-#define KN02_CSR_LEDIAG (1<<12) /* ECC diagn. latch strobe */
-#define KN02_CSR_TXDIS (1<<11) /* DZ11 transmit disable */
-#define KN02_CSR_BNK32M (1<<10) /* 32M/8M stride */
-#define KN02_CSR_DIAGDN (1<<9) /* DIAGDN manufact. jumper */
-#define KN02_CSR_BAUD38 (1<<8) /* DZ11 38/19kbps ext. rate */
-#define KN02_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */
-#define KN02_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
-
-
-/*
- * CPU interrupt bits.
- */
-#define KN02_CPU_INR_RES_6 6 /* unused */
-#define KN02_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */
-#define KN02_CPU_INR_RES_4 4 /* unused */
-#define KN02_CPU_INR_RTC 3 /* DS1287 RTC */
-#define KN02_CPU_INR_CASCADE 2 /* CSR cascade */
-
-/*
- * CSR interrupt bits.
- */
-#define KN02_CSR_INR_DZ11 7 /* DZ11 (DC7085) serial */
-#define KN02_CSR_INR_LANCE 6 /* LANCE (Am7990) Ethernet */
-#define KN02_CSR_INR_ASC 5 /* ASC (NCR53C94) SCSI */
-#define KN02_CSR_INR_RES_4 4 /* unused */
-#define KN02_CSR_INR_RES_3 3 /* unused */
-#define KN02_CSR_INR_TC2 2 /* TURBOchannel slot #2 */
-#define KN02_CSR_INR_TC1 1 /* TURBOchannel slot #1 */
-#define KN02_CSR_INR_TC0 0 /* TURBOchannel slot #0 */
-
-
-#define KN02_IRQ_BASE 8 /* first IRQ assigned to CSR */
-#define KN02_IRQ_LINES 8 /* number of CSR interrupts */
-
-#define KN02_IRQ_NR(n) ((n) + KN02_IRQ_BASE)
-#define KN02_IRQ_MASK(n) (1 << (n))
-#define KN02_IRQ_ALL 0xff
-
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-extern u32 cached_kn02_csr;
-extern void init_kn02_irqs(int base);
-#endif
-
-#endif /* __ASM_MIPS_DEC_KN02_H */
diff --git a/include/asm-mips/dec/kn02ba.h b/include/asm-mips/dec/kn02ba.h
deleted file mode 100644
index c957a4f1b32..00000000000
--- a/include/asm-mips/dec/kn02ba.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * include/asm-mips/dec/kn02ba.h
- *
- * DECstation 5000/1xx (3min or KN02-BA) definitions.
- *
- * Copyright (C) 2002, 2003 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_MIPS_DEC_KN02BA_H
-#define __ASM_MIPS_DEC_KN02BA_H
-
-#include <asm/dec/kn02xa.h> /* For common definitions. */
-
-/*
- * CPU interrupt bits.
- */
-#define KN02BA_CPU_INR_HALT 6 /* HALT button */
-#define KN02BA_CPU_INR_CASCADE 5 /* I/O ASIC cascade */
-#define KN02BA_CPU_INR_TC2 4 /* TURBOchannel slot #2 */
-#define KN02BA_CPU_INR_TC1 3 /* TURBOchannel slot #1 */
-#define KN02BA_CPU_INR_TC0 2 /* TURBOchannel slot #0 */
-
-/*
- * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits.
- */
-#define KN02BA_IO_INR_RES_15 15 /* unused */
-#define KN02BA_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */
-#define KN02BA_IO_INR_RES_13 13 /* unused */
-#define KN02BA_IO_INR_BUS 12 /* memory, I/O bus read/write errors */
-#define KN02BA_IO_INR_RES_11 11 /* unused */
-#define KN02BA_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */
-#define KN02BA_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */
-#define KN02BA_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */
-#define KN02BA_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */
-#define KN02BA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
-#define KN02BA_IO_INR_RTC 5 /* DS1287 RTC */
-#define KN02BA_IO_INR_PSU 4 /* power supply unit warning */
-#define KN02BA_IO_INR_RES_3 3 /* unused */
-#define KN02BA_IO_INR_ASC_DATA 2 /* SCSI data ready (for PIO) */
-#define KN02BA_IO_INR_PBNC 1 /* ~HALT button debouncer */
-#define KN02BA_IO_INR_PBNO 0 /* HALT button debouncer */
-
-
-/*
- * Memory Error Register bits.
- */
-#define KN02BA_MER_RES_27 (1<<27) /* unused */
-
-/*
- * Memory Size Register bits.
- */
-#define KN02BA_MSR_RES_17 (0x3ff<<17) /* unused */
-
-/*
- * I/O ASIC System Support Register bits.
- */
-#define KN02BA_IO_SSR_TXDIS1 (1<<14) /* SCC1 transmit disable */
-#define KN02BA_IO_SSR_TXDIS0 (1<<13) /* SCC0 transmit disable */
-#define KN02BA_IO_SSR_RES_12 (1<<12) /* unused */
-
-#define KN02BA_IO_SSR_LEDS (0xff<<0) /* ~diagnostic LEDs */
-
-#endif /* __ASM_MIPS_DEC_KN02BA_H */
diff --git a/include/asm-mips/dec/kn02ca.h b/include/asm-mips/dec/kn02ca.h
deleted file mode 100644
index 92c0fe25609..00000000000
--- a/include/asm-mips/dec/kn02ca.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * include/asm-mips/dec/kn02ca.h
- *
- * Personal DECstation 5000/xx (Maxine or KN02-CA) definitions.
- *
- * Copyright (C) 2002, 2003 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_MIPS_DEC_KN02CA_H
-#define __ASM_MIPS_DEC_KN02CA_H
-
-#include <asm/dec/kn02xa.h> /* For common definitions. */
-
-/*
- * CPU interrupt bits.
- */
-#define KN02CA_CPU_INR_HALT 6 /* HALT from ACCESS.Bus */
-#define KN02CA_CPU_INR_CASCADE 5 /* I/O ASIC cascade */
-#define KN02CA_CPU_INR_BUS 4 /* memory, I/O bus read/write errors */
-#define KN02CA_CPU_INR_RTC 3 /* DS1287 RTC */
-#define KN02CA_CPU_INR_TIMER 2 /* ARC periodic timer */
-
-/*
- * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits.
- */
-#define KN02CA_IO_INR_FLOPPY 15 /* 82077 FDC */
-#define KN02CA_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */
-#define KN02CA_IO_INR_POWERON 13 /* (*) ACCESS.Bus/power-on reset */
-#define KN02CA_IO_INR_TC0 12 /* TURBOchannel slot #0 */
-#define KN02CA_IO_INR_TIMER 12 /* ARC periodic timer (?) */
-#define KN02CA_IO_INR_ISDN 11 /* Am79C30A ISDN */
-#define KN02CA_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */
-#define KN02CA_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */
-#define KN02CA_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */
-#define KN02CA_IO_INR_HDFLOPPY 7 /* (*) HD (1.44MB) floppy status */
-#define KN02CA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
-#define KN02CA_IO_INR_TC1 5 /* TURBOchannel slot #1 */
-#define KN02CA_IO_INR_XDFLOPPY 4 /* (*) XD (2.88MB) floppy status */
-#define KN02CA_IO_INR_VIDEO 3 /* framebuffer */
-#define KN02CA_IO_INR_XVIDEO 2 /* ~framebuffer */
-#define KN02CA_IO_INR_AB_XMIT 1 /* ACCESS.bus transmit */
-#define KN02CA_IO_INR_AB_RECV 0 /* ACCESS.bus receive */
-
-
-/*
- * Memory Error Register bits.
- */
-#define KN02CA_MER_INTR (1<<27) /* ARC IRQ status & ack */
-
-/*
- * Memory Size Register bits.
- */
-#define KN02CA_MSR_INTREN (1<<26) /* ARC periodic IRQ enable */
-#define KN02CA_MSR_MS10EN (1<<25) /* 10/1ms IRQ period select */
-#define KN02CA_MSR_PFORCE (0xf<<21) /* byte lane error force */
-#define KN02CA_MSR_MABEN (1<<20) /* A side VFB address enable */
-#define KN02CA_MSR_LASTBANK (0x7<<17) /* onboard RAM bank # */
-
-/*
- * I/O ASIC System Support Register bits.
- */
-#define KN03CA_IO_SSR_RES_14 (1<<14) /* unused */
-#define KN03CA_IO_SSR_RES_13 (1<<13) /* unused */
-#define KN03CA_IO_SSR_ISDN_RST (1<<12) /* ~ISDN (Am79C30A) reset */
-
-#define KN03CA_IO_SSR_FLOPPY_RST (1<<7) /* ~FDC (82077) reset */
-#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */
-#define KN03CA_IO_SSR_AB_RST (1<<5) /* ACCESS.bus reset */
-#define KN03CA_IO_SSR_RES_4 (1<<4) /* unused */
-#define KN03CA_IO_SSR_RES_3 (1<<4) /* unused */
-#define KN03CA_IO_SSR_RES_2 (1<<2) /* unused */
-#define KN03CA_IO_SSR_RES_1 (1<<1) /* unused */
-#define KN03CA_IO_SSR_LED (1<<0) /* power LED */
-
-#endif /* __ASM_MIPS_DEC_KN02CA_H */
diff --git a/include/asm-mips/dec/kn02xa.h b/include/asm-mips/dec/kn02xa.h
deleted file mode 100644
index b56b4577f6e..00000000000
--- a/include/asm-mips/dec/kn02xa.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Hardware info common to DECstation 5000/1xx systems (otherwise
- * known as 3min or kn02ba) and Personal DECstations 5000/xx ones
- * (otherwise known as maxine or kn02ca).
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
- * are by courtesy of Chris Fraser.
- * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki
- *
- * These are addresses which have to be known early in the boot process.
- * For other addresses refer to tc.h, ioasic_addrs.h and friends.
- */
-#ifndef __ASM_MIPS_DEC_KN02XA_H
-#define __ASM_MIPS_DEC_KN02XA_H
-
-#include <asm/dec/ioasic_addrs.h>
-
-#define KN02XA_SLOT_BASE 0x1c000000
-
-/*
- * Memory control ASIC registers.
- */
-#define KN02XA_MER 0x0c400000 /* memory error register */
-#define KN02XA_MSR 0x0c800000 /* memory size register */
-
-/*
- * CPU control ASIC registers.
- */
-#define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */
-#define KN02XA_EAR 0x0e000004 /* error address register */
-#define KN02XA_BOOT0 0x0e000008 /* boot 0 register */
-#define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */
-
-/*
- * Memory Error Register bits, common definitions.
- * The rest is defined in system-specific headers.
- */
-#define KN02XA_MER_RES_28 (0xf<<28) /* unused */
-#define KN02XA_MER_RES_17 (0x3ff<<17) /* unused */
-#define KN02XA_MER_PAGERR (1<<16) /* 2k page boundary error */
-#define KN02XA_MER_TRANSERR (1<<15) /* transfer length error */
-#define KN02XA_MER_PARDIS (1<<14) /* parity error disable */
-#define KN02XA_MER_SIZE (1<<13) /* r/o mirror of MSR_SIZE */
-#define KN02XA_MER_RES_12 (1<<12) /* unused */
-#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask: */
-#define KN02XA_MER_BYTERR_3 (0x8<<8) /* byte lane #3 */
-#define KN02XA_MER_BYTERR_2 (0x4<<8) /* byte lane #2 */
-#define KN02XA_MER_BYTERR_1 (0x2<<8) /* byte lane #1 */
-#define KN02XA_MER_BYTERR_0 (0x1<<8) /* byte lane #0 */
-#define KN02XA_MER_RES_0 (0xff<<0) /* unused */
-
-/*
- * Memory Size Register bits, common definitions.
- * The rest is defined in system-specific headers.
- */
-#define KN02XA_MSR_RES_27 (0x1f<<27) /* unused */
-#define KN02XA_MSR_RES_14 (0x7<<14) /* unused */
-#define KN02XA_MSR_SIZE (1<<13) /* 16M/4M stride */
-#define KN02XA_MSR_RES_0 (0x1fff<<0) /* unused */
-
-/*
- * Error Address Register bits.
- */
-#define KN02XA_EAR_RES_29 (0x7<<29) /* unused */
-#define KN02XA_EAR_ADDRESS (0x7ffffff<<2) /* address involved */
-#define KN02XA_EAR_RES_0 (0x3<<0) /* unused */
-
-
-#ifndef __ASSEMBLY__
-
-#include <linux/interrupt.h>
-
-struct pt_regs;
-
-extern void dec_kn02xa_be_init(void);
-extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup);
-extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id);
-#endif
-
-#endif /* __ASM_MIPS_DEC_KN02XA_H */
diff --git a/include/asm-mips/dec/kn03.h b/include/asm-mips/dec/kn03.h
deleted file mode 100644
index edede923ffb..00000000000
--- a/include/asm-mips/dec/kn03.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Hardware info about DECstation 5000/2x0 systems (otherwise known as
- * 3max+) and DECsystem 5900 systems (otherwise known as bigmax) which
- * differ mechanically but are otherwise identical (both are known as
- * KN03).
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
- * are by courtesy of Chris Fraser.
- * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki
- */
-#ifndef __ASM_MIPS_DEC_KN03_H
-#define __ASM_MIPS_DEC_KN03_H
-
-#include <asm/dec/ecc.h>
-#include <asm/dec/ioasic_addrs.h>
-
-#define KN03_SLOT_BASE 0x1f800000
-
-/*
- * CPU interrupt bits.
- */
-#define KN03_CPU_INR_HALT 6 /* HALT button */
-#define KN03_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */
-#define KN03_CPU_INR_RES_4 4 /* unused */
-#define KN03_CPU_INR_RTC 3 /* DS1287 RTC */
-#define KN03_CPU_INR_CASCADE 2 /* I/O ASIC cascade */
-
-/*
- * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits.
- */
-#define KN03_IO_INR_3MAXP 15 /* (*) 3max+/bigmax ID */
-#define KN03_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */
-#define KN03_IO_INR_TC2 13 /* TURBOchannel slot #2 */
-#define KN03_IO_INR_TC1 12 /* TURBOchannel slot #1 */
-#define KN03_IO_INR_TC0 11 /* TURBOchannel slot #0 */
-#define KN03_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */
-#define KN03_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */
-#define KN03_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */
-#define KN03_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */
-#define KN03_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
-#define KN03_IO_INR_RTC 5 /* DS1287 RTC */
-#define KN03_IO_INR_PSU 4 /* power supply unit warning */
-#define KN03_IO_INR_RES_3 3 /* unused */
-#define KN03_IO_INR_ASC_DATA 2 /* SCSI data ready (for PIO) */
-#define KN03_IO_INR_PBNC 1 /* ~HALT button debouncer */
-#define KN03_IO_INR_PBNO 0 /* HALT button debouncer */
-
-
-/*
- * Memory Control Register bits.
- */
-#define KN03_MCR_RES_16 (0xffff<<16) /* unused */
-#define KN03_MCR_DIAGCHK (1<<15) /* diagn/norml ECC reads */
-#define KN03_MCR_DIAGGEN (1<<14) /* diagn/norml ECC writes */
-#define KN03_MCR_CORRECT (1<<13) /* ECC correct/check */
-#define KN03_MCR_RES_11 (0x3<<12) /* unused */
-#define KN03_MCR_BNK32M (1<<10) /* 32M/8M stride */
-#define KN03_MCR_RES_7 (0x7<<7) /* unused */
-#define KN03_MCR_CHECK (0x7f<<0) /* diagnostic check bits */
-
-/*
- * I/O ASIC System Support Register bits.
- */
-#define KN03_IO_SSR_TXDIS1 (1<<14) /* SCC1 transmit disable */
-#define KN03_IO_SSR_TXDIS0 (1<<13) /* SCC0 transmit disable */
-#define KN03_IO_SSR_RES_12 (1<<12) /* unused */
-
-#define KN03_IO_SSR_LEDS (0xff<<0) /* ~diagnostic LEDs */
-
-#endif /* __ASM_MIPS_DEC_KN03_H */
diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h
deleted file mode 100644
index 56d22dc8803..00000000000
--- a/include/asm-mips/dec/kn05.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * include/asm-mips/dec/kn05.h
- *
- * DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
- * or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
- * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
- * definitions.
- *
- * Copyright (C) 2002, 2003, 2005, 2008 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * WARNING! All this information is pure guesswork based on the
- * ROM. It is provided here in hope it will give someone some
- * food for thought. No documentation for the KN05 nor the KN04
- * module has been located so far.
- */
-#ifndef __ASM_MIPS_DEC_KN05_H
-#define __ASM_MIPS_DEC_KN05_H
-
-#include <asm/dec/ioasic_addrs.h>
-
-/*
- * The oncard MB (Memory Buffer) ASIC provides an additional address
- * decoder. Certain address ranges within the "high" 16 slots are
- * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
- * Others are handled locally. "Low" slots are always passed.
- */
-#define KN4K_SLOT_BASE 0x1fc00000
-
-#define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */
-#define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */
-#define KN4K_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
-#define KN4K_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
-#define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */
-#define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */
-#define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */
-#define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */
-#define KN4K_RES_08 (8*IOASIC_SLOT_SIZE) /* unused? */
-#define KN4K_RES_09 (9*IOASIC_SLOT_SIZE) /* unused? */
-#define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */
-#define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */
-#define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
-#define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */
-#define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */
-#define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */
-
-/*
- * Bits for the MB interrupt register.
- * The register appears read-only.
- */
-#define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */
-#define KN4K_MB_INT_RTC (1<<1) /* RTC? */
-#define KN4K_MB_INT_MT (1<<3) /* I/O ASIC cascade */
-
-/*
- * Bits for the MB control & status register.
- * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware.
- */
-#define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */
-#define KN4K_MB_CSR_F (1<<1) /* ??? */
-#define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */
-#define KN4K_MB_CSR_OD (1<<10) /* ??? */
-#define KN4K_MB_CSR_CP (1<<11) /* ??? */
-#define KN4K_MB_CSR_UNC (1<<12) /* ??? */
-#define KN4K_MB_CSR_IM (1<<13) /* ??? */
-#define KN4K_MB_CSR_NC (1<<14) /* ??? */
-#define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */
-#define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */
-#define KN4K_MB_CSR_FW (1<<21) /* ??? */
-#define KN4K_MB_CSR_W (1<<31) /* ??? */
-
-#endif /* __ASM_MIPS_DEC_KN05_H */
diff --git a/include/asm-mips/dec/kn230.h b/include/asm-mips/dec/kn230.h
deleted file mode 100644
index ff1bf17de8d..00000000000
--- a/include/asm-mips/dec/kn230.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * include/asm-mips/dec/kn230.h
- *
- * DECsystem 5100 (MIPSmate or KN230) definitions.
- *
- * Copyright (C) 2002, 2003 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_MIPS_DEC_KN230_H
-#define __ASM_MIPS_DEC_KN230_H
-
-/*
- * CPU interrupt bits.
- */
-#define KN230_CPU_INR_HALT 6 /* HALT button */
-#define KN230_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */
-#define KN230_CPU_INR_RTC 4 /* DS1287 RTC */
-#define KN230_CPU_INR_SII 3 /* SII (DC7061) SCSI */
-#define KN230_CPU_INR_LANCE 3 /* LANCE (Am7990) Ethernet */
-#define KN230_CPU_INR_DZ11 2 /* DZ11 (DC7085) serial */
-
-#endif /* __ASM_MIPS_DEC_KN230_H */
diff --git a/include/asm-mips/dec/machtype.h b/include/asm-mips/dec/machtype.h
deleted file mode 100644
index a6ecdebc430..00000000000
--- a/include/asm-mips/dec/machtype.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Various machine type macros
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 1998, 2000 Harald Koerfgen
- */
-
-#ifndef __ASM_DEC_MACHTYPE_H
-#define __ASM_DEC_MACHTYPE_H
-
-#include <asm/bootinfo.h>
-
-#define TURBOCHANNEL (mips_machtype == MACH_DS5000_200 || \
- mips_machtype == MACH_DS5000_1XX || \
- mips_machtype == MACH_DS5000_XX || \
- mips_machtype == MACH_DS5000_2X0 || \
- mips_machtype == MACH_DS5900)
-
-#define IOASIC (mips_machtype == MACH_DS5000_1XX || \
- mips_machtype == MACH_DS5000_XX || \
- mips_machtype == MACH_DS5000_2X0 || \
- mips_machtype == MACH_DS5900)
-
-#endif
diff --git a/include/asm-mips/dec/prom.h b/include/asm-mips/dec/prom.h
deleted file mode 100644
index b9c8203688d..00000000000
--- a/include/asm-mips/dec/prom.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * include/asm-mips/dec/prom.h
- *
- * DECstation PROM interface.
- *
- * Copyright (C) 2002 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * Based on arch/mips/dec/prom/prom.h by the Anonymous.
- */
-#ifndef _ASM_DEC_PROM_H
-#define _ASM_DEC_PROM_H
-
-#include <linux/types.h>
-
-#include <asm/addrspace.h>
-
-/*
- * PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's.
- * Many of these will work for MIPSen as well!
- */
-#define VEC_RESET (u64 *)CKSEG1ADDR(0x1fc00000)
- /* Prom base address */
-
-#define PMAX_PROM_ENTRY(x) (VEC_RESET + (x)) /* Prom jump table */
-
-#define PMAX_PROM_HALT PMAX_PROM_ENTRY(2) /* valid on MIPSen */
-#define PMAX_PROM_AUTOBOOT PMAX_PROM_ENTRY(5) /* valid on MIPSen */
-#define PMAX_PROM_OPEN PMAX_PROM_ENTRY(6)
-#define PMAX_PROM_READ PMAX_PROM_ENTRY(7)
-#define PMAX_PROM_CLOSE PMAX_PROM_ENTRY(10)
-#define PMAX_PROM_LSEEK PMAX_PROM_ENTRY(11)
-#define PMAX_PROM_GETCHAR PMAX_PROM_ENTRY(12)
-#define PMAX_PROM_PUTCHAR PMAX_PROM_ENTRY(13) /* 12 on MIPSen */
-#define PMAX_PROM_GETS PMAX_PROM_ENTRY(15)
-#define PMAX_PROM_PRINTF PMAX_PROM_ENTRY(17)
-#define PMAX_PROM_GETENV PMAX_PROM_ENTRY(33) /* valid on MIPSen */
-
-
-/*
- * Magic number indicating REX PROM available on DECstation. Found in
- * register a2 on transfer of control to program from PROM.
- */
-#define REX_PROM_MAGIC 0x30464354
-
-#ifdef CONFIG_64BIT
-
-#define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */
-
-#else /* !CONFIG_64BIT */
-
-#define prom_is_rex(magic) ((magic) == REX_PROM_MAGIC)
-
-#endif /* !CONFIG_64BIT */
-
-
-/*
- * 3MIN/MAXINE PROM entry points for DS5000/1xx's, DS5000/xx's and
- * DS5000/2x0.
- */
-#define REX_PROM_GETBITMAP 0x84/4 /* get mem bitmap */
-#define REX_PROM_GETCHAR 0x24/4 /* getch() */
-#define REX_PROM_GETENV 0x64/4 /* get env. variable */
-#define REX_PROM_GETSYSID 0x80/4 /* get system id */
-#define REX_PROM_GETTCINFO 0xa4/4
-#define REX_PROM_PRINTF 0x30/4 /* printf() */
-#define REX_PROM_SLOTADDR 0x6c/4 /* slotaddr */
-#define REX_PROM_BOOTINIT 0x54/4 /* open() */
-#define REX_PROM_BOOTREAD 0x58/4 /* read() */
-#define REX_PROM_CLEARCACHE 0x7c/4
-
-
-/*
- * Used by rex_getbitmap().
- */
-typedef struct {
- int pagesize;
- unsigned char bitmap[0];
-} memmap;
-
-
-/*
- * Function pointers as read from a PROM's callback vector.
- */
-extern int (*__rex_bootinit)(void);
-extern int (*__rex_bootread)(void);
-extern int (*__rex_getbitmap)(memmap *);
-extern unsigned long *(*__rex_slot_address)(int);
-extern void *(*__rex_gettcinfo)(void);
-extern int (*__rex_getsysid)(void);
-extern void (*__rex_clear_cache)(void);
-
-extern int (*__prom_getchar)(void);
-extern char *(*__prom_getenv)(char *);
-extern int (*__prom_printf)(char *, ...);
-
-extern int (*__pmax_open)(char*, int);
-extern int (*__pmax_lseek)(int, long, int);
-extern int (*__pmax_read)(int, void *, int);
-extern int (*__pmax_close)(int);
-
-
-#ifdef CONFIG_64BIT
-
-/*
- * On MIPS64 we have to call PROM functions via a helper
- * dispatcher to accomodate ABI incompatibilities.
- */
-#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \
- __asm__(#fun " = call_o32")
-
-int __DEC_PROM_O32(_rex_bootinit, (int (*)(void)));
-int __DEC_PROM_O32(_rex_bootread, (int (*)(void)));
-int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), memmap *));
-unsigned long *__DEC_PROM_O32(_rex_slot_address,
- (unsigned long *(*)(int), int));
-void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void)));
-int __DEC_PROM_O32(_rex_getsysid, (int (*)(void)));
-void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void)));
-
-int __DEC_PROM_O32(_prom_getchar, (int (*)(void)));
-char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), char *));
-int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), char *, ...));
-
-
-#define rex_bootinit() _rex_bootinit(__rex_bootinit)
-#define rex_bootread() _rex_bootread(__rex_bootread)
-#define rex_getbitmap(x) _rex_getbitmap(__rex_getbitmap, x)
-#define rex_slot_address(x) _rex_slot_address(__rex_slot_address, x)
-#define rex_gettcinfo() _rex_gettcinfo(__rex_gettcinfo)
-#define rex_getsysid() _rex_getsysid(__rex_getsysid)
-#define rex_clear_cache() _rex_clear_cache(__rex_clear_cache)
-
-#define prom_getchar() _prom_getchar(__prom_getchar)
-#define prom_getenv(x) _prom_getenv(__prom_getenv, x)
-#define prom_printf(x...) _prom_printf(__prom_printf, x)
-
-#else /* !CONFIG_64BIT */
-
-/*
- * On plain MIPS we just call PROM functions directly.
- */
-#define rex_bootinit __rex_bootinit
-#define rex_bootread __rex_bootread
-#define rex_getbitmap __rex_getbitmap
-#define rex_slot_address __rex_slot_address
-#define rex_gettcinfo __rex_gettcinfo
-#define rex_getsysid __rex_getsysid
-#define rex_clear_cache __rex_clear_cache
-
-#define prom_getchar __prom_getchar
-#define prom_getenv __prom_getenv
-#define prom_printf __prom_printf
-
-#define pmax_open __pmax_open
-#define pmax_lseek __pmax_lseek
-#define pmax_read __pmax_read
-#define pmax_close __pmax_close
-
-#endif /* !CONFIG_64BIT */
-
-
-extern void prom_meminit(u32);
-extern void prom_identify_arch(u32);
-extern void prom_init_cmdline(s32, s32 *, u32);
-
-extern void register_prom_console(void);
-extern void unregister_prom_console(void);
-
-#endif /* _ASM_DEC_PROM_H */
diff --git a/include/asm-mips/dec/system.h b/include/asm-mips/dec/system.h
deleted file mode 100644
index b2afaccd683..00000000000
--- a/include/asm-mips/dec/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * include/asm-mips/dec/system.h
- *
- * Generic DECstation/DECsystem bits.
- *
- * Copyright (C) 2005, 2006 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_DEC_SYSTEM_H
-#define __ASM_DEC_SYSTEM_H
-
-extern unsigned long dec_kn_slot_base, dec_kn_slot_size;
-extern int dec_tc_bus;
-
-#endif /* __ASM_DEC_SYSTEM_H */
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
deleted file mode 100644
index b0bccd2c4ed..00000000000
--- a/include/asm-mips/delay.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 by Waldorf Electronics
- * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2007 Maciej W. Rozycki
- */
-#ifndef _ASM_DELAY_H
-#define _ASM_DELAY_H
-
-#include <linux/param.h>
-#include <linux/smp.h>
-
-#include <asm/compiler.h>
-#include <asm/war.h>
-
-static inline void __delay(unsigned long loops)
-{
- if (sizeof(long) == 4)
- __asm__ __volatile__ (
- " .set noreorder \n"
- " .align 3 \n"
- "1: bnez %0, 1b \n"
- " subu %0, 1 \n"
- " .set reorder \n"
- : "=r" (loops)
- : "0" (loops));
- else if (sizeof(long) == 8 && !DADDI_WAR)
- __asm__ __volatile__ (
- " .set noreorder \n"
- " .align 3 \n"
- "1: bnez %0, 1b \n"
- " dsubu %0, 1 \n"
- " .set reorder \n"
- : "=r" (loops)
- : "0" (loops));
- else if (sizeof(long) == 8 && DADDI_WAR)
- __asm__ __volatile__ (
- " .set noreorder \n"
- " .align 3 \n"
- "1: bnez %0, 1b \n"
- " dsubu %0, %2 \n"
- " .set reorder \n"
- : "=r" (loops)
- : "0" (loops), "r" (1));
-}
-
-
-/*
- * Division by multiplication: you don't have to worry about
- * loss of precision.
- *
- * Use only for very small delays ( < 1 msec). Should probably use a
- * lookup table, really, as the multiplications take much too long with
- * short delays. This is a "reasonable" implementation, though (and the
- * first constant multiplications gets optimized away if the delay is
- * a constant)
- */
-
-static inline void __udelay(unsigned long usecs, unsigned long lpj)
-{
- unsigned long hi, lo;
-
- /*
- * The rates of 128 is rounded wrongly by the catchall case
- * for 64-bit. Excessive precission? Probably ...
- */
-#if defined(CONFIG_64BIT) && (HZ == 128)
- usecs *= 0x0008637bd05af6c7UL; /* 2**64 / (1000000 / HZ) */
-#elif defined(CONFIG_64BIT)
- usecs *= (0x8000000000000000UL / (500000 / HZ));
-#else /* 32-bit junk follows here */
- usecs *= (unsigned long) (((0x8000000000000000ULL / (500000 / HZ)) +
- 0x80000000ULL) >> 32);
-#endif
-
- if (sizeof(long) == 4)
- __asm__("multu\t%2, %3"
- : "=h" (usecs), "=l" (lo)
- : "r" (usecs), "r" (lpj)
- : GCC_REG_ACCUM);
- else if (sizeof(long) == 8 && !R4000_WAR)
- __asm__("dmultu\t%2, %3"
- : "=h" (usecs), "=l" (lo)
- : "r" (usecs), "r" (lpj)
- : GCC_REG_ACCUM);
- else if (sizeof(long) == 8 && R4000_WAR)
- __asm__("dmultu\t%3, %4\n\tmfhi\t%0"
- : "=r" (usecs), "=h" (hi), "=l" (lo)
- : "r" (usecs), "r" (lpj)
- : GCC_REG_ACCUM);
-
- __delay(usecs);
-}
-
-#define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val
-
-#define udelay(usecs) __udelay((usecs), __udelay_val)
-
-/* make sure "usecs *= ..." in udelay do not overflow. */
-#if HZ >= 1000
-#define MAX_UDELAY_MS 1
-#elif HZ <= 200
-#define MAX_UDELAY_MS 5
-#else
-#define MAX_UDELAY_MS (1000 / HZ)
-#endif
-
-#endif /* _ASM_DELAY_H */
diff --git a/include/asm-mips/device.h b/include/asm-mips/device.h
deleted file mode 100644
index d8f9872b0e2..00000000000
--- a/include/asm-mips/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#include <asm-generic/device.h>
-
diff --git a/include/asm-mips/div64.h b/include/asm-mips/div64.h
deleted file mode 100644
index d1d699105c1..00000000000
--- a/include/asm-mips/div64.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright (C) 2000, 2004 Maciej W. Rozycki
- * Copyright (C) 2003, 07 Ralf Baechle (ralf@linux-mips.org)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef _ASM_DIV64_H
-#define _ASM_DIV64_H
-
-#include <linux/types.h>
-
-#if (_MIPS_SZLONG == 32)
-
-#include <asm/compiler.h>
-
-/*
- * No traps on overflows for any of these...
- */
-
-#define do_div64_32(res, high, low, base) ({ \
- unsigned long __quot32, __mod32; \
- unsigned long __cf, __tmp, __tmp2, __i; \
- \
- __asm__(".set push\n\t" \
- ".set noat\n\t" \
- ".set noreorder\n\t" \
- "move %2, $0\n\t" \
- "move %3, $0\n\t" \
- "b 1f\n\t" \
- " li %4, 0x21\n" \
- "0:\n\t" \
- "sll $1, %0, 0x1\n\t" \
- "srl %3, %0, 0x1f\n\t" \
- "or %0, $1, %5\n\t" \
- "sll %1, %1, 0x1\n\t" \
- "sll %2, %2, 0x1\n" \
- "1:\n\t" \
- "bnez %3, 2f\n\t" \
- " sltu %5, %0, %z6\n\t" \
- "bnez %5, 3f\n" \
- "2:\n\t" \
- " addiu %4, %4, -1\n\t" \
- "subu %0, %0, %z6\n\t" \
- "addiu %2, %2, 1\n" \
- "3:\n\t" \
- "bnez %4, 0b\n\t" \
- " srl %5, %1, 0x1f\n\t" \
- ".set pop" \
- : "=&r" (__mod32), "=&r" (__tmp), \
- "=&r" (__quot32), "=&r" (__cf), \
- "=&r" (__i), "=&r" (__tmp2) \
- : "Jr" (base), "0" (high), "1" (low)); \
- \
- (res) = __quot32; \
- __mod32; })
-
-#define do_div(n, base) ({ \
- unsigned long long __quot; \
- unsigned long __mod; \
- unsigned long long __div; \
- unsigned long __upper, __low, __high, __base; \
- \
- __div = (n); \
- __base = (base); \
- \
- __high = __div >> 32; \
- __low = __div; \
- __upper = __high; \
- \
- if (__high) \
- __asm__("divu $0, %z2, %z3" \
- : "=h" (__upper), "=l" (__high) \
- : "Jr" (__high), "Jr" (__base) \
- : GCC_REG_ACCUM); \
- \
- __mod = do_div64_32(__low, __upper, __low, __base); \
- \
- __quot = __high; \
- __quot = __quot << 32 | __low; \
- (n) = __quot; \
- __mod; })
-
-#endif /* (_MIPS_SZLONG == 32) */
-
-#if (_MIPS_SZLONG == 64)
-
-/*
- * Hey, we're already 64-bit, no
- * need to play games..
- */
-#define do_div(n, base) ({ \
- unsigned long __quot; \
- unsigned int __mod; \
- unsigned long __div; \
- unsigned int __base; \
- \
- __div = (n); \
- __base = (base); \
- \
- __mod = __div % __base; \
- __quot = __div / __base; \
- \
- (n) = __quot; \
- __mod; })
-
-#endif /* (_MIPS_SZLONG == 64) */
-
-#endif /* _ASM_DIV64_H */
diff --git a/include/asm-mips/dma-mapping.h b/include/asm-mips/dma-mapping.h
deleted file mode 100644
index c64afb40cd0..00000000000
--- a/include/asm-mips/dma-mapping.h
+++ /dev/null
@@ -1,81 +0,0 @@
-#ifndef _ASM_DMA_MAPPING_H
-#define _ASM_DMA_MAPPING_H
-
-#include <asm/scatterlist.h>
-#include <asm/cache.h>
-
-void *dma_alloc_noncoherent(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t flag);
-
-void dma_free_noncoherent(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_handle);
-
-void *dma_alloc_coherent(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t flag);
-
-void dma_free_coherent(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_handle);
-
-extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
- enum dma_data_direction direction);
-extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
- size_t size, enum dma_data_direction direction);
-extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
- enum dma_data_direction direction);
-extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size, enum dma_data_direction direction);
-extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
- size_t size, enum dma_data_direction direction);
-extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
- int nhwentries, enum dma_data_direction direction);
-extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
- size_t size, enum dma_data_direction direction);
-extern void dma_sync_single_for_device(struct device *dev,
- dma_addr_t dma_handle, size_t size, enum dma_data_direction direction);
-extern void dma_sync_single_range_for_cpu(struct device *dev,
- dma_addr_t dma_handle, unsigned long offset, size_t size,
- enum dma_data_direction direction);
-extern void dma_sync_single_range_for_device(struct device *dev,
- dma_addr_t dma_handle, unsigned long offset, size_t size,
- enum dma_data_direction direction);
-extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
- int nelems, enum dma_data_direction direction);
-extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
- int nelems, enum dma_data_direction direction);
-extern int dma_mapping_error(struct device *dev, dma_addr_t dma_addr);
-extern int dma_supported(struct device *dev, u64 mask);
-
-static inline int
-dma_set_mask(struct device *dev, u64 mask)
-{
- if(!dev->dma_mask || !dma_supported(dev, mask))
- return -EIO;
-
- *dev->dma_mask = mask;
-
- return 0;
-}
-
-static inline int
-dma_get_cache_alignment(void)
-{
- /* XXX Largest on any MIPS */
- return 128;
-}
-
-extern int dma_is_consistent(struct device *dev, dma_addr_t dma_addr);
-
-extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
- enum dma_data_direction direction);
-
-#if 0
-#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
-
-extern int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
- dma_addr_t device_addr, size_t size, int flags);
-extern void dma_release_declared_memory(struct device *dev);
-extern void * dma_mark_declared_memory_occupied(struct device *dev,
- dma_addr_t device_addr, size_t size);
-#endif
-
-#endif /* _ASM_DMA_MAPPING_H */
diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h
deleted file mode 100644
index 1353c81065d..00000000000
--- a/include/asm-mips/dma.h
+++ /dev/null
@@ -1,315 +0,0 @@
-/*
- * linux/include/asm/dma.h: Defines for using and allocating dma channels.
- * Written by Hennus Bergman, 1992.
- * High DMA channel support & info by Hannu Savolainen
- * and John Boyd, Nov. 1992.
- *
- * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
- * and can only be used for expansion cards. Onboard DMA controllers, such
- * as the R4030 on Jazz boards behave totally different!
- */
-
-#ifndef _ASM_DMA_H
-#define _ASM_DMA_H
-
-#include <asm/io.h> /* need byte IO */
-#include <linux/spinlock.h> /* And spinlocks */
-#include <linux/delay.h>
-#include <asm/system.h>
-
-
-#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
-#define dma_outb outb_p
-#else
-#define dma_outb outb
-#endif
-
-#define dma_inb inb
-
-/*
- * NOTES about DMA transfers:
- *
- * controller 1: channels 0-3, byte operations, ports 00-1F
- * controller 2: channels 4-7, word operations, ports C0-DF
- *
- * - ALL registers are 8 bits only, regardless of transfer size
- * - channel 4 is not used - cascades 1 into 2.
- * - channels 0-3 are byte - addresses/counts are for physical bytes
- * - channels 5-7 are word - addresses/counts are for physical words
- * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
- * - transfer count loaded to registers is 1 less than actual count
- * - controller 2 offsets are all even (2x offsets for controller 1)
- * - page registers for 5-7 don't use data bit 0, represent 128K pages
- * - page registers for 0-3 use bit 0, represent 64K pages
- *
- * DMA transfers are limited to the lower 16MB of _physical_ memory.
- * Note that addresses loaded into registers must be _physical_ addresses,
- * not logical addresses (which may differ if paging is active).
- *
- * Address mapping for channels 0-3:
- *
- * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
- * | ... | | ... | | ... |
- * | ... | | ... | | ... |
- * | ... | | ... | | ... |
- * P7 ... P0 A7 ... A0 A7 ... A0
- * | Page | Addr MSB | Addr LSB | (DMA registers)
- *
- * Address mapping for channels 5-7:
- *
- * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
- * | ... | \ \ ... \ \ \ ... \ \
- * | ... | \ \ ... \ \ \ ... \ (not used)
- * | ... | \ \ ... \ \ \ ... \
- * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
- * | Page | Addr MSB | Addr LSB | (DMA registers)
- *
- * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
- * and counts _must_ be word-alig