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authorSamuel Ortiz <sameo@openedhand.com>2008-06-20 11:09:51 +0200
committerSamuel Ortiz <samuel@sortiz.org>2008-07-20 19:55:00 +0200
commit3b26bf17226f66bfd6cd4e36ac81f83fe994043a (patch)
treef619c0570a31cbb0cdd2e3c148bd66bb962b7b74 /drivers/mfd
parent1effe5bc6cfbac4506d7944d68dadbd29ad62645 (diff)
mfd: New asic3 gpio configuration code
The ASIC3 GPIO configuration code is a bit obscure and hardly readable. This patch changes it so that it is now more readable and understandable, by being more explicit. Signed-off-by: Samuel Ortiz <sameo@openedhand.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Diffstat (limited to 'drivers/mfd')
-rw-r--r--drivers/mfd/asic3.c99
1 files changed, 43 insertions, 56 deletions
diff --git a/drivers/mfd/asic3.c b/drivers/mfd/asic3.c
index dfee0a2ba16..36b46ded1bf 100644
--- a/drivers/mfd/asic3.c
+++ b/drivers/mfd/asic3.c
@@ -465,69 +465,54 @@ static void asic3_gpio_set(struct gpio_chip *chip,
return;
}
-static inline u32 asic3_get_gpio(struct asic3 *asic, unsigned int base,
- unsigned int function)
+static int asic3_gpio_probe(struct platform_device *pdev,
+ u16 *gpio_config, int num)
{
- return asic3_read_register(asic, base + function);
-}
-
-static void asic3_set_gpio(struct asic3 *asic, unsigned int base,
- unsigned int function, u32 bits, u32 val)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&asic->lock, flags);
- val |= (asic3_read_register(asic, base + function) & ~bits);
-
- asic3_write_register(asic, base + function, val);
- spin_unlock_irqrestore(&asic->lock, flags);
-}
-
-#define asic3_set_gpio_a(asic, fn, bits, val) \
- asic3_set_gpio(asic, ASIC3_GPIO_A_Base, ASIC3_GPIO_##fn, bits, val)
-#define asic3_set_gpio_b(asic, fn, bits, val) \
- asic3_set_gpio(asic, ASIC3_GPIO_B_Base, ASIC3_GPIO_##fn, bits, val)
-#define asic3_set_gpio_c(asic, fn, bits, val) \
- asic3_set_gpio(asic, ASIC3_GPIO_C_Base, ASIC3_GPIO_##fn, bits, val)
-#define asic3_set_gpio_d(asic, fn, bits, val) \
- asic3_set_gpio(asic, ASIC3_GPIO_D_Base, ASIC3_GPIO_##fn, bits, val)
-
-#define asic3_set_gpio_banks(asic, fn, bits, pdata, field) \
- do { \
- asic3_set_gpio_a((asic), fn, (bits), (pdata)->gpio_a.field); \
- asic3_set_gpio_b((asic), fn, (bits), (pdata)->gpio_b.field); \
- asic3_set_gpio_c((asic), fn, (bits), (pdata)->gpio_c.field); \
- asic3_set_gpio_d((asic), fn, (bits), (pdata)->gpio_d.field); \
- } while (0)
-
-
-static int asic3_gpio_probe(struct platform_device *pdev)
-{
- struct asic3_platform_data *pdata = pdev->dev.platform_data;
struct asic3 *asic = platform_get_drvdata(pdev);
+ u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
+ u16 out_reg[ASIC3_NUM_GPIO_BANKS];
+ u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
+ int i;
+ memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS);
+ memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS);
+ memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS);
+
+ /* Enable all GPIOs */
asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, Mask), 0xffff);
asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, Mask), 0xffff);
asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, Mask), 0xffff);
asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, Mask), 0xffff);
- asic3_set_gpio_a(asic, SleepMask, 0xffff, 0xffff);
- asic3_set_gpio_b(asic, SleepMask, 0xffff, 0xffff);
- asic3_set_gpio_c(asic, SleepMask, 0xffff, 0xffff);
- asic3_set_gpio_d(asic, SleepMask, 0xffff, 0xffff);
-
- if (pdata) {
- asic3_set_gpio_banks(asic, Out, 0xffff, pdata, init);
- asic3_set_gpio_banks(asic, Direction, 0xffff, pdata, dir);
- asic3_set_gpio_banks(asic, SleepMask, 0xffff, pdata,
- sleep_mask);
- asic3_set_gpio_banks(asic, SleepOut, 0xffff, pdata, sleep_out);
- asic3_set_gpio_banks(asic, BattFaultOut, 0xffff, pdata,
- batt_fault_out);
- asic3_set_gpio_banks(asic, SleepConf, 0xffff, pdata,
- sleep_conf);
- asic3_set_gpio_banks(asic, AltFunction, 0xffff, pdata,
- alt_function);
+ for (i = 0; i < num; i++) {
+ u8 alt, pin, dir, init, bank_num, bit_num;
+ u16 config = gpio_config[i];
+
+ pin = ASIC3_CONFIG_GPIO_PIN(config);
+ alt = ASIC3_CONFIG_GPIO_ALT(config);
+ dir = ASIC3_CONFIG_GPIO_DIR(config);
+ init = ASIC3_CONFIG_GPIO_INIT(config);
+
+ bank_num = ASIC3_GPIO_TO_BANK(pin);
+ bit_num = ASIC3_GPIO_TO_BIT(pin);
+
+ alt_reg[bank_num] |= (alt << bit_num);
+ out_reg[bank_num] |= (init << bit_num);
+ dir_reg[bank_num] |= (dir << bit_num);
+ }
+
+ for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
+ asic3_write_register(asic,
+ ASIC3_BANK_TO_BASE(i) +
+ ASIC3_GPIO_Direction,
+ dir_reg[i]);
+ asic3_write_register(asic,
+ ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_Out,
+ out_reg[i]);
+ asic3_write_register(asic,
+ ASIC3_BANK_TO_BASE(i) +
+ ASIC3_GPIO_AltFunction,
+ alt_reg[i]);
}
return gpiochip_add(&asic->gpio);
@@ -598,7 +583,9 @@ static int asic3_probe(struct platform_device *pdev)
asic->gpio.direction_input = asic3_gpio_direction_input;
asic->gpio.direction_output = asic3_gpio_direction_output;
- ret = asic3_gpio_probe(pdev);
+ ret = asic3_gpio_probe(pdev,
+ pdata->gpio_config,
+ pdata->gpio_config_num);
if (ret < 0) {
printk(KERN_ERR "GPIO probe failed\n");
goto out_irq;