path: root/arch/ia64/dig
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authorRuss Anderson <rja@sgi.com>2006-03-24 09:49:52 -0800
committerTony Luck <tony.luck@intel.com>2006-03-24 09:49:52 -0800
commitd2a28ad9fa7bf16761d070d8a3338375e1574b32 (patch)
tree9da2c18c91a4ee12fa6a9b2d23dcb55d13dd0ca8 /arch/ia64/dig
parenta5b00bb4fe60796c791238cf5653b82110031c93 (diff)
[IA64] MCA recovery: kernel context recovery table
Memory errors encountered by user applications may surface when the CPU is running in kernel context. The current code will not attempt recovery if the MCA surfaces in kernel context (privilage mode 0). This patch adds a check for cases where the user initiated the load that surfaces in kernel interrupt code. An example is a user process lauching a load from memory and the data in memory had bad ECC. Before the bad data gets to the CPU register, and interrupt comes in. The code jumps to the IVT interrupt entry point and begins execution in kernel context. The process of saving the user registers (SAVE_REST) causes the bad data to be loaded into a CPU register, triggering the MCA. The MCA surfaces in kernel context, even though the load was initiated from user context. As suggested by David and Tony, this patch uses an exception table like approach, puting the tagged recovery addresses in a searchable table. One difference from the exception table is that MCAs do not surface in precise places (such as with a TLB miss), so instead of tagging specific instructions, address ranges are registers. A single macro is used to do the tagging, with the input parameter being the label of the starting address and the macro being the ending address. This limits clutter in the code. This patch only tags one spot, the interrupt ivt entry. Testing showed that spot to be a "heavy hitter" with MCAs surfacing while saving user registers. Other spots can be added as needed by adding a single macro. Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck <tony.luck@intel.com>
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