diff options
| author | Anson Huang <b20788@freescale.com> | 2011-12-30 14:55:14 +0800 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2011-12-30 14:58:46 +0800 |
| commit | 8abc99e4745fe1861f9510811bb4470f689b5b41 (patch) | |
| tree | a3d37a4c2ed567496bddde08c0e32a91ff651156 | |
| parent | 1703ca7108c66b9d88d66b1e730447553bc1b161 (diff) | |
ENGR00171087 [MX6]Need to add L1 Icache invalidate
As there might be dirty data line on any core of MX6
SOC when power on or reset, we need to do L1 I-cache
invalidation in the resume process and start up
process for all cores.
This is very important for us, as not all of the hardware
will do cache invalidation during power on or reset, so
we need to do the invalidation for all cache(L1, L2,
I and D) before first time enabling. Please keep in mind.
Signed-off-by: Anson Huang <b20788@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx6/headsmp.S | 3 | ||||
| -rw-r--r-- | arch/arm/mach-mx6/mx6q_suspend.S | 4 |
2 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/headsmp.S b/arch/arm/mach-mx6/headsmp.S index 3adc6e8a14d..d9fca6a575a 100644 --- a/arch/arm/mach-mx6/headsmp.S +++ b/arch/arm/mach-mx6/headsmp.S @@ -115,6 +115,9 @@ ENTRY(mx6_secondary_startup) offset is passed from GPR parameter, currently we store it at r8, future code change should avoid using r8. *****************************************************************************/ + /* Invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 @ Invalidate I-Cache /* count the offset value and store it in r8 */ ldr r3, =mx6_secondary_startup mrc p15, 0, r0, c0, c0, 5 diff --git a/arch/arm/mach-mx6/mx6q_suspend.S b/arch/arm/mach-mx6/mx6q_suspend.S index 31bccf15e29..29d5a76e86c 100644 --- a/arch/arm/mach-mx6/mx6q_suspend.S +++ b/arch/arm/mach-mx6/mx6q_suspend.S @@ -460,8 +460,10 @@ when SOC exit stop mode, arm core restart from here, currently are running with MMU off. ****************************************************************/ resume: + /* Invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 @ Invalidate I-Cache ldr r0, =SRC_BASE_ADDR - mov r1, #0x0 str r1, [r0, #SRC_GPR1_OFFSET] /* clear SRC_GPR1 */ ldr r0, [r0, #SRC_GPR2_OFFSET] |