diff options
| author | RichardZhu <richard.zhu@linaro.org> | 2011-11-16 11:28:50 +0800 |
|---|---|---|
| committer | Eric Miao <eric.miao@linaro.org> | 2011-12-02 14:41:52 +0800 |
| commit | dfa3d1a3ea9fc48c6e542bb21a8fdc570309d21c (patch) | |
| tree | 594be1be22346fd1e967502fe3b2eefcaa337e7d | |
| parent | 898c020c8fc6debde972cd73906164f95fd879b1 (diff) | |
mmc: sdhci-esdhc-imx: workaround for TC intr coming ealier than DMA intri
On mx6, if TC interrupt bit is set but DMA interrupt bit is clear,
read status register again in case DMA interrupt will come in next
time cycle.
Signed-off-by: Tony Lin <tony.lin@freescale.com>
Signed-off-by: RichardZhu <richard.zhu@linaro.org>
| -rw-r--r-- | drivers/mmc/host/sdhci-esdhc-imx.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 4b976f00ea8..a3dd778ab0a 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -170,6 +170,19 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) } if (unlikely(reg == SDHCI_INT_STATUS)) { + if (is_imx6q_usdhc(imx_data)) { + /* + * on mx6q, there is low possibility that + * DATA END interrupt comes ealier than DMA + * END interrupt which is conflict with standard + * host controller spec. In this case, read the + * status register again will workaround this issue. + */ + if ((val & SDHCI_INT_DATA_END) && \ + !(val & SDHCI_INT_DMA_END)) + val = readl(host->ioaddr + reg); + } + if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) { val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR; val |= SDHCI_INT_ADMA_ERROR; |