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authorNicolas Pitre <nicolas.pitre@linaro.org>2011-04-25 15:58:38 -0400
committerNicolas Pitre <nicolas.pitre@linaro.org>2011-04-25 15:58:38 -0400
commitca1841de3a426de8cfac6ca61f0f54e6283d0653 (patch)
treefc9ca7db1f9ada5301b3684ae75cfe8470071425 /arch/x86/kernel
parentc5325bf1df96152c969b44cae2b8131be5621c47 (diff)
parent8fd62c82872a5a721c9fb0071ca0f7a49c1732e4 (diff)
Merge commit 'v2.6.38.4' into linaro-2.6.38
Diffstat (limited to 'arch/x86/kernel')
-rw-r--r--arch/x86/kernel/cpu/amd.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 7c7bedb83c5..a2b9c7d4132 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -594,6 +594,29 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
}
}
#endif
+
+ /* As a rule processors have APIC timer running in deep C states */
+ if (c->x86 >= 0xf && !cpu_has_amd_erratum(amd_erratum_400))
+ set_cpu_cap(c, X86_FEATURE_ARAT);
+
+ /*
+ * Disable GART TLB Walk Errors on Fam10h. We do this here
+ * because this is always needed when GART is enabled, even in a
+ * kernel which has no MCE support built in.
+ */
+ if (c->x86 == 0x10) {
+ /*
+ * BIOS should disable GartTlbWlk Errors themself. If
+ * it doesn't do it here as suggested by the BKDG.
+ *
+ * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
+ */
+ u64 mask;
+
+ rdmsrl(MSR_AMD64_MCx_MASK(4), mask);
+ mask |= (1 << 10);
+ wrmsrl(MSR_AMD64_MCx_MASK(4), mask);
+ }
}
#ifdef CONFIG_X86_32