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authorNicolas Pitre <nicolas.pitre@linaro.org>2011-04-25 15:58:38 -0400
committerNicolas Pitre <nicolas.pitre@linaro.org>2011-04-25 15:58:38 -0400
commitca1841de3a426de8cfac6ca61f0f54e6283d0653 (patch)
treefc9ca7db1f9ada5301b3684ae75cfe8470071425 /arch/x86/include
parentc5325bf1df96152c969b44cae2b8131be5621c47 (diff)
parent8fd62c82872a5a721c9fb0071ca0f7a49c1732e4 (diff)
downloadlinux-linaro-android-ca1841de3a426de8cfac6ca61f0f54e6283d0653.tar.gz
Merge commit 'v2.6.38.4' into linaro-2.6.38
Diffstat (limited to 'arch/x86/include')
-rw-r--r--arch/x86/include/asm/msr-index.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 43a18c77676..99b402c6a91 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -92,11 +92,15 @@
#define MSR_IA32_MC0_ADDR 0x00000402
#define MSR_IA32_MC0_MISC 0x00000403
+#define MSR_AMD64_MC0_MASK 0xc0010044
+
#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
+#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
+
/* These are consecutive and not in the normal 4er MCE bank block */
#define MSR_IA32_MC0_CTL2 0x00000280
#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))