From 452e8e72ada5141f58008a902e1d4be42ce15abb Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 8 Aug 2005 00:47:14 +0200 Subject: Fix build problems for PM856 Board --- include/configs/PM854.h | 2 +- include/configs/PM856.h | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 07e3f06ac..89b5f3635 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -49,7 +49,7 @@ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF /* diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 5dae1b6b0..4d834878e 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -39,6 +39,7 @@ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_MPC8560 1 /* MPC8560 specific */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ #define CONFIG_PM856 1 /* PM856 board specific */ #define CONFIG_PCI @@ -48,6 +49,7 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF /* @@ -253,7 +255,9 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" #define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 @@ -262,7 +266,7 @@ #endif /* CONFIG_TSEC_ENET */ -#define CONFIG_ETHPRIME "ENET0" +#define CONFIG_ETHPRIME "TSEC0" #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ #undef CONFIG_ETHER_NONE /* define if ether on something else */ -- cgit v1.2.3