From 71919cf15337c62b9ab389875a6a0855f0ed4461 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Mon, 2 Apr 2012 02:57:54 +0000 Subject: MIPS: board.c: fix init of flash data in bd_info Boards with CONFIG_SYS_NO_FLASH should not forced to define CONFIG_SYS_FLASH_BASE. In this case the flash data in bd_info should be initialized with 0 like the other archs do. Signed-off-by: Daniel Schwierzeck --- arch/mips/lib/board.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c index d998f0e74..38e6e77a3 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c @@ -294,15 +294,19 @@ void board_init_r(gd_t *id, ulong dest_addr) /* configure available FLASH banks */ size = flash_init(); display_flash_config(size); + bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; bd->bi_flashsize = size; -#endif - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; #if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE bd->bi_flashoffset = monitor_flash_len; /* reserved area for U-Boot */ #else bd->bi_flashoffset = 0; #endif +#else + bd->bi_flashstart = 0; + bd->bi_flashsize = 0; + bd->bi_flashoffset = 0; +#endif #ifdef CONFIG_CMD_NAND puts("NAND: "); -- cgit v1.2.3 From 979cfeaf36bf8719d4a1a98f1e8a3e16ef3d1fba Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Mon, 2 Apr 2012 02:57:55 +0000 Subject: MIPS: fix inconsistency in config option for cache operation mode Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to use the new config option in dcache_enable(). Fix this to avoid inconsistencies if someone wants to disable and enable D-caches. Signed-off-by: Daniel Schwierzeck --- arch/mips/cpu/mips32/cache.S | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 5ce0ec45f..e683e8be8 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -30,6 +30,10 @@ #include #include +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + #define RA t8 /* @@ -224,7 +228,7 @@ LEAF(dcache_enable) mfc0 t0, CP0_CONFIG ori t0, CONF_CM_CMASK xori t0, CONF_CM_CMASK - ori t0, CONF_CM_CACHABLE_NONCOHERENT + ori t0, CONFIG_SYS_MIPS_CACHE_MODE mtc0 t0, CP0_CONFIG jr ra END(dcache_enable) -- cgit v1.2.3 From 6cb461b4f1531dbae5c0bae857f649b7943114ec Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Mon, 2 Apr 2012 02:57:56 +0000 Subject: MIPS: fix endianess handling Make endianess of target CPU configurable. Use the new config option for dbau1550_el and pb1000 boards. Adapt linking of standalone applications to pass through endianess options to LD. Build tested with: - ELDK 4 mips_4KC- and mips4KCle - Sourcery CodeBench Lite 2011.03-93 With this patch all 26 MIPS boards can be compiled now in one step by running "MAKEALL -a mips". Signed-off-by: Daniel Schwierzeck --- arch/mips/cpu/mips32/config.mk | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/mips/cpu/mips32/config.mk b/arch/mips/cpu/mips32/config.mk index 4d1b27379..a1cd590a0 100644 --- a/arch/mips/cpu/mips32/config.mk +++ b/arch/mips/cpu/mips32/config.mk @@ -27,14 +27,23 @@ # Note: Toolchains with binutils prior to v2.16 # are no longer supported by U-Boot MIPS tree! # -MIPSFLAGS = -march=mips32r2 +MIPSFLAGS := -march=mips32r2 +# Handle special prefix in ELDK 4.0 toolchain ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) -ENDIANNESS = -EL -else -ENDIANNESS = -EB +ENDIANNESS := -EL endif -MIPSFLAGS += $(ENDIANNESS) +ifdef CONFIG_SYS_LITTLE_ENDIAN +ENDIANNESS := -EL +endif + +ifdef CONFIG_SYS_BIG_ENDIAN +ENDIANNESS := -EB +endif + +# Default to EB if no endianess is configured +ENDIANNESS ?= -EB -PLATFORM_CPPFLAGS += $(MIPSFLAGS) +PLATFORM_CPPFLAGS += $(MIPSFLAGS) $(ENDIANNESS) +PLATFORM_LDFLAGS += $(ENDIANNESS) -- cgit v1.2.3