From 3380a7e653325adb9312f02ed4150c72131b6431 Mon Sep 17 00:00:00 2001 From: Girish K S Date: Sat, 6 Oct 2012 14:16:02 +0900 Subject: arm: exynos: fix issue in clock and pinmux clock: the mmc get clock api return the clock value without dividing the sclk by value of clk_sel register. The divider value calculated in the dw_mmc driver for clk_div is wrong. This patch adds the divider to fix the issue. pinmux: The initialization of the sd_cdn pin was ignored, This patch adds the selection and initialization of the early pin state. Signed-off-by: Girish K S --- arch/arm/cpu/armv7/exynos/clock.c | 31 ++++++++++++++++++++++++------- arch/arm/cpu/armv7/exynos/pinmux.c | 4 ++-- 2 files changed, 26 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index c0180ea87..e496dd479 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -531,7 +531,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index) unsigned int sel; unsigned int ratio; unsigned int pre_ratio; - unsigned int addr; + unsigned int addr, addr_mmc; sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf; @@ -565,6 +565,10 @@ static unsigned long exynos5_get_mmc_clk(int dev_index) uclk = (sclk /(ratio + 1))/(pre_ratio + 1); + /* Actual sclk mmc is available after mmc divider */ + ratio = readl(addr_mmc); + ratio = (ratio >> 24 ) & 0x7; + return uclk; } @@ -576,12 +580,6 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) unsigned int addr; unsigned int val; - /* - * CLK_DIV_FSYS1 - * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24] - * CLK_DIV_FSYS2 - * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] - */ if (dev_index < 2) { addr = (unsigned int)&clk->div_fsys1; } else { @@ -589,6 +587,25 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) dev_index -= 2; } + /* + * CLK_DIV_FSYS1 + * MMC0_RATIO[3:0], MMC1_RATIO[3:0] + * CLK_DIV_FSYS2 + * MMC2_RATIO[3:0], MMC3_RATIO[3:0] + * Bypass the divider ratio and use only pre ratio to select + * the sclk mmc + */ + + val = readl(addr); + val &= ~(0xf << (dev_index * 16)); + writel(val, addr); + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] + */ val = readl(addr); val &= ~(0xff << ((dev_index << 4) + 8)); val |= (div & 0xff) << ((dev_index << 4) + 8); diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 0746878a2..52d6e6766 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -341,12 +341,12 @@ static int exynos5_mmc_config(int peripheral, int flags) s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); } } - for (i = 0; i < 2; i++) { + for (i = 0; i < 2 ; i++) { s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); } - for (i = 3; i <= 6; i++) { + for (i = 2; i <= 6; i++) { s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); -- cgit v1.2.3