From 819833af39a91fa1c1e8252862bbda6f5a602f7b Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 12 Apr 2010 22:28:08 -0500 Subject: Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser --- arch/microblaze/include/asm/asm.h | 98 +++++++ arch/microblaze/include/asm/bitops.h | 392 +++++++++++++++++++++++++ arch/microblaze/include/asm/byteorder.h | 55 ++++ arch/microblaze/include/asm/config.h | 27 ++ arch/microblaze/include/asm/errno.h | 1 + arch/microblaze/include/asm/global_data.h | 61 ++++ arch/microblaze/include/asm/io.h | 163 ++++++++++ arch/microblaze/include/asm/microblaze_intc.h | 43 +++ arch/microblaze/include/asm/microblaze_timer.h | 41 +++ arch/microblaze/include/asm/posix_types.h | 76 +++++ arch/microblaze/include/asm/processor.h | 1 + arch/microblaze/include/asm/ptrace.h | 116 ++++++++ arch/microblaze/include/asm/string.h | 31 ++ arch/microblaze/include/asm/system.h | 161 ++++++++++ arch/microblaze/include/asm/types.h | 60 ++++ arch/microblaze/include/asm/u-boot.h | 48 +++ arch/microblaze/include/asm/unaligned.h | 16 + 17 files changed, 1390 insertions(+) create mode 100644 arch/microblaze/include/asm/asm.h create mode 100644 arch/microblaze/include/asm/bitops.h create mode 100644 arch/microblaze/include/asm/byteorder.h create mode 100644 arch/microblaze/include/asm/config.h create mode 100644 arch/microblaze/include/asm/errno.h create mode 100644 arch/microblaze/include/asm/global_data.h create mode 100644 arch/microblaze/include/asm/io.h create mode 100644 arch/microblaze/include/asm/microblaze_intc.h create mode 100644 arch/microblaze/include/asm/microblaze_timer.h create mode 100644 arch/microblaze/include/asm/posix_types.h create mode 100644 arch/microblaze/include/asm/processor.h create mode 100644 arch/microblaze/include/asm/ptrace.h create mode 100644 arch/microblaze/include/asm/string.h create mode 100644 arch/microblaze/include/asm/system.h create mode 100644 arch/microblaze/include/asm/types.h create mode 100644 arch/microblaze/include/asm/u-boot.h create mode 100644 arch/microblaze/include/asm/unaligned.h (limited to 'arch/microblaze/include/asm') diff --git a/arch/microblaze/include/asm/asm.h b/arch/microblaze/include/asm/asm.h new file mode 100644 index 000000000..deb23e094 --- /dev/null +++ b/arch/microblaze/include/asm/asm.h @@ -0,0 +1,98 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* FSL macros */ +#define NGET(val, fslnum) \ + __asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val)); + +#define GET(val, fslnum) \ + __asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val)); + +#define NCGET(val, fslnum) \ + __asm__ __volatile__ ("ncget %0, rfsl" #fslnum :"=r" (val)); + +#define CGET(val, fslnum) \ + __asm__ __volatile__ ("cget %0, rfsl" #fslnum :"=r" (val)); + +#define NPUT(val, fslnum) \ + __asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val)); + +#define PUT(val, fslnum) \ + __asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val)); + +#define NCPUT(val, fslnum) \ + __asm__ __volatile__ ("ncput %0, rfsl" #fslnum ::"r" (val)); + +#define CPUT(val, fslnum) \ + __asm__ __volatile__ ("cput %0, rfsl" #fslnum ::"r" (val)); + +/* CPU dependent */ +/* machine status register */ +#define MFS(val, reg) \ + __asm__ __volatile__ ("mfs %0," #reg :"=r" (val)); + +#define MTS(val, reg) \ + __asm__ __volatile__ ("mts " #reg ", %0"::"r" (val)); + +/* get return address from interrupt */ +#define R14(val) \ + __asm__ __volatile__ ("addi %0, r14, 0":"=r" (val)); + +#define NOP __asm__ __volatile__ ("nop"); + +/* use machine status registe USE_MSR_REG */ +#ifdef XILINX_USE_MSR_INSTR +#define MSRSET(val) \ + __asm__ __volatile__ ("msrset r0," #val ); + +#define MSRCLR(val) \ + __asm__ __volatile__ ("msrclr r0," #val ); + +#else +#define MSRSET(val) \ +{ \ + register unsigned tmp; \ + __asm__ __volatile__ (" \ + mfs %0, rmsr; \ + ori %0, %0, "#val"; \ + mts rmsr, %0; \ + nop;" \ + : "=r" (tmp) \ + : "d" (val) \ + : "memory"); \ +} + +#define MSRCLR(val) \ +{ \ + register unsigned tmp; \ + __asm__ __volatile__ (" \ + mfs %0, rmsr; \ + andi %0, %0, ~"#val"; \ + mts rmsr, %0; \ + nop;" \ + : "=r" (tmp) \ + : "d" (val) \ + : "memory"); \ +} +#endif diff --git a/arch/microblaze/include/asm/bitops.h b/arch/microblaze/include/asm/bitops.h new file mode 100644 index 000000000..e8c835f7c --- /dev/null +++ b/arch/microblaze/include/asm/bitops.h @@ -0,0 +1,392 @@ +#ifndef _MICROBLAZE_BITOPS_H +#define _MICROBLAZE_BITOPS_H + +/* + * Copyright 1992, Linus Torvalds. + */ + +#include +#include /* swab32 */ +#include /* save_flags */ + +#ifdef __KERNEL__ +/* + * Function prototypes to keep gcc -Wall happy + */ + +/* + * The __ functions are not atomic + */ + +extern void set_bit(int nr, volatile void * addr); +extern void __set_bit(int nr, volatile void * addr); + +extern void clear_bit(int nr, volatile void * addr); +#define __clear_bit(nr, addr) clear_bit(nr, addr) +#define PLATFORM__CLEAR_BIT + +extern void change_bit(int nr, volatile void * addr); +extern void __change_bit(int nr, volatile void * addr); +extern int test_and_set_bit(int nr, volatile void * addr); +extern int __test_and_set_bit(int nr, volatile void * addr); +extern int test_and_clear_bit(int nr, volatile void * addr); +extern int __test_and_clear_bit(int nr, volatile void * addr); +extern int test_and_change_bit(int nr, volatile void * addr); +extern int __test_and_change_bit(int nr, volatile void * addr); +extern int __constant_test_bit(int nr, const volatile void * addr); +extern int __test_bit(int nr, volatile void * addr); +extern int find_first_zero_bit(void * addr, unsigned size); +extern int find_next_zero_bit (void * addr, int size, int offset); + +/* + * ffz = Find First Zero in word. Undefined if no zero exists, + * so code should check against ~0UL first.. + */ +extern __inline__ unsigned long ffz(unsigned long word) +{ + unsigned long result = 0; + + while(word & 1) { + result++; + word >>= 1; + } + return result; +} + + +extern __inline__ void set_bit(int nr, volatile void * addr) +{ + int * a = (int *) addr; + int mask; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_flags_cli(flags); + *a |= mask; + restore_flags(flags); +} + +extern __inline__ void __set_bit(int nr, volatile void * addr) +{ + int * a = (int *) addr; + int mask; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a |= mask; +} +#define PLATFORM__SET_BIT + +/* + * clear_bit() doesn't provide any barrier for the compiler. + */ +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() + +extern __inline__ void clear_bit(int nr, volatile void * addr) +{ + int * a = (int *) addr; + int mask; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_flags_cli(flags); + *a &= ~mask; + restore_flags(flags); +} + +extern __inline__ void change_bit(int nr, volatile void * addr) +{ + int mask; + unsigned long flags; + unsigned long *ADDR = (unsigned long *) addr; + + ADDR += nr >> 5; + mask = 1 << (nr & 31); + save_flags_cli(flags); + *ADDR ^= mask; + restore_flags(flags); +} + +extern __inline__ void __change_bit(int nr, volatile void * addr) +{ + int mask; + unsigned long *ADDR = (unsigned long *) addr; + + ADDR += nr >> 5; + mask = 1 << (nr & 31); + *ADDR ^= mask; +} + +extern __inline__ int test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_flags_cli(flags); + retval = (mask & *a) != 0; + *a |= mask; + restore_flags(flags); + + return retval; +} + +extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a |= mask; + return retval; +} + +extern __inline__ int test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_flags_cli(flags); + retval = (mask & *a) != 0; + *a &= ~mask; + restore_flags(flags); + + return retval; +} + +extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a &= ~mask; + return retval; +} + +extern __inline__ int test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_flags_cli(flags); + retval = (mask & *a) != 0; + *a ^= mask; + restore_flags(flags); + + return retval; +} + +extern __inline__ int __test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a ^= mask; + return retval; +} + +/* + * This routine doesn't need to be atomic. + */ +extern __inline__ int __constant_test_bit(int nr, const volatile void * addr) +{ + return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0; +} + +extern __inline__ int __test_bit(int nr, volatile void * addr) +{ + int * a = (int *) addr; + int mask; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + return ((mask & *a) != 0); +} + +#define test_bit(nr,addr) \ +(__builtin_constant_p(nr) ? \ + __constant_test_bit((nr),(addr)) : \ + __test_bit((nr),(addr))) + +#define find_first_zero_bit(addr, size) \ + find_next_zero_bit((addr), (size), 0) + +extern __inline__ int find_next_zero_bit (void * addr, int size, int offset) +{ + unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (32-offset); + if (size < 32) + goto found_first; + if (~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while (size & ~31UL) { + if (~(tmp = *(p++))) + goto found_middle; + result += 32; + size -= 32; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp |= ~0UL >> size; +found_middle: + return result + ffz(tmp); +} + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + + +extern __inline__ int ext2_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + unsigned long flags; + volatile unsigned char *ADDR = (unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + save_flags_cli(flags); + retval = (mask & *ADDR) != 0; + *ADDR |= mask; + restore_flags(flags); + return retval; +} + +extern __inline__ int ext2_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + unsigned long flags; + volatile unsigned char *ADDR = (unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + save_flags_cli(flags); + retval = (mask & *ADDR) != 0; + *ADDR &= ~mask; + restore_flags(flags); + return retval; +} + +extern __inline__ int ext2_test_bit(int nr, const volatile void * addr) +{ + int mask; + const volatile unsigned char *ADDR = (const unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + return ((mask & *ADDR) != 0); +} + +#define ext2_find_first_zero_bit(addr, size) \ + ext2_find_next_zero_bit((addr), (size), 0) + +extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) +{ + unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if(offset) { + /* We hold the little endian value in tmp, but then the + * shift is illegal. So we could keep a big endian value + * in tmp, like this: + * + * tmp = __swab32(*(p++)); + * tmp |= ~0UL >> (32-offset); + * + * but this would decrease preformance, so we change the + * shift: + */ + tmp = *(p++); + tmp |= __swab32(~0UL >> (32-offset)); + if(size < 32) + goto found_first; + if(~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while(size & ~31UL) { + if(~(tmp = *(p++))) + goto found_middle; + result += 32; + size -= 32; + } + if(!size) + return result; + tmp = *p; + +found_first: + /* tmp is little endian, so we would have to swab the shift, + * see above. But then we have to swab tmp below for ffz, so + * we might as well do this here. + */ + return result + ffz(__swab32(tmp) | (~0UL << size)); +found_middle: + return result + ffz(__swab32(tmp)); +} + +/* Bitmap functions for the minix filesystem. */ +#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) +#define minix_set_bit(nr,addr) set_bit(nr,addr) +#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) +#define minix_test_bit(nr,addr) test_bit(nr,addr) +#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) + +/** + * hweightN - returns the hamming weight of a N-bit word + * @x: the word to weigh + * + * The Hamming Weight of a number is the total number of bits set in it. + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#endif /* __KERNEL__ */ + +#endif /* _MICROBLAZE_BITOPS_H */ diff --git a/arch/microblaze/include/asm/byteorder.h b/arch/microblaze/include/asm/byteorder.h new file mode 100644 index 000000000..a4a75b7a6 --- /dev/null +++ b/arch/microblaze/include/asm/byteorder.h @@ -0,0 +1,55 @@ +/* + * include/asm-microblaze/byteorder.h -- Endian id and conversion ops + * + * Copyright (C) 2003 John Williams + * Copyright (C) 2001 NEC Corporation + * Copyright (C) 2001 Miles Bader + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + * + * Written by Miles Bader + * Microblaze port by John Williams + */ + +#ifndef __MICROBLAZE_BYTEORDER_H__ +#define __MICROBLAZE_BYTEORDER_H__ + +#include + +#ifdef __GNUC__ + +/* This is effectively a dupe of the arch-independent byteswap + code in include/linux/byteorder/swab.h, however we force a cast + of the result up to 32 bits. This in turn forces the compiler + to explicitly clear the high 16 bits, which it wasn't doing otherwise. + + I think this is a symptom of a bug in mb-gcc. JW 20040303 +*/ + + +static __inline__ __u16 ___arch__swab16 (__u16 half_word) +{ + /* 32 bit temp to cast result, forcing clearing of high word */ + __u32 temp; + + temp = ((half_word & 0x00FFU) << 8) | ((half_word & 0xFF00U) >> 8); + + return (__u16) temp; +} + +#define __arch__swab16(x) ___arch__swab16(x) + +/* Microblaze has no arch-specific endian conversion insns */ + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#endif /* __GNUC__ */ + +#include + +#endif /* __MICROBLAZE_BYTEORDER_H__ */ diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h new file mode 100644 index 000000000..8a9064b3c --- /dev/null +++ b/arch/microblaze/include/asm/config.h @@ -0,0 +1,27 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +/* Relocation to SDRAM works on all Microblaze boards */ +#define CONFIG_RELOC_FIXUP_WORKS + +#endif diff --git a/arch/microblaze/include/asm/errno.h b/arch/microblaze/include/asm/errno.h new file mode 100644 index 000000000..4c82b503d --- /dev/null +++ b/arch/microblaze/include/asm/errno.h @@ -0,0 +1 @@ +#include diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h new file mode 100644 index 000000000..ec7837f6b --- /dev/null +++ b/arch/microblaze/include/asm/global_data.h @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t) + */ + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long have_console; /* serial_init() was called */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + unsigned long fb_base; /* base address of frame buffer */ + void **jt; /* jump table */ +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ +#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ + +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31") + +#endif /* __ASM_GBL_DATA_H */ diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h new file mode 100644 index 000000000..7e190d15c --- /dev/null +++ b/arch/microblaze/include/asm/io.h @@ -0,0 +1,163 @@ +/* + * include/asm-microblaze/io.h -- Misc I/O operations + * + * Copyright (C) 2003 John Williams + * Copyright (C) 2001,02 NEC Corporation + * Copyright (C) 2001,02 Miles Bader + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + * + * Written by Miles Bader + * Microblaze port by John Williams + */ + +#ifndef __MICROBLAZE_IO_H__ +#define __MICROBLAZE_IO_H__ + +#include + +#define IO_SPACE_LIMIT 0xFFFFFFFF + +#define readb(addr) \ + ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; }) +#define readw(addr) \ + ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; }) +#define readl(addr) \ + ({ unsigned long __v = (*(volatile unsigned long *) (addr)); __v; }) + +#define writeb(b, addr) \ + (void)((*(volatile unsigned char *) (addr)) = (b)) +#define writew(b, addr) \ + (void)((*(volatile unsigned short *) (addr)) = (b)) +#define writel(b, addr) \ + (void)((*(volatile unsigned int *) (addr)) = (b)) + +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) + +#define inb(addr) readb (addr) +#define inw(addr) readw (addr) +#define inl(addr) readl (addr) +#define outb(x, addr) ((void) writeb (x, addr)) +#define outw(x, addr) ((void) writew (x, addr)) +#define outl(x, addr) ((void) writel (x, addr)) + +/* Some #definitions to keep strange Xilinx code happy */ +#define in_8(addr) readb (addr) +#define in_be16(addr) readw (addr) +#define in_be32(addr) readl (addr) + +#define out_8(addr,x ) outb (x,addr) +#define out_be16(addr,x ) outw (x,addr) +#define out_be32(addr,x ) outl (x,addr) + + +#define inb_p(port) inb((port)) +#define outb_p(val, port) outb((val), (port)) +#define inw_p(port) inw((port)) +#define outw_p(val, port) outw((val), (port)) +#define inl_p(port) inl((port)) +#define outl_p(val, port) outl((val), (port)) + +/* Some defines to keep the MTD flash drivers happy */ + +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl +#define __raw_writeb writeb +#define __raw_writew writew +#define __raw_writel writel + +static inline void io_insb (unsigned long port, void *dst, unsigned long count) +{ + unsigned char *p = dst; + while (count--) + *p++ = inb (port); +} +static inline void io_insw (unsigned long port, void *dst, unsigned long count) +{ + unsigned short *p = dst; + while (count--) + *p++ = inw (port); +} +static inline void io_insl (unsigned long port, void *dst, unsigned long count) +{ + unsigned long *p = dst; + while (count--) + *p++ = inl (port); +} + +static inline void +io_outsb (unsigned long port, const void *src, unsigned long count) +{ + const unsigned char *p = src; + while (count--) + outb (*p++, port); +} +static inline void +io_outsw (unsigned long port, const void *src, unsigned long count) +{ + const unsigned short *p = src; + while (count--) + outw (*p++, port); +} +static inline void +io_outsl (unsigned long port, const void *src, unsigned long count) +{ + const unsigned long *p = src; + while (count--) + outl (*p++, port); +} + +#define outsb(a,b,l) io_outsb(a,b,l) +#define outsw(a,b,l) io_outsw(a,b,l) +#define outsl(a,b,l) io_outsl(a,b,l) + +#define insb(a,b,l) io_insb(a,b,l) +#define insw(a,b,l) io_insw(a,b,l) +#define insl(a,b,l) io_insl(a,b,l) + + +#define iounmap(addr) ((void)0) +#define ioremap(physaddr, size) (physaddr) +#define ioremap_nocache(physaddr, size) (physaddr) +#define ioremap_writethrough(physaddr, size) (physaddr) +#define ioremap_fullcache(physaddr, size) (physaddr) + +static inline void sync(void) +{ +} + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + +#endif /* __MICROBLAZE_IO_H__ */ diff --git a/arch/microblaze/include/asm/microblaze_intc.h b/arch/microblaze/include/asm/microblaze_intc.h new file mode 100644 index 000000000..4c385aa24 --- /dev/null +++ b/arch/microblaze/include/asm/microblaze_intc.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +typedef volatile struct microblaze_intc_t { + int isr; /* interrupt status register */ + int ipr; /* interrupt pending register */ + int ier; /* interrupt enable register */ + int iar; /* interrupt acknowledge register */ + int sie; /* set interrupt enable bits */ + int cie; /* clear interrupt enable bits */ + int ivr; /* interrupt vector register */ + int mer; /* master enable register */ +} microblaze_intc_t; + +struct irq_action { + interrupt_handler_t *handler; /* pointer to interrupt rutine */ + void *arg; + int count; /* number of interrupt */ +}; + +void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, + void *arg); diff --git a/arch/microblaze/include/asm/microblaze_timer.h b/arch/microblaze/include/asm/microblaze_timer.h new file mode 100644 index 000000000..844c8db11 --- /dev/null +++ b/arch/microblaze/include/asm/microblaze_timer.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define TIMER_ENABLE_ALL 0x400 /* ENALL */ +#define TIMER_PWM 0x200 /* PWMA0 */ +#define TIMER_INTERRUPT 0x100 /* T0INT */ +#define TIMER_ENABLE 0x080 /* ENT0 */ +#define TIMER_ENABLE_INTR 0x040 /* ENIT0 */ +#define TIMER_RESET 0x020 /* LOAD0 */ +#define TIMER_RELOAD 0x010 /* ARHT0 */ +#define TIMER_EXT_CAPTURE 0x008 /* CAPT0 */ +#define TIMER_EXT_COMPARE 0x004 /* GENT0 */ +#define TIMER_DOWN_COUNT 0x002 /* UDT0 */ +#define TIMER_CAPTURE_MODE 0x001 /* MDT0 */ + +typedef volatile struct microblaze_timer_t { + int control; /* control/statuc register TCSR */ + int loadreg; /* load register TLR */ + int counter; /* timer/counter register */ +} microblaze_timer_t; diff --git a/arch/microblaze/include/asm/posix_types.h b/arch/microblaze/include/asm/posix_types.h new file mode 100644 index 000000000..9a2cc663e --- /dev/null +++ b/arch/microblaze/include/asm/posix_types.h @@ -0,0 +1,76 @@ +/* + * include/asm-microblaze/posix_types.h -- Kernel versions of standard types + * + * Copyright (C) 2003 John Williams + * Copyright (C) 2001,2002 NEC Corporation + * Copyright (C) 2001,2002 Miles Bader + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + * + * Written by Miles Bader + * Microblaze port by John Williams + */ + +#ifndef __MICROBLAZE_POSIX_TYPES_H__ +#define __MICROBLAZE_POSIX_TYPES_H__ + +#include + + +typedef unsigned int __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned long long __kernel_ino64_t; +typedef unsigned int __kernel_mode_t; +typedef unsigned int __kernel_nlink_t; +typedef long __kernel_off_t; +typedef long long __kernel_loff_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned int __kernel_uid_t; +typedef unsigned int __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(fd, fd_set) \ + __set_bit (fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits) +#undef __FD_CLR +#define __FD_CLR(fd, fd_set) \ + __clear_bit (fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits) +#undef __FD_ISSET +#define __FD_ISSET(fd, fd_set) \ + __test_bit (fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits) +#undef __FD_ZERO +#define __FD_ZERO(fd_set) \ + memset (fd_set, 0, sizeof (*(fd_set *)fd_set)) + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif /* __MICROBLAZE_POSIX_TYPES_H__ */ diff --git a/arch/microblaze/include/asm/processor.h b/arch/microblaze/include/asm/processor.h new file mode 100644 index 000000000..78b8976ca --- /dev/null +++ b/arch/microblaze/include/asm/processor.h @@ -0,0 +1 @@ +/* FIXME: Implement this! */ diff --git a/arch/microblaze/include/asm/ptrace.h b/arch/microblaze/include/asm/ptrace.h new file mode 100644 index 000000000..b796d4faf --- /dev/null +++ b/arch/microblaze/include/asm/ptrace.h @@ -0,0 +1,116 @@ +/* + * include/asm-microblaze/ptrace.h -- Access to CPU registers + * + * Copyright (C) 2003 John Williams + * Copyright (C) 2001,2002 NEC Corporation + * Copyright (C) 2001,2002 Miles Bader + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + * + * Written by Miles Bader + * Microblaze port by John Williams + */ + +#ifndef __MICROBLAZE_PTRACE_H__ +#define __MICROBLAZE_PTRACE_H__ + + +/* Microblaze general purpose registers with special meanings. */ +#define GPR_ZERO 0 /* constant zero */ +#define GPR_ASM 18 /* reserved for assembler */ +#define GPR_SP 1 /* stack pointer */ +#define GPR_GP 2 /* global data pointer */ +#define GPR_EP 30 /* `element pointer' */ +#define GPR_LP 15 /* link pointer (current return address) */ + +/* These aren't official names, but they make some code more descriptive. */ +#define GPR_ARG0 5 +#define GPR_ARG1 6 +#define GPR_ARG2 7 +#define GPR_ARG3 8 +#define GPR_ARG4 9 +#define GPR_ARG5 10 +#define GPR_RVAL0 3 +#define GPR_RVAL1 4 +#define GPR_RVAL GPR_RVAL0 + +#define NUM_GPRS 32 + +/* `system' registers. */ +/* Note these are old v850 values, microblaze has many fewer */ +#define SR_EIPC 0 +#define SR_EIPSW 1 +#define SR_FEPC 2 +#define SR_FEPSW 3 +#define SR_ECR 4 +#define SR_PSW 5 +#define SR_CTPC 16 +#define SR_CTPSW 17 +#define SR_DBPC 18 +#define SR_DBPSW 19 +#define SR_CTBP 20 +#define SR_DIR 21 +#define SR_ASID 23 + + +#ifndef __ASSEMBLY__ + +typedef unsigned long microblaze_reg_t; + +/* How processor state is stored on the stack during a syscall/signal. + If you change this structure, change the associated assembly-language + macros below too (PT_*)! */ +struct pt_regs +{ + /* General purpose registers. */ + microblaze_reg_t gpr[NUM_GPRS]; + + microblaze_reg_t pc; /* program counter */ + microblaze_reg_t psw; /* program status word */ + + microblaze_reg_t kernel_mode; /* 1 if in `kernel mode', 0 if user mode */ + microblaze_reg_t single_step; /* 1 if in single step mode */ +}; + + +#define instruction_pointer(regs) ((regs)->pc) +#define user_mode(regs) (!(regs)->kernel_mode) + +/* When a struct pt_regs is used to save user state for a system call in + the kernel, the system call is stored in the space for R0 (since it's + never used otherwise, R0 being a constant 0). Non-system-calls + simply store 0 there. */ +#define PT_REGS_SYSCALL(regs) (regs)->gpr[0] +#define PT_REGS_SET_SYSCALL(regs, val) ((regs)->gpr[0] = (val)) + +#endif /* !__ASSEMBLY__ */ + + +/* The number of bytes used to store each register. */ +#define _PT_REG_SIZE 4 + +/* Offset of a general purpose register in a stuct pt_regs. */ +#define PT_GPR(num) ((num) * _PT_REG_SIZE) + +/* Offsets of various special registers & fields in a struct pt_regs. */ +#define NUM_SPECIAL 4 +#define PT_PC ((NUM_GPRS + 0) * _PT_REG_SIZE) +#define PT_PSW ((NUM_GPRS + 1) * _PT_REG_SIZE) +#define PT_KERNEL_MODE ((NUM_GPRS + 2) * _PT_REG_SIZE) +#define PT_SINGLESTEP ((NUM_GPRS + 3) * _PT_REG_SIZE) + +#define PT_SYSCALL PT_GPR(0) + +/* Size of struct pt_regs, including alignment. */ +#define PT_SIZE ((NUM_GPRS + NUM_SPECIAL) * _PT_REG_SIZE) + +/* These are `magic' values for PTRACE_PEEKUSR that return info about where + a process is located in memory. */ +#define PT_TEXT_ADDR (PT_SIZE + 1) +#define PT_TEXT_LEN (PT_SIZE + 2) +#define PT_DATA_ADDR (PT_SIZE + 3) +#define PT_DATA_LEN (PT_SIZE + 4) + +#endif /* __MICROBLAZE_PTRACE_H__ */ diff --git a/arch/microblaze/include/asm/string.h b/arch/microblaze/include/asm/string.h new file mode 100644 index 000000000..724f5bdfa --- /dev/null +++ b/arch/microblaze/include/asm/string.h @@ -0,0 +1,31 @@ +/* + * include/asm-microblaze/string.h -- Architecture specific string routines + * + * Copyright (C) 2003 John Williams + * Copyright (C) 2001,2002 NEC Corporation + * Copyright (C) 2001,2002 Miles Bader + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + * + * Written by Miles Bader + * Microblaze port by John Williams + */ + +#ifndef __MICROBLAZE_STRING_H__ +#define __MICROBLAZE_STRING_H__ + +#if 0 +#define __HAVE_ARCH_BCOPY +#define __HAVE_ARCH_MEMCPY +#define __HAVE_ARCH_MEMSET +#define __HAVE_ARCH_MEMMOVE + +extern void *memcpy (void *, const void *, __kernel_size_t); +extern void bcopy (const char *, char *, int); +extern void *memset (void *, int, __kernel_size_t); +extern void *memmove (void *, const void *, __kernel_size_t); +#endif + +#endif /* __MICROBLAZE_STRING_H__ */ diff --git a/arch/microblaze/include/asm/system.h b/arch/microblaze/include/asm/system.h new file mode 100644 index 000000000..0297a1159 --- /dev/null +++ b/arch/microblaze/include/asm/system.h @@ -0,0 +1,161 @@ +/* + * include/asm-microblaze/system.h -- Low-level interrupt/thread ops + * + * Copyright (C) 2003 John Williams (jwilliams@itee.uq.edu.au) + * based upon microblaze version + * Copyright (C) 2001 NEC Corporation + * Copyright (C) 2001 Miles Bader + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + * + * Written by Miles Bader + * Microblaze port by John Williams + * Microblaze port by John Williams + */ + +#ifndef __MICROBLAZE_SYSTEM_H__ +#define __MICROBLAZE_SYSTEM_H__ + +#if 0 +#include +#endif +#include + +#define prepare_to_switch() do { } while (0) + +/* + * switch_to(n) should switch tasks to task ptr, first checking that + * ptr isn't the current task, in which case it does nothing. + */ +struct thread_struct; +extern void *switch_thread (struct thread_struct *last, + struct thread_struct *next); +#define switch_to(prev,next,last) do { \ + if (prev != next) { \ + (last) = switch_thread (&prev->thread, &next->thread); \ + } \ +} while (0) + + +/* Enable/disable interrupts. */ +#define __sti() \ +{ \ + register unsigned tmp; \ + __asm__ __volatile__ (" \ + mfs %0, rmsr; \ + ori %0, %0, 2; \ + mts rmsr, %0" \ + : "=r" (tmp) \ + : \ + : "memory"); \ +} + +#define __cli() \ +{ \ + register unsigned tmp; \ + __asm__ __volatile__ (" \ + mfs %0, rmsr; \ + andi %0, %0, ~2; \ + mts rmsr, %0" \ + : "=r" (tmp) \ + : \ + : "memory"); \ +} + +#define __save_flags(flags) \ + __asm__ __volatile__ ("mfs %0, rmsr" : "=r" (flags)) +#define __restore_flags(flags) \ + __asm__ __volatile__ ("mts rmsr, %0" :: "r" (flags)) + +#define __save_flags_cli(flags) \ +{ \ + register unsigned tmp; \ + __asm__ __volatile__ (" \ + mfs %0, rmsr; \ + andi %1, %0, ~2; \ + mts rmsr, %1;" \ + : "=r" (flags), "=r" (tmp) \ + : \ + : "memory"); \ +} + +#define __save_flags_sti(flags) \ +{ \ + register unsigned tmp; \ + __asm__ __volatile__ (" \ + mfs %0, rmsr; \ + ori %1, %0, 2; \ + mts rmsr, %1;" \ + : "=r" (flags) ,"=r" (tmp) \ + : \ + : "memory"); \ +} + +/* For spinlocks etc */ +#define local_irq_save(flags) __save_flags_cli (flags) +#define local_irq_set(flags) __save_flags_sti (flags) +#define local_irq_restore(flags) __restore_flags (flags) +#define local_irq_disable() __cli () +#define local_irq_enable() __sti () + +#define cli() __cli () +#define sti() __sti () +#define save_flags(flags) __save_flags (flags) +#define restore_flags(flags) __restore_flags (flags) +#define save_flags_cli(flags) __save_flags_cli (flags) + +/* + * Force strict CPU ordering. + * Not really required on microblaze... + */ +#define nop() __asm__ __volatile__ ("nop") +#define mb() __asm__ __volatile__ ("nop" ::: "memory") +#define rmb() mb () +#define wmb() mb () +#define set_mb(var, value) do { var = value; mb(); } while (0) +#define set_wmb(var, value) do { var = value; wmb (); } while (0) + +#ifdef CONFIG_SMP +#define smp_mb() mb () +#define smp_rmb() rmb () +#define smp_wmb() wmb () +#else +#define smp_mb() barrier () +#define smp_rmb() barrier () +#define smp_wmb() barrier () +#endif + +#define xchg(ptr, with) \ + ((__typeof__ (*(ptr)))__xchg ((unsigned long)(with), (ptr), sizeof (*(ptr)))) +#define tas(ptr) (xchg ((ptr), 1)) + +extern inline unsigned long __xchg (unsigned long with, + __volatile__ void *ptr, int size) +{ + unsigned long tmp, flags; + + save_flags_cli (flags); + + switch (size) { + case 1: + tmp = *(unsigned char *)ptr; + *(unsigned char *)ptr = with; + break; + case 2: + tmp = *(unsigned short *)ptr; + *(unsigned short *)ptr = with; + break; + case 4: + tmp = *(unsigned long *)ptr; + *(unsigned long *)ptr = with; + break; + } + + restore_flags (flags); + + return tmp; +} + +#endif /* __MICROBLAZE_SYSTEM_H__ */ diff --git a/arch/microblaze/include/asm/types.h b/arch/microblaze/include/asm/types.h new file mode 100644 index 000000000..77094f62d --- /dev/null +++ b/arch/microblaze/include/asm/types.h @@ -0,0 +1,60 @@ +#ifndef _ASM_TYPES_H +#define _ASM_TYPES_H + +/* + * This file is never included by application software unless + * explicitly requested (e.g., via linux/types.h) in which case the + * application is Linux specific so (user-) name space pollution is + * not a major issue. However, for interoperability, libraries still + * need to be careful to avoid a name clashes. + */ + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; +#endif /* __KERNEL__ */ + +#endif /* _ASM_TYPES_H */ diff --git a/arch/microblaze/include/asm/u-boot.h b/arch/microblaze/include/asm/u-boot.h new file mode 100644 index 000000000..543a6b177 --- /dev/null +++ b/arch/microblaze/include/asm/u-boot.h @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ + +typedef struct bd_info { + unsigned long bi_memstart; /* start of DRAM memory */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned long bi_baudrate; /* Console Baudrate */ +} bd_t; + + +#endif /* _U_BOOT_H_ */ diff --git a/arch/microblaze/include/asm/unaligned.h b/arch/microblaze/include/asm/unaligned.h new file mode 100644 index 000000000..785c2e915 --- /dev/null +++ b/arch/microblaze/include/asm/unaligned.h @@ -0,0 +1,16 @@ +#ifndef _ASM_MICROBLAZE_UNALIGNED_H +#define _ASM_MICROBLAZE_UNALIGNED_H + +#ifdef __KERNEL__ + +/* + * The Microblaze can do unaligned accesses itself in big endian mode. + */ +#include +#include + +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be + +#endif /* __KERNEL__ */ +#endif /* _ASM_MICROBLAZE_UNALIGNED_H */ -- cgit v1.2.3