From 63cbf0c63b2cd06417503d30c353545d2ba19082 Mon Sep 17 00:00:00 2001 From: Inderpal Singh Date: Mon, 12 Nov 2012 09:25:08 +0530 Subject: DRIVERS: USB: Initialize HSIC PHYs and enable network support Arndale board has AX88760, which is USB 2.0 Hub & USB 2.0 Ethernet Combo controller, connected to HSIC Phy of USB host controller via USB3503 hub. This patch initializes the HSIC PHYs, performs reset sequence for USB3503 hub and enables the relevant config options for network to work. Signed-off-by: Inderpal Singh --- arch/arm/include/asm/arch-exynos/ehci.h | 19 +++++++++++++++ drivers/usb/host/ehci-exynos.c | 43 ++++++++++++++++++++++++++++++--- include/configs/arndale5250.h | 7 +++--- 3 files changed, 62 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h index 8aeff8ab2..663d3191b 100644 --- a/arch/arm/include/asm/arch-exynos/ehci.h +++ b/arch/arm/include/asm/arch-exynos/ehci.h @@ -37,6 +37,25 @@ #define HOST_CTRL0_FSEL_MASK (7 << 16) +#define HSIC_CTRL_REFCLKSEL (0x2) +#define HSIC_CTRL_REFCLKSEL_MASK (0x3) +#define HSIC_CTRL_REFCLKSEL_SHIFT (23) + +#define HSIC_CTRL_REFCLKDIV_12 (0x24) +#define HSIC_CTRL_REFCLKDIV_15 (0x1C) +#define HSIC_CTRL_REFCLKDIV_16 (0x1A) +#define HSIC_CTRL_REFCLKDIV_19_2 (0x15) +#define HSIC_CTRL_REFCLKDIV_20 (0x14) +#define HSIC_CTRL_REFCLKDIV_MASK (0x7f) +#define HSIC_CTRL_REFCLKDIV_SHIFT (16) + +#define HSIC_CTRL_SIDDQ (0x1 << 6) +#define HSIC_CTRL_FORCESLEEP (0x1 << 5) +#define HSIC_CTRL_FORCESUSPEND (0x1 << 4) +#define HSIC_CTRL_WORDINTERFACE (0x1 << 3) +#define HSIC_CTRL_UTMISWRST (0x1 << 2) +#define HSIC_CTRL_PHYSWRST (0x1 << 0) + #define EHCICTRL_ENAINCRXALIGN (1 << 29) #define EHCICTRL_ENAINCR4 (1 << 28) #define EHCICTRL_ENAINCR8 (1 << 27) diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index 9f0ed06a8..28d6d1d19 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -26,11 +26,14 @@ #include #include #include +#include #include "ehci.h" /* Setup the EHCI host controller. */ static void setup_usb_phy(struct exynos_usb_phy *usb) { + u32 hsic_ctrl; + set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN); set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN); @@ -57,6 +60,33 @@ static void setup_usb_phy(struct exynos_usb_phy *usb) HOST_CTRL0_UTMISWRST); udelay(20); + /* HSIC phy reset */ + clrbits_le32(&usb->hsicphyctrl1, + HSIC_CTRL_FORCESUSPEND | + HSIC_CTRL_FORCESLEEP | + HSIC_CTRL_SIDDQ); + + clrbits_le32(&usb->hsicphyctrl2, + HSIC_CTRL_FORCESUSPEND | + HSIC_CTRL_FORCESLEEP | + HSIC_CTRL_SIDDQ); + + hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK) + << HSIC_CTRL_REFCLKDIV_SHIFT) + | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK) + << HSIC_CTRL_REFCLKSEL_SHIFT) + | HSIC_CTRL_PHYSWRST); + + setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); + setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); + + udelay(10); + + clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST); + clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST); + + udelay(80); + /* EHCI Ctrl setting */ setbits_le32(&usb->ehcictrl, EHCICTRL_ENAINCRXALIGN | @@ -79,6 +109,7 @@ static void reset_usb_phy(struct exynos_usb_phy *usb) set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE); } +struct exynos5_gpio_part1 *gpio; /* * EHCI-initialization * Create the appropriate control structures to manage @@ -87,14 +118,20 @@ static void reset_usb_phy(struct exynos_usb_phy *usb) int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { struct exynos_usb_phy *usb; - + gpio = (struct exynos5_gpio_part1 *) EXYNOS5_GPIO_PART1_BASE; usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy(); + + s5p_gpio_direction_output(&gpio->x3, 5, 0); + s5p_gpio_direction_output(&gpio->d1, 7, 0); + setup_usb_phy(usb); + s5p_gpio_direction_output(&gpio->x3, 5, 1); + s5p_gpio_direction_output(&gpio->d1, 7, 1); + *hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci(); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr + *hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n", (uint32_t)*hccr, (uint32_t)*hcor, (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); diff --git a/include/configs/arndale5250.h b/include/configs/arndale5250.h index 9698c6905..c0241f49d 100644 --- a/include/configs/arndale5250.h +++ b/include/configs/arndale5250.h @@ -110,6 +110,7 @@ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_EXYNOS #define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 /* MMC SPL */ #define CONFIG_SPL @@ -209,10 +210,8 @@ /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET -#define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE 0x5000000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_ENV_SROM_BANK 1 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX #endif /*CONFIG_CMD_NET*/ /* Enable devicetree support */ -- cgit v1.2.3