diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpio/Makefile | 3 | ||||
| -rw-r--r-- | drivers/gpio/mx31_gpio.c | 73 | ||||
| -rw-r--r-- | drivers/net/smc911x.c | 457 | ||||
| -rw-r--r-- | drivers/net/smc911x.h | 494 | ||||
| -rw-r--r-- | drivers/net/tsec.c | 30 | ||||
| -rw-r--r-- | drivers/spi/mxc_spi.c | 93 | ||||
| -rw-r--r-- | drivers/video/Makefile | 2 | ||||
| -rw-r--r-- | drivers/video/mx3fb.c | 856 | ||||
| -rw-r--r-- | drivers/video/s6e63d6.c | 76 |
9 files changed, 1610 insertions, 474 deletions
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index dd618ed71..f10144fe7 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk LIB := $(obj)libgpio.a -COBJS-$(CONFIG_PCA953X) += pca953x.o +COBJS-$(CONFIG_MX31_GPIO) += mx31_gpio.o +COBJS-$(CONFIG_PCA953X) += pca953x.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mx31_gpio.c new file mode 100644 index 000000000..737aafa82 --- /dev/null +++ b/drivers/gpio/mx31_gpio.c @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2009 + * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/arch/mx31.h> +#include <asm/arch/mx31-regs.h> + +/* GPIO port description */ +static unsigned long gpio_ports[] = { + [0] = GPIO1_BASE, + [1] = GPIO2_BASE, + [2] = GPIO3_BASE, +}; + +int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction) +{ + unsigned int port = gpio >> 5; + u32 l; + + if (port >= ARRAY_SIZE(gpio_ports)) + return 1; + + gpio &= 0x1f; + + l = __REG(gpio_ports[port] + GPIO_GDIR); + switch (direction) { + case MX31_GPIO_DIRECTION_OUT: + l |= 1 << gpio; + break; + case MX31_GPIO_DIRECTION_IN: + l &= ~(1 << gpio); + } + __REG(gpio_ports[port] + GPIO_GDIR) = l; + + return 0; +} + +void mx31_gpio_set(unsigned int gpio, unsigned int value) +{ + unsigned int port = gpio >> 5; + u32 l; + + if (port >= ARRAY_SIZE(gpio_ports)) + return; + + gpio &= 0x1f; + + l = __REG(gpio_ports[port] + GPIO_DR); + if (value) + l |= 1 << gpio; + else + l &= ~(1 << gpio); + __REG(gpio_ports[port] + GPIO_DR) = l; +} diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 9cc4fce00..1ded8f01d 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -27,38 +27,7 @@ #include <net.h> #include <miiphy.h> -#if defined (CONFIG_DRIVER_SMC911X_32_BIT) && \ - defined (CONFIG_DRIVER_SMC911X_16_BIT) -#error "SMC911X: Only one of CONFIG_DRIVER_SMC911X_32_BIT and \ - CONFIG_DRIVER_SMC911X_16_BIT shall be set" -#endif - -#if defined (CONFIG_DRIVER_SMC911X_32_BIT) -static inline u32 __smc911x_reg_read(u32 addr) -{ - return *(volatile u32*)addr; -} -u32 smc911x_reg_read(u32 addr) __attribute__((weak, alias("__smc911x_reg_read"))); - -static inline void __smc911x_reg_write(u32 addr, u32 val) -{ - *(volatile u32*)addr = val; -} -void smc911x_reg_write(u32 addr, u32 val) __attribute__((weak, alias("__smc911x_reg_write"))); -#elif defined (CONFIG_DRIVER_SMC911X_16_BIT) -static inline u32 smc911x_reg_read(u32 addr) -{ - volatile u16 *addr_16 = (u16 *)addr; - return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16)); -} -static inline void smc911x_reg_write(u32 addr, u32 val) -{ - *(volatile u16*)addr = (u16)val; - *(volatile u16*)(addr + 2) = (u16)(val >> 16); -} -#else -#error "SMC911X: undefined bus width" -#endif /* CONFIG_DRIVER_SMC911X_16_BIT */ +#include "smc911x.h" u32 pkt_data_pull(u32 addr) \ __attribute__ ((weak, alias ("smc911x_reg_read"))); @@ -67,370 +36,6 @@ void pkt_data_push(u32 addr, u32 val) \ #define mdelay(n) udelay((n)*1000) -/* Below are the register offsets and bit definitions - * of the Lan911x memory space - */ -#define RX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x00) - -#define TX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x20) -#define TX_CMD_A_INT_ON_COMP 0x80000000 -#define TX_CMD_A_INT_BUF_END_ALGN 0x03000000 -#define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000 -#define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000 -#define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000 -#define TX_CMD_A_INT_DATA_OFFSET 0x001F0000 -#define TX_CMD_A_INT_FIRST_SEG 0x00002000 -#define TX_CMD_A_INT_LAST_SEG 0x00001000 -#define TX_CMD_A_BUF_SIZE 0x000007FF -#define TX_CMD_B_PKT_TAG 0xFFFF0000 -#define TX_CMD_B_ADD_CRC_DISABLE 0x00002000 -#define TX_CMD_B_DISABLE_PADDING 0x00001000 -#define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF - -#define RX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x40) -#define RX_STS_PKT_LEN 0x3FFF0000 -#define RX_STS_ES 0x00008000 -#define RX_STS_BCST 0x00002000 -#define RX_STS_LEN_ERR 0x00001000 -#define RX_STS_RUNT_ERR 0x00000800 -#define RX_STS_MCAST 0x00000400 -#define RX_STS_TOO_LONG 0x00000080 -#define RX_STS_COLL 0x00000040 -#define RX_STS_ETH_TYPE 0x00000020 -#define RX_STS_WDOG_TMT 0x00000010 -#define RX_STS_MII_ERR 0x00000008 -#define RX_STS_DRIBBLING 0x00000004 -#define RX_STS_CRC_ERR 0x00000002 -#define RX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x44) -#define TX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x48) -#define TX_STS_TAG 0xFFFF0000 -#define TX_STS_ES 0x00008000 -#define TX_STS_LOC 0x00000800 -#define TX_STS_NO_CARR 0x00000400 -#define TX_STS_LATE_COLL 0x00000200 -#define TX_STS_MANY_COLL 0x00000100 -#define TX_STS_COLL_CNT 0x00000078 -#define TX_STS_MANY_DEFER 0x00000004 -#define TX_STS_UNDERRUN 0x00000002 -#define TX_STS_DEFERRED 0x00000001 -#define TX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x4C) -#define ID_REV (CONFIG_DRIVER_SMC911X_BASE + 0x50) -#define ID_REV_CHIP_ID 0xFFFF0000 /* RO */ -#define ID_REV_REV_ID 0x0000FFFF /* RO */ - -#define INT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x54) -#define INT_CFG_INT_DEAS 0xFF000000 /* R/W */ -#define INT_CFG_INT_DEAS_CLR 0x00004000 -#define INT_CFG_INT_DEAS_STS 0x00002000 -#define INT_CFG_IRQ_INT 0x00001000 /* RO */ -#define INT_CFG_IRQ_EN 0x00000100 /* R/W */ -#define INT_CFG_IRQ_POL 0x00000010 /* R/W Not Affected by SW Reset */ -#define INT_CFG_IRQ_TYPE 0x00000001 /* R/W Not Affected by SW Reset */ - -#define INT_STS (CONFIG_DRIVER_SMC911X_BASE + 0x58) -#define INT_STS_SW_INT 0x80000000 /* R/WC */ -#define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */ -#define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */ -#define INT_STS_RXDFH_INT 0x00800000 /* R/WC */ -#define INT_STS_RXDF_INT 0x00400000 /* R/WC */ -#define INT_STS_TX_IOC 0x00200000 /* R/WC */ -#define INT_STS_RXD_INT 0x00100000 /* R/WC */ -#define INT_STS_GPT_INT 0x00080000 /* R/WC */ -#define INT_STS_PHY_INT 0x00040000 /* RO */ -#define INT_STS_PME_INT 0x00020000 /* R/WC */ -#define INT_STS_TXSO 0x00010000 /* R/WC */ -#define INT_STS_RWT 0x00008000 /* R/WC */ -#define INT_STS_RXE 0x00004000 /* R/WC */ -#define INT_STS_TXE 0x00002000 /* R/WC */ -/*#define INT_STS_ERX 0x00001000*/ /* R/WC */ -#define INT_STS_TDFU 0x00000800 /* R/WC */ -#define INT_STS_TDFO 0x00000400 /* R/WC */ -#define INT_STS_TDFA 0x00000200 /* R/WC */ -#define INT_STS_TSFF 0x00000100 /* R/WC */ -#define INT_STS_TSFL 0x00000080 /* R/WC */ -/*#define INT_STS_RXDF 0x00000040*/ /* R/WC */ -#define INT_STS_RDFO 0x00000040 /* R/WC */ -#define INT_STS_RDFL 0x00000020 /* R/WC */ -#define INT_STS_RSFF 0x00000010 /* R/WC */ -#define INT_STS_RSFL 0x00000008 /* R/WC */ -#define INT_STS_GPIO2_INT 0x00000004 /* R/WC */ -#define INT_STS_GPIO1_INT 0x00000002 /* R/WC */ -#define INT_STS_GPIO0_INT 0x00000001 /* R/WC */ -#define INT_EN (CONFIG_DRIVER_SMC911X_BASE + 0x5C) -#define INT_EN_SW_INT_EN 0x80000000 /* R/W */ -#define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */ -#define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */ -#define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */ -/*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */ -#define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */ -#define INT_EN_RXD_INT_EN 0x00100000 /* R/W */ -#define INT_EN_GPT_INT_EN 0x00080000 /* R/W */ -#define INT_EN_PHY_INT_EN 0x00040000 /* R/W */ -#define INT_EN_PME_INT_EN 0x00020000 /* R/W */ -#define INT_EN_TXSO_EN 0x00010000 /* R/W */ -#define INT_EN_RWT_EN 0x00008000 /* R/W */ -#define INT_EN_RXE_EN 0x00004000 /* R/W */ -#define INT_EN_TXE_EN 0x00002000 /* R/W */ -/*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */ -#define INT_EN_TDFU_EN 0x00000800 /* R/W */ -#define INT_EN_TDFO_EN 0x00000400 /* R/W */ -#define INT_EN_TDFA_EN 0x00000200 /* R/W */ -#define INT_EN_TSFF_EN 0x00000100 /* R/W */ -#define INT_EN_TSFL_EN 0x00000080 /* R/W */ -/*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */ -#define INT_EN_RDFO_EN 0x00000040 /* R/W */ -#define INT_EN_RDFL_EN 0x00000020 /* R/W */ -#define INT_EN_RSFF_EN 0x00000010 /* R/W */ -#define INT_EN_RSFL_EN 0x00000008 /* R/W */ -#define INT_EN_GPIO2_INT 0x00000004 /* R/W */ -#define INT_EN_GPIO1_INT 0x00000002 /* R/W */ -#define INT_EN_GPIO0_INT 0x00000001 /* R/W */ - -#define BYTE_TEST (CONFIG_DRIVER_SMC911X_BASE + 0x64) -#define FIFO_INT (CONFIG_DRIVER_SMC911X_BASE + 0x68) -#define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */ -#define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */ -#define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */ -#define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */ - -#define RX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x6C) -#define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */ -#define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */ -#define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */ -#define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */ -#define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */ -#define RX_CFG_RX_DUMP 0x00008000 /* R/W */ -#define RX_CFG_RXDOFF 0x00001F00 /* R/W */ -/*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */ - -#define TX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x70) -/*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */ -/*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/ /* R/W Self Clearing */ -#define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */ -#define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */ -#define TX_CFG_TXSAO 0x00000004 /* R/W */ -#define TX_CFG_TX_ON 0x00000002 /* R/W */ -#define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */ - -#define HW_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x74) -#define HW_CFG_TTM 0x00200000 /* R/W */ -#define HW_CFG_SF 0x00100000 /* R/W */ -#define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */ -#define HW_CFG_TR 0x00003000 /* R/W */ -#define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */ -#define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */ -#define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */ -#define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */ -#define HW_CFG_SMI_SEL 0x00000010 /* R/W */ -#define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */ -#define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */ -#define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */ -#define HW_CFG_SRST_TO 0x00000002 /* RO */ -#define HW_CFG_SRST 0x00000001 /* Self Clearing */ - -#define RX_DP_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x78) -#define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */ -#define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */ - -#define RX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x7C) -#define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */ -#define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */ - -#define TX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x80) -#define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */ -#define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */ - -#define PMT_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x84) -#define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */ -#define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */ -#define PMT_CTRL_WOL_EN 0x00000200 /* R/W */ -#define PMT_CTRL_ED_EN 0x00000100 /* R/W */ -#define PMT_CTRL_PME_TYPE 0x00000040 /* R/W Not Affected by SW Reset */ -#define PMT_CTRL_WUPS 0x00000030 /* R/WC */ -#define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */ -#define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */ -#define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */ -#define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */ -#define PMT_CTRL_PME_IND 0x00000008 /* R/W */ -#define PMT_CTRL_PME_POL 0x00000004 /* R/W */ -#define PMT_CTRL_PME_EN 0x00000002 /* R/W Not Affected by SW Reset */ -#define PMT_CTRL_READY 0x00000001 /* RO */ - -#define GPIO_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x88) -#define GPIO_CFG_LED3_EN 0x40000000 /* R/W */ -#define GPIO_CFG_LED2_EN 0x20000000 /* R/W */ -#define GPIO_CFG_LED1_EN 0x10000000 /* R/W */ -#define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */ -#define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */ -#define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */ -#define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */ -#define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */ -#define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */ -#define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */ -#define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */ -#define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */ -#define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */ -#define GPIO_CFG_GPIOD4 0x00000010 /* R/W */ -#define GPIO_CFG_GPIOD3 0x00000008 /* R/W */ -#define GPIO_CFG_GPIOD2 0x00000004 /* R/W */ -#define GPIO_CFG_GPIOD1 0x00000002 /* R/W */ -#define GPIO_CFG_GPIOD0 0x00000001 /* R/W */ - -#define GPT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x8C) -#define GPT_CFG_TIMER_EN 0x20000000 /* R/W */ -#define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */ - -#define GPT_CNT (CONFIG_DRIVER_SMC911X_BASE + 0x90) -#define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */ - -#define ENDIAN (CONFIG_DRIVER_SMC911X_BASE + 0x98) -#define FREE_RUN (CONFIG_DRIVER_SMC911X_BASE + 0x9C) -#define RX_DROP (CONFIG_DRIVER_SMC911X_BASE + 0xA0) -#define MAC_CSR_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xA4) -#define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */ -#define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */ -#define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */ - -#define MAC_CSR_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xA8) -#define AFC_CFG (CONFIG_DRIVER_SMC911X_BASE + 0xAC) -#define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */ -#define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */ -#define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */ -#define AFC_CFG_FCMULT 0x00000008 /* R/W */ -#define AFC_CFG_FCBRD 0x00000004 /* R/W */ -#define AFC_CFG_FCADD 0x00000002 /* R/W */ -#define AFC_CFG_FCANY 0x00000001 /* R/W */ - -#define E2P_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xB0) -#define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */ -#define E2P_CMD_EPC_CMD 0x70000000 /* R/W */ -#define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */ -#define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */ -#define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */ -#define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */ -#define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */ -#define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */ -#define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */ -#define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */ -#define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */ -#define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */ -#define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */ - -#define E2P_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xB4) -#define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */ -/* end of LAN register offsets and bit definitions */ - -/* MAC Control and Status registers */ -#define MAC_CR 0x01 /* R/W */ - -/* MAC_CR - MAC Control Register */ -#define MAC_CR_RXALL 0x80000000 -/* TODO: delete this bit? It is not described in the data sheet. */ -#define MAC_CR_HBDIS 0x10000000 -#define MAC_CR_RCVOWN 0x00800000 -#define MAC_CR_LOOPBK 0x00200000 -#define MAC_CR_FDPX 0x00100000 -#define MAC_CR_MCPAS 0x00080000 -#define MAC_CR_PRMS 0x00040000 -#define MAC_CR_INVFILT 0x00020000 -#define MAC_CR_PASSBAD 0x00010000 -#define MAC_CR_HFILT 0x00008000 -#define MAC_CR_HPFILT 0x00002000 -#define MAC_CR_LCOLL 0x00001000 -#define MAC_CR_BCAST 0x00000800 -#define MAC_CR_DISRTY 0x00000400 -#define MAC_CR_PADSTR 0x00000100 -#define MAC_CR_BOLMT_MASK 0x000000C0 -#define MAC_CR_DFCHK 0x00000020 -#define MAC_CR_TXEN 0x00000008 -#define MAC_CR_RXEN 0x00000004 - -#define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */ -#define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */ -#define HASHH 0x04 /* R/W */ -#define HASHL 0x05 /* R/W */ - -#define MII_ACC 0x06 /* R/W */ -#define MII_ACC_PHY_ADDR 0x0000F800 -#define MII_ACC_MIIRINDA 0x000007C0 -#define MII_ACC_MII_WRITE 0x00000002 -#define MII_ACC_MII_BUSY 0x00000001 - -#define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */ - -#define FLOW 0x08 /* R/W */ -#define FLOW_FCPT 0xFFFF0000 -#define FLOW_FCPASS 0x00000004 -#define FLOW_FCEN 0x00000002 -#define FLOW_FCBSY 0x00000001 - -#define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */ -#define VLAN1_VTI1 0x0000ffff - -#define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */ -#define VLAN2_VTI2 0x0000ffff - -#define WUFF 0x0B /* WO */ - -#define WUCSR 0x0C /* R/W */ -#define WUCSR_GUE 0x00000200 -#define WUCSR_WUFR 0x00000040 -#define WUCSR_MPR 0x00000020 -#define WUCSR_WAKE_EN 0x00000004 -#define WUCSR_MPEN 0x00000002 - -/* Chip ID values */ -#define CHIP_9115 0x115 -#define CHIP_9116 0x116 -#define CHIP_9117 0x117 -#define CHIP_9118 0x118 -#define CHIP_9211 0x9211 -#define CHIP_9215 0x115a -#define CHIP_9216 0x116a -#define CHIP_9217 0x117a -#define CHIP_9218 0x118a - -struct chip_id { - u16 id; - char *name; -}; - -static const struct chip_id chip_ids[] = { - { CHIP_9115, "LAN9115" }, - { CHIP_9116, "LAN9116" }, - { CHIP_9117, "LAN9117" }, - { CHIP_9118, "LAN9118" }, - { CHIP_9211, "LAN9211" }, - { CHIP_9215, "LAN9215" }, - { CHIP_9216, "LAN9216" }, - { CHIP_9217, "LAN9217" }, - { CHIP_9218, "LAN9218" }, - { 0, NULL }, -}; - -#define DRIVERNAME "smc911x" - -u32 smc911x_get_mac_csr(u8 reg) -{ - while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) - ; - smc911x_reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg); - while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) - ; - - return smc911x_reg_read(MAC_CSR_DATA); -} - -void smc911x_set_mac_csr(u8 reg, u32 data) -{ - while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) - ; - smc911x_reg_write(MAC_CSR_DATA, data); - smc911x_reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg); - while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) - ; -} - static int smx911x_handle_mac_address(bd_t *bd) { unsigned long addrh, addrl; @@ -541,48 +146,6 @@ err_out: printf(DRIVERNAME ": autonegotiation timed out\n"); } -static void smc911x_reset(void) -{ - int timeout; - - /* Take out of PM setting first */ - if (smc911x_reg_read(PMT_CTRL) & PMT_CTRL_READY) { - /* Write to the bytetest will take out of powerdown */ - smc911x_reg_write(BYTE_TEST, 0x0); - - timeout = 10; - - while (timeout-- && !(smc911x_reg_read(PMT_CTRL) & PMT_CTRL_READY)) - udelay(10); - if (!timeout) { - printf(DRIVERNAME - ": timeout waiting for PM restore\n"); - return; - } - } - - /* Disable interrupts */ - smc911x_reg_write(INT_EN, 0); - - smc911x_reg_write(HW_CFG, HW_CFG_SRST); - - timeout = 1000; - while (timeout-- && smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY) - udelay(10); - - if (!timeout) { - printf(DRIVERNAME ": reset timeout\n"); - return; - } - - /* Reset the FIFO level and flow control settings */ - smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN); - smc911x_reg_write(AFC_CFG, 0x0050287F); - - /* Set to LED outputs */ - smc911x_reg_write(GPIO_CFG, 0x70070000); -} - static void smc911x_enable(void) { /* Enable TX */ @@ -601,26 +164,10 @@ static void smc911x_enable(void) int eth_init(bd_t *bd) { - unsigned long val, i; - printf(DRIVERNAME ": initializing\n"); - val = smc911x_reg_read(BYTE_TEST); - if (val != 0x87654321) { - printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val); + if (smc911x_detect_chip()) goto err_out; - } - - val = smc911x_reg_read(ID_REV) >> 16; - for (i = 0; chip_ids[i].id != 0; i++) { - if (chip_ids[i].id == val) break; - } - if (!chip_ids[i].id) { - printf(DRIVERNAME ": Unknown chip ID %04lx\n", val); - goto err_out; - } - - printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name); smc911x_reset(); diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h new file mode 100644 index 000000000..80d2ce0aa --- /dev/null +++ b/drivers/net/smc911x.h @@ -0,0 +1,494 @@ +/* + * SMSC LAN9[12]1[567] Network driver + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SMC911X_H_ +#define _SMC911X_H_ + +#include <linux/types.h> + +#if defined (CONFIG_DRIVER_SMC911X_32_BIT) && \ + defined (CONFIG_DRIVER_SMC911X_16_BIT) +#error "SMC911X: Only one of CONFIG_DRIVER_SMC911X_32_BIT and \ + CONFIG_DRIVER_SMC911X_16_BIT shall be set" +#endif + +#if defined (CONFIG_DRIVER_SMC911X_32_BIT) +static inline u32 __smc911x_reg_read(u32 addr) +{ + return *(volatile u32*)addr; +} +u32 smc911x_reg_read(u32 addr) __attribute__((weak, alias("__smc911x_reg_read"))); + +static inline void __smc911x_reg_write(u32 addr, u32 val) +{ + *(volatile u32*)addr = val; +} +void smc911x_reg_write(u32 addr, u32 val) __attribute__((weak, alias("__smc911x_reg_write"))); +#elif defined (CONFIG_DRIVER_SMC911X_16_BIT) +static inline u32 smc911x_reg_read(u32 addr) +{ + volatile u16 *addr_16 = (u16 *)addr; + return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16)); +} +static inline void smc911x_reg_write(u32 addr, u32 val) +{ + *(volatile u16*)addr = (u16)val; + *(volatile u16*)(addr + 2) = (u16)(val >> 16); +} +#else +#error "SMC911X: undefined bus width" +#endif /* CONFIG_DRIVER_SMC911X_16_BIT */ + +/* Below are the register offsets and bit definitions + * of the Lan911x memory space + */ +#define RX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x00) + +#define TX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x20) +#define TX_CMD_A_INT_ON_COMP 0x80000000 +#define TX_CMD_A_INT_BUF_END_ALGN 0x03000000 +#define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000 +#define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000 +#define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000 +#define TX_CMD_A_INT_DATA_OFFSET 0x001F0000 +#define TX_CMD_A_INT_FIRST_SEG 0x00002000 +#define TX_CMD_A_INT_LAST_SEG 0x00001000 +#define TX_CMD_A_BUF_SIZE 0x000007FF +#define TX_CMD_B_PKT_TAG 0xFFFF0000 +#define TX_CMD_B_ADD_CRC_DISABLE 0x00002000 +#define TX_CMD_B_DISABLE_PADDING 0x00001000 +#define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF + +#define RX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x40) +#define RX_STS_PKT_LEN 0x3FFF0000 +#define RX_STS_ES 0x00008000 +#define RX_STS_BCST 0x00002000 +#define RX_STS_LEN_ERR 0x00001000 +#define RX_STS_RUNT_ERR 0x00000800 +#define RX_STS_MCAST 0x00000400 +#define RX_STS_TOO_LONG 0x00000080 +#define RX_STS_COLL 0x00000040 +#define RX_STS_ETH_TYPE 0x00000020 +#define RX_STS_WDOG_TMT 0x00000010 +#define RX_STS_MII_ERR 0x00000008 +#define RX_STS_DRIBBLING 0x00000004 +#define RX_STS_CRC_ERR 0x00000002 +#define RX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x44) +#define TX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x48) +#define TX_STS_TAG 0xFFFF0000 +#define TX_STS_ES 0x00008000 +#define TX_STS_LOC 0x00000800 +#define TX_STS_NO_CARR 0x00000400 +#define TX_STS_LATE_COLL 0x00000200 +#define TX_STS_MANY_COLL 0x00000100 +#define TX_STS_COLL_CNT 0x00000078 +#define TX_STS_MANY_DEFER 0x00000004 +#define TX_STS_UNDERRUN 0x00000002 +#define TX_STS_DEFERRED 0x00000001 +#define TX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x4C) +#define ID_REV (CONFIG_DRIVER_SMC911X_BASE + 0x50) +#define ID_REV_CHIP_ID 0xFFFF0000 /* RO */ +#define ID_REV_REV_ID 0x0000FFFF /* RO */ + +#define INT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x54) +#define INT_CFG_INT_DEAS 0xFF000000 /* R/W */ +#define INT_CFG_INT_DEAS_CLR 0x00004000 +#define INT_CFG_INT_DEAS_STS 0x00002000 +#define INT_CFG_IRQ_INT 0x00001000 /* RO */ +#define INT_CFG_IRQ_EN 0x00000100 /* R/W */ +#define INT_CFG_IRQ_POL 0x00000010 /* R/W Not Affected by SW Reset */ +#define INT_CFG_IRQ_TYPE 0x00000001 /* R/W Not Affected by SW Reset */ + +#define INT_STS (CONFIG_DRIVER_SMC911X_BASE + 0x58) +#define INT_STS_SW_INT 0x80000000 /* R/WC */ +#define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */ +#define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */ +#define INT_STS_RXDFH_INT 0x00800000 /* R/WC */ +#define INT_STS_RXDF_INT 0x00400000 /* R/WC */ +#define INT_STS_TX_IOC 0x00200000 /* R/WC */ +#define INT_STS_RXD_INT 0x00100000 /* R/WC */ +#define INT_STS_GPT_INT 0x00080000 /* R/WC */ +#define INT_STS_PHY_INT 0x00040000 /* RO */ +#define INT_STS_PME_INT 0x00020000 /* R/WC */ +#define INT_STS_TXSO 0x00010000 /* R/WC */ +#define INT_STS_RWT 0x00008000 /* R/WC */ +#define INT_STS_RXE 0x00004000 /* R/WC */ +#define INT_STS_TXE 0x00002000 /* R/WC */ +/*#define INT_STS_ERX 0x00001000*/ /* R/WC */ +#define INT_STS_TDFU 0x00000800 /* R/WC */ +#define INT_STS_TDFO 0x00000400 /* R/WC */ +#define INT_STS_TDFA 0x00000200 /* R/WC */ +#define INT_STS_TSFF 0x00000100 /* R/WC */ +#define INT_STS_TSFL 0x00000080 /* R/WC */ +/*#define INT_STS_RXDF 0x00000040*/ /* R/WC */ +#define INT_STS_RDFO 0x00000040 /* R/WC */ +#define INT_STS_RDFL 0x00000020 /* R/WC */ +#define INT_STS_RSFF 0x00000010 /* R/WC */ +#define INT_STS_RSFL 0x00000008 /* R/WC */ +#define INT_STS_GPIO2_INT 0x00000004 /* R/WC */ +#define INT_STS_GPIO1_INT 0x00000002 /* R/WC */ +#define INT_STS_GPIO0_INT 0x00000001 /* R/WC */ +#define INT_EN (CONFIG_DRIVER_SMC911X_BASE + 0x5C) +#define INT_EN_SW_INT_EN 0x80000000 /* R/W */ +#define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */ +#define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */ +#define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */ +/*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */ +#define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */ +#define INT_EN_RXD_INT_EN 0x00100000 /* R/W */ +#define INT_EN_GPT_INT_EN 0x00080000 /* R/W */ +#define INT_EN_PHY_INT_EN 0x00040000 /* R/W */ +#define INT_EN_PME_INT_EN 0x00020000 /* R/W */ +#define INT_EN_TXSO_EN 0x00010000 /* R/W */ +#define INT_EN_RWT_EN 0x00008000 /* R/W */ +#define INT_EN_RXE_EN 0x00004000 /* R/W */ +#define INT_EN_TXE_EN 0x00002000 /* R/W */ +/*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */ +#define INT_EN_TDFU_EN 0x00000800 /* R/W */ +#define INT_EN_TDFO_EN 0x00000400 /* R/W */ +#define INT_EN_TDFA_EN 0x00000200 /* R/W */ +#define INT_EN_TSFF_EN 0x00000100 /* R/W */ +#define INT_EN_TSFL_EN 0x00000080 /* R/W */ +/*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */ +#define INT_EN_RDFO_EN 0x00000040 /* R/W */ +#define INT_EN_RDFL_EN 0x00000020 /* R/W */ +#define INT_EN_RSFF_EN 0x00000010 /* R/W */ +#define INT_EN_RSFL_EN 0x00000008 /* R/W */ +#define INT_EN_GPIO2_INT 0x00000004 /* R/W */ +#define INT_EN_GPIO1_INT 0x00000002 /* R/W */ +#define INT_EN_GPIO0_INT 0x00000001 /* R/W */ + +#define BYTE_TEST (CONFIG_DRIVER_SMC911X_BASE + 0x64) +#define FIFO_INT (CONFIG_DRIVER_SMC911X_BASE + 0x68) +#define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */ +#define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */ +#define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */ +#define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */ + +#define RX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x6C) +#define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */ +#define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */ +#define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */ +#define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */ +#define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */ +#define RX_CFG_RX_DUMP 0x00008000 /* R/W */ +#define RX_CFG_RXDOFF 0x00001F00 /* R/W */ +/*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */ + +#define TX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x70) +/*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */ +/*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/ /* R/W Self Clearing */ +#define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */ +#define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */ +#define TX_CFG_TXSAO 0x00000004 /* R/W */ +#define TX_CFG_TX_ON 0x00000002 /* R/W */ +#define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */ + +#define HW_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x74) +#define HW_CFG_TTM 0x00200000 /* R/W */ +#define HW_CFG_SF 0x00100000 /* R/W */ +#define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */ +#define HW_CFG_TR 0x00003000 /* R/W */ +#define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */ +#define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */ +#define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */ +#define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */ +#define HW_CFG_SMI_SEL 0x00000010 /* R/W */ +#define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */ +#define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */ +#define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */ +#define HW_CFG_SRST_TO 0x00000002 /* RO */ +#define HW_CFG_SRST 0x00000001 /* Self Clearing */ + +#define RX_DP_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x78) +#define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */ +#define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */ + +#define RX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x7C) +#define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */ +#define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */ + +#define TX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x80) +#define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */ +#define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */ + +#define PMT_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x84) +#define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */ +#define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */ +#define PMT_CTRL_WOL_EN 0x00000200 /* R/W */ +#define PMT_CTRL_ED_EN 0x00000100 /* R/W */ +#define PMT_CTRL_PME_TYPE 0x00000040 /* R/W Not Affected by SW Reset */ +#define PMT_CTRL_WUPS 0x00000030 /* R/WC */ +#define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */ +#define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */ +#define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */ +#define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */ +#define PMT_CTRL_PME_IND 0x00000008 /* R/W */ +#define PMT_CTRL_PME_POL 0x00000004 /* R/W */ +#define PMT_CTRL_PME_EN 0x00000002 /* R/W Not Affected by SW Reset */ +#define PMT_CTRL_READY 0x00000001 /* RO */ + +#define GPIO_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x88) +#define GPIO_CFG_LED3_EN 0x40000000 /* R/W */ +#define GPIO_CFG_LED2_EN 0x20000000 /* R/W */ +#define GPIO_CFG_LED1_EN 0x10000000 /* R/W */ +#define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */ +#define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */ +#define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */ +#define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */ +#define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */ +#define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */ +#define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */ +#define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */ +#define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */ +#define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */ +#define GPIO_CFG_GPIOD4 0x00000010 /* R/W */ +#define GPIO_CFG_GPIOD3 0x00000008 /* R/W */ +#define GPIO_CFG_GPIOD2 0x00000004 /* R/W */ +#define GPIO_CFG_GPIOD1 0x00000002 /* R/W */ +#define GPIO_CFG_GPIOD0 0x00000001 /* R/W */ + +#define GPT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x8C) +#define GPT_CFG_TIMER_EN 0x20000000 /* R/W */ +#define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */ + +#define GPT_CNT (CONFIG_DRIVER_SMC911X_BASE + 0x90) +#define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */ + +#define ENDIAN (CONFIG_DRIVER_SMC911X_BASE + 0x98) +#define FREE_RUN (CONFIG_DRIVER_SMC911X_BASE + 0x9C) +#define RX_DROP (CONFIG_DRIVER_SMC911X_BASE + 0xA0) +#define MAC_CSR_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xA4) +#define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */ +#define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */ +#define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */ + +#define MAC_CSR_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xA8) +#define AFC_CFG (CONFIG_DRIVER_SMC911X_BASE + 0xAC) +#define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */ +#define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */ +#define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */ +#define AFC_CFG_FCMULT 0x00000008 /* R/W */ +#define AFC_CFG_FCBRD 0x00000004 /* R/W */ +#define AFC_CFG_FCADD 0x00000002 /* R/W */ +#define AFC_CFG_FCANY 0x00000001 /* R/W */ + +#define E2P_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xB0) +#define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */ +#define E2P_CMD_EPC_CMD 0x70000000 /* R/W */ +#define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */ +#define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */ +#define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */ +#define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */ +#define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */ +#define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */ +#define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */ +#define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */ +#define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */ +#define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */ +#define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */ + +#define E2P_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xB4) +#define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */ +/* end of LAN register offsets and bit definitions */ + +/* MAC Control and Status registers */ +#define MAC_CR 0x01 /* R/W */ + +/* MAC_CR - MAC Control Register */ +#define MAC_CR_RXALL 0x80000000 +/* TODO: delete this bit? It is not described in the data sheet. */ +#define MAC_CR_HBDIS 0x10000000 +#define MAC_CR_RCVOWN 0x00800000 +#define MAC_CR_LOOPBK 0x00200000 +#define MAC_CR_FDPX 0x00100000 +#define MAC_CR_MCPAS 0x00080000 +#define MAC_CR_PRMS 0x00040000 +#define MAC_CR_INVFILT 0x00020000 +#define MAC_CR_PASSBAD 0x00010000 +#define MAC_CR_HFILT 0x00008000 +#define MAC_CR_HPFILT 0x00002000 +#define MAC_CR_LCOLL 0x00001000 +#define MAC_CR_BCAST 0x00000800 +#define MAC_CR_DISRTY 0x00000400 +#define MAC_CR_PADSTR 0x00000100 +#define MAC_CR_BOLMT_MASK 0x000000C0 +#define MAC_CR_DFCHK 0x00000020 +#define MAC_CR_TXEN 0x00000008 +#define MAC_CR_RXEN 0x00000004 + +#define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */ +#define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */ +#define HASHH 0x04 /* R/W */ +#define HASHL 0x05 /* R/W */ + +#define MII_ACC 0x06 /* R/W */ +#define MII_ACC_PHY_ADDR 0x0000F800 +#define MII_ACC_MIIRINDA 0x000007C0 +#define MII_ACC_MII_WRITE 0x00000002 +#define MII_ACC_MII_BUSY 0x00000001 + +#define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */ + +#define FLOW 0x08 /* R/W */ +#define FLOW_FCPT 0xFFFF0000 +#define FLOW_FCPASS 0x00000004 +#define FLOW_FCEN 0x00000002 +#define FLOW_FCBSY 0x00000001 + +#define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */ +#define VLAN1_VTI1 0x0000ffff + +#define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */ +#define VLAN2_VTI2 0x0000ffff + +#define WUFF 0x0B /* WO */ + +#define WUCSR 0x0C /* R/W */ +#define WUCSR_GUE 0x00000200 +#define WUCSR_WUFR 0x00000040 +#define WUCSR_MPR 0x00000020 +#define WUCSR_WAKE_EN 0x00000004 +#define WUCSR_MPEN 0x00000002 + +/* Chip ID values */ +#define CHIP_9115 0x115 +#define CHIP_9116 0x116 +#define CHIP_9117 0x117 +#define CHIP_9118 0x118 +#define CHIP_9211 0x9211 +#define CHIP_9215 0x115a +#define CHIP_9216 0x116a +#define CHIP_9217 0x117a +#define CHIP_9218 0x118a + +struct chip_id { + u16 id; + char *name; +}; + +static const struct chip_id chip_ids[] = { + { CHIP_9115, "LAN9115" }, + { CHIP_9116, "LAN9116" }, + { CHIP_9117, "LAN9117" }, + { CHIP_9118, "LAN9118" }, + { CHIP_9211, "LAN9211" }, + { CHIP_9215, "LAN9215" }, + { CHIP_9216, "LAN9216" }, + { CHIP_9217, "LAN9217" }, + { CHIP_9218, "LAN9218" }, + { 0, NULL }, +}; + + +#define DRIVERNAME "smc911x" + +static u32 smc911x_get_mac_csr(u8 reg) +{ + while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; + smc911x_reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg); + while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; + + return smc911x_reg_read(MAC_CSR_DATA); +} + +static void smc911x_set_mac_csr(u8 reg, u32 data) +{ + while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; + smc911x_reg_write(MAC_CSR_DATA, data); + smc911x_reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg); + while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; +} + +static int smc911x_detect_chip(void) +{ + unsigned long val, i; + + val = smc911x_reg_read(BYTE_TEST); + if (val != 0x87654321) { + printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val); + return -1; + } + + val = smc911x_reg_read(ID_REV) >> 16; + for (i = 0; chip_ids[i].id != 0; i++) { + if (chip_ids[i].id == val) break; + } + if (!chip_ids[i].id) { + printf(DRIVERNAME ": Unknown chip ID %04lx\n", val); + return -1; + } + + printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name); + + return 0; +} + +static void smc911x_reset(void) +{ + int timeout; + + /* Take out of PM setting first */ + if (smc911x_reg_read(PMT_CTRL) & PMT_CTRL_READY) { + /* Write to the bytetest will take out of powerdown */ + smc911x_reg_write(BYTE_TEST, 0x0); + + timeout = 10; + + while (timeout-- && !(smc911x_reg_read(PMT_CTRL) & PMT_CTRL_READY)) + udelay(10); + if (!timeout) { + printf(DRIVERNAME + ": timeout waiting for PM restore\n"); + return; + } + } + + /* Disable interrupts */ + smc911x_reg_write(INT_EN, 0); + + smc911x_reg_write(HW_CFG, HW_CFG_SRST); + + timeout = 1000; + while (timeout-- && smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY) + udelay(10); + + if (!timeout) { + printf(DRIVERNAME ": reset timeout\n"); + return; + } + + /* Reset the FIFO level and flow control settings */ + smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN); + smc911x_reg_write(AFC_CFG, 0x0050287F); + + /* Set to LED outputs */ + smc911x_reg_write(GPIO_CFG, 0x70070000); +} + +#endif diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 9edba6a7b..1f5d1b44a 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -1332,6 +1332,35 @@ struct phy_info phy_info_cis8201 = { {miim_end,} }, }; +struct phy_info phy_info_VSC8211 = { + 0xfc4b, + "Vitesse VSC8211", + 4, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + {MIIM_CIS8201_AUX_CONSTAT, + MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, + /* Set up the interface mode */ + {MIIM_CIS8201_EXT_CON1, + MIIM_CIS8201_EXTCON1_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_CIS8201_AUX_CONSTAT, miim_read, + &mii_parse_cis8201}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; struct phy_info phy_info_VSC8244 = { 0x3f1b, "Vitesse VSC8244", @@ -1590,6 +1619,7 @@ struct phy_info *phy_info[] = { &phy_info_M88E1149S, &phy_info_dm9161, &phy_info_lxt971, + &phy_info_VSC8211, &phy_info_VSC8244, &phy_info_VSC8601, &phy_info_dp83865, diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 5957ada3a..fad98403a 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -21,6 +21,7 @@ #include <common.h> #include <malloc.h> #include <spi.h> +#include <asm/errno.h> #include <asm/io.h> #ifdef CONFIG_MX27 @@ -32,6 +33,8 @@ #else +#include <asm/arch/mx31.h> + #define MXC_CSPIRXDATA 0x00 #define MXC_CSPITXDATA 0x04 #define MXC_CSPICTRL 0x08 @@ -68,6 +71,7 @@ struct mxc_spi_slave { struct spi_slave slave; unsigned long base; u32 ctrl_reg; + int gpio; }; static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) @@ -85,26 +89,33 @@ static inline void reg_write(unsigned long addr, u32 val) *(volatile unsigned long*)addr = val; } -static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen) +static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen, + unsigned long flags) { struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL); - if (MXC_CSPICTRL_BITCOUNT(bitlen - 1) != (cfg_reg & MXC_CSPICTRL_BITCOUNT(31))) { - cfg_reg = (cfg_reg & ~MXC_CSPICTRL_BITCOUNT(31)) | - MXC_CSPICTRL_BITCOUNT(bitlen - 1); - reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg); - } + mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(31)) | + MXC_CSPICTRL_BITCOUNT(bitlen - 1); - reg_write(mxcs->base + MXC_CSPITXDATA, data); + if (cfg_reg != mxcs->ctrl_reg) + reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg); - cfg_reg |= MXC_CSPICTRL_XCH; + if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN)) + mx31_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL); - reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg); + reg_write(mxcs->base + MXC_CSPITXDATA, data); + + reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_XCH); while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH) ; + if (mxcs->gpio > 0 && (flags & SPI_XFER_END)) { + mx31_gpio_set(mxcs->gpio, + !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL)); + } + return reg_read(mxcs->base + MXC_CSPIRXDATA); } @@ -122,8 +133,17 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout; i < n_blks; - i++, in_l++, out_l++, bitlen -= 32) - *in_l = spi_xchg_single(slave, *out_l, bitlen); + i++, in_l++, out_l++, bitlen -= 32) { + u32 data = spi_xchg_single(slave, *out_l, bitlen, flags); + + /* Check if we're only transfering 8 or 16 bits */ + if (!i) { + if (bitlen < 9) + *(u8 *)din = data; + else if (bitlen < 17) + *(u16 *)din = data; + } + } return 0; } @@ -132,16 +152,55 @@ void spi_init(void) { } +static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) +{ + int ret; + + /* + * Some SPI devices require active chip-select over multiple + * transactions, we achieve this using a GPIO. Still, the SPI + * controller has to be configured to use one of its own chipselects. + * To use this feature you have to call spi_setup_slave() with + * cs = internal_cs | (gpio << 8), and you have to use some unused + * on this SPI controller cs between 0 and 3. + */ + if (cs > 3) { + mxcs->gpio = cs >> 8; + cs &= 3; + ret = mx31_gpio_direction(mxcs->gpio, MX31_GPIO_DIRECTION_OUT); + if (ret) { + printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); + return -EINVAL; + } + } else { + mxcs->gpio = -1; + } + + return cs; +} + struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { unsigned int ctrl_reg; struct mxc_spi_slave *mxcs; + int ret; - if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]) || - cs > 3) + if (bus >= ARRAY_SIZE(spi_bases)) return NULL; + mxcs = malloc(sizeof(struct mxc_spi_slave)); + if (!mxcs) + return NULL; + + ret = decode_cs(mxcs, cs); + if (ret < 0) { + free(mxcs); + return NULL; + } + + cs = ret; + ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | MXC_CSPICTRL_BITCOUNT(31) | MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */ @@ -155,10 +214,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (mode & SPI_CS_HIGH) ctrl_reg |= MXC_CSPICTRL_SSPOL; - mxcs = malloc(sizeof(struct mxc_spi_slave)); - if (!mxcs) - return NULL; - mxcs->slave.bus = bus; mxcs->slave.cs = cs; mxcs->base = spi_bases[bus]; @@ -169,7 +224,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, void spi_free_slave(struct spi_slave *slave) { - free(slave); + struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); + + free(mxcs); } int spi_claim_bus(struct spi_slave *slave) diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 7fba29fbc..bc0085269 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -28,8 +28,10 @@ LIB := $(obj)libvideo.a COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o +COBJS-$(CONFIG_S6E63D6) += s6e63d6.o COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o +COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o COBJS-$(CONFIG_SED156X) += sed156x.o COBJS-$(CONFIG_VIDEO_SM501) += sm501.o diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c new file mode 100644 index 000000000..1e1d50765 --- /dev/null +++ b/drivers/video/mx3fb.c @@ -0,0 +1,856 @@ +/* + * Copyright (C) 2009 + * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <lcd.h> +#include <asm/arch/mx31.h> +#include <asm/arch/mx31-regs.h> +#include <asm/errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; + +short console_col; +short console_row; + +void lcd_initcolregs(void) +{ +} + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ +} + +void lcd_disable(void) +{ +} + +void lcd_panel_disable(void) +{ +} + +#define msleep(a) udelay(a * 1000) + +#define XRES 240 +#define YRES 320 +#define PANEL_TYPE IPU_PANEL_TFT +#define PIXEL_CLK 185925 +#define PIXEL_FMT IPU_PIX_FMT_RGB666 +#define H_START_WIDTH 9 /* left_margin */ +#define H_SYNC_WIDTH 1 /* hsync_len */ +#define H_END_WIDTH (16 + 1) /* right_margin + hsync_len */ +#define V_START_WIDTH 7 /* upper_margin */ +#define V_SYNC_WIDTH 1 /* vsync_len */ +#define V_END_WIDTH (9 + 1) /* lower_margin + vsync_len */ +#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) +#define IF_CONF 0 +#define IF_CLK_DIV 0x175 + +#define LCD_COLOR_IPU LCD_COLOR16 + +static ushort colormap[256]; + +vidinfo_t panel_info = { + .vl_col = XRES, + .vl_row = YRES, + .vl_bpix = LCD_COLOR_IPU, + .cmap = colormap, +}; + +#define BIT_PER_PIXEL NBITS(LCD_COLOR_IPU) + +/* IPU DMA Controller channel definitions. */ +enum ipu_channel { + IDMAC_IC_0 = 0, /* IC (encoding task) to memory */ + IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */ + IDMAC_ADC_0 = 1, + IDMAC_IC_2 = 2, + IDMAC_ADC_1 = 2, + IDMAC_IC_3 = 3, + IDMAC_IC_4 = 4, + IDMAC_IC_5 = 5, + IDMAC_IC_6 = 6, + IDMAC_IC_7 = 7, /* IC (sensor data) to memory */ + IDMAC_IC_8 = 8, + IDMAC_IC_9 = 9, + IDMAC_IC_10 = 10, + IDMAC_IC_11 = 11, + IDMAC_IC_12 = 12, + IDMAC_IC_13 = 13, + IDMAC_SDC_0 = 14, /* Background synchronous display data */ + IDMAC_SDC_1 = 15, /* Foreground data (overlay) */ + IDMAC_SDC_2 = 16, + IDMAC_SDC_3 = 17, + IDMAC_ADC_2 = 18, + IDMAC_ADC_3 = 19, + IDMAC_ADC_4 = 20, + IDMAC_ADC_5 = 21, + IDMAC_ADC_6 = 22, + IDMAC_ADC_7 = 23, + IDMAC_PF_0 = 24, + IDMAC_PF_1 = 25, + IDMAC_PF_2 = 26, + IDMAC_PF_3 = 27, + IDMAC_PF_4 = 28, + IDMAC_PF_5 = 29, + IDMAC_PF_6 = 30, + IDMAC_PF_7 = 31, +}; + +/* More formats can be copied from the Linux driver if needed */ +enum pixel_fmt { + /* 2 bytes */ + IPU_PIX_FMT_RGB565, + IPU_PIX_FMT_RGB666, + IPU_PIX_FMT_BGR666, + /* 3 bytes */ + IPU_PIX_FMT_RGB24, +}; + +struct pixel_fmt_cfg { + u32 b0; + u32 b1; + u32 b2; + u32 acc; +}; + +static struct pixel_fmt_cfg fmt_cfg[] = { + [IPU_PIX_FMT_RGB24] = { + 0x1600AAAA, 0x00E05555, 0x00070000, 3, + }, + [IPU_PIX_FMT_RGB666] = { + 0x0005000F, 0x000B000F, 0x0011000F, 1, + }, + [IPU_PIX_FMT_BGR666] = { + 0x0011000F, 0x000B000F, 0x0005000F, 1, + }, + [IPU_PIX_FMT_RGB565] = { + 0x0004003F, 0x000A000F, 0x000F003F, 1, + } +}; + +enum ipu_panel { + IPU_PANEL_SHARP_TFT, + IPU_PANEL_TFT, +}; + +/* IPU Common registers */ +/* IPU_CONF and its bits already defined in mx31-regs.h */ +#define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE) +#define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE) +#define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE) +#define IPU_CHA_CUR_BUF (0x10 + IPU_BASE) +#define IPU_FS_PROC_FLOW (0x14 + IPU_BASE) +#define IPU_FS_DISP_FLOW (0x18 + IPU_BASE) +#define IPU_TASKS_STAT (0x1C + IPU_BASE) +#define IPU_IMA_ADDR (0x20 + IPU_BASE) +#define IPU_IMA_DATA (0x24 + IPU_BASE) +#define IPU_INT_CTRL_1 (0x28 + IPU_BASE) +#define IPU_INT_CTRL_2 (0x2C + IPU_BASE) +#define IPU_INT_CTRL_3 (0x30 + IPU_BASE) +#define IPU_INT_CTRL_4 (0x34 + IPU_BASE) +#define IPU_INT_CTRL_5 (0x38 + IPU_BASE) +#define IPU_INT_STAT_1 (0x3C + IPU_BASE) +#define IPU_INT_STAT_2 (0x40 + IPU_BASE) +#define IPU_INT_STAT_3 (0x44 + IPU_BASE) +#define IPU_INT_STAT_4 (0x48 + IPU_BASE) +#define IPU_INT_STAT_5 (0x4C + IPU_BASE) +#define IPU_BRK_CTRL_1 (0x50 + IPU_BASE) +#define IPU_BRK_CTRL_2 (0x54 + IPU_BASE) +#define IPU_BRK_STAT (0x58 + IPU_BASE) +#define IPU_DIAGB_CTRL (0x5C + IPU_BASE) + +/* Image Converter Registers */ +#define IC_CONF (0x88 + IPU_BASE) +#define IC_PRP_ENC_RSC (0x8C + IPU_BASE) +#define IC_PRP_VF_RSC (0x90 + IPU_BASE) +#define IC_PP_RSC (0x94 + IPU_BASE) +#define IC_CMBP_1 (0x98 + IPU_BASE) +#define IC_CMBP_2 (0x9C + IPU_BASE) +#define PF_CONF (0xA0 + IPU_BASE) +#define IDMAC_CONF (0xA4 + IPU_BASE) +#define IDMAC_CHA_EN (0xA8 + IPU_BASE) +#define IDMAC_CHA_PRI (0xAC + IPU_BASE) +#define IDMAC_CHA_BUSY (0xB0 + IPU_BASE) + +/* Image Converter Register bits */ +#define IC_CONF_PRPENC_EN 0x00000001 +#define IC_CONF_PRPENC_CSC1 0x00000002 +#define IC_CONF_PRPENC_ROT_EN 0x00000004 +#define IC_CONF_PRPVF_EN 0x00000100 +#define IC_CONF_PRPVF_CSC1 0x00000200 +#define IC_CONF_PRPVF_CSC2 0x00000400 +#define IC_CONF_PRPVF_CMB 0x00000800 +#define IC_CONF_PRPVF_ROT_EN 0x00001000 +#define IC_CONF_PP_EN 0x00010000 +#define IC_CONF_PP_CSC1 0x00020000 +#define IC_CONF_PP_CSC2 0x00040000 +#define IC_CONF_PP_CMB 0x00080000 +#define IC_CONF_PP_ROT_EN 0x00100000 +#define IC_CONF_IC_GLB_LOC_A 0x10000000 +#define IC_CONF_KEY_COLOR_EN 0x20000000 +#define IC_CONF_RWS_EN 0x40000000 +#define IC_CONF_CSI_MEM_WR_EN 0x80000000 + +/* SDC Registers */ +#define SDC_COM_CONF (0xB4 + IPU_BASE) +#define SDC_GW_CTRL (0xB8 + IPU_BASE) +#define SDC_FG_POS (0xBC + IPU_BASE) +#define SDC_BG_POS (0xC0 + IPU_BASE) +#define SDC_CUR_POS (0xC4 + IPU_BASE) +#define SDC_PWM_CTRL (0xC8 + IPU_BASE) +#define SDC_CUR_MAP (0xCC + IPU_BASE) +#define SDC_HOR_CONF (0xD0 + IPU_BASE) +#define SDC_VER_CONF (0xD4 + IPU_BASE) +#define SDC_SHARP_CONF_1 (0xD8 + IPU_BASE) +#define SDC_SHARP_CONF_2 (0xDC + IPU_BASE) + +/* Register bits */ +#define SDC_COM_TFT_COLOR 0x00000001UL +#define SDC_COM_FG_EN 0x00000010UL +#define SDC_COM_GWSEL 0x00000020UL +#define SDC_COM_GLB_A 0x00000040UL +#define SDC_COM_KEY_COLOR_G 0x00000080UL +#define SDC_COM_BG_EN 0x00000200UL +#define SDC_COM_SHARP 0x00001000UL + +#define SDC_V_SYNC_WIDTH_L 0x00000001UL + +/* Display Interface registers */ +#define DI_DISP_IF_CONF (0x0124 + IPU_BASE) +#define DI_DISP_SIG_POL (0x0128 + IPU_BASE) +#define DI_SER_DISP1_CONF (0x012C + IPU_BASE) +#define DI_SER_DISP2_CONF (0x0130 + IPU_BASE) +#define DI_HSP_CLK_PER (0x0134 + IPU_BASE) +#define DI_DISP0_TIME_CONF_1 (0x0138 + IPU_BASE) +#define DI_DISP0_TIME_CONF_2 (0x013C + IPU_BASE) +#define DI_DISP0_TIME_CONF_3 (0x0140 + IPU_BASE) +#define DI_DISP1_TIME_CONF_1 (0x0144 + IPU_BASE) +#define DI_DISP1_TIME_CONF_2 (0x0148 + IPU_BASE) +#define DI_DISP1_TIME_CONF_3 (0x014C + IPU_BASE) +#define DI_DISP2_TIME_CONF_1 (0x0150 + IPU_BASE) +#define DI_DISP2_TIME_CONF_2 (0x0154 + IPU_BASE) +#define DI_DISP2_TIME_CONF_3 (0x0158 + IPU_BASE) +#define DI_DISP3_TIME_CONF (0x015C + IPU_BASE) +#define DI_DISP0_DB0_MAP (0x0160 + IPU_BASE) +#define DI_DISP0_DB1_MAP (0x0164 + IPU_BASE) +#define DI_DISP0_DB2_MAP (0x0168 + IPU_BASE) +#define DI_DISP0_CB0_MAP (0x016C + IPU_BASE) +#define DI_DISP0_CB1_MAP (0x0170 + IPU_BASE) +#define DI_DISP0_CB2_MAP (0x0174 + IPU_BASE) +#define DI_DISP1_DB0_MAP (0x0178 + IPU_BASE) +#define DI_DISP1_DB1_MAP (0x017C + IPU_BASE) +#define DI_DISP1_DB2_MAP (0x0180 + IPU_BASE) +#define DI_DISP1_CB0_MAP (0x0184 + IPU_BASE) +#define DI_DISP1_CB1_MAP (0x0188 + IPU_BASE) +#define DI_DISP1_CB2_MAP (0x018C + IPU_BASE) +#define DI_DISP2_DB0_MAP (0x0190 + IPU_BASE) +#define DI_DISP2_DB1_MAP (0x0194 + IPU_BASE) +#define DI_DISP2_DB2_MAP (0x0198 + IPU_BASE) +#define DI_DISP2_CB0_MAP (0x019C + IPU_BASE) +#define DI_DISP2_CB1_MAP (0x01A0 + IPU_BASE) +#define DI_DISP2_CB2_MAP (0x01A4 + IPU_BASE) +#define DI_DISP3_B0_MAP (0x01A8 + IPU_BASE) +#define DI_DISP3_B1_MAP (0x01AC + IPU_BASE) +#define DI_DISP3_B2_MAP (0x01B0 + IPU_BASE) +#define DI_DISP_ACC_CC (0x01B4 + IPU_BASE) +#define DI_DISP_LLA_CONF (0x01B8 + IPU_BASE) +#define DI_DISP_LLA_DATA (0x01BC + IPU_BASE) + +/* DI_DISP_SIG_POL bits */ +#define DI_D3_VSYNC_POL (1 << 28) +#define DI_D3_HSYNC_POL (1 << 27) +#define DI_D3_DRDY_SHARP_POL (1 << 26) +#define DI_D3_CLK_POL (1 << 25) +#define DI_D3_DATA_POL (1 << 24) + +/* DI_DISP_IF_CONF bits */ +#define DI_D3_CLK_IDLE (1 << 26) +#define DI_D3_CLK_SEL (1 << 25) +#define DI_D3_DATAMSK (1 << 24) + +#define IOMUX_PADNUM_MASK 0x1ff +#define IOMUX_GPIONUM_SHIFT 9 +#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT) + +#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) + +#define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode) + +enum lcd_pin { + MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), + MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), + MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), + MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), + MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), + + MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), + MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), + MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), + + MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), + MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), + MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), + MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), + MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), + MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), + MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), + MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), + MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), + MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), + MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), + MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), + MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), + MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), + MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), + MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), + MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), + MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), +}; + +struct chan_param_mem_planar { + /* Word 0 */ + u32 xv:10; + u32 yv:10; + u32 xb:12; + + u32 yb:12; + u32 res1:2; + u32 nsb:1; + u32 lnpb:6; + u32 ubo_l:11; + + u32 ubo_h:15; + u32 vbo_l:17; + + u32 vbo_h:9; + u32 res2:3; + u32 fw:12; + u32 fh_l:8; + + u32 fh_h:4; + u32 res3:28; + + /* Word 1 */ + u32 eba0; + + u32 eba1; + + u32 bpp:3; + u32 sl:14; + u32 pfs:3; + u32 bam:3; + u32 res4:2; + u32 npb:6; + u32 res5:1; + + u32 sat:2; + u32 res6:30; +} __attribute__ ((packed)); + +struct chan_param_mem_interleaved { + /* Word 0 */ + u32 xv:10; + u32 yv:10; + u32 xb:12; + + u32 yb:12; + u32 sce:1; + u32 res1:1; + u32 nsb:1; + u32 lnpb:6; + u32 sx:10; + u32 sy_l:1; + + u32 sy_h:9; + u32 ns:10; + u32 sm:10; + u32 sdx_l:3; + + u32 sdx_h:2; + u32 sdy:5; + u32 sdrx:1; + u32 sdry:1; + u32 sdr1:1; + u32 res2:2; + u32 fw:12; + u32 fh_l:8; + + u32 fh_h:4; + u32 res3:28; + + /* Word 1 */ + u32 eba0; + + u32 eba1; + + u32 bpp:3; + u32 sl:14; + u32 pfs:3; + u32 bam:3; + u32 res4:2; + u32 npb:6; + u32 res5:1; + + u32 sat:2; + u32 scc:1; + u32 ofs0:5; + u32 ofs1:5; + u32 ofs2:5; + u32 ofs3:5; + u32 wid0:3; + u32 wid1:3; + u32 wid2:3; + + u32 wid3:3; + u32 dec_sel:1; + u32 res6:28; +} __attribute__ ((packed)); + +union chan_param_mem { + struct chan_param_mem_planar pp; + struct chan_param_mem_interleaved ip; +}; + +static inline u32 reg_read(unsigned long reg) +{ + return __REG(reg); +} + +static inline void reg_write(u32 value, unsigned long reg) +{ + __REG(reg) = value; +} + +/* + * sdc_init_panel() - initialize a synchronous LCD panel. + * @width: width of panel in pixels. + * @height: height of panel in pixels. + * @pixel_fmt: pixel format of buffer as FOURCC ASCII code. + * @return: 0 on success or negative error code on failure. + */ +static int sdc_init_panel(u16 width, u16 height, enum pixel_fmt pixel_fmt) +{ + u32 reg; + uint32_t old_conf; + + /* Init panel size and blanking periods */ + reg = ((H_SYNC_WIDTH - 1) << 26) | + ((u32)(width + H_START_WIDTH + H_END_WIDTH - 1) << 16); + reg_write(reg, SDC_HOR_CONF); + + reg = ((V_SYNC_WIDTH - 1) << 26) | SDC_V_SYNC_WIDTH_L | + ((u32)(height + V_START_WIDTH + V_END_WIDTH - 1) << 16); + reg_write(reg, SDC_VER_CONF); + + switch (PANEL_TYPE) { + case IPU_PANEL_SHARP_TFT: + reg_write(0x00FD0102L, SDC_SHARP_CONF_1); + reg_write(0x00F500F4L, SDC_SHARP_CONF_2); + reg_write(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF); + break; + case IPU_PANEL_TFT: + reg_write(SDC_COM_TFT_COLOR, SDC_COM_CONF); + break; + default: + return -EINVAL; + } + + /* Init clocking */ + + /* + * Calculate divider: fractional part is 4 bits so simply multiple by + * 2^4 to get fractional part, as long as we stay under ~250MHz and on + * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz + */ + + reg_write((((IF_CLK_DIV / 8) - 1) << 22) | + IF_CLK_DIV, DI_DISP3_TIME_CONF); + + /* DI settings */ + old_conf = reg_read(DI_DISP_IF_CONF) & 0x78FFFFFF; + reg_write(old_conf | IF_CONF, DI_DISP_IF_CONF); + + old_conf = reg_read(DI_DISP_SIG_POL) & 0xE0FFFFFF; + reg_write(old_conf | SIG_POL, DI_DISP_SIG_POL); + + reg_write(fmt_cfg[pixel_fmt].b0, DI_DISP3_B0_MAP); + reg_write(fmt_cfg[pixel_fmt].b1, DI_DISP3_B1_MAP); + reg_write(fmt_cfg[pixel_fmt].b2, DI_DISP3_B2_MAP); + reg_write(reg_read(DI_DISP_ACC_CC) | + ((fmt_cfg[pixel_fmt].acc - 1) << 12), DI_DISP_ACC_CC); + + return 0; +} + +static void ipu_ch_param_set_size(union chan_param_mem *params, + uint32_t pixel_fmt, uint16_t width, + uint16_t height, uint16_t stride) +{ + params->pp.fw = width - 1; + params->pp.fh_l = height - 1; + params->pp.fh_h = (height - 1) >> 8; + params->pp.sl = stride - 1; + + /* See above, for further formats see the Linux driver */ + switch (pixel_fmt) { + case IPU_PIX_FMT_RGB565: + params->ip.bpp = 2; + params->ip.pfs = 4; + params->ip.npb = 7; + params->ip.sat = 2; /* SAT = 32-bit access */ + params->ip.ofs0 = 0; /* Red bit offset */ + params->ip.ofs1 = 5; /* Green bit offset */ + params->ip.ofs2 = 11; /* Blue bit offset */ + params->ip.ofs3 = 16; /* Alpha bit offset */ + params->ip.wid0 = 4; /* Red bit width - 1 */ + params->ip.wid1 = 5; /* Green bit width - 1 */ + params->ip.wid2 = 4; /* Blue bit width - 1 */ + break; + case IPU_PIX_FMT_RGB24: + params->ip.bpp = 1; /* 24 BPP & RGB PFS */ + params->ip.pfs = 4; + params->ip.npb = 7; + params->ip.sat = 2; /* SAT = 32-bit access */ + params->ip.ofs0 = 16; /* Red bit offset */ + params->ip.ofs1 = 8; /* Green bit offset */ + params->ip.ofs2 = 0; /* Blue bit offset */ + params->ip.ofs3 = 24; /* Alpha bit offset */ + params->ip.wid0 = 7; /* Red bit width - 1 */ + params->ip.wid1 = 7; /* Green bit width - 1 */ + params->ip.wid2 = 7; /* Blue bit width - 1 */ + break; + default: + break; + } + + params->pp.nsb = 1; +} + +static void ipu_ch_param_set_buffer(union chan_param_mem *params, + void *buf0, void *buf1) +{ + params->pp.eba0 = (u32)buf0; + params->pp.eba1 = (u32)buf1; +} + +static void ipu_write_param_mem(uint32_t addr, uint32_t *data, + uint32_t num_words) +{ + for (; num_words > 0; num_words--) { + reg_write(addr, IPU_IMA_ADDR); + reg_write(*data++, IPU_IMA_DATA); + addr++; + if ((addr & 0x7) == 5) { + addr &= ~0x7; /* set to word 0 */ + addr += 8; /* increment to next row */ + } + } +} + +static uint32_t bpp_to_pixfmt(int bpp) +{ + switch (bpp) { + case 16: + return IPU_PIX_FMT_RGB565; + default: + return 0; + } +} + +static uint32_t dma_param_addr(enum ipu_channel channel) +{ + /* Channel Parameter Memory */ + return 0x10000 | (channel << 4); +} + +static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem) +{ + union chan_param_mem params = {}; + uint32_t reg; + uint32_t stride_bytes; + + stride_bytes = (XRES * ((BIT_PER_PIXEL + 7) / 8) + 3) & ~3; + + /* Build parameter memory data for DMA channel */ + ipu_ch_param_set_size(¶ms, bpp_to_pixfmt(BIT_PER_PIXEL), + XRES, YRES, stride_bytes); + ipu_ch_param_set_buffer(¶ms, fbmem, NULL); + params.pp.bam = 0; + /* Some channels (rotation) have restriction on burst length */ + + switch (channel) { + case IDMAC_SDC_0: + /* In original code only IPU_PIX_FMT_RGB565 was setting burst */ + params.pp.npb = 16 - 1; + break; + default: + break; + } + + ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10); + + /* Disable double-buffering */ + reg = reg_read(IPU_CHA_DB_MODE_SEL); + reg &= ~(1UL << channel); + reg_write(reg, IPU_CHA_DB_MODE_SEL); +} + +static void ipu_channel_set_priority(enum ipu_channel channel, + int prio) +{ + u32 reg = reg_read(IDMAC_CHA_PRI); + + if (prio) + reg |= 1UL << channel; + else + reg &= ~(1UL << channel); + + reg_write(reg, IDMAC_CHA_PRI); +} + +/* + * ipu_enable_channel() - enable an IPU channel. + * @channel: channel ID. + * @return: 0 on success or negative error code on failure. + */ +static int ipu_enable_channel(enum ipu_channel channel) +{ + uint32_t reg; + + /* Reset to buffer 0 */ + reg_write(1UL << channel, IPU_CHA_CUR_BUF); + + switch (channel) { + case IDMAC_SDC_0: + ipu_channel_set_priority(channel, 1); + break; + default: + break; + } + + reg = reg_read(IDMAC_CHA_EN); + reg_write(reg | (1UL << channel), IDMAC_CHA_EN); + + return 0; +} + +static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf) +{ + uint32_t reg; + + reg = reg_read(IPU_CHA_BUF0_RDY); + if (reg & (1UL << channel)) + return -EACCES; + + /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */ + reg_write(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR); + reg_write((u32)buf, IPU_IMA_DATA); + + return 0; +} + +static int idmac_tx_submit(enum ipu_channel channel, void *buf) +{ + int ret; + + ipu_init_channel_buffer(channel, buf); + + + /* ipu_idmac.c::ipu_submit_channel_buffers() */ + ret = ipu_update_channel_buffer(channel, buf); + if (ret < 0) + return ret; + + /* ipu_idmac.c::ipu_select_buffer() */ + /* Mark buffer 0 as ready. */ + reg_write(1UL << channel, IPU_CHA_BUF0_RDY); + + + ret = ipu_enable_channel(channel); + return ret; +} + +static void sdc_enable_channel(void *fbmem) +{ + int ret; + u32 reg; + + ret = idmac_tx_submit(IDMAC_SDC_0, fbmem); + + /* mx3fb.c::sdc_fb_init() */ + if (ret >= 0) { + reg = reg_read(SDC_COM_CONF); + reg_write(reg | SDC_COM_BG_EN, SDC_COM_CONF); + } + + /* + * Attention! Without this msleep the channel keeps generating + * interrupts. Next sdc_set_brightness() is going to be called + * from mx3fb_blank(). + */ + msleep(2); +} + +/* + * mx3fb_set_par() - set framebuffer parameters and change the operating mode. + * @return: 0 on success or negative error code on failure. + */ +static int mx3fb_set_par(void) +{ + int ret; + + ret = sdc_init_panel(XRES, YRES, PIXEL_FMT); + if (ret < 0) + return ret; + + reg_write((H_START_WIDTH << 16) | V_START_WIDTH, SDC_BG_POS); + + return 0; +} + +/* References in this function refer to respective Linux kernel sources */ +void lcd_enable(void) +{ + u32 reg; + + /* pcm037.c::mxc_board_init() */ + + /* Display Interface #3 */ + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC)); + + + /* ipu_idmac.c::ipu_probe() */ + + /* Start the clock */ + __REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22); + + + /* ipu_idmac.c::ipu_idmac_init() */ + + /* Service request counter to maximum - shouldn't be needed */ + reg_write(0x00000070, IDMAC_CONF); + + + /* ipu_idmac.c::ipu_init_channel() */ + + /* Enable IPU sub modules */ + reg = reg_read(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN; + reg_write(reg, IPU_CONF); + + + /* mx3fb.c::init_fb_chan() */ + + /* set Display Interface clock period */ + reg_write(0x00100010L, DI_HSP_CLK_PER); + /* Might need to trigger HSP clock change - see 44.3.3.8.5 */ + + + /* mx3fb.c::sdc_set_brightness() */ + + /* This might be board-specific */ + reg_write(0x03000000UL | 255 << 16, SDC_PWM_CTRL); + + + /* mx3fb.c::sdc_set_global_alpha() */ + + /* Use global - not per-pixel - Alpha-blending */ + reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL; + reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); + + reg = reg_read(SDC_COM_CONF); + reg_write(reg | SDC_COM_GLB_A, SDC_COM_CONF); + + + /* mx3fb.c::sdc_set_color_key() */ + + /* Disable colour-keying for background */ + reg = reg_read(SDC_COM_CONF) & + ~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G); + reg_write(reg, SDC_COM_CONF); + + + mx3fb_set_par(); + + sdc_enable_channel(lcd_base); + + /* + * Linux driver calls sdc_set_brightness() here again, + * once is enough for us + */ +} + +void lcd_ctrl_init(void *lcdbase) +{ + u32 mem_len = XRES * YRES * BIT_PER_PIXEL / 8; + /* + * We rely on lcdbase being a physical address, i.e., either MMU off, + * or 1-to-1 mapping. Might want to add some virt2phys here. + */ + if (!lcdbase) + return; + + memset(lcdbase, 0, mem_len); +} + +ulong calc_fbsize(void) +{ + return ((panel_info.vl_col * panel_info.vl_row * + NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE; +} + +int overwrite_console(void) +{ + /* Keep stdout / stderr on serial, our LCD is for splashscreen only */ + return 1; +} diff --git a/drivers/video/s6e63d6.c b/drivers/video/s6e63d6.c new file mode 100644 index 000000000..d16350663 --- /dev/null +++ b/drivers/video/s6e63d6.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2009 + * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <spi.h> +#include <s6e63d6.h> + +/* + * Each transfer is performed as: + * 1. chip-select active + * 2. send 8-bit start code + * 3. send 16-bit data + * 4. chip-select inactive + */ +static int send_word(struct s6e63d6 *data, u8 rs, u16 word) +{ + /* + * The start byte looks like (binary): + * 01110<ID><RS><R/W> + * RS is 0 for index or 1 for data, and R/W is 0 for write. + */ + u32 buf8 = 0x70 | data->id | (rs & 2); + u32 buf16 = cpu_to_le16(word); + u32 buf_in; + int err; + + err = spi_xfer(data->slave, 8, &buf8, &buf_in, SPI_XFER_BEGIN); + if (err) + return err; + + return spi_xfer(data->slave, 16, &buf16, &buf_in, SPI_XFER_END); +} + +/* Index and param differ in Register Select bit */ +int s6e63d6_index(struct s6e63d6 *data, u8 idx) +{ + return send_word(data, 0, idx); +} + +int s6e63d6_param(struct s6e63d6 *data, u16 param) +{ + return send_word(data, 2, param); +} + +int s6e63d6_init(struct s6e63d6 *data) +{ + if (data->id != 0 && data->id != 4) { + printf("s6e63d6: invalid ID %u\n", data->id); + return 1; + } + + data->slave = spi_setup_slave(data->bus, data->cs, 100000, SPI_MODE_3); + if (!data->slave) + return 1; + + return 0; +} |