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-rw-r--r--board/altera/common/AMDLV065D.c20
-rw-r--r--board/altera/common/epled.c6
-rw-r--r--board/armltd/integrator/integrator.c2
-rw-r--r--board/freescale/common/Makefile1
-rw-r--r--board/freescale/common/ngpixis.c136
-rw-r--r--board/freescale/common/ngpixis.h57
-rw-r--r--board/freescale/common/pixis.c254
-rw-r--r--board/freescale/mpc8536ds/mpc8536ds.c1
-rw-r--r--board/freescale/mpc8544ds/mpc8544ds.c1
-rw-r--r--board/freescale/mpc8572ds/mpc8572ds.c1
-rw-r--r--board/freescale/mpc8610hpcd/mpc8610hpcd.c2
-rw-r--r--board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c1
-rw-r--r--board/freescale/mpc8641hpcn/mpc8641hpcn.c2
-rw-r--r--board/freescale/p2020ds/p2020ds.c56
-rw-r--r--board/matrix_vision/mvsmr/Makefile51
-rw-r--r--board/matrix_vision/mvsmr/bootscript42
-rw-r--r--board/matrix_vision/mvsmr/config.mk31
-rw-r--r--board/matrix_vision/mvsmr/fpga.c129
-rw-r--r--board/matrix_vision/mvsmr/fpga.h (renamed from board/freescale/common/pixis.h)21
-rw-r--r--board/matrix_vision/mvsmr/mvsmr.c264
-rw-r--r--board/matrix_vision/mvsmr/mvsmr.h43
-rw-r--r--board/matrix_vision/mvsmr/u-boot.lds138
-rw-r--r--board/psyent/common/AMDLV065D.c18
-rw-r--r--board/psyent/pk1c20/led.c6
-rw-r--r--board/samsung/smdkc100/smdkc100.c39
25 files changed, 1113 insertions, 209 deletions
diff --git a/board/altera/common/AMDLV065D.c b/board/altera/common/AMDLV065D.c
index 0fcf354cd..7a1b4d3c2 100644
--- a/board/altera/common/AMDLV065D.c
+++ b/board/altera/common/AMDLV065D.c
@@ -122,12 +122,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (unsigned char *) info->start[sect];
- writeb (addr, 0xaa);
- writeb (addr, 0x55);
- writeb (addr, 0x80);
- writeb (addr, 0xaa);
- writeb (addr, 0x55);
- writeb (addr2, 0x30);
+ writeb (0xaa, addr);
+ writeb (0x55, addr);
+ writeb (0x80, addr);
+ writeb (0xaa, addr);
+ writeb (0x55, addr);
+ writeb (0x30, addr2);
/* Now just wait for 0xff & provide some user
* feedback while we wait.
*/
@@ -169,10 +169,10 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
return (2);
}
- writeb (cmd, 0xaa);
- writeb (cmd, 0x55);
- writeb (cmd, 0xa0);
- writeb (dst, b);
+ writeb (0xaa, cmd);
+ writeb (0x55, cmd);
+ writeb (0xa0, cmd);
+ writeb (b, dst);
/* Verify write */
start = get_timer (0);
diff --git a/board/altera/common/epled.c b/board/altera/common/epled.c
index e5e770576..d0197358f 100644
--- a/board/altera/common/epled.c
+++ b/board/altera/common/epled.c
@@ -39,7 +39,7 @@ void __led_init (led_id_t mask, int state)
val &= ~mask;
else
val |= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
void __led_set (led_id_t mask, int state)
@@ -50,7 +50,7 @@ void __led_set (led_id_t mask, int state)
val &= ~mask;
else
val |= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
void __led_toggle (led_id_t mask)
@@ -58,5 +58,5 @@ void __led_toggle (led_id_t mask)
nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
val ^= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
index 518944e07..9bb56b520 100644
--- a/board/armltd/integrator/integrator.c
+++ b/board/armltd/integrator/integrator.c
@@ -132,9 +132,7 @@ int board_eth_init(bd_t *bis)
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
-#ifdef CONFIG_PCI
rc += pci_eth_init(bis);
-#endif
return rc;
}
#endif
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 02a824d9f..620eb16d4 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -33,6 +33,7 @@ COBJS-${CONFIG_FSL_CADMUS} += cadmus.o
COBJS-${CONFIG_FSL_VIA} += cds_via.o
COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o
COBJS-${CONFIG_FSL_PIXIS} += pixis.o
+COBJS-${CONFIG_FSL_NGPIXIS} += ngpixis.o
COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o
COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o
COBJS-${CONFIG_FSL_SGMII_RISER} += sgmii_riser.o
diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c
new file mode 100644
index 000000000..bb6794e85
--- /dev/null
+++ b/board/freescale/common/ngpixis.c
@@ -0,0 +1,136 @@
+/**
+ * Copyright 2010 Freescale Semiconductor
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ *
+ * A "switch" is black rectangular block on the motherboard. It contains
+ * eight "bits". The ngPIXIS has a set of memory-mapped registers (SWx) that
+ * shadow the actual physical switches. There is also another set of
+ * registers (ENx) that tell the ngPIXIS which bits of SWx should actually be
+ * used to override the values of the bits in the physical switches.
+ *
+ * The following macros need to be defined:
+ *
+ * PIXIS_BASE - The virtual address of the base of the PIXIS register map
+ *
+ * PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value
+ * is used in the PIXIS_SW() macro to determine which offset in
+ * the PIXIS register map corresponds to the physical switch that controls
+ * the boot bank.
+ *
+ * PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use.
+ *
+ * PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK.
+ *
+ * PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to
+ * boot from the alternate bank.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+
+#include "ngpixis.h"
+
+/*
+ * Reset the board. This ignores the ENx registers.
+ */
+void pixis_reset(void)
+{
+ out_8(&pixis->rst, 0);
+
+ while (1);
+}
+
+/*
+ * Reset the board. Like pixis_reset(), but it honors the ENx registers.
+ */
+void pixis_bank_reset(void)
+{
+ out_8(&pixis->vctl, 0);
+ out_8(&pixis->vctl, 1);
+
+ while (1);
+}
+
+/**
+ * Set the boot bank to the power-on default bank
+ */
+void clear_altbank(void)
+{
+ /* Tell the ngPIXIS to use this the bits in the physical switch for the
+ * boot bank value, instead of the SWx register. We need to be careful
+ * only to set the bits in SWx that correspond to the boot bank.
+ */
+ clrbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK);
+}
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void set_altbank(void)
+{
+ /* Program the alternate bank number into the SWx register.
+ */
+ clrsetbits_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK,
+ PIXIS_LBMAP_ALTBANK);
+
+ /* Tell the ngPIXIS to use this the bits in the SWx register for the
+ * boot bank value, instead of the physical switch. We need to be
+ * careful only to set the bits in SWx that correspond to the boot bank.
+ */
+ setbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK);
+}
+
+
+int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned int i;
+ char *p_altbank = NULL;
+ char *unknown_param = NULL;
+
+ /* No args is a simple reset request.
+ */
+ if (argc <= 1)
+ pixis_reset();
+
+ for (i = 1; i < argc; i++) {
+ if (strcmp(argv[i], "altbank") == 0) {
+ p_altbank = argv[i];
+ continue;
+ }
+
+ unknown_param = argv[i];
+ }
+
+ if (unknown_param) {
+ printf("Invalid option: %s\n", unknown_param);
+ return 1;
+ }
+
+ if (p_altbank)
+ set_altbank();
+ else
+ clear_altbank();
+
+ pixis_bank_reset();
+
+ /* Shouldn't be reached. */
+ return 0;
+}
+
+U_BOOT_CMD(
+ pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
+ "Reset the board using the FPGA sequencer",
+ "- hard reset to default bank\n"
+ "pixis_reset altbank - reset to alternate bank\n"
+ );
diff --git a/board/freescale/common/ngpixis.h b/board/freescale/common/ngpixis.h
new file mode 100644
index 000000000..284d044c8
--- /dev/null
+++ b/board/freescale/common/ngpixis.h
@@ -0,0 +1,57 @@
+/**
+ * Copyright 2010 Freescale Semiconductor
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/* ngPIXIS register set. Hopefully, this won't change too much over time.
+ * Feel free to add board-specific #ifdefs where necessary.
+ */
+typedef struct ngpixis {
+ u8 id;
+ u8 arch;
+ u8 scver;
+ u8 csr;
+ u8 rst;
+ u8 res1;
+ u8 aux;
+ u8 spd;
+ u8 brdcfg0;
+ u8 dma;
+ u8 addr;
+ u8 res2[2];
+ u8 data;
+ u8 led;
+ u8 res3;
+ u8 vctl;
+ u8 vstat;
+ u8 vcfgen0;
+ u8 res4;
+ u8 ocmcsr;
+ u8 ocmmsg;
+ u8 gmdbg;
+ u8 res5[2];
+ u8 sclk[3];
+ u8 dclk[3];
+ u8 watch;
+ struct {
+ u8 sw;
+ u8 en;
+ } s[8];
+} ngpixis_t __attribute__ ((aligned(1)));
+
+/* Pointer to the PIXIS register set */
+#define pixis ((ngpixis_t *)PIXIS_BASE)
+
+/* The PIXIS SW register that corresponds to board switch X, where x >= 1 */
+#define PIXIS_SW(x) (pixis->s[(x) - 1].sw)
+
+/* The PIXIS EN register that corresponds to board switch X, where x >= 1 */
+#define PIXIS_EN(x) (pixis->s[(x) - 1].en)
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index 7210512bf..119eaf95a 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2006 Freescale Semiconductor
+ * Copyright 2006,2010 Freescale Semiconductor
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
@@ -24,33 +24,26 @@
#include <common.h>
#include <command.h>
-#include <watchdog.h>
-#include <asm/cache.h>
#include <asm/io.h>
-#include "pixis.h"
-
-
-static ulong strfractoint(uchar *strptr);
-
+#define pixis_base (u8 *)PIXIS_BASE
/*
* Simple board reset.
*/
void pixis_reset(void)
{
- u8 *pixis_base = (u8 *)PIXIS_BASE;
out_8(pixis_base + PIXIS_RST, 0);
-}
+ while (1);
+}
/*
* Per table 27, page 58 of MPC8641HPCN spec.
*/
-int set_px_sysclk(ulong sysclk)
+static int set_px_sysclk(unsigned long sysclk)
{
u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
switch (sysclk) {
case 33:
@@ -117,13 +110,13 @@ int set_px_sysclk(ulong sysclk)
return 1;
}
-
-int set_px_mpxpll(ulong mpxpll)
+/* Set the CFG_SYSPLL bits
+ *
+ * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
+ * read_from_px_regs() is called.
+ */
+static int set_px_mpxpll(unsigned long mpxpll)
{
- u8 tmp;
- u8 val;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
switch (mpxpll) {
case 2:
case 4:
@@ -133,28 +126,19 @@ int set_px_mpxpll(ulong mpxpll)
case 12:
case 14:
case 16:
- val = (u8) mpxpll;
- break;
- default:
- printf("Unsupported MPXPLL ratio.\n");
- return 0;
+ clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
+ return 1;
}
- tmp = in_8(pixis_base + PIXIS_VSPEED1);
- tmp = (tmp & 0xF0) | (val & 0x0F);
- out_8(pixis_base + PIXIS_VSPEED1, tmp);
-
- return 1;
+ printf("Unsupported MPXPLL ratio.\n");
+ return 0;
}
-
-int set_px_corepll(ulong corepll)
+static int set_px_corepll(unsigned long corepll)
{
- u8 tmp;
u8 val;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
- switch ((int)corepll) {
+ switch (corepll) {
case 20:
val = 0x08;
break;
@@ -178,113 +162,132 @@ int set_px_corepll(ulong corepll)
return 0;
}
- tmp = in_8(pixis_base + PIXIS_VSPEED0);
- tmp = (tmp & 0xE0) | (val & 0x1F);
- out_8(pixis_base + PIXIS_VSPEED0, tmp);
-
+ clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
return 1;
}
+#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
+#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
+#endif
-void read_from_px_regs(int set)
+/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
+ *
+ * The PIXIS can be programmed to look at either the on-board dip switches
+ * or various other PIXIS registers to determine the values for COREPLL,
+ * MPXPLL, and SYSCLK.
+ *
+ * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
+ * register that tells the pixis to use the various PIXIS register.
+ */
+static void read_from_px_regs(int set)
{
- u8 *pixis_base = (u8 *)PIXIS_BASE;
- u8 mask = 0x1C; /* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */
u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
if (set)
- tmp = tmp | mask;
+ tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
else
- tmp = tmp & ~mask;
+ tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
+
out_8(pixis_base + PIXIS_VCFGEN0, tmp);
}
+/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
+ * register that tells the pixis to use the PX_VBOOT[LBMAP] register.
+ */
+#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
+#define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04
+#endif
-void read_from_px_regs_altbank(int set)
+/* Configure the source of the boot location
+ *
+ * The PIXIS can be programmed to look at either the on-board dip switches
+ * or the PX_VBOOT[LBMAP] register to determine where we should boot.
+ *
+ * If we want to boot from the alternate boot bank, we need to tell the PIXIS
+ * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
+ */
+static void read_from_px_regs_altbank(int set)
{
- u8 *pixis_base = (u8 *)PIXIS_BASE;
- u8 mask = 0x04; /* FLASHBANK and FLASHMAP controlled by PIXIS */
u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
if (set)
- tmp = tmp | mask;
+ tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
else
- tmp = tmp & ~mask;
+ tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
+
out_8(pixis_base + PIXIS_VCFGEN1, tmp);
}
+/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
+ * tells the PIXIS what the alternate flash bank is.
+ *
+ * Note that it's not really a mask. It contains the actual LBMAP bits that
+ * must be set to select the alternate bank. This code assumes that the
+ * primary bank has these bits set to 0, and the alternate bank has these
+ * bits set to 1.
+ */
#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
#define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
#endif
-void clear_altbank(void)
+/* Tell the PIXIS to boot from the default flash bank
+ *
+ * Program the default flash bank into the VBOOT register. This register is
+ * used only if PX_VCFGEN1[FLASH]=1.
+ */
+static void clear_altbank(void)
{
- u8 tmp;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- tmp = in_8(pixis_base + PIXIS_VBOOT);
- tmp &= ~CONFIG_SYS_PIXIS_VBOOT_MASK;
-
- out_8(pixis_base + PIXIS_VBOOT, tmp);
+ clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
}
-
-void set_altbank(void)
+/* Tell the PIXIS to boot from the alternate flash bank
+ *
+ * Program the alternate flash bank into the VBOOT register. This register is
+ * used only if PX_VCFGEN1[FLASH]=1.
+ */
+static void set_altbank(void)
{
- u8 tmp;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- tmp = in_8(pixis_base + PIXIS_VBOOT);
- tmp |= CONFIG_SYS_PIXIS_VBOOT_MASK;
-
- out_8(pixis_base + PIXIS_VBOOT, tmp);
+ setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
}
-
-void set_px_go(void)
+/* Reset the board with watchdog disabled.
+ *
+ * This respects the altbank setting.
+ */
+static void set_px_go(void)
{
- u8 tmp;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
+ /* Disable the VELA sequencer and watchdog */
+ clrbits_8(pixis_base + PIXIS_VCTL, 9);
- tmp = in_8(pixis_base + PIXIS_VCTL);
- tmp = tmp & 0x1E; /* clear GO bit */
- out_8(pixis_base + PIXIS_VCTL, tmp);
+ /* Reboot by starting the VELA sequencer */
+ setbits_8(pixis_base + PIXIS_VCTL, 0x1);
- tmp = in_8(pixis_base + PIXIS_VCTL);
- tmp = tmp | 0x01; /* set GO bit - start reset sequencer */
- out_8(pixis_base + PIXIS_VCTL, tmp);
+ while (1);
}
-
-void set_px_go_with_watchdog(void)
+/* Reset the board with watchdog enabled.
+ *
+ * This respects the altbank setting.
+ */
+static void set_px_go_with_watchdog(void)
{
- u8 tmp;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
+ /* Disable the VELA sequencer */
+ clrbits_8(pixis_base + PIXIS_VCTL, 1);
- tmp = in_8(pixis_base + PIXIS_VCTL);
- tmp = tmp & 0x1E;
- out_8(pixis_base + PIXIS_VCTL, tmp);
+ /* Enable the watchdog and reboot by starting the VELA sequencer */
+ setbits_8(pixis_base + PIXIS_VCTL, 0x9);
- tmp = in_8(pixis_base + PIXIS_VCTL);
- tmp = tmp | 0x09;
- out_8(pixis_base + PIXIS_VCTL, tmp);
+ while (1);
}
-
-int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
- int flag, int argc, char *argv[])
+/* Disable the watchdog
+ *
+ */
+static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *argv[])
{
- u8 tmp;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- tmp = in_8(pixis_base + PIXIS_VCTL);
- tmp = tmp & 0x1E;
- out_8(pixis_base + PIXIS_VCTL, tmp);
-
- /* setting VCTL[WDEN] to 0 to disable watch dog */
- tmp = in_8(pixis_base + PIXIS_VCTL);
- tmp &= ~0x08;
- out_8(pixis_base + PIXIS_VCTL, tmp);
+ /* Disable the VELA sequencer and the watchdog */
+ clrbits_8(pixis_base + PIXIS_VCTL, 9);
return 0;
}
@@ -296,16 +299,17 @@ U_BOOT_CMD(
);
#ifdef CONFIG_PIXIS_SGMII_CMD
-int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+
+/* Enable or disable SGMII mode for a TSEC
+ */
+static int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int which_tsec = -1;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
- uchar mask;
- uchar switch_mask;
+ unsigned char mask;
+ unsigned char switch_mask;
- if (argc > 2)
- if (strcmp(argv[1], "all") != 0)
- which_tsec = simple_strtoul(argv[1], NULL, 0);
+ if ((argc > 2) && (strcmp(argv[1], "all") != 0))
+ which_tsec = simple_strtoul(argv[1], NULL, 0);
switch (which_tsec) {
#ifdef CONFIG_TSEC1
@@ -363,6 +367,7 @@ U_BOOT_CMD(
" off - disables SGMII\n"
" switch - use switch settings"
);
+
#endif
/*
@@ -371,14 +376,13 @@ U_BOOT_CMD(
* FPGA register values.
* input: strptr i.e. argv[2]
*/
-
-static ulong strfractoint(uchar *strptr)
+static unsigned long strfractoint(char *strptr)
{
- int i, j, retval;
+ int i, j;
int mulconst;
- int intarr_len = 0, decarr_len = 0, no_dec = 0;
- ulong intval = 0, decval = 0;
- uchar intarr[3], decarr[3];
+ int intarr_len, no_dec = 0;
+ unsigned long intval = 0, decval = 0;
+ char intarr[3], decarr[3];
/* Assign the integer part to intarr[]
* If there is no decimal point i.e.
@@ -412,26 +416,21 @@ static ulong strfractoint(uchar *strptr)
j++;
}
- decarr_len = j;
decarr[j] = '\0';
mulconst = 1;
- for (i = 0; i < decarr_len; i++)
+ for (i = 0; i < j; i++)
mulconst *= 10;
- decval = simple_strtoul((char *)decarr, NULL, 10);
+ decval = simple_strtoul(decarr, NULL, 10);
}
- intval = simple_strtoul((char *)intarr, NULL, 10);
+ intval = simple_strtoul(intarr, NULL, 10);
intval = intval * mulconst;
- retval = intval + decval;
-
- return retval;
+ return intval + decval;
}
-
-int
-pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
unsigned int i;
char *p_cf = NULL;
@@ -440,7 +439,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
char *p_cf_mpxpll = NULL;
char *p_altbank = NULL;
char *p_wd = NULL;
- unsigned int unknown_param = 0;
+ int unknown_param = 0;
/*
* No args is a simple reset request.
@@ -493,9 +492,9 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
*/
read_from_px_regs(0);
- if (p_altbank) {
+ if (p_altbank)
read_from_px_regs_altbank(0);
- }
+
clear_altbank();
/*
@@ -507,7 +506,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
unsigned long mpxpll;
sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
- corepll = strfractoint((uchar *) p_cf_corepll);
+ corepll = strfractoint(p_cf_corepll);
mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
if (!(set_px_sysclk(sysclk)
@@ -536,11 +535,10 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/*
* Reset with watchdog specified.
*/
- if (p_wd) {
+ if (p_wd)
set_px_go_with_watchdog();
- } else {
+ else
set_px_go();
- }
/*
* Shouldn't be reached.
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 81a56b55e..253ed181f 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -39,7 +39,6 @@
#include <netdev.h>
#include <sata.h>
-#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
phys_size_t fixed_sdram(void);
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index b35e02f68..0be2d892d 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -35,7 +35,6 @@
#include <tsec.h>
#include <netdev.h>
-#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
int checkboard (void)
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 74085c326..6029a5185 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -36,7 +36,6 @@
#include <tsec.h>
#include <netdev.h>
-#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
long int fixed_sdram(void);
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index ab5f80045..2ef7b2323 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -34,8 +34,6 @@
#include <spd_sdram.h>
#include <netdev.h>
-#include "../common/pixis.h"
-
void sdram_init(void);
phys_size_t fixed_sdram(void);
void mpc8610hpcd_diu_init(void);
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
index 4186a2ecd..94fb1ebf8 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -29,7 +29,6 @@
#ifdef CONFIG_FSL_DIU_FB
-#include "../common/pixis.h"
#include "../common/fsl_diu_fb.h"
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 443c9fd8e..b352c334c 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -31,8 +31,6 @@
#include <fdt_support.h>
#include <netdev.h>
-#include "../common/pixis.h"
-
phys_size_t fixed_sdram(void);
int board_early_init_f(void)
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index f6eae55d1..f0ff209c0 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -38,7 +38,7 @@
#include <asm/mp.h>
#include <netdev.h>
-#include "../common/pixis.h"
+#include "../common/ngpixis.h"
#include "../common/sgmii_riser.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -47,30 +47,24 @@ phys_size_t fixed_sdram(void);
int checkboard(void)
{
- u8 sw7;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
+ u8 sw;
puts("Board: P2020DS ");
#ifdef CONFIG_PHYS_64BIT
puts("(36-bit addrmap) ");
#endif
- printf("Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
- in_8(pixis_base + PIXIS_PVER));
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
- sw7 = in_8(pixis_base + PIXIS_SW(7));
- switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
- case 0:
- case 1:
- printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
- break;
- case 2:
- case 3:
- puts ("Promjet\n");
- break;
- }
+ sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
+ sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ /* The lower two bits are the actual vbank number */
+ printf("vBank: %d\n", sw & 3);
+ else
+ puts("Promjet\n");
return 0;
}
@@ -371,30 +365,22 @@ unsigned long get_board_ddr_clk(ulong dummy)
return gd->mem_clk;
}
-unsigned long
-calculate_board_sys_clk(ulong dummy)
+unsigned long calculate_board_sys_clk(ulong dummy)
{
ulong val;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
- val = ics307_clk_freq(
- in_8(pixis_base + PIXIS_VSYSCLK0),
- in_8(pixis_base + PIXIS_VSYSCLK1),
- in_8(pixis_base + PIXIS_VSYSCLK2));
+ val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]),
+ in_8(&pixis->sclk[2]));
debug("sysclk val = %lu\n", val);
return val;
}
-unsigned long
-calculate_board_ddr_clk(ulong dummy)
+unsigned long calculate_board_ddr_clk(ulong dummy)
{
ulong val;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
- val = ics307_clk_freq(
- in_8(pixis_base + PIXIS_VDDRCLK0),
- in_8(pixis_base + PIXIS_VDDRCLK1),
- in_8(pixis_base + PIXIS_VDDRCLK2));
+ val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]),
+ in_8(&pixis->dclk[2]));
debug("ddrclk val = %lu\n", val);
return val;
}
@@ -403,9 +389,8 @@ unsigned long get_board_sys_clk(ulong dummy)
{
u8 i;
ulong val = 0;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
- i = in_8(pixis_base + PIXIS_SPD);
+ i = in_8(&pixis->spd);
i &= 0x07;
switch (i) {
@@ -442,9 +427,8 @@ unsigned long get_board_ddr_clk(ulong dummy)
{
u8 i;
ulong val = 0;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
- i = in_8(pixis_base + PIXIS_SPD);
+ i = in_8(&pixis->spd);
i &= 0x38;
i >>= 3;
diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile
new file mode 100644
index 000000000..b179e6d78
--- /dev/null
+++ b/board/matrix_vision/mvsmr/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004-2008
+# Matrix-Vision GmbH, info@matrix-vision.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o fpga.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+ @mkimage -T script -C none -n mvSMR_Script -d bootscript bootscript.img
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/matrix_vision/mvsmr/bootscript b/board/matrix_vision/mvsmr/bootscript
new file mode 100644
index 000000000..02c802c8c
--- /dev/null
+++ b/board/matrix_vision/mvsmr/bootscript
@@ -0,0 +1,42 @@
+echo
+echo "==== running autoscript ===="
+echo
+setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}'
+setenv ramkernel 'setenv kernel_boot ${loadaddr}'
+setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}'
+setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}'
+setenv bootfromflash run flashkernel cpird addcons boot24
+setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel'
+if test ${console} = yes;
+then
+setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8'
+else
+setenv addcons 'setenv bootargs ${bootargs} console=tty0'
+fi
+setenv set_static_ip 'setenv ipaddr ${static_ipaddr}'
+setenv set_static_nm 'setenv netmask ${static_netmask}'
+setenv set_static_gw 'setenv gatewayip ${static_gateway}'
+setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}'
+if test ${servicemode} != yes;
+then
+ echo "=== forced flash mode ==="
+ run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
+fi
+if test ${autoscript_boot} != no;
+then
+ if test ${netboot} = yes;
+ then
+ bootp
+ if test $? = 0;
+ then
+ echo "=== bootp succeeded -> netboot ==="
+ run set_ip bootfromnet addcons boot24
+ else
+ echo "=== netboot failed ==="
+ fi
+ fi
+ echo "=== bootfromflash ==="
+ run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
+else
+ echo "=== boot stopped with autoscript_boot no ==="
+fi
diff --git a/board/matrix_vision/mvsmr/config.mk b/board/matrix_vision/mvsmr/config.mk
new file mode 100644
index 000000000..b1da812c4
--- /dev/null
+++ b/board/matrix_vision/mvsmr/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFF800000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+LDSCRIPT := $(SRCTREE)/board/matrix_vision/mvsmr/u-boot.lds
diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c
new file mode 100644
index 000000000..6320a6903
--- /dev/null
+++ b/board/matrix_vision/mvsmr/fpga.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2010
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/io.h>
+#include "fpga.h"
+#include "mvsmr.h"
+
+Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
+ fpga_pre_config_fn,
+ fpga_pgm_fn,
+ fpga_clk_fn,
+ fpga_init_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ 0
+};
+
+Xilinx_desc spartan3 = {
+ Xilinx_Spartan2,
+ slave_serial,
+ XILINX_XC3S200_SIZE,
+ (void *) &fpga_fns,
+ 0,
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvsmr_init_fpga(void)
+{
+ fpga_init();
+ fpga_add(fpga_xilinx, &spartan3);
+
+ return 1;
+}
+
+int fpga_init_fn(int cookie)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+ if (in_be32(&gpio->simple_ival) & FPGA_CONFIG)
+ return 0;
+
+ return 1;
+}
+
+int fpga_done_fn(int cookie)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ int result = 0;
+
+ udelay(10);
+ if (in_be32(&gpio->simple_ival) & FPGA_DONE)
+ result = 1;
+
+ return result;
+}
+
+int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+ if (!assert)
+ setbits_8(&gpio->sint_dvo, FPGA_STATUS);
+ else
+ clrbits_8(&gpio->sint_dvo, FPGA_STATUS);
+
+ return assert;
+}
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+ if (assert_clk)
+ setbits_be32(&gpio->simple_dvo, FPGA_CCLK);
+ else
+ clrbits_be32(&gpio->simple_dvo, FPGA_CCLK);
+
+ return assert_clk;
+}
+
+int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+ if (assert_write)
+ setbits_be32(&gpio->simple_dvo, FPGA_DIN);
+ else
+ clrbits_be32(&gpio->simple_dvo, FPGA_DIN);
+
+ return assert_write;
+}
+
+int fpga_pre_config_fn(int cookie)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+ setbits_8(&gpio->sint_dvo, FPGA_STATUS);
+
+ return 0;
+}
diff --git a/board/freescale/common/pixis.h b/board/matrix_vision/mvsmr/fpga.h
index ff62a62c7..ee690e681 100644
--- a/board/freescale/common/pixis.h
+++ b/board/matrix_vision/mvsmr/fpga.h
@@ -1,5 +1,6 @@
/*
- * Copyright 2006 Freescale Semiconductor
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,14 +19,14 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
*/
-extern void pixis_reset(void);
-extern int set_px_sysclk(ulong sysclk);
-extern int set_px_mpxpll(ulong mpxpll);
-extern int set_px_corepll(ulong corepll);
-extern void read_from_px_regs(int set);
-extern void read_from_px_regs_altbank(int set);
-extern void set_altbank(void);
-extern void set_px_go(void);
-extern void set_px_go_with_watchdog(void);
+extern int mvsmr_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_init_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_pre_config_fn(int cookie);
diff --git a/board/matrix_vision/mvsmr/mvsmr.c b/board/matrix_vision/mvsmr/mvsmr.c
new file mode 100644
index 000000000..69655c4cf
--- /dev/null
+++ b/board/matrix_vision/mvsmr/mvsmr.c
@@ -0,0 +1,264 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2005-2010
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <malloc.h>
+#include <pci.h>
+#include <i2c.h>
+#include <fpga.h>
+#include <environment.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include "fpga.h"
+#include "mvsmr.h"
+#include "../common/mv_common.h"
+
+#define SDRAM_DDR 1
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x715f0f00
+#define SDRAM_CONFIG1 0xd3722930
+#define SDRAM_CONFIG2 0x46770000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_start(int hi_addr)
+{
+ long hi_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 |
+ hi_bit);
+
+ /* precharge all banks */
+ out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
+ hi_bit);
+
+ /* set mode register: extended mode */
+ out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
+
+ /* set mode register: reset DLL */
+ out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
+
+ /* precharge all banks */
+ out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
+ hi_bit);
+
+ /* auto refresh */
+ out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 |
+ hi_bit);
+
+ /* set mode register */
+ out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+ /* normal operation */
+ out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
+}
+
+phys_addr_t initdram(int board_type)
+{
+ ulong dramsize = 0;
+ ulong test1,
+ test2;
+
+ /* setup SDRAM chip selects */
+ out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
+
+ /* setup config registers */
+ out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+ out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else
+ dramsize = test2;
+
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ if (dramsize > 0)
+ out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 +
+ __builtin_ffs(dramsize >> 20) - 1);
+ else
+ out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0);
+
+ return dramsize;
+}
+
+void mvsmr_init_gpio(void)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ struct mpc5xxx_wu_gpio *wu_gpio =
+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+ struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+ printf("Ports : 0x%08x\n", gpio->port_config);
+ printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG));
+
+ out_be32(&gpio->simple_ddr, SIMPLE_DDR);
+ out_be32(&gpio->simple_dvo, SIMPLE_DVO);
+ out_be32(&gpio->simple_ode, SIMPLE_ODE);
+ out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
+
+ out_8(&gpio->sint_ode, SINT_ODE);
+ out_8(&gpio->sint_ddr, SINT_DDR);
+ out_8(&gpio->sint_dvo, SINT_DVO);
+ out_8(&gpio->sint_inten, SINT_INTEN);
+ out_be16(&gpio->sint_itype, SINT_ITYPE);
+ out_8(&gpio->sint_gpioe, SINT_GPIOEN);
+
+ out_8(&wu_gpio->ode, WKUP_ODE);
+ out_8(&wu_gpio->ddr, WKUP_DIR);
+ out_8(&wu_gpio->dvo, WKUP_DO);
+ out_8(&wu_gpio->enable, WKUP_EN);
+
+ out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */
+ out_be32(&timers->gpt1.emsr, 0x00000234);
+ out_be32(&timers->gpt2.emsr, 0x00000234);
+ out_be32(&timers->gpt3.emsr, 0x00000234);
+ out_be32(&timers->gpt4.emsr, 0x00000234);
+ out_be32(&timers->gpt5.emsr, 0x00000234);
+ out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */
+ out_be32(&timers->gpt7.emsr, 0x00000024);
+}
+
+int misc_init_r(void)
+{
+ char *s = getenv("reset_env");
+
+ if (s) {
+ printf(" === FACTORY RESET ===\n");
+ mv_reset_environment();
+ saveenv();
+ }
+
+ return -1;
+}
+
+void mvsmr_get_dbg_present(void)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
+
+ if (in_be32(&gpio->simple_ival) & COP_PRESENT) {
+ setenv("dbg_present", "no\0");
+ setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0");
+ } else {
+ setenv("dbg_present", "yes\0");
+ setenv("bootstopkey", "s\0");
+ setbits_8(&psc->command, PSC_RX_ENABLE);
+ }
+}
+
+void mvsmr_get_service_mode(void)
+{
+ struct mpc5xxx_wu_gpio *wu_gpio =
+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+
+ if (in_8(&wu_gpio->ival) & SERVICE_MODE)
+ setenv("servicemode", "no\0");
+ else
+ setenv("servicemode", "yes\0");
+}
+
+int mvsmr_get_mac(void)
+{
+ unsigned char mac[6];
+ struct mpc5xxx_wu_gpio *wu_gpio =
+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+
+ if (in_8(&wu_gpio->ival) & LAN_PRSNT) {
+ setenv("lan_present", "no\0");
+ return -1;
+ } else
+ setenv("lan_present", "yes\0");
+
+ i2c_read(0x50, 0, 1, mac, 6);
+
+ eth_setenv_enetaddr("ethaddr", mac);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ mvsmr_init_gpio();
+ printf("Board: Matrix Vision mvSMR\n");
+
+ return 0;
+}
+
+void flash_preinit(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1);
+}
+
+void flash_afterinit(ulong size)
+{
+ out_be32((u32 *)MPC5XXX_BOOTCS_START,
+ START_REG(CONFIG_SYS_BOOTCS_START | size));
+ out_be32((u32 *)MPC5XXX_CS0_START,
+ START_REG(CONFIG_SYS_BOOTCS_START | size));
+ out_be32((u32 *)MPC5XXX_BOOTCS_STOP,
+ STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
+ out_be32((u32 *)MPC5XXX_CS0_STOP,
+ STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
+}
+
+struct pci_controller hose;
+
+void pci_init_board(void)
+{
+ mvsmr_get_dbg_present();
+ mvsmr_get_service_mode();
+ mvsmr_init_fpga();
+ mv_load_fpga();
+ pci_mpc5xxx_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ if (!mvsmr_get_mac())
+ return cpu_eth_init(bis);
+
+ return pci_eth_init(bis);
+}
diff --git a/board/matrix_vision/mvsmr/mvsmr.h b/board/matrix_vision/mvsmr/mvsmr.h
new file mode 100644
index 000000000..b8320f1e6
--- /dev/null
+++ b/board/matrix_vision/mvsmr/mvsmr.h
@@ -0,0 +1,43 @@
+#include <pci.h>
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0
+#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1
+#define FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2
+#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3
+#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4
+#define S_FPGA_DIN MPC5XXX_GPIO_SINT_PSC3_5
+#define S_FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_6
+#define S_FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_7
+#define S_FPGA_CONFIG MPC5XXX_GPIO_SINT_PSC3_8
+#define S_FPGA_STATUS MPC5XXX_GPIO_WKUP_PSC3_9
+
+#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0
+#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1
+#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2
+#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3
+#define SERVICE_MODE MPC5XXX_GPIO_WKUP_6
+#define FLASH_RBY MPC5XXX_GPIO_WKUP_7
+#define UART_EN1 MPC5XXX_GPIO_WKUP_PSC1_4
+#define LAN_PRSNT MPC5XXX_GPIO_WKUP_PSC2_4
+
+#define SIMPLE_DDR (FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\
+ S_FPGA_CCLK)
+#define SIMPLE_DVO (FPGA_CONFIG)
+#define SIMPLE_ODE (FPGA_CONFIG)
+#define SIMPLE_GPIOEN (FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\
+ S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT)
+
+#define SINT_ODE 0x1
+#define SINT_DDR 0x3
+#define SINT_DVO 0x1
+#define SINT_INTEN 0
+#define SINT_ITYPE 0
+#define SINT_GPIOEN (FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG)
+
+#define WKUP_ODE (MAN_RST | S_FPGA_STATUS)
+#define WKUP_DIR (MAN_RST | WD_TS | S_FPGA_STATUS)
+#define WKUP_DO (MAN_RST | WD_TS | S_FPGA_STATUS)
+#define WKUP_EN (MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\
+ FLASH_RBY | UART_EN1 | LAN_PRSNT)
diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds
new file mode 100644
index 000000000..cfbb6ef39
--- /dev/null
+++ b/board/matrix_vision/mvsmr/u-boot.lds
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2010
+ * André Schwarz, Matrix Vision GmbH, as@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the first two sectors (=8KB) of our S29GL flash chip */
+ cpu/mpc5xxx/start.o (.text)
+ cpu/mpc5xxx/traps.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/cache.o (.text)
+ lib_ppc/time.o (.text)
+
+ /* This is only needed to force failure if size of above code will ever */
+ /* increase and grow into reserved space. */
+ . = ALIGN(0x2000); /* location counter has to be 0x4000 now */
+ . += 0x4000; /* ->0x8000, i.e. move to env_offset */
+
+ . = env_offset; /* ld error as soon as above ALIGN misplaces lc */
+ common/env_embedded.o (.ppcenv)
+
+ *(.text)
+ *(.got1)
+ . = ALIGN(16);
+ *(.eh_frame)
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c
index 0fcf354cd..72b0a9f80 100644
--- a/board/psyent/common/AMDLV065D.c
+++ b/board/psyent/common/AMDLV065D.c
@@ -122,12 +122,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (unsigned char *) info->start[sect];
- writeb (addr, 0xaa);
- writeb (addr, 0x55);
- writeb (addr, 0x80);
- writeb (addr, 0xaa);
- writeb (addr, 0x55);
- writeb (addr2, 0x30);
+ writeb (0xaa, addr);
+ writeb (0x55, addr);
+ writeb (0x80, addr);
+ writeb (0xaa, addr);
+ writeb (0x55, addr);
+ writeb (0x30, addr2);
/* Now just wait for 0xff & provide some user
* feedback while we wait.
*/
@@ -169,9 +169,9 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
return (2);
}
- writeb (cmd, 0xaa);
- writeb (cmd, 0x55);
- writeb (cmd, 0xa0);
+ writeb (0xaa, cmd);
+ writeb (0x55, cmd);
+ writeb (0xa0, cmd);
writeb (dst, b);
/* Verify write */
diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c
index e5e770576..d0197358f 100644
--- a/board/psyent/pk1c20/led.c
+++ b/board/psyent/pk1c20/led.c
@@ -39,7 +39,7 @@ void __led_init (led_id_t mask, int state)
val &= ~mask;
else
val |= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
void __led_set (led_id_t mask, int state)
@@ -50,7 +50,7 @@ void __led_set (led_id_t mask, int state)
val &= ~mask;
else
val |= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
void __led_toggle (led_id_t mask)
@@ -58,5 +58,5 @@ void __led_toggle (led_id_t mask)
nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
val ^= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c
index 15a1a27c3..fb466c6ec 100644
--- a/board/samsung/smdkc100/smdkc100.c
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -23,10 +23,40 @@
*/
#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/smc.h>
+#include <asm/arch/gpio.h>
+#include <netdev.h>
+
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+static void smc9115_pre_init(void)
+{
+ u32 smc_bw_conf, smc_bc_conf;
+
+ struct s5pc100_gpio *const gpio =
+ (struct s5pc100_gpio *)S5PC100_GPIO_BASE;
+
+ /* gpio configuration GPK0CON */
+ gpio_cfg_pin(&gpio->gpio_k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
+
+ /* Ethernet needs bus width of 16 bits */
+ smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
+ smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe)
+ | SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4)
+ | SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
+
+ /* Select and configure the SROMC bank */
+ s5pc1xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+}
+
int board_init(void)
{
+ smc9115_pre_init();
+
gd->bd->bi_arch_number = MACH_TYPE_SMDKC100;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
@@ -49,3 +79,12 @@ int checkboard(void)
return 0;
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}