diff options
Diffstat (limited to 'board')
52 files changed, 1856 insertions, 638 deletions
diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile index f73338906..31b89e46b 100644 --- a/board/LaCie/edminiv2/Makefile +++ b/board/LaCie/edminiv2/Makefile @@ -1,5 +1,5 @@ # -# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr> +# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> # # Based on original Kirkwood support which is # (C) Copyright 2009 diff --git a/board/LaCie/edminiv2/config.mk b/board/LaCie/edminiv2/config.mk index 2ffd1250a..b2ee41613 100644 --- a/board/LaCie/edminiv2/config.mk +++ b/board/LaCie/edminiv2/config.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr> +# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> # # (C) Copyright 2009 # Marvell Semiconductor <www.marvell.com> diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index bb388edd1..ee2689332 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr> + * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> * * (C) Copyright 2009 * Marvell Semiconductor <www.marvell.com> diff --git a/board/Marvell/aspenite/aspenite.c b/board/Marvell/aspenite/aspenite.c index 046ffd62c..34ac7aa55 100644 --- a/board/Marvell/aspenite/aspenite.c +++ b/board/Marvell/aspenite/aspenite.c @@ -33,9 +33,14 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { u32 mfp_cfg[] = { + /* I2C */ + MFP105_CI2C_SDA, + MFP106_CI2C_SCL, + /* Enable Console on UART1 */ MFP107_UART1_RXD, MFP108_UART1_TXD, + MFP_EOC /*End of configureation*/ }; /* configure MFP's */ diff --git a/board/Marvell/dkb/dkb.c b/board/Marvell/dkb/dkb.c index 72a2d2a98..00f73e79f 100644 --- a/board/Marvell/dkb/dkb.c +++ b/board/Marvell/dkb/dkb.c @@ -36,6 +36,10 @@ int board_early_init_f(void) MFP47_UART2_RXD, MFP48_UART2_TXD, + /* I2C */ + MFP53_CI2C_SCL, + MFP54_CI2C_SDA, + MFP_EOC /*End of configureation*/ }; /* configure MFP's */ diff --git a/board/armltd/vexpress/config.mk b/board/armltd/vexpress/config.mk deleted file mode 100644 index 36395f22e..000000000 --- a/board/armltd/vexpress/config.mk +++ /dev/null @@ -1,22 +0,0 @@ -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Linux-Kernel is expected to be at 0x60008000 -# -CONFIG_SYS_TEXT_BASE = 0x60800000 diff --git a/board/cm_t35/Makefile b/board/cm_t35/Makefile index 862b8dc1b..83d7a568f 100644 --- a/board/cm_t35/Makefile +++ b/board/cm_t35/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := cm_t35.o +COBJS := cm_t35.o leds.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index 459df0b49..f82111bac 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -1,8 +1,9 @@ /* - * (C) Copyright 2010 + * (C) Copyright 2011 * CompuLab, Ltd. <www.compulab.co.il> * - * Author: Mike Rapoport <mike@compulab.co.il> + * Authors: Mike Rapoport <mike@compulab.co.il> + * Igor Grinberg <grinberg@compulab.co.il> * * Derived from omap3evm and Beagle Board by * Manikandan Pillai <mani.pillai@ti.com> @@ -24,11 +25,11 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc. */ #include <common.h> +#include <status_led.h> #include <netdev.h> #include <net.h> #include <i2c.h> @@ -41,9 +42,11 @@ #include <asm/arch/sys_proto.h> #include <asm/mach-types.h> +DECLARE_GLOBAL_DATA_PTR; + const omap3_sysinfo sysinfo = { DDR_DISCRETE, - "CM-T35 board", + "CM-T3x board", "NAND", }; @@ -73,31 +76,33 @@ static u32 gpmc_nand_config[GPMC_MAX_REG] = { */ int board_init(void) { - DECLARE_GLOBAL_DATA_PTR; - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0], CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M); /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_CM_T35; + if (get_cpu_family() == CPU_OMAP34XX) + gd->bd->bi_arch_number = MACH_TYPE_CM_T35; + else + gd->bd->bi_arch_number = MACH_TYPE_CM_T3730; + /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); +#endif + return 0; } /* * Routine: misc_init_r - * Description: Init I2C and display die ID + * Description: display die ID */ int misc_init_r(void) { -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - dieid_num_r(); return 0; @@ -109,7 +114,7 @@ int misc_init_r(void) * hardware. Many pins need to be moved from protect to primary * mode. */ -void set_muxconf_regs(void) +static void cm_t3x_set_common_muxconf(void) { /* SDRC */ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ @@ -184,7 +189,7 @@ void set_muxconf_regs(void) /* SB-T35 Ethernet */ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ - /* CM-T35 Ethernet */ + /* CM-T3x Ethernet */ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/ @@ -200,12 +205,6 @@ void set_muxconf_regs(void) MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/ @@ -218,12 +217,6 @@ void set_muxconf_regs(void) MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/ /* serial interface */ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/ @@ -253,19 +246,72 @@ void set_muxconf_regs(void) MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/ - MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M4)); /*green LED*/ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ + + /* MMC1 */ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ +} + +static void cm_t35_set_muxconf(void) +{ + /* DSS */ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/ + + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/ + + /* MMC1 */ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/ } -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) +static void cm_t3730_set_muxconf(void) { - return omap_mmc_init(0); + /* DSS */ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/ + + MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/ + MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/ + MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/ + MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/ + MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/ +} + +void set_muxconf_regs(void) +{ + cm_t3x_set_common_muxconf(); + + if (get_cpu_family() == CPU_OMAP34XX) + cm_t35_set_muxconf(); + else + cm_t3730_set_muxconf(); } -#endif /* * Routine: setup_net_chip_gmpc @@ -277,7 +323,7 @@ static void setup_net_chip_gmpc(void) struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5], - CM_T35_SMC911X_BASE, GPMC_SIZE_16M); + CM_T3X_SMC911X_BASE, GPMC_SIZE_16M); enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4], SB_T35_SMC911X_BASE, GPMC_SIZE_16M); @@ -356,9 +402,9 @@ int board_eth_init(bd_t *bis) rc1 = handle_mac_address(); if (rc1) - printf("CM-T35: No MAC address found\n"); + printf("CM-T3x: No MAC address found\n"); - rc1 = smc911x_initialize(0, CM_T35_SMC911X_BASE); + rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE); if (rc1 > 0) rc++; diff --git a/board/cm_t35/leds.c b/board/cm_t35/leds.c new file mode 100644 index 000000000..71c5b0de5 --- /dev/null +++ b/board/cm_t35/leds.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2011 + * CompuLab, Ltd. <www.compulab.co.il> + * + * Author: Igor Grinberg <grinberg@compulab.co.il> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#include <common.h> +#include <status_led.h> +#include <asm/arch/gpio.h> + +static unsigned int leds[] = { GREEN_LED_GPIO }; + +void __led_init(led_id_t mask, int state) +{ + if (omap_request_gpio(leds[mask]) != 0) { + printf("%s: failed requesting GPIO%u\n", __func__, leds[mask]); + return; + } + + omap_set_gpio_direction(leds[mask], 0); +} + +void __led_set(led_id_t mask, int state) +{ + omap_set_gpio_dataout(leds[mask], state == STATUS_LED_ON); +} + +void __led_toggle(led_id_t mask) +{ + omap_set_gpio_dataout(leds[mask], !omap_get_gpio_datain(leds[mask])); +} diff --git a/board/freescale/mx53evk/config.mk b/board/comelit/dig297/Makefile index 0e60454de..8dffedd34 100644 --- a/board/freescale/mx53evk/config.mk +++ b/board/comelit/dig297/Makefile @@ -1,5 +1,6 @@ # -# Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this # project. @@ -20,5 +21,29 @@ # MA 02111-1307 USA # -IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg -ALL += $(obj)u-boot.imx +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := dig297.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c new file mode 100644 index 000000000..0062f120d --- /dev/null +++ b/board/comelit/dig297/dig297.c @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2011 Comelit Group SpA + * Luca Ceresoli <luca.ceresoli@comelit.it> + * + * Based on board/ti/beagle/beagle.c: + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * Author : + * Sunil Kumar <sunilsaini05@gmail.com> + * Shashi Ranjan <shashiranjanmca05@gmail.com> + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <netdev.h> +#include <twl4030.h> +#include <asm/io.h> +#include <asm/arch/omap3-regs.h> +#include <asm/arch/mux.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> +#include "dig297.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CMD_NET +static void setup_net_chip(void); + +#define NET_LAN9221_RESET_GPIO 12 + +/* GPMC CS 5 connected to an SMSC LAN9220 ethernet controller */ +#define NET_LAN9220_GPMC_CONFIG1 (DEVICESIZE_16BIT) +#define NET_LAN9220_GPMC_CONFIG2 (CSWROFFTIME(8) | \ + CSRDOFFTIME(7) | \ + ADVONTIME(1)) +#define NET_LAN9220_GPMC_CONFIG3 (ADVWROFFTIME(2) | \ + ADVRDOFFTIME(2) | \ + ADVONTIME(1)) +#define NET_LAN9220_GPMC_CONFIG4 (WEOFFTIME(8) | \ + WEONTIME(1) | \ + OEOFFTIME(7)| \ + OEONTIME(1)) +#define NET_LAN9220_GPMC_CONFIG5 (PAGEBURSTACCESSTIME(0) | \ + RDACCESSTIME(6) | \ + WRCYCLETIME(0x1D) | \ + RDCYCLETIME(0x1D)) +#define NET_LAN9220_GPMC_CONFIG6 ((1 << 31) | \ + WRACCESSTIME(0x1D) | \ + WRDATAONADMUXBUS(3)) + +static const u32 gpmc_lan_config[] = { + NET_LAN9220_GPMC_CONFIG1, + NET_LAN9220_GPMC_CONFIG2, + NET_LAN9220_GPMC_CONFIG3, + NET_LAN9220_GPMC_CONFIG4, + NET_LAN9220_GPMC_CONFIG5, + NET_LAN9220_GPMC_CONFIG6, + /* CONFIG7: computed by enable_gpmc_cs_config() */ +}; +#endif /* CONFIG_CMD_NET */ + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CPS; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: Configure board specific parts + */ +int misc_init_r(void) +{ + struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE; + struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; + + twl4030_power_init(); + twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); + + /* + * GPIO list + * - 159 OUT (GPIO5+31): reset for remote camera interface connector. + * - 19 OUT (GPIO1+19): integrated speaker amplifier (1=on, 0=shdn). + * - 20 OUT (GPIO1+20): handset amplifier (1=on, 0=shdn). + */ + + /* Configure GPIOs to output */ + writel(~(GPIO19 | GPIO20), &gpio1_base->oe); + writel(~(GPIO31), &gpio5_base->oe); + + /* Set GPIO values */ + writel((GPIO19 | GPIO20), &gpio1_base->setdataout); + writel(0, &gpio5_base->setdataout); + +#if defined(CONFIG_CMD_NET) + setup_net_chip(); +#endif + + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_DIG297(); +} + +#ifdef CONFIG_CMD_NET +/* + * Routine: setup_net_chip + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. + */ +static void setup_net_chip(void) +{ + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + + /* Configure GPMC registers */ + enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], + CONFIG_SMC911X_BASE, GPMC_SIZE_16M); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale); + + /* Make GPIO 12 as output pin and send a magic pulse through it */ + if (!omap_request_gpio(NET_LAN9221_RESET_GPIO)) { + omap_set_gpio_direction(NET_LAN9221_RESET_GPIO, 0); + omap_set_gpio_dataout(NET_LAN9221_RESET_GPIO, 1); + udelay(1); + omap_set_gpio_dataout(NET_LAN9221_RESET_GPIO, 0); + udelay(31000); /* Should be >= 30ms according to datasheet */ + omap_set_gpio_dataout(NET_LAN9221_RESET_GPIO, 1); + } +} +#endif /* CONFIG_CMD_NET */ + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + return rc; +} diff --git a/board/comelit/dig297/dig297.h b/board/comelit/dig297/dig297.h new file mode 100644 index 000000000..68ba7c5a2 --- /dev/null +++ b/board/comelit/dig297/dig297.h @@ -0,0 +1,383 @@ +/* + * (C) Copyright 2011 Comelit Group SpA + * Luca Ceresoli <luca.ceresoli@comelit.it> + * + * Based on board/ti/beagle/beagle.h: + * (C) Copyright 2008 + * Dirk Behme <dirk.behme@gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _DIG297_H_ +#define _DIG297_H_ + +const omap3_sysinfo sysinfo = { + DDR_STACKED, + "OMAP3 DIG297 board", + "NAND", +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DIG297() \ +/*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /*sdrc_cke1: NC*/\ +/*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*NAND*/\ + /* GPMC_nCS1/2: not available on CUS package*/\ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\ + MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M0)) /*GPMC_nBE1: NC*/\ + /* GPMC_WAIT2: not available on CUS package*/\ + MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | DIS | M0)) /*GPMC_WAIT3: NC*/\ + /* GPMC_CLK: NC (only asyncronous peripherals are connected) */\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + /* GPMC_WAIT1: not available on CUS package*/\ +/*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + /* DSS_ACBIAS: AC BIAS: connected to TFT, not to be driven */\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTU | EN | M7))\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ +/*CAMERA*/\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ +/*Audio Interface */\ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ +/*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ +/*Wireless LAN */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ +/*Bluetooth*/\ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\ + MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\ + MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\ + MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\ + MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\ +/*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \ + MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\ + MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ +/*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ +/* USB EHCI (port 2) */\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA0*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA1*/\ +/* MCSPI1: to TOUCH controller TSC2046 (ADS7846 compatible).*/\ + /* + * McSPI1_CLK. + * IEN needed fot the McSPI to "receive" the clock and be able to + * sample SOMI. See http://e2e.ti.com/support/arm174_microprocessors/ + * omap_applications_processors/f/42/p/29444/102394.aspx#102394 + */\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTD | EN | M0)) /*McSPI1_SIMO*/\ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) /*McSPI1_SOMI*/\ + MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTU | EN | M0)) /*McSPI1_CS0*/\ +/* MCSPI2: to HIMAX TFT controller.*/\ + MUX_VAL(CP(MCSPI2_CLK), (IDIS | PTD | EN | M0)) /*MCSPI2_CLK*/\ + MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | EN | M0)) /*MCSPI3_SIMO*/\ + /* MCSPI3_SOMI: NC because HIMAX in monodirectional (no SOMI line) */\ + MUX_VAL(CP(MCSPI2_SOMI), (IDIS | PTU | DIS | M7))\ + MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTU | EN | M0)) /*MCSPI3_CS0*/\ + MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTU | DIS | M7)) /*Safe mode: NC*/\ +/* GPIO */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M4)) /*GPIO_12*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) /*GPIO_13*/\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M4)) /*GPIO_14*/\ + MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTD | EN | M4)) /*GPIO_15*/\ + MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTD | EN | M4)) /*GPIO_16*/\ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M4)) /*GPIO_17*/\ + MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTD | EN | M4)) /*GPIO_18*/\ + MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTD | EN | M4)) /*GPIO_19*/\ + MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTD | EN | M4)) /*GPIO_20*/\ + MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTD | EN | M4)) /*GPIO_21*/\ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M4)) /*GPIO_23*/\ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) /*GPIO_24*/\ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | EN | M4)) /*GPIO_25*/\ + MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | EN | M4)) /*GPIO_26*/\ + MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | EN | M4)) /*GPIO_27*/\ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M4)) /*GPIO_156*/\ + MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\ + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ + MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M4)) /*GPIO_161*/\ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | EN | M4)) /*GPIO_164*/\ + MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | DIS | M4)) /*GPIO_170*/\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) /*GPIO_177*/\ +/*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */ + +#endif diff --git a/board/davedenx/qong/fpga.c b/board/davedenx/qong/fpga.c index 656d5cde9..789acf069 100644 --- a/board/davedenx/qong/fpga.c +++ b/board/davedenx/qong/fpga.c @@ -23,8 +23,8 @@ */ #include <common.h> -#include <asm/arch/mx31.h> -#include <asm/arch/mx31-regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> #include <mxc_gpio.h> #include <fpga.h> #include <lattice.h> diff --git a/board/davedenx/qong/lowlevel_init.S b/board/davedenx/qong/lowlevel_init.S index 80bed9232..85fbfc364 100644 --- a/board/davedenx/qong/lowlevel_init.S +++ b/board/davedenx/qong/lowlevel_init.S @@ -20,7 +20,7 @@ * MA 02111-1307 USA */ -#include <asm/arch/mx31-regs.h> +#include <asm/arch/imx-regs.h> .macro REG reg, val ldr r2, =\reg diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index 8a81cfc68..b1238d505 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -23,16 +23,24 @@ #include <common.h> #include <netdev.h> -#include <asm/arch/mx31.h> -#include <asm/arch/mx31-regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> #include <asm/io.h> #include <nand.h> #include <fsl_pmic.h> #include <mxc_gpio.h> #include "qong_fpga.h" +#include <watchdog.h> DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_HW_WATCHDOG +void hw_watchdog_reset(void) +{ + mxc_hw_watchdog_reset(); +} +#endif + int dram_init (void) { /* dram_init must store complete ramsize in gd->ram_size */ @@ -202,6 +210,10 @@ int board_late_init(void) pmic_reg_write(REG_POWER_CTL0, val | COINCHEN); pmic_reg_write(REG_INT_STATUS1, RTCRSTI); +#ifdef CONFIG_HW_WATCHDOG + mxc_hw_watchdog_enable(); +#endif + return 0; } diff --git a/board/eukrea/cpu9260/config.mk b/board/eukrea/cpu9260/config.mk deleted file mode 100644 index 207769233..000000000 --- a/board/eukrea/cpu9260/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x21f00000 diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c index 61b6c3323..9ec48a0d2 100644 --- a/board/eukrea/cpu9260/cpu9260.c +++ b/board/eukrea/cpu9260/cpu9260.c @@ -29,12 +29,13 @@ #include <common.h> #include <asm/sizes.h> #include <asm/arch/at91sam9260.h> -#include <asm/arch/at91sam9_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> -#include <asm/arch/gpio.h> +#include <asm/arch/at91_matrix.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/clk.h> #include <asm/arch/io.h> #include <asm/arch/hardware.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) @@ -53,116 +54,103 @@ DECLARE_GLOBAL_DATA_PTR; static void cpu9260_nand_hw_init(void) { unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE; + at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa); /* Configure SMC CS3 for NAND/SmartMedia */ #if defined(CONFIG_CPU9G20) - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(4) | - AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(4)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_DBW_8 | - AT91_SMC_TDF_(3)); + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); #elif defined(CONFIG_CPU9260) - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_DBW_8 | - AT91_SMC_TDF_(2)); + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); #endif - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); + writel(1 << AT91SAM9260_ID_PIOC, &pmc->pcer); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif #ifdef CONFIG_MACB static void cpu9260_macb_hw_init(void) { - unsigned long rstc; + unsigned long rstcmr; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE; /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); - - /* - * Disable pull-up on: - * RXDV (PA17) => PHY normal mode (not Test mode) - * ERX0 (PA14) => PHY ADDR0 - * ERX1 (PA15) => PHY ADDR1 - * ERX2 (PA25) => PHY ADDR2 - * ERX3 (PA26) => PHY ADDR3 - * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 - * - * PHY has internal pull-down - */ - writel(pin_to_mask(AT91_PIN_PA14) | - pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA17) | - pin_to_mask(AT91_PIN_PA25) | - pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); - - rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + writel(1 << AT91SAM9260_ID_EMAC, &pmc->pcer); + + at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1); + + rstcmr = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; /* Need to reset PHY -> 500ms reset */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (AT91_RSTC_ERSTL & (0x0D << 8)) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0xD) | + AT91_RSTC_MR_URSTEN, &rstc->mr); - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end hardware reset */ - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)) + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) ; /* Restore NRST value */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (rstc) | - AT91_RSTC_URSTEN); - - /* Re-enable pull-up */ - writel(pin_to_mask(AT91_PIN_PA14) | - pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA17) | - pin_to_mask(AT91_PIN_PA25) | - pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), - pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + writel(AT91_RSTC_KEY | rstcmr | AT91_RSTC_MR_URSTEN, &rstc->mr); at91_macb_hw_init(); } #endif -int board_init(void) +int board_early_init_f(void) { - /* Enable Ctrlc */ - console_init_f(); + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + writel((1 << AT91SAM9260_ID_PIOA) | + (1 << AT91SAM9260_ID_PIOC) | + (1 << AT91SAM9260_ID_PIOB), + &pmc->pcer); + + at91_serial_hw_init(); + + return 0; +} + +int board_init(void) +{ /* arch number of the board */ #if defined(CONFIG_CPU9G20) gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20; @@ -171,9 +159,8 @@ int board_init(void) #endif /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); #ifdef CONFIG_CMD_NAND cpu9260_nand_hw_init(); #endif @@ -188,26 +175,16 @@ int board_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - if (get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != - PHYS_SDRAM_SIZE) - return -1; - - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } -#ifdef CONFIG_RESET_PHY_R -void reset_phy(void) -{ -} -#endif - int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00); + rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0); #endif return rc; } diff --git a/board/eukrea/cpu9260/led.c b/board/eukrea/cpu9260/led.c index e73543bb1..d0906bc89 100644 --- a/board/eukrea/cpu9260/led.c +++ b/board/eukrea/cpu9260/led.c @@ -35,65 +35,67 @@ static unsigned int saved_state[4] = {STATUS_LED_OFF, STATUS_LED_OFF, void coloured_LED_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); + writel(1 << AT91SAM9260_ID_PIOC, &pmc->pcer); - at91_set_gpio_output(CONFIG_RED_LED, 1); - at91_set_gpio_output(CONFIG_GREEN_LED, 1); - at91_set_gpio_output(CONFIG_YELLOW_LED, 1); - at91_set_gpio_output(CONFIG_BLUE_LED, 1); + at91_set_pio_output(CONFIG_RED_LED, 1); + at91_set_pio_output(CONFIG_GREEN_LED, 1); + at91_set_pio_output(CONFIG_YELLOW_LED, 1); + at91_set_pio_output(CONFIG_BLUE_LED, 1); - at91_set_gpio_value(CONFIG_RED_LED, 1); - at91_set_gpio_value(CONFIG_GREEN_LED, 1); - at91_set_gpio_value(CONFIG_YELLOW_LED, 1); - at91_set_gpio_value(CONFIG_BLUE_LED, 1); + at91_set_pio_value(CONFIG_RED_LED, 1); + at91_set_pio_value(CONFIG_GREEN_LED, 1); + at91_set_pio_value(CONFIG_YELLOW_LED, 1); + at91_set_pio_value(CONFIG_BLUE_LED, 1); } void red_LED_off(void) { - at91_set_gpio_value(CONFIG_RED_LED, 1); + at91_set_pio_value(CONFIG_RED_LED, 1); saved_state[STATUS_LED_RED] = STATUS_LED_OFF; } void green_LED_off(void) { - at91_set_gpio_value(CONFIG_GREEN_LED, 1); + at91_set_pio_value(CONFIG_GREEN_LED, 1); saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF; } void yellow_LED_off(void) { - at91_set_gpio_value(CONFIG_YELLOW_LED, 1); + at91_set_pio_value(CONFIG_YELLOW_LED, 1); saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF; } void blue_LED_off(void) { - at91_set_gpio_value(CONFIG_BLUE_LED, 1); + at91_set_pio_value(CONFIG_BLUE_LED, 1); saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF; } void red_LED_on(void) { - at91_set_gpio_value(CONFIG_RED_LED, 0); + at91_set_pio_value(CONFIG_RED_LED, 0); saved_state[STATUS_LED_RED] = STATUS_LED_ON; } void green_LED_on(void) { - at91_set_gpio_value(CONFIG_GREEN_LED, 0); + at91_set_pio_value(CONFIG_GREEN_LED, 0); saved_state[STATUS_LED_GREEN] = STATUS_LED_ON; } void yellow_LED_on(void) { - at91_set_gpio_value(CONFIG_YELLOW_LED, 0); + at91_set_pio_value(CONFIG_YELLOW_LED, 0); saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON; } void blue_LED_on(void) { - at91_set_gpio_value(CONFIG_BLUE_LED, 0); + at91_set_pio_value(CONFIG_BLUE_LED, 0); saved_state[STATUS_LED_BLUE] = STATUS_LED_ON; } diff --git a/board/eukrea/cpuat91/Makefile b/board/eukrea/cpuat91/Makefile index 15da3d87a..1d62b1309 100644 --- a/board/eukrea/cpuat91/Makefile +++ b/board/eukrea/cpuat91/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := cpuat91.o +COBJS := $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/eukrea/cpuat91/config.mk b/board/eukrea/cpuat91/config.mk deleted file mode 100644 index 463f46bc5..000000000 --- a/board/eukrea/cpuat91/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x21F00000 diff --git a/board/eukrea/cpuat91/cpuat91.c b/board/eukrea/cpuat91/cpuat91.c index cd4d42c6b..4c4dad655 100644 --- a/board/eukrea/cpuat91/cpuat91.c +++ b/board/eukrea/cpuat91/cpuat91.c @@ -47,24 +47,23 @@ int board_init(void) /* arch number of CPUAT91-Board */ gd->bd->bi_arch_number = MACH_TYPE_CPUAT91; /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; return 0; } int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } #ifdef CONFIG_DRIVER_AT91EMAC int board_eth_init(bd_t *bis) { - int rc = 0; - rc = at91emac_register(bis, 0); - return rc; + return at91emac_register(bis, (u32) AT91_EMAC_BASE); } #endif diff --git a/board/faraday/a320evb/a320evb.c b/board/faraday/a320evb/a320evb.c index b9343e42d..2578be4f9 100644 --- a/board/faraday/a320evb/a320evb.c +++ b/board/faraday/a320evb/a320evb.c @@ -21,7 +21,7 @@ #include <netdev.h> #include <asm/io.h> -#include <asm/arch/ftsmc020.h> +#include <faraday/ftsmc020.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/faraday/a320evb/lowlevel_init.S b/board/faraday/a320evb/lowlevel_init.S index 97718c0c0..4262c116c 100644 --- a/board/faraday/a320evb/lowlevel_init.S +++ b/board/faraday/a320evb/lowlevel_init.S @@ -21,7 +21,7 @@ #include <version.h> #include <asm/macro.h> -#include <asm/arch/ftsdmc020.h> +#include <faraday/ftsdmc020.h> /* * parameters for the SDRAM controller diff --git a/board/freescale/mx31ads/lowlevel_init.S b/board/freescale/mx31ads/lowlevel_init.S index e16605836..5c18bc196 100644 --- a/board/freescale/mx31ads/lowlevel_init.S +++ b/board/freescale/mx31ads/lowlevel_init.S @@ -17,7 +17,7 @@ * MA 02111-1307 USA */ -#include <asm/arch/mx31-regs.h> +#include <asm/arch/imx-regs.h> .macro REG reg, val ldr r2, =\reg diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c index bc25c6deb..a298e0530 100644 --- a/board/freescale/mx31ads/mx31ads.c +++ b/board/freescale/mx31ads/mx31ads.c @@ -23,8 +23,8 @@ #include <common.h> #include <netdev.h> #include <asm/io.h> -#include <asm/arch/mx31.h> -#include <asm/arch/mx31-regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/mx31pdk/lowlevel_init.S b/board/freescale/mx31pdk/lowlevel_init.S index cd0503ec3..5b35bb476 100644 --- a/board/freescale/mx31pdk/lowlevel_init.S +++ b/board/freescale/mx31pdk/lowlevel_init.S @@ -21,7 +21,7 @@ */ #include <config.h> -#include <asm/arch/mx31-regs.h> +#include <asm/arch/imx-regs.h> #include <asm/macro.h> .globl lowlevel_init diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index a9f0fb477..826fb4a86 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -26,8 +26,8 @@ #include <common.h> #include <netdev.h> -#include <asm/arch/mx31.h> -#include <asm/arch/mx31-regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> DECLARE_GLOBAL_DATA_PTR; @@ -70,7 +70,7 @@ int board_init(void) int checkboard(void) { - printf("Board: i.MX31 MAX PDK (3DS)\n"); + printf("Board: MX31PDK\n"); return 0; } diff --git a/board/freescale/mx51evk/config.mk b/board/freescale/mx51evk/config.mk deleted file mode 100644 index 6e90671d0..000000000 --- a/board/freescale/mx51evk/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -CONFIG_SYS_TEXT_BASE = 0x97800000 -IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg -ALL += $(obj)u-boot.imx diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c index 3d7b7f70c..82daaa324 100644 --- a/board/imx31_phycore/imx31_phycore.c +++ b/board/imx31_phycore/imx31_phycore.c @@ -25,8 +25,8 @@ #include <common.h> #include <s6e63d6.h> #include <netdev.h> -#include <asm/arch/mx31.h> -#include <asm/arch/mx31-regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S index c5d6eb05f..c47137d09 100644 --- a/board/imx31_phycore/lowlevel_init.S +++ b/board/imx31_phycore/lowlevel_init.S @@ -21,7 +21,7 @@ * MA 02111-1307 USA */ -#include <asm/arch/mx31-regs.h> +#include <asm/arch/imx-regs.h> .macro REG reg, val ldr r2, =\reg diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c index e658c3529..22de7e340 100644 --- a/board/innokom/innokom.c +++ b/board/innokom/innokom.c @@ -45,12 +45,7 @@ DECLARE_GLOBAL_DATA_PTR; */ int i2c_init_board(void) { - int i, icr; - - /* disable I2C controller first, otherwhise it thinks we want to */ - /* talk to the slave port... */ - icr = readl(ICR); - writel(readl(ICR) & ~(ICR_SCLE | ICR_IUE), ICR); + int i; /* set gpio pin low _before_ we change direction to output */ writel(GPIO_bit(70), GPCR(70)); @@ -63,8 +58,6 @@ int i2c_init_board(void) udelay(10); } - writel(icr, ICR); - return 0; } diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index dc57d5c48..269858c6e 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -141,9 +141,9 @@ void tx25_fec_init(void) int board_init() { #ifdef CONFIG_MXC_UART - extern void mx25_uart_init_pins(void); + extern void mx25_uart1_init_pins(void); - mx25_uart_init_pins(); + mx25_uart1_init_pins(); #endif /* board id for linux */ gd->bd->bi_arch_number = MACH_TYPE_TX25; diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c index a07ba0efc..2ed742fb5 100644 --- a/board/logicpd/imx31_litekit/imx31_litekit.c +++ b/board/logicpd/imx31_litekit/imx31_litekit.c @@ -24,8 +24,8 @@ #include <common.h> #include <netdev.h> -#include <asm/arch/mx31.h> -#include <asm/arch/mx31-regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/logicpd/imx31_litekit/lowlevel_init.S b/board/logicpd/imx31_litekit/lowlevel_init.S index 0003a4242..95b0c080c 100644 --- a/board/logicpd/imx31_litekit/lowlevel_init.S +++ b/board/logicpd/imx31_litekit/lowlevel_init.S @@ -21,7 +21,7 @@ * MA 02111-1307 USA */ -#include <asm/arch/mx31-regs.h> +#include <asm/arch/imx-regs.h> .macro REG reg, val ldr r2, =\reg diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 369cb2228..3d6c24847 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -30,6 +30,7 @@ #include <asm/arch/clk_rst.h> #include <asm/arch/pinmux.h> #include <asm/arch/uart.h> +#include "board.h" DECLARE_GLOBAL_DATA_PTR; @@ -37,6 +38,24 @@ const struct tegra2_sysinfo sysinfo = { CONFIG_TEGRA2_BOARD_STRING }; +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + /* Initialize periph clocks */ + clock_init(); + + /* Initialize periph pinmuxes */ + pinmux_init(); + + /* Initialize periph GPIOs */ + gpio_init(); + + /* Init UART, scratch regs, and start CPU */ + tegra2_start(); + return 0; +} +#endif /* EARLY_INIT */ + /* * Routine: timer_init * Description: init the timestamp and lastinc value @@ -54,10 +73,10 @@ int timer_init(void) static void clock_init_uart(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - static int pllp_init_done; u32 reg; - if (!pllp_init_done) { + reg = readl(&clkrst->crc_pllp_base); + if (!(reg & PLL_BASE_OVRRIDE)) { /* Override pllp setup for 216MHz operation. */ reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP); reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM); @@ -68,8 +87,6 @@ static void clock_init_uart(void) reg &= ~PLL_BYPASS; writel(reg, &clkrst->crc_pllp_base); - - pllp_init_done++; } /* Now do the UART reset/clock enable */ @@ -172,6 +189,15 @@ void pinmux_init(void) } /* + * Routine: gpio_init + * Description: Do individual peripheral GPIO configs + */ +void gpio_init(void) +{ + gpio_config_uart(); +} + +/* * Routine: board_init * Description: Early hardware init. */ @@ -182,11 +208,5 @@ int board_init(void) /* board id for Linux */ gd->bd->bi_arch_number = CONFIG_MACH_TYPE; - /* Initialize peripheral clocks */ - clock_init(); - - /* Initialize periph pinmuxes */ - pinmux_init(); - return 0; } diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h new file mode 100644 index 000000000..350bc5750 --- /dev/null +++ b/board/nvidia/common/board.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void tegra2_start(void); +void clock_init(void); +void pinmux_init(void); +void gpio_init(void); +void gpio_config_uart(void); + +#endif /* BOARD_H */ diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile index 3a146cb9c..9fb6b575a 100644 --- a/board/nvidia/harmony/Makefile +++ b/board/nvidia/harmony/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +COBJS := $(BOARD).o COBJS += ../common/board.o SRCS := $(COBJS:.o=.c) diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c new file mode 100644 index 000000000..f1ab05089 --- /dev/null +++ b/board/nvidia/harmony/harmony.c @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/tegra2.h> + +/* + * Routine: gpio_config_uart + * Description: Does nothing on Harmony - no conflict w/SPI. + */ +void gpio_config_uart(void) +{ +} diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile index 3a146cb9c..9fb6b575a 100644 --- a/board/nvidia/seaboard/Makefile +++ b/board/nvidia/seaboard/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +COBJS := $(BOARD).o COBJS += ../common/board.o SRCS := $(COBJS:.o=.c) diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c new file mode 100644 index 000000000..4b9a8f33e --- /dev/null +++ b/board/nvidia/seaboard/seaboard.c @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/gpio.h> + +/* + * Routine: gpio_config_uart + * Description: Force GPIO_PI3 low on Seaboard so UART4 works. + */ +void gpio_config_uart(void) +{ + int gp = GPIO_PI3; + struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + u32 val; + + /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ + val = readl(&bank->gpio_config[GPIO_PORT(gp)]); + val |= 1 << GPIO_BIT(gp); + writel(val, &bank->gpio_config[GPIO_PORT(gp)]); + + val = readl(&bank->gpio_out[GPIO_PORT(gp)]); + val &= ~(1 << GPIO_BIT(gp)); + writel(val, &bank->gpio_out[GPIO_PORT(gp)]); + + val = readl(&bank->gpio_dir_out[GPIO_PORT(gp)]); + val |= 1 << GPIO_BIT(gp); + writel(val, &bank->gpio_dir_out[GPIO_PORT(gp)]); +} diff --git a/board/st/nhk8815/Makefile b/board/st/nhk8815/Makefile index 3f360dcf2..60b87b192 100644 --- a/board/st/nhk8815/Makefile +++ b/board/st/nhk8815/Makefile @@ -30,7 +30,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o COBJS := nhk8815.o -SOBJS := platform.o +SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/st/nhk8815/config.mk b/board/st/nhk8815/config.mk deleted file mode 100644 index 1789717fc..000000000 --- a/board/st/nhk8815/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# (C) Copyright 2007 -# STMicroelectronics, <www.st.com> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# -# image should be loaded at 0x01000000 -# - -CONFIG_SYS_TEXT_BASE = 0x03F80000 diff --git a/board/st/nhk8815/nhk8815.c b/board/st/nhk8815/nhk8815.c index faef8109d..9b6201127 100644 --- a/board/st/nhk8815/nhk8815.c +++ b/board/st/nhk8815/nhk8815.c @@ -82,13 +82,18 @@ int board_late_init(void) int dram_init(void) { - /* set dram bank start addr and size */ + gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - return 0; } #ifdef CONFIG_CMD_NET diff --git a/board/st/nhk8815/platform.S b/board/st/nhk8815/platform.S deleted file mode 100644 index 2a6711023..000000000 --- a/board/st/nhk8815/platform.S +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2005 - * STMicrolelctronics, <www.st.com> - * - * (C) Copyright 2004, ARM Ltd. - * Philippe Robin, <philippe.robin@arm.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> - -.globl lowlevel_init -lowlevel_init: - /* Jump to the flash address */ - ldr r0, =CFG_ONENAND_BASE - - /* - * Make it independent whether we boot from 0x0 or 0x30000000. - * Non-portable: it relies on the knowledge that ip has to be updated - */ - orr ip, ip, r0 /* adjust return address of cpu_init_crit */ - orr lr, lr, r0 /* adjust return address */ - orr pc, pc, r0 /* jump to the normal address */ - nop - - /* Initialize PLL, Remap clear, FSMC, MPMC here! */ - /* What about GPIO, CLCD and UART */ - - /* PLL Initialization */ - /* Prog the PLL1 @ 266 MHz ==> SDRAM Clock = 100.8 MHz */ - ldr r0, =NOMADIK_SRC_BASE - - ldr r1, =0x2B013502 - - str r1, [r0, #0x14] - - /* Used to set all the timers clock to 2.4MHZ */ - ldr r1, =0x2AAAA004 - str r1, [r0] - - ldr r1, =0x10000000 - str r1, [r0, #0x10] - - /* FSMC setup ---- */ - ldr r0, =NOMADIK_FSMC_BASE - - ldr r1, =0x10DB /* For 16-bit NOR flash */ - str r1, [r0, #0x08] - - ldr r1, =0x03333333 /* For 16-bit NOR flash */ - str r1, [r0, #0xc] - - /* oneNAND setting */ - ldr r1, =0x0000105B /* BCR0 Prog control register */ - str r1, [r0] - - ldr r1, =0x0A200551 /* BTR0 Prog timing register */ - str r1, [r0, #0x04] - - /* preload the instructions into icache */ - add r0, pc, #0x1F - bic r0, r0, #0x1F - mcr p15, 0, r0, c7, c13, 1 - add r0, r0, #0x20 - mcr p15, 0, r0, c7, c13, 1 - - /* Now Clear Remap */ - ldr r0, =NOMADIK_SRC_BASE - - ldr r1, =0x2004 - str r1, [r0] - - ldr r1, =0x10000000 - str r1, [r0, #0x10] - - ldr r0, =0x101E9000 - ldr r1, =0x2004 - str r1, [r0] - - ldr r0, =NOMADIK_SRC_BASE - ldr r1, =0x2104 - str r1, [r0] - - /* FSMC setup -- */ - mov r0, #(NOMADIK_FSMC_BASE & 0x10000000) - orr r0, r0, #(NOMADIK_FSMC_BASE & 0x0FFFFFFF) - - ldr r1, =0x10DB /* For 16-bit NOR flash */ - str r1, [r0, #0x8] - - ldr r1, =0x03333333 /* For 16-bit NOR flash */ - str r1, [r0, #0xc] - - /* MPMC Setup */ - ldr r0, =NOMADIK_MPMC_BASE - - ldr r1, =0xF00003 - str r1, [r0] /* Enable the MPMC and the DLL */ - - ldr r1, =0x183 - str r1, [r0, #0x20] - - ldr r2, =NOMADIK_PMU_BASE - - ldr r1, =0x1111 - str r1, [r2] - - ldr r1, =0x1111 /* Prog the, mand delay strategy */ - str r1, [r0, #0x28] - - ldr r1, =0x103 /* NOP ,mand */ - str r1, [r0, #0x20] - - /* FIXME -- Wait required here */ - - ldr r1, =0x103 /* PALL ,mand*/ - str r1, [r0, #0x20] - - ldr r1, =0x1 - str r1, [r0, #0x24] /* To do at least two auto-refresh */ - - /* FIXME -- Wait required here */ - - /* Auto-refresh period = 7.8us @ SDRAM Clock = 100.8 MHz */ - ldr r1, =0x31 - str r1, [r0, #0x24] - - /* Prog Little Endian, Not defined in 8800 board */ - ldr r1, =0x0 - str r1, [r0, #0x8] - - - ldr r1, =0x2 - str r1, [r0, #0x30] /* Prog tRP timing */ - - ldr r1, =0x4 /* Change for 8815 */ - str r1, [r0, #0x34] /* Prog tRAS timing */ - - ldr r1, =0xB - str r1, [r0, #0x38] /* Prog tSREX timing */ - - - ldr r1, =0x1 - str r1, [r0, #0x44] /* Prog tWR timing */ - - ldr r1, =0x8 - str r1, [r0, #0x48] /* Prog tRC timing */ - - ldr r1, =0xA - str r1, [r0, #0x4C] /* Prog tRFC timing */ - - ldr r1, =0xB - str r1, [r0, #0x50] /* Prog tXSR timing */ - - ldr r1, =0x1 - str r1, [r0, #0x54] /* Prog tRRD timing */ - - ldr r1, =0x1 - str r1, [r0, #0x58] /* Prog tMRD timing */ - - ldr r1, =0x1 - str r1, [r0, #0x5C] /* Prog tCDLR timing */ - - /* DDR-SDRAM MEMORY IS ON BANK0 8815 */ - ldr r1, =0x304 /* Prog RAS and CAS for CS 0 */ - str r1, [r0, #0x104] - - /* SDR-SDRAM MEMORY IS ON BANK1 8815 */ - ldr r1, =0x304 /* Prog RAS and CAS for CS 1 */ - str r1, [r0, #0x124] - /* THE DATA BUS WIDE IS PROGRAM FOR 16-BITS */ - /* DDR-SDRAM MEMORY IS ON BANK0*/ - - ldr r1, =0x884 /* 8815 : config reg in BRC for CS0 */ - str r1, [r0, #0x100] - - /*SDR-SDRAM MEMORY IS ON BANK1*/ - - ldr r1, =0x884 /* 8815 : config reg in BRC for CS1 */ - str r1, [r0, #0x120] - - ldr r1, =0x83 /*MODE Mand*/ - str r1, [r0, #0x20] - - /* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK0 */ - - ldr r1, =0x62000 /*Data in*/ - ldr r1, [r1] - - /* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK1 */ - - ldr r1, =0x8062000 - ldr r1, [r1] - - ldr r1, =0x003 - str r1, [r0, #0x20] - - /* ENABLE ALL THE BUFFER FOR EACH AHB PORT*/ - - ldr r1, =0x01 /* Enable buffer 0 */ - str r1, [r0, #0x400] - - ldr r1, =0x01 /* Enable buffer 1 */ - str r1, [r0, #0x420] - - ldr r1, =0x01 /* Enable buffer 2 */ - str r1, [r0, #0x440] - - ldr r1, =0x01 /* Enable buffer 3 */ - str r1, [r0, #0x460] - - ldr r1, =0x01 /* Enable buffer 4 */ - str r1, [r0, #0x480] - - ldr r1, =0x01 /* Enable buffer 5 */ - str r1, [r0, #0x4A0] - - /* GPIO settings */ - - ldr r0, =NOMADIK_GPIO1_BASE - - ldr r1, =0xC0600000 - str r1, [r0, #0x20] - - ldr r1, =0x3F9FFFFF /* ABHI change this for uart1 */ - str r1, [r0, #0x24] - - ldr r1, =0x3F9FFFFF /* ABHI change this for uart1 */ - str r1, [r0, #0x28] - - ldr r0, =NOMADIK_GPIO0_BASE - - ldr r1, =0xFFFFFFFF - str r1, [r0, #0x20] - - ldr r1, =0x00 - str r1, [r0, #0x24] - - ldr r1, =0x00 - str r1, [r0, #0x28] - - /* Configure CPLD_CTRL register for enabling MUX logic for UART0/UART2 */ - - ldr r0, =NOMADIK_FSMC_BASE - - ldr r1, =0x10DB /* INIT FSMC bank 0 */ - str r1, [r0, #0x00] - - ldr r1, =0x0FFFFFFF - str r1, [r0, #0x04] - - ldr r1, =0x010DB /* INIT FSMC bank 1 */ - str r1, [r0, #0x08] - - ldr r1, =0x00FFFFFFF - str r1, [r0, #0x0C] - - ldr r0, =NOMADIK_UART0_BASE - - ldr r1, =0x00000000 - str r1, [r0, #0x30] - - ldr r1, =0x0000004e - str r1, [r0, #0x24] - - ldr r1, =0x00000008 - str r1, [r0, #0x28] - - ldr r1, =0x00000060 - str r1, [r0, #0x2C] - - ldr r1, =0x00000301 - str r1, [r0, #0x30] - - ldr r1, =0x00000066 - str r1, [r0] - - ldr r0, =NOMADIK_UART1_BASE - - ldr r1, =0x00000000 - str r1, [r0, #0x30] - - ldr r1, =0x0000004e - str r1, [r0, #0x24] - - ldr r1, =0x00000008 - str r1, [r0, #0x28] - - ldr r1, =0x00000060 - str r1, [r0, #0x2C] - - ldr r1, =0x00000301 - str r1, [r0, #0x30] - - ldr r1, =0x00000066 - str r1, [r0] - - ldr r0, =NOMADIK_UART2_BASE - - ldr r1, =0x00000000 - str r1, [r0, #0x30] - - ldr r1, =0x0000004e - str r1, [r0, #0x24] - - ldr r1, =0x00000008 - str r1, [r0, #0x28] - - ldr r1, =0x00000060 - str r1, [r0, #0x2C] - - ldr r1, =0x00000301 - str r1, [r0, #0x30] - - ldr r1, =0x00000066 - str r1, [r0] - - /* Configure CPLD to enable UART0 */ - - mov pc, lr diff --git a/board/ti/am3517crane/Makefile b/board/ti/am3517crane/Makefile new file mode 100644 index 000000000..1fe2bca0a --- /dev/null +++ b/board/ti/am3517crane/Makefile @@ -0,0 +1,46 @@ +# +# Author: Srinath R <srinath@mistralsolutions.com> +# +# Based on logicpd/am3517evm/Makefile +# +# Copyright (C) 2011 Mistral Solutions Pvt Ltd +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := am3517crane.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c new file mode 100644 index 000000000..d007044b2 --- /dev/null +++ b/board/ti/am3517crane/am3517crane.c @@ -0,0 +1,75 @@ +/* + * am3517crane.c - board file for AM3517 CraneBoard + * + * Author: Srinath.R <srinath@mistralsolutions.com> + * + * Based on logicpd/am3517evm/am3517evm.c + * + * Copyright (C) 2011 Mistral Solutions Pvt Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include <i2c.h> +#include "am3517crane.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_CRANEBOARD; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: Init i2c, ethernet, etc... (done here so udelay works) + */ +int misc_init_r(void) +{ +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_AM3517CRANE(); +} diff --git a/board/ti/am3517crane/am3517crane.h b/board/ti/am3517crane/am3517crane.h new file mode 100644 index 000000000..41db97272 --- /dev/null +++ b/board/ti/am3517crane/am3517crane.h @@ -0,0 +1,395 @@ +/* + * am3517crane.h - Header file for the AM3517 CraneBoard. + * + * Author: Srinath R <srinath@mistralsolutions.com> + * + * Based on logicpd/am3517evm/am3517evm.h + * + * Copyright (C) 2011 Mistral Solutions Pvt Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _AM3517CRANE_H_ +#define _AM3517CRANE_H_ + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "CraneBoard", + "NAND", +}; +/* AM3517 specific mux configuration */ +#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 +/* CCDC */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 +#define CONTROL_PADCONF_CCDC_HD 0x01E8 +#define CONTROL_PADCONF_CCDC_VD 0x01EA +#define CONTROL_PADCONF_CCDC_WEN 0x01EC +#define CONTROL_PADCONF_CCDC_DATA0 0x01EE +#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 +#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 +#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 +#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 +#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 +#define CONTROL_PADCONF_CCDC_DATA6 0x01FA +#define CONTROL_PADCONF_CCDC_DATA7 0x01FC +/* RMII */ +#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE +#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 +#define CONTROL_PADCONF_RMII_RXD0 0x0202 +#define CONTROL_PADCONF_RMII_RXD1 0x0204 +#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 +#define CONTROL_PADCONF_RMII_RXER 0x0208 +#define CONTROL_PADCONF_RMII_TXD0 0x020A +#define CONTROL_PADCONF_RMII_TXD1 0x020C +#define CONTROL_PADCONF_RMII_TXEN 0x020E +#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 +#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 +/* CAN */ +#define CONTROL_PADCONF_HECC1_TXD 0x0214 +#define CONTROL_PADCONF_HECC1_RXD 0x0216 +#define CONTROL_PADCONF_SYS_BOOT7 0x0218 +#define CONTROL_PADCONF_SDRC_DQS0N 0x021A +#define CONTROL_PADCONF_SDRC_DQS1N 0x021C +#define CONTROL_PADCONF_SDRC_DQS2N 0x021E +#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 +#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 +#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 +#define CONTROL_PADCONF_SYS_BOOT8 0x0226 + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_AM3517CRANE()\ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_CKE0), (M0))\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(SDRC_CKE0), (M0))\ + MUX_VAL(CP(SDRC_CKE1), (M0))\ + /*sdrc_strben_dly0*/\ + MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0))\ + /*sdrc_strben_dly1*/\ + MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0))\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (M7))\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | DIS | M4))\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_A6), (M7))\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_A9), (M7))\ + MUX_VAL(CP(GPMC_A10), (M7))\ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_NCS2), (M7))\ + MUX_VAL(CP(GPMC_NCS3), (M7))\ + MUX_VAL(CP(GPMC_NCS4), (M7))\ + MUX_VAL(CP(GPMC_NCS5), (M7))\ + MUX_VAL(CP(GPMC_NCS6), (M7))\ + MUX_VAL(CP(GPMC_NCS7), (M7))\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0))/*TP*/\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_NBE1), (M7))\ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_WAIT1), (M7))\ + MUX_VAL(CP(GPMC_WAIT2), (M7))\ + MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4))/*GPIO_65*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0))\ + /*MMC1*/\ + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0))\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0))\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0))\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0))\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0))\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | DIS | M0))\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | DIS | M0))\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | DIS | M0))\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M0))\ + /*MMC2*/\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0))\ + /*McBSP*/\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0))\ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0))\ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0))\ + \ + MUX_VAL(CP(MCBSP2_FSX), (M7))\ + MUX_VAL(CP(MCBSP2_CLKX), (M7))\ + MUX_VAL(CP(MCBSP2_DR), (M7))\ + MUX_VAL(CP(MCBSP2_DX), (M7))\ + \ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0))\ + \ + MUX_VAL(CP(MCBSP4_CLKX), (M7))\ + MUX_VAL(CP(MCBSP4_DR), (M7))\ + MUX_VAL(CP(MCBSP4_DX), (M7))\ + MUX_VAL(CP(MCBSP4_FSX), (M7))\ + /*UART*/\ + MUX_VAL(CP(UART1_TX), (M7))\ + MUX_VAL(CP(UART1_RTS), (M7))\ + MUX_VAL(CP(UART1_CTS), (M7))\ + MUX_VAL(CP(UART1_RX), (M7))\ + \ + MUX_VAL(CP(UART2_CTS), (M7))\ + MUX_VAL(CP(UART2_RTS), (M7))\ + MUX_VAL(CP(UART2_TX), (M7))\ + MUX_VAL(CP(UART2_RX), (M7))\ + \ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0))\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0))\ + /*I2C 1, 2, 3*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\ + /*McSPI*/\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4))/*GPIO_171 TP*/\ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4))/*GPIO_172 TP*/\ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4))/*GPIO_173 TP*/\ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTU | EN | M4))/*GPIO_174 TP*/\ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4))/*GPIO_175 TP*/\ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4))/*GPIO_176 TP*/\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4))/*GPIO_176 TP*/\ + \ + MUX_VAL(CP(MCSPI2_CLK), (M7))\ + MUX_VAL(CP(MCSPI2_SIMO), (M7))\ + MUX_VAL(CP(MCSPI2_SOMI), (M7))\ + MUX_VAL(CP(MCSPI2_CS0), (M7))\ + MUX_VAL(CP(MCSPI2_CS1), (M7))\ + /*CCDC*/\ + MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1))/*CCDC_DATA8*/\ + MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1))/*CCDC_DATA9 */\ + MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0))\ + /*RMII*/\ + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0))\ + MUX_VAL(CP(RMII_MDIO_CLK), (M0))\ + MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0))\ + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0))\ + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0))\ + MUX_VAL(CP(RMII_RXER), (PTD | M0))\ + MUX_VAL(CP(RMII_TXD0), (PTD | M0))\ + MUX_VAL(CP(RMII_TXD1), (PTD | M0))\ + MUX_VAL(CP(RMII_TXEN), (PTD | M0))\ + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0))\ + /*HECC*/\ + MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0))\ + /*HSUSB*/\ + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0))\ + /*HDQ*/\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4))\ + /*Control and debug*/\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M4))/*GPIO_1 TPS_SLEEP*/\ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0))\ + /*SYS_nRESWARM*/\ + MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | EN | M0))/*GPIO_30 ToExp*/\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))/*GPIO_10 TP*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0))\ + /*JTAG*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0))\ + /*ETK (ES2 onwards)*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M3))\ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3))\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M3))\ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M3))\ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3))\ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M3))\ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M3))\ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M3))\ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M3))\ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M3))\ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M3))\ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M3))\ + MUX_VAL(CP(ETK_D10_ES2), (M7))\ + MUX_VAL(CP(ETK_D11_ES2), (M7))\ + MUX_VAL(CP(ETK_D12_ES2), (M7))\ + MUX_VAL(CP(ETK_D13_ES2), (M7))\ + MUX_VAL(CP(ETK_D14_ES2), (M7))\ + MUX_VAL(CP(ETK_D15_ES2), (M7))\ + /*Die to Die*/\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0))\ + +#endif /* _AM3517CRANE_H_ */ diff --git a/board/ti/am3517crane/config.mk b/board/ti/am3517crane/config.mk new file mode 100644 index 000000000..c6a18b510 --- /dev/null +++ b/board/ti/am3517crane/config.mk @@ -0,0 +1,29 @@ +# +# Author: Srinath R <srinath@mistralsolutions.com> +# +# Based on logicpd/am3517evm/config.mk +# +# Copyright (C) 2011 Mistral Solutions Pvt Ltd +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/ti/beagle/Makefile b/board/ti/beagle/Makefile index 3b4aaace2..d9f445f00 100644 --- a/board/ti/beagle/Makefile +++ b/board/ti/beagle/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := beagle.o +COBJS-y := $(BOARD).o +COBJS-$(CONFIG_STATUS_LED) += led.o +COBJS := $(sort $(COBJS-y)) SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index c066d6ef5..4e194a2d7 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -30,6 +30,9 @@ * MA 02111-1307 USA */ #include <common.h> +#ifdef CONFIG_STATUS_LED +#include <status_led.h> +#endif #include <twl4030.h> #include <asm/io.h> #include <asm/arch/mmc_host_def.h> @@ -37,8 +40,19 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/gpio.h> #include <asm/mach-types.h> +#ifdef CONFIG_USB_EHCI +#include <usb.h> +#include <asm/arch/clocks.h> +#include <asm/arch/clocks_omap3.h> +#include <asm/arch/ehci_omap3.h> +/* from drivers/usb/host/ehci-core.h */ +extern struct ehci_hccr *hccr; +extern volatile struct ehci_hcor *hcor; +#endif #include "beagle.h" +#define pr_debug(fmt, args...) debug(fmt, ##args) + #define TWL4030_I2C_BUS 0 #define EXPANSION_EEPROM_I2C_BUS 1 #define EXPANSION_EEPROM_I2C_ADDRESS 0x50 @@ -48,7 +62,12 @@ #define TINCANTOOLS_TRAINER 0x04000100 #define TINCANTOOLS_SHOWDOG 0x03000100 #define KBADC_BEAGLEFPGA 0x01000600 - +#define LW_BEAGLETOUCH 0x01000700 +#define BRAINMUX_LCDOG 0x01000800 +#define BRAINMUX_LCDOGTOUCH 0x02000800 +#define BBTOYS_WIFI 0x01000B00 +#define BBTOYS_VGA 0x02000B00 +#define BBTOYS_LCD 0x03000B00 #define BEAGLE_NO_EEPROM 0xffffffff DECLARE_GLOBAL_DATA_PTR; @@ -74,6 +93,10 @@ int board_init(void) /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) + status_led_set (STATUS_LED_BOOT, STATUS_LED_ON); +#endif + return 0; } @@ -148,23 +171,24 @@ int misc_init_r(void) { struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; + struct control_prog_io *prog_io_base = (struct gpio *)OMAP34XX_CTRL_BASE; + + /* Enable i2c2 pullup resisters */ + writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1); switch (get_board_revision()) { case REVISION_AXBX: printf("Beagle Rev Ax/Bx\n"); setenv("beaglerev", "AxBx"); - setenv("mpurate", "600"); break; case REVISION_CX: printf("Beagle Rev C1/C2/C3\n"); setenv("beaglerev", "Cx"); - setenv("mpurate", "600"); MUX_BEAGLE_C(); break; case REVISION_C4: printf("Beagle Rev C4\n"); setenv("beaglerev", "C4"); - setenv("mpurate", "720"); MUX_BEAGLE_C(); /* Set VAUX2 to 1.8V for EHCI PHY */ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, @@ -172,10 +196,19 @@ int misc_init_r(void) TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, TWL4030_PM_RECEIVER_DEV_GRP_P1); break; - case REVISION_XM: + case REVISION_XM_A: printf("Beagle xM Rev A\n"); setenv("beaglerev", "xMA"); - setenv("mpurate", "1000"); + MUX_BEAGLE_XM(); + /* Set VAUX2 to 1.8V for EHCI PHY */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, + TWL4030_PM_RECEIVER_VAUX2_VSEL_18, + TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + break; + case REVISION_XM_B: + printf("Beagle xM Rev B\n"); + setenv("beaglerev", "xMB"); MUX_BEAGLE_XM(); /* Set VAUX2 to 1.8V for EHCI PHY */ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, @@ -185,6 +218,12 @@ int misc_init_r(void) break; default: printf("Beagle unknown 0x%02x\n", get_board_revision()); + MUX_BEAGLE_XM(); + /* Set VAUX2 to 1.8V for EHCI PHY */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, + TWL4030_PM_RECEIVER_VAUX2_VSEL_18, + TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); } switch (get_expansion_id()) { @@ -223,6 +262,29 @@ int misc_init_r(void) MUX_KBADC_BEAGLEFPGA(); setenv("buddy", "beaglefpga"); break; + case LW_BEAGLETOUCH: + printf("Recognized Liquidware BeagleTouch board\n"); + setenv("buddy", "beagletouch"); + break; + case BRAINMUX_LCDOG: + printf("Recognized Brainmux LCDog board\n"); + setenv("buddy", "lcdog"); + break; + case BRAINMUX_LCDOGTOUCH: + printf("Recognized Brainmux LCDog Touch board\n"); + setenv("buddy", "lcdogtouch"); + break; + case BBTOYS_WIFI: + printf("Recognized BeagleBoardToys WiFi board\n"); + MUX_BBTOYS_WIFI() + setenv("buddy", "bbtoys-wifi"); + break;; + case BBTOYS_VGA: + printf("Recognized BeagleBoardToys VGA board\n"); + break;; + case BBTOYS_LCD: + printf("Recognized BeagleBoardToys LCD board\n"); + break;; case BEAGLE_NO_EEPROM: printf("No EEPROM on expansion board\n"); setenv("buddy", "none"); @@ -273,3 +335,98 @@ int board_mmc_init(bd_t *bis) return 0; } #endif + +#ifdef CONFIG_USB_EHCI + +#define GPIO_PHY_RESET 147 + +/* Reset is needed otherwise the kernel-driver will throw an error. */ +int ehci_hcd_stop(void) +{ + pr_debug("Resetting OMAP3 EHCI\n"); + omap_set_gpio_dataout(GPIO_PHY_RESET, 0); + writel(OMAP_UHH_SYSCONFIG_SOFTRESET, OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG); + return 0; +} + +/* Call usb_stop() before starting the kernel */ +void show_boot_progress(int val) +{ + if(val == 15) + usb_stop(); +} + +/* + * Initialize the OMAP3 EHCI controller and PHY on the BeagleBoard. + * Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37. + * See there for additional Copyrights. + */ +int ehci_hcd_init(void) +{ + pr_debug("Initializing OMAP3 ECHI\n"); + + /* Put the PHY in RESET */ + omap_request_gpio(GPIO_PHY_RESET); + omap_set_gpio_direction(GPIO_PHY_RESET, 0); + omap_set_gpio_dataout(GPIO_PHY_RESET, 0); + + /* Hold the PHY in RESET for enough time till DIR is high */ + /* Refer: ISSUE1 */ + udelay(10); + + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */ + sr32(&prcm_base->iclken_usbhost, 0, 1, 1); + /* + * Enable USBHOST_48M_FCLK (USBHOST_FCLK1) + * and USBHOST_120M_FCLK (USBHOST_FCLK2) + */ + sr32(&prcm_base->fclken_usbhost, 0, 2, 3); + /* Enable USBTTL_ICLK */ + sr32(&prcm_base->iclken3_core, 2, 1, 1); + /* Enable USBTTL_FCLK */ + sr32(&prcm_base->fclken3_core, 2, 1, 1); + pr_debug("USB clocks enabled\n"); + + /* perform TLL soft reset, and wait until reset is complete */ + writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, + OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG); + /* Wait for TLL reset to complete */ + while (!(readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS) + & OMAP_USBTLL_SYSSTATUS_RESETDONE)); + pr_debug("TLL reset done\n"); + + writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | + OMAP_USBTLL_SYSCONFIG_SIDLEMODE | + OMAP_USBTLL_SYSCONFIG_CACTIVITY, + OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG); + + /* Put UHH in NoIdle/NoStandby mode */ + writel(OMAP_UHH_SYSCONFIG_ENAWAKEUP + | OMAP_UHH_SYSCONFIG_SIDLEMODE + | OMAP_UHH_SYSCONFIG_CACTIVITY + | OMAP_UHH_SYSCONFIG_MIDLEMODE, + OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG); + + /* setup burst configurations */ + writel(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN + | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN + | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN, + OMAP3_UHH_BASE + OMAP_UHH_HOSTCONFIG); + + /* + * Refer ISSUE1: + * Hold the PHY in RESET for enough time till + * PHY is settled and ready + */ + udelay(10); + omap_set_gpio_dataout(GPIO_PHY_RESET, 1); + + hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE); + hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10); + + pr_debug("OMAP3 EHCI init done\n"); + return 0; +} + +#endif /* CONFIG_USB_EHCI */ diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h index b22b65337..a7401b1e7 100644 --- a/board/ti/beagle/beagle.h +++ b/board/ti/beagle/beagle.h @@ -37,7 +37,8 @@ const omap3_sysinfo sysinfo = { #define REVISION_AXBX 0x7 #define REVISION_CX 0x6 #define REVISION_C4 0x5 -#define REVISION_XM 0x0 +#define REVISION_XM_A 0x0 +#define REVISION_XM_B 0x1 /* * IEN - Input Enable @@ -273,18 +274,18 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\ /* USB EHCI (port 2) */\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA2*/\ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA7*/\ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA4*/\ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA5*/\ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA6*/\ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA3*/\ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA0*/\ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA1*/\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)) /*HSUSB2_DATA2*/\ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)) /*HSUSB2_DATA7*/\ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)) /*HSUSB2_DATA4*/\ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)) /*HSUSB2_DATA5*/\ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)) /*HSUSB2_DATA6*/\ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)) /*HSUSB2_DATA3*/\ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DIR*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_NXT*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DATA0*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DATA1*/\ /*Control and debug */\ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ @@ -383,7 +384,8 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ + MUX_VAL(CP(UART2_RX), (IDIS | PTU | EN | M4)) /*GPIO_147*/ #define MUX_BEAGLE_XM() \ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | EN | M4)) /*GPIO_56*/\ @@ -457,4 +459,16 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCBSP1_DR), (IEN | PTU | EN | M1)) /*MCSPI4_SOMI*/\ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/ +#define MUX_BBTOYS_WIFI() \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ + MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) /*GPIO_136 FM_EN/BT_WU*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137 WLAN_IRQ*/\ + MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) /*GPIO_138 BT_EN*/\ + MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_139 WLAN_EN*/ + #endif diff --git a/board/ti/beagle/led.c b/board/ti/beagle/led.c new file mode 100644 index 000000000..df2655298 --- /dev/null +++ b/board/ti/beagle/led.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2010 Texas Instruments, Inc. + * Jason Kridner <jkridner@beagleboard.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <status_led.h> +#include <asm/arch/cpu.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> + +static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF}; + +/* GPIO pins for the LEDs */ +#define BEAGLE_LED_USR0 149 +#define BEAGLE_LED_USR1 150 + +#ifdef STATUS_LED_GREEN +void green_LED_off (void) +{ + __led_set (STATUS_LED_GREEN, 0); +} + +void green_LED_on (void) +{ + __led_set (STATUS_LED_GREEN, 1); +} +#endif + +void __led_init (led_id_t mask, int state) +{ + __led_set (mask, state); +} + +void __led_toggle (led_id_t mask) +{ +#ifdef STATUS_LED_BIT + if (STATUS_LED_BIT & mask) { + if (STATUS_LED_ON == saved_state[0]) + __led_set(STATUS_LED_BIT, 0); + else + __led_set(STATUS_LED_BIT, 1); + } +#endif +#ifdef STATUS_LED_BIT1 + if (STATUS_LED_BIT1 & mask) { + if (STATUS_LED_ON == saved_state[1]) + __led_set(STATUS_LED_BIT1, 0); + else + __led_set(STATUS_LED_BIT1, 1); + } +#endif +} + +void __led_set (led_id_t mask, int state) +{ +#ifdef STATUS_LED_BIT + if (STATUS_LED_BIT & mask) { + if (!omap_request_gpio(BEAGLE_LED_USR0)) { + omap_set_gpio_direction(BEAGLE_LED_USR0, 0); + omap_set_gpio_dataout(BEAGLE_LED_USR0, state); + } + saved_state[0] = state; + } +#endif +#ifdef STATUS_LED_BIT1 + if (STATUS_LED_BIT1 & mask) { + if (!omap_request_gpio(BEAGLE_LED_USR1)) { + omap_set_gpio_direction(BEAGLE_LED_USR1, 0); + omap_set_gpio_dataout(BEAGLE_LED_USR1, state); + } + saved_state[1] = state; + } +#endif +} + |