diff options
Diffstat (limited to 'arch/powerpc/cpu')
32 files changed, 304 insertions, 918 deletions
diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile index ae2f6dc8c..37b06f346 100644 --- a/arch/powerpc/cpu/mpc512x/Makefile +++ b/arch/powerpc/cpu/mpc512x/Makefile @@ -38,7 +38,6 @@ COBJS-y += serial.o COBJS-y += speed.o COBJS-$(CONFIG_FSL_DIU_FB) += diu.o COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_diu_fb.o -COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_logo_bmp.o COBJS-$(CONFIG_CMD_IDE) += ide.o COBJS-$(CONFIG_IIM) += iim.o COBJS-$(CONFIG_PCI) += pci.o diff --git a/arch/powerpc/cpu/mpc512x/diu.c b/arch/powerpc/cpu/mpc512x/diu.c index 9ef5609f3..fa4a0bc97 100644 --- a/arch/powerpc/cpu/mpc512x/diu.c +++ b/arch/powerpc/cpu/mpc512x/diu.c @@ -36,12 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_FSL_DIU_LOGO_BMP -extern unsigned int FSL_Logo_BMP[]; -#else -#define FSL_Logo_BMP NULL -#endif - static int xres, yres; void diu_set_pixel_clock(unsigned int pixclock) @@ -64,28 +58,9 @@ void diu_set_pixel_clock(unsigned int pixclock) debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr)); } -char *valid_bmp(char *addr) -{ - unsigned long h_addr; - bd_t *bd = gd->bd; - - h_addr = simple_strtoul(addr, NULL, 16); - if (h_addr < bd->bi_flashstart || - h_addr >= (bd->bi_flashstart + bd->bi_flashsize - 1)) { - printf("bmp addr %lx is not a valid flash address\n", h_addr); - return 0; - } else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) { - printf("bmp addr is not a bmp\n"); - return 0; - } else - return (char *)h_addr; -} - int mpc5121_diu_init(void) { unsigned int pixel_format; - char *bmp = NULL; - char *bmp_env; #if defined(CONFIG_VIDEO_XRES) & defined(CONFIG_VIDEO_YRES) xres = CONFIG_VIDEO_XRES; @@ -97,47 +72,10 @@ int mpc5121_diu_init(void) pixel_format = 0x88883316; debug("mpc5121_diu_init\n"); - bmp_env = getenv("diu_bmp_addr"); - if (bmp_env) { - bmp = valid_bmp(bmp_env); - } - if (!bmp) - bmp = (char *)FSL_Logo_BMP; - return fsl_diu_init(xres, pixel_format, 0, (unsigned char *)bmp); -} - -int mpc5121diu_init_show_bmp(cmd_tbl_t *cmdtp, - int flag, int argc, char * const argv[]) -{ - unsigned int addr; - - if (argc < 2) - return cmd_usage(cmdtp); - - if (!strncmp(argv[1], "init", 4)) { -#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) - fsl_diu_clear_screen(); - drv_video_init(); -#else - return mpc5121_diu_init(); -#endif - } else { - addr = simple_strtoul(argv[1], NULL, 16); - fsl_diu_clear_screen(); - fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0); - } - return 0; + return fsl_diu_init(xres, pixel_format, 0); } -U_BOOT_CMD( - diufb, CONFIG_SYS_MAXARGS, 1, mpc5121diu_init_show_bmp, - "Init or Display BMP file", - "init\n - initialize DIU\n" - "addr\n - display bmp at address 'addr'" - ); - - #if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) /* @@ -158,7 +96,7 @@ void *video_hw_init(void) pGD->frameAdrs = (unsigned int)fsl_fb_open(&info); pGD->winSizeX = xres; - pGD->winSizeY = yres - info->logo_height; + pGD->winSizeY = yres; pGD->plnSizeX = pGD->winSizeX; pGD->plnSizeY = pGD->winSizeY; @@ -167,7 +105,7 @@ void *video_hw_init(void) pGD->isaBase = 0; pGD->pciBase = 0; - pGD->memSize = info->screen_size - info->logo_size; + pGD->memSize = info->screen_size; /* Cursor Start Address */ pGD->dprBase = 0; diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 83cba9360..f01c09a91 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -126,6 +126,12 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ SCCR_PCICM | #endif +#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */ + SCCR_PCIEXP1CM | +#endif +#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */ + SCCR_PCIEXP2CM | +#endif #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ SCCR_TSECCM | #endif @@ -158,6 +164,12 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) | #endif +#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */ + (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */ + (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) | +#endif #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) | #endif diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c index a42b230ff..288d99ffc 100644 --- a/arch/powerpc/cpu/mpc83xx/pci.c +++ b/arch/powerpc/cpu/mpc83xx/pci.c @@ -133,7 +133,7 @@ static void pci_init_bus(int bus, struct pci_region *reg) * If fewer than three regions are requested, then the region * list is terminated with a region of size 0. */ -void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot) +void mpc83xx_pci_init(int num_buses, struct pci_region **reg) { volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; int i; @@ -150,9 +150,9 @@ void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot) /* * Release PCI RST Output signal. * Power on to RST high must be at least 100 ms as per PCI spec. - * On warm boots only 1 ms is required. + * On warm boots only 1 ms is required, but we play it safe. */ - udelay(warmboot ? 1000 : 100000); + udelay(100000); for (i = 0; i < num_buses; i++) immr->pci_ctrl[i].gcr = 1; diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index 77f8906b9..1771c4823 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -30,6 +30,22 @@ DECLARE_GLOBAL_DATA_PTR; #define PCIE_MAX_BUSES 2 +static struct { + u32 base; + u32 size; +} mpc83xx_pcie_cfg_space[] = { + { + .base = CONFIG_SYS_PCIE1_CFG_BASE, + .size = CONFIG_SYS_PCIE1_CFG_SIZE, + }, +#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE) + { + .base = CONFIG_SYS_PCIE2_CFG_BASE, + .size = CONFIG_SYS_PCIE2_CFG_SIZE, + }, +#endif +}; + #ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) @@ -124,10 +140,7 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, hose->first_busno = pci_last_busno() + 1; hose->last_busno = 0xff; - if (bus == 0) - hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE1_CFG_BASE; - else - hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE2_CFG_BASE; + hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base; pci_set_ops(hose, pcie_read_config_byte, @@ -182,15 +195,9 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) PEX_CSB_OBCTRL_CFGWE); out_win = &pex->bridge.pex_outbound_win[0]; - if (bus) { - out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG | - CONFIG_SYS_PCIE2_CFG_SIZE); - out_le32(&out_win->bar, CONFIG_SYS_PCIE2_CFG_BASE); - } else { - out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG | - CONFIG_SYS_PCIE1_CFG_SIZE); - out_le32(&out_win->bar, CONFIG_SYS_PCIE1_CFG_BASE); - } + out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG | + mpc83xx_pcie_cfg_space[bus].size); + out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base); out_le32(&out_win->tarl, 0); out_le32(&out_win->tarh, 0); @@ -301,16 +308,21 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs * must have been set to cover all of the requested regions. */ -void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot) +void mpc83xx_pcie_init(int num_buses, struct pci_region **reg) { int i; /* * Release PCI RST Output signal. * Power on to RST high must be at least 100 ms as per PCI spec. - * On warm boots only 1 ms is required. + * On warm boots only 1 ms is required, but we play it safe. */ - udelay(warmboot ? 1000 : 100000); + udelay(100000); + + if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) { + printf("Second PCIE host contoller not configured!\n"); + num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space); + } for (i = 0; i < num_buses; i++) mpc83xx_pcie_init_bus(i, reg[i]); diff --git a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c index f65cd886a..a31b17e9e 100644 --- a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c +++ b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c @@ -45,7 +45,7 @@ #include <common.h> #include <asm/processor.h> #include <i2c.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440) diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c index 005315be8..ec7291f9c 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c @@ -50,7 +50,7 @@ #include <common.h> #include <asm/processor.h> #include <i2c.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/mmu.h> #include "ecc.h" diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index ff5ef5f0c..cf9d66d53 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -41,7 +41,7 @@ #include <common.h> #include <command.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <i2c.h> #include <asm/io.h> #include <asm/processor.h> @@ -469,7 +469,7 @@ phys_size_t initdram(int board_type) /*------------------------------------------------------------------ * Reset the DDR-SDRAM controller. *-----------------------------------------------------------------*/ - mtsdr(SDR0_SRST, (0x80000000 >> 10)); + mtsdr(SDR0_SRST, SDR0_SRST0_DMC); mtsdr(SDR0_SRST, 0x00000000); /* diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 2cfc37f75..e90c93e49 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -38,7 +38,7 @@ #undef DEBUG #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/io.h> #include <asm/processor.h> diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pci.c b/arch/powerpc/cpu/ppc4xx/4xx_pci.c index bfba95257..80b0c1c6f 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_pci.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_pci.c @@ -594,35 +594,35 @@ int __pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(SD0_AMP1, reg); - mtsdr(SD0_AMP1, (reg & 0x000000FF) | 0x0000FF00); - reg = mfdcr(PLB3_ACR); - mtdcr(PLB3_ACR, reg | 0x80000000); + mfsdr(SDR0_AMP1, reg); + mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00); + reg = mfdcr(PLB3A0_ACR); + mtdcr(PLB3A0_ACR, reg | 0x80000000); /* * Set priority for all PLB4 devices to 0. */ - mfsdr(SD0_AMP0, reg); - mtsdr(SD0_AMP0, (reg & 0x000000FF) | 0x0000FF00); - reg = mfdcr(PLB4_ACR) | 0xa0000000; - mtdcr(PLB4_ACR, reg); + mfsdr(SDR0_AMP0, reg); + mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00); + reg = mfdcr(PLB4A0_ACR) | 0xa0000000; + mtdcr(PLB4A0_ACR, reg); /* * Set Nebula PLB4 arbiter to fair mode. */ /* Segment0 */ - reg = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; - reg = (reg & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; - reg = (reg & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; - reg = (reg & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; - mtdcr(PLB0_ACR, reg); + reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR; + reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED; + reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP; + reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP; + mtdcr(PLB4A0_ACR, reg); /* Segment1 */ - reg = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; - reg = (reg & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; - reg = (reg & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; - reg = (reg & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; - mtdcr(PLB1_ACR, reg); + reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR; + reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED; + reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP; + reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP; + mtdcr(PLB4A1_ACR, reg); #if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ) hose->fixup_irq = board_pci_fixup_irq; diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c index 10b58b711..b76890e09 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c @@ -27,7 +27,7 @@ #include <common.h> #include <pci.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/errno.h> diff --git a/arch/powerpc/cpu/ppc4xx/4xx_uart.c b/arch/powerpc/cpu/ppc4xx/4xx_uart.c index e6ab570c0..2660aa84d 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_uart.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_uart.c @@ -2,6 +2,9 @@ * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * * See file CREDITS for list of people who contributed to this * project. * @@ -49,15 +52,7 @@ #include <asm/processor.h> #include <asm/io.h> #include <watchdog.h> -#include <ppc4xx.h> - -#ifdef CONFIG_SERIAL_MULTI -#include <serial.h> -#endif - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO -#include <malloc.h> -#endif +#include <asm/ppc4xx.h> DECLARE_GLOBAL_DATA_PTR; @@ -66,24 +61,6 @@ DECLARE_GLOBAL_DATA_PTR; defined(CONFIG_405EX) || defined(CONFIG_440) #if defined(CONFIG_440) -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300) -#define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000400) -#else -#define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000200) -#define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300) -#endif - -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600) -#endif - -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000500) -#define UART3_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600) -#endif #if defined(CONFIG_440GP) #define CR0_MASK 0x3fff0000 @@ -116,16 +93,14 @@ DECLARE_GLOBAL_DATA_PTR; #define MTREG(a, d) mtsdr(a, d) #endif /* #if defined(CONFIG_440GP) */ #elif defined(CONFIG_405EP) || defined(CONFIG_405EZ) -#define UART0_BASE 0xef600300 -#define UART1_BASE 0xef600400 #define UCR0_MASK 0x0000007f #define UCR1_MASK 0x00007f00 #define UCR0_UDIV_POS 0 #define UCR1_UDIV_POS 8 #define UDIV_MAX 127 #elif defined(CONFIG_405EX) -#define UART0_BASE 0xef600200 -#define UART1_BASE 0xef600300 +#define MFREG(a, d) mfsdr(a, d) +#define MTREG(a, d) mtsdr(a, d) #define CR0_MASK 0x000000ff #define CR0_EXTCLK_ENA 0x00800000 #define CR0_UDIV_POS 0 @@ -133,748 +108,198 @@ DECLARE_GLOBAL_DATA_PTR; #define UART0_SDR SDR0_UART0 #define UART1_SDR SDR0_UART1 #else /* CONFIG_405GP || CONFIG_405CR */ -#define UART0_BASE 0xef600300 -#define UART1_BASE 0xef600400 #define CR0_MASK 0x00001fff #define CR0_EXTCLK_ENA 0x000000c0 #define CR0_UDIV_POS 1 #define UDIV_MAX 32 #endif -/* using serial port 0 or 1 as U-Boot console ? */ -#if defined(CONFIG_UART1_CONSOLE) -#define ACTING_UART0_BASE UART1_BASE -#define ACTING_UART1_BASE UART0_BASE -#else -#define ACTING_UART0_BASE UART0_BASE -#define ACTING_UART1_BASE UART1_BASE -#endif - #if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK) #error "External serial clock not supported on AMCC PPC405EP!" #endif -#define UART_RBR 0x00 -#define UART_THR 0x00 -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/*-----------------------------------------------------------------------------+ - | Line Status Register. - +-----------------------------------------------------------------------------*/ -#define asyncLSRDataReady1 0x01 -#define asyncLSROverrunError1 0x02 -#define asyncLSRParityError1 0x04 -#define asyncLSRFramingError1 0x08 -#define asyncLSRBreakInterrupt1 0x10 -#define asyncLSRTxHoldEmpty1 0x20 -#define asyncLSRTxShiftEmpty1 0x40 -#define asyncLSRRxFifoError1 0x80 - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO -/*-----------------------------------------------------------------------------+ - | Fifo - +-----------------------------------------------------------------------------*/ -typedef struct { - char *rx_buffer; - ulong rx_put; - ulong rx_get; -} serial_buffer_t; - -volatile static serial_buffer_t buf_info; -#endif - -static void serial_init_common(u32 base, u32 udiv, u16 bdiv) -{ - PPC4xx_SYS_INFO sys_info; - u8 val; - - get_sys_info(&sys_info); - - /* Correct UART frequency in bd-info struct now that - * the UART divisor is available - */ -#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK - gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK; -#else - gd->uart_clk = sys_info.freqUART / udiv; -#endif - - out_8((u8 *)base + UART_LCR, 0x80); /* set DLAB bit */ - out_8((u8 *)base + UART_DLL, bdiv); /* set baudrate divisor */ - out_8((u8 *)base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ - out_8((u8 *)base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out_8((u8 *)base + UART_FCR, 0x00); /* disable FIFO */ - out_8((u8 *)base + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in_8((u8 *)base + UART_LSR); /* clear line status */ - val = in_8((u8 *)base + UART_RBR); /* read receive buffer */ - out_8((u8 *)base + UART_SCR, 0x00); /* set scratchpad */ - out_8((u8 *)base + UART_IER, 0x00); /* set interrupt enable reg */ -} - -#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \ - !defined(CONFIG_SYS_EXT_SERIAL_CLOCK) -static void serial_divs (int baudrate, unsigned long *pudiv, - unsigned short *pbdiv) +#if (defined(CONFIG_405EX) || defined(CONFIG_405EZ) || \ + defined(CONFIG_440)) && !defined(CONFIG_SYS_EXT_SERIAL_CLOCK) +/* + * For some SoC's, the cpu clock is on divider chain A, UART on + * divider chain B ... so cpu clock is irrelevant. Get the + * "optimized" values that are subject to the 1/2 opb clock + * constraint. + */ +static u16 serial_bdiv(int baudrate, u32 *udiv) { sys_info_t sysinfo; - unsigned long div; /* total divisor udiv * bdiv */ - unsigned long umin; /* minimum udiv */ - unsigned short diff; /* smallest diff */ - unsigned long udiv; /* best udiv */ - unsigned short idiff; /* current diff */ - unsigned short ibdiv; /* current bdiv */ - unsigned long i; - unsigned long est; /* current estimate */ + u32 div; /* total divisor udiv * bdiv */ + u32 umin; /* minimum udiv */ + u16 diff; /* smallest diff */ + u16 idiff; /* current diff */ + u16 ibdiv; /* current bdiv */ + u32 i; + u32 est; /* current estimate */ + u32 max; +#if defined(CONFIG_405EZ) + u32 cpr_pllc; + u32 plloutb; + u32 reg; +#endif get_sys_info(&sysinfo); - udiv = 32; /* Assume lowest possible serial clk */ - div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */ - umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */ - diff = 32; /* highest possible */ - - /* i is the test udiv value -- start with the largest - * possible (32) to minimize serial clock and constrain - * search to umin. - */ - for (i = 32; i > umin; i--) { - ibdiv = div / i; - est = i * ibdiv; - idiff = (est > div) ? (est-div) : (div-est); - if (idiff == 0) { - udiv = i; - break; /* can't do better */ - } else if (idiff < diff) { - udiv = i; /* best so far */ - diff = idiff; /* update lowest diff*/ - } - } - - *pudiv = udiv; - *pbdiv = div / udiv; -} - -#elif defined(CONFIG_405EZ) - -static void serial_divs (int baudrate, unsigned long *pudiv, - unsigned short *pbdiv) -{ - sys_info_t sysinfo; - unsigned long div; /* total divisor udiv * bdiv */ - unsigned long umin; /* minimum udiv */ - unsigned short diff; /* smallest diff */ - unsigned long udiv; /* best udiv */ - unsigned short idiff; /* current diff */ - unsigned short ibdiv; /* current bdiv */ - unsigned long i; - unsigned long est; /* current estimate */ - unsigned long plloutb; - unsigned long cpr_pllc; - u32 reg; - +#if defined(CONFIG_405EZ) /* check the pll feedback source */ mfcpr(CPR0_PLLC, cpr_pllc); - - get_sys_info(&sysinfo); - plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ? sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB); - udiv = 256; /* Assume lowest possible serial clk */ div = plloutb / (16 * baudrate); /* total divisor */ umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */ - diff = 256; /* highest possible */ + max = 256; /* highest possible */ +#else /* 405EZ */ + div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */ + umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */ + max = 32; /* highest possible */ +#endif /* 405EZ */ + + *udiv = diff = max; - /* i is the test udiv value -- start with the largest - * possible (256) to minimize serial clock and constrain + /* + * i is the test udiv value -- start with the largest + * possible (max) to minimize serial clock and constrain * search to umin. */ - for (i = 256; i > umin; i--) { + for (i = max; i > umin; i--) { ibdiv = div / i; est = i * ibdiv; - idiff = (est > div) ? (est-div) : (div-est); + idiff = (est > div) ? (est - div) : (div - est); if (idiff == 0) { - udiv = i; - break; /* can't do better */ + *udiv = i; + break; /* can't do better */ } else if (idiff < diff) { - udiv = i; /* best so far */ - diff = idiff; /* update lowest diff*/ + *udiv = i; /* best so far */ + diff = idiff; /* update lowest diff*/ } } - *pudiv = udiv; - mfcpr(CPC0_PERD0, reg); +#if defined(CONFIG_405EZ) + mfcpr(CPR0_PERD0, reg); reg &= ~0x0000ffff; - reg |= ((udiv - 0) << 8) | (udiv - 0); - mtcpr(CPC0_PERD0, reg); - *pbdiv = div / udiv; + reg |= ((*udiv - 0) << 8) | (*udiv - 0); + mtcpr(CPR0_PERD0, reg); +#endif + + return div / *udiv; } -#endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */ +#endif /* #if (defined(CONFIG_405EP) ... */ /* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. + * This function returns the UART clock used by the common + * NS16550 driver. Additionally the SoC internal divisors for + * optimal UART baudrate are configured. */ - -#if defined(CONFIG_440) -int serial_init_dev(unsigned long base) +int get_serial_clock(void) { - unsigned long reg; - unsigned long udiv; - unsigned short bdiv; -#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK - unsigned long tmp; -#endif - - MFREG(UART0_SDR, reg); - reg &= ~CR0_MASK; - -#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK - reg |= CR0_EXTCLK_ENA; - udiv = 1; - tmp = gd->baudrate * 16; - bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp; -#else - /* For 440, the cpu clock is on divider chain A, UART on divider - * chain B ... so cpu clock is irrelevant. Get the "optimized" - * values that are subject to the 1/2 opb clock constraint - */ - serial_divs (gd->baudrate, &udiv, &bdiv); + u32 clk; + u32 udiv; +#if defined(CONFIG_405CR) || defined(CONFIG_405EP) || defined(CONFIG_405GP) + u32 tmp; #endif - - reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ - - /* - * Configure input clock to baudrate generator for all - * available serial ports here - */ - MTREG(UART0_SDR, reg); -#if defined(UART1_SDR) - MTREG(UART1_SDR, reg); -#endif -#if defined(UART2_SDR) - MTREG(UART2_SDR, reg); -#endif -#if defined(UART3_SDR) - MTREG(UART3_SDR, reg); +#if !defined(CONFIG_405EZ) + u32 reg; #endif - - serial_init_common(base, udiv, bdiv); - - return (0); -} - -#else /* !defined(CONFIG_440) */ - -int serial_init_dev (unsigned long base) -{ - unsigned long reg; - unsigned long tmp; - unsigned long clk; - unsigned long udiv; - unsigned short bdiv; - -#ifdef CONFIG_405EX - clk = tmp = 0; - mfsdr(UART0_SDR, reg); - reg &= ~CR0_MASK; -#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK - reg |= CR0_EXTCLK_ENA; - udiv = 1; - tmp = gd->baudrate * 16; - bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp; -#else - serial_divs(gd->baudrate, &udiv, &bdiv); +#if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK) + PPC4xx_SYS_INFO sys_info; #endif - reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ /* - * Configure input clock to baudrate generator for all - * available serial ports here + * Programming of the internal divisors is SoC specific. + * Let's handle this in some #ifdef's for the SoC's. */ - mtsdr(UART0_SDR, reg); - -#if defined(UART1_SDR) - mtsdr(UART1_SDR, reg); -#endif -#elif defined(CONFIG_405EZ) - serial_divs(gd->baudrate, &udiv, &bdiv); - clk = tmp = reg = 0; -#else -#ifdef CONFIG_405EP - reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK); - clk = gd->cpu_clk; - tmp = CONFIG_SYS_BASE_BAUD * 16; - udiv = (clk + tmp / 2) / tmp; - if (udiv > UDIV_MAX) /* max. n bits for udiv */ - udiv = UDIV_MAX; - reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ - reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ - mtdcr (CPC0_UCR, reg); -#else /* CONFIG_405EP */ +#if defined(CONFIG_405CR) || defined(CONFIG_405GP) + tmp = 0; reg = mfdcr(CPC0_CR0) & ~CR0_MASK; #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK clk = CONFIG_SYS_EXT_SERIAL_CLOCK; udiv = 1; reg |= CR0_EXTCLK_ENA; -#else +#else /* CONFIG_SYS_EXT_SERIAL_CLOCK */ clk = gd->cpu_clk; #ifdef CONFIG_SYS_405_UART_ERRATA_59 udiv = 31; /* Errata 59: stuck at 31 */ -#else +#else /* CONFIG_SYS_405_UART_ERRATA_59 */ tmp = CONFIG_SYS_BASE_BAUD * 16; udiv = (clk + tmp / 2) / tmp; if (udiv > UDIV_MAX) /* max. n bits for udiv */ udiv = UDIV_MAX; -#endif -#endif +#endif /* CONFIG_SYS_405_UART_ERRATA_59 */ +#endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */ reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ mtdcr (CPC0_CR0, reg); -#endif /* CONFIG_405EP */ - tmp = gd->baudrate * udiv * 16; - bdiv = (clk + tmp / 2) / tmp; -#endif /* CONFIG_405EX */ - - serial_init_common(base, udiv, bdiv); - - return (0); -} - -#endif /* if defined(CONFIG_440) */ - -void serial_setbrg_dev(unsigned long base) -{ - serial_init_dev(base); -} - -void serial_putc_dev(unsigned long base, const char c) -{ - int i; - - if (c == '\n') - serial_putc_dev(base, '\r'); - - /* check THRE bit, wait for transmiter available */ - for (i = 1; i < 3500; i++) { - if ((in_8((u8 *)base + UART_LSR) & 0x20) == 0x20) - break; - udelay (100); - } - - out_8((u8 *)base + UART_THR, c); /* put character out */ -} - -void serial_puts_dev (unsigned long base, const char *s) -{ - while (*s) - serial_putc_dev (base, *s++); -} - -int serial_getc_dev (unsigned long base) -{ - unsigned char status = 0; - - while (1) { -#if defined(CONFIG_HW_WATCHDOG) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ -#endif /* CONFIG_HW_WATCHDOG */ - - status = in_8((u8 *)base + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) - break; - - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - out_8((u8 *)base + UART_LSR, - asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1); - } - } - - return (0x000000ff & (int) in_8((u8 *)base)); -} - -int serial_tstc_dev (unsigned long base) -{ - unsigned char status; - - status = in_8((u8 *)base + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) - return (1); - - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - out_8((u8 *)base + UART_LSR, - asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1); - } - - return 0; -} - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - -void serial_isr (void *arg) -{ - int space; - int c; - const int rx_get = buf_info.rx_get; - int rx_put = buf_info.rx_put; - - if (rx_get <= rx_put) - space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); - else - space = rx_get - rx_put; - - while (serial_tstc_dev (ACTING_UART0_BASE)) { - c = serial_getc_dev (ACTING_UART0_BASE); - if (space) { - buf_info.rx_buffer[rx_put++] = c; - space--; - } - if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) - rx_put = 0; - if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) { - /* Stop flow by setting RTS inactive */ - out_8((u8 *)ACTING_UART0_BASE + UART_MCR, - in_8((u8 *)ACTING_UART0_BASE + UART_MCR) & - (0xFF ^ 0x02)); - } - } - buf_info.rx_put = rx_put; -} - -void serial_buffered_init (void) -{ - serial_puts ("Switching to interrupt driven serial input mode.\n"); - buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO); - buf_info.rx_put = 0; - buf_info.rx_get = 0; - - if (in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10) - serial_puts ("Check CTS signal present on serial port: OK.\n"); - else - serial_puts ("WARNING: CTS signal not present on serial port.\n"); - - irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ , - serial_isr /*interrupt_handler_t *handler */ , - (void *) &buf_info /*void *arg */ ); - - /* Enable "RX Data Available" Interrupt on UART */ - out_8(ACTING_UART0_BASE + UART_IER, 0x01); - /* Set DTR active */ - out_8(ACTING_UART0_BASE + UART_MCR, - in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x01); - /* Start flow by setting RTS active */ - out_8(ACTING_UART0_BASE + UART_MCR, - in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02); - /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */ - out_8(ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1); -} - -void serial_buffered_putc (const char c) -{ - /* Wait for CTS */ -#if defined(CONFIG_HW_WATCHDOG) - while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)) - WATCHDOG_RESET (); -#else - while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)); -#endif - serial_putc (c); -} - -void serial_buffered_puts (const char *s) -{ - serial_puts (s); -} - -int serial_buffered_getc (void) -{ - int space; - int c; - int rx_get = buf_info.rx_get; - int rx_put; - -#if defined(CONFIG_HW_WATCHDOG) - while (rx_get == buf_info.rx_put) - WATCHDOG_RESET (); +#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK + clk = CONFIG_SYS_EXT_SERIAL_CLOCK; #else - while (rx_get == buf_info.rx_put); + clk = CONFIG_SYS_BASE_BAUD * 16; #endif - c = buf_info.rx_buffer[rx_get++]; - if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) - rx_get = 0; - buf_info.rx_get = rx_get; - - rx_put = buf_info.rx_put; - if (rx_get <= rx_put) - space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); - else - space = rx_get - rx_put; - - if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) { - /* Start flow by setting RTS active */ - out_8(ACTING_UART0_BASE + UART_MCR, - in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02); - } +#endif /* CONFIG_405CR */ - return c; -} +#if defined(CONFIG_405EP) + reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK); + clk = gd->cpu_clk; + tmp = CONFIG_SYS_BASE_BAUD * 16; + udiv = (clk + tmp / 2) / tmp; + if (udiv > UDIV_MAX) /* max. n bits for udiv */ + udiv = UDIV_MAX; + reg |= udiv << UCR0_UDIV_POS; /* set the UART divisor */ + reg |= udiv << UCR1_UDIV_POS; /* set the UART divisor */ + mtdcr(CPC0_UCR, reg); + clk = CONFIG_SYS_BASE_BAUD * 16; +#endif /* CONFIG_405EP */ -int serial_buffered_tstc (void) -{ - return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0; -} +#if defined(CONFIG_405EX) || defined(CONFIG_440) + MFREG(UART0_SDR, reg); + reg &= ~CR0_MASK; -#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ +#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK + reg |= CR0_EXTCLK_ENA; + udiv = 1; + clk = CONFIG_SYS_EXT_SERIAL_CLOCK; +#else /* CONFIG_SYS_EXT_SERIAL_CLOCK */ + clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16; +#endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */ -#if defined(CONFIG_CMD_KGDB) -/* - AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port - number 0 or number 1 - - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 : - configuration has been already done - - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 : - configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE -*/ -#if (CONFIG_KGDB_SER_INDEX & 2) -void kgdb_serial_init (void) -{ - u8 val; - u16 br_reg; + reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ - get_clocks (); - br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) + - 5) / 10; /* - * Init onboard 16550 UART + * Configure input clock to baudrate generator for all + * available serial ports here */ - out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out_8((u8 *)ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */ - out_8((u8 *)ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */ - out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */ - out_8((u8 *)ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */ - out_8((u8 *)ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in_8((u8 *)ACTING_UART1_BASE + UART_LSR); /* clear line status */ - val = in_8((u8 *)ACTING_UART1_BASE + UART_RBR); /* read receive buffer */ - out_8((u8 *)ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */ - out_8((u8 *)ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ -} - -void putDebugChar (const char c) -{ - if (c == '\n') - serial_putc ('\r'); - - out_8((u8 *)ACTING_UART1_BASE + UART_THR, c); /* put character out */ - - /* check THRE bit, wait for transfer done */ - while ((in_8((u8 *)ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20); -} - -void putDebugStr (const char *s) -{ - while (*s) - serial_putc (*s++); -} - -int getDebugChar (void) -{ - unsigned char status = 0; - - while (1) { - status = in_8((u8 *)ACTING_UART1_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) - break; - - if ((status & (asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - out_8((u8 *)ACTING_UART1_BASE + UART_LSR, - asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1); - } - } - - return (0x000000ff & (int) in_8((u8 *)ACTING_UART1_BASE)); -} - -void kgdb_interruptible (int yes) -{ - return; -} - -#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */ - -void kgdb_serial_init (void) -{ - serial_printf ("[on serial] "); -} - -void putDebugChar (int c) -{ - serial_putc (c); -} - -void putDebugStr (const char *str) -{ - serial_puts (str); -} - -int getDebugChar (void) -{ - return serial_getc (); -} - -void kgdb_interruptible (int yes) -{ - return; -} -#endif /* (CONFIG_KGDB_SER_INDEX & 2) */ + MTREG(UART0_SDR, reg); +#if defined(UART1_SDR) + MTREG(UART1_SDR, reg); #endif +#if defined(UART2_SDR) + MTREG(UART2_SDR, reg); +#endif +#if defined(UART3_SDR) + MTREG(UART3_SDR, reg); +#endif +#endif /* CONFIG_405EX ... */ +#if defined(CONFIG_405EZ) + clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16; +#endif /* CONFIG_405EZ */ -#if defined(CONFIG_SERIAL_MULTI) -int serial0_init(void) -{ - return (serial_init_dev(UART0_BASE)); -} - -int serial1_init(void) -{ - return (serial_init_dev(UART1_BASE)); -} - -void serial0_setbrg (void) -{ - serial_setbrg_dev(UART0_BASE); -} - -void serial1_setbrg (void) -{ - serial_setbrg_dev(UART1_BASE); -} - -void serial0_putc(const char c) -{ - serial_putc_dev(UART0_BASE,c); -} - -void serial1_putc(const char c) -{ - serial_putc_dev(UART1_BASE, c); -} - -void serial0_puts(const char *s) -{ - serial_puts_dev(UART0_BASE, s); -} - -void serial1_puts(const char *s) -{ - serial_puts_dev(UART1_BASE, s); -} - -int serial0_getc(void) -{ - return(serial_getc_dev(UART0_BASE)); -} - -int serial1_getc(void) -{ - return(serial_getc_dev(UART1_BASE)); -} - -int serial0_tstc(void) -{ - return (serial_tstc_dev(UART0_BASE)); -} - -int serial1_tstc(void) -{ - return (serial_tstc_dev(UART1_BASE)); -} - -struct serial_device serial0_device = -{ - "serial0", - "UART0", - serial0_init, - NULL, - serial0_setbrg, - serial0_getc, - serial0_tstc, - serial0_putc, - serial0_puts, -}; - -struct serial_device serial1_device = -{ - "serial1", - "UART1", - serial1_init, - NULL, - serial1_setbrg, - serial1_getc, - serial1_tstc, - serial1_putc, - serial1_puts, -}; + /* + * Correct UART frequency in bd-info struct now that + * the UART divisor is available + */ +#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK + gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK; #else -/* - * Wrapper functions - */ -int serial_init(void) -{ - return serial_init_dev(ACTING_UART0_BASE); -} - -void serial_setbrg(void) -{ - serial_setbrg_dev(ACTING_UART0_BASE); -} - -void serial_putc(const char c) -{ - serial_putc_dev(ACTING_UART0_BASE, c); -} - -void serial_puts(const char *s) -{ - serial_puts_dev(ACTING_UART0_BASE, s); -} - -int serial_getc(void) -{ - return serial_getc_dev(ACTING_UART0_BASE); -} + get_sys_info(&sys_info); + gd->uart_clk = sys_info.freqUART / udiv; +#endif -int serial_tstc(void) -{ - return serial_tstc_dev(ACTING_UART0_BASE); + return clk; } -#endif /* CONFIG_SERIAL_MULTI */ - #endif /* CONFIG_405GP || CONFIG_405CR */ diff --git a/arch/powerpc/cpu/ppc4xx/cache.S b/arch/powerpc/cpu/ppc4xx/cache.S index 269716fce..757d7da02 100644 --- a/arch/powerpc/cpu/ppc4xx/cache.S +++ b/arch/powerpc/cpu/ppc4xx/cache.S @@ -14,7 +14,7 @@ #include <config.h> #include <config.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> #include <asm/cache.h> diff --git a/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c index b4eac4057..fd81b70e7 100644 --- a/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c +++ b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c @@ -23,7 +23,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/cache.h> diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c index 851065cbd..6009b0ce0 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu.c +++ b/arch/powerpc/cpu/ppc4xx/cpu.c @@ -35,7 +35,7 @@ #include <watchdog.h> #include <command.h> #include <asm/cache.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -98,8 +98,8 @@ int pci_arbiter_enabled(void) #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long val; - mfsdr(SDR0_XCR, val); - return (val & 0x80000000); + mfsdr(SDR0_XCR0, val); + return (val & SDR0_XCR0_PAE_MASK); #endif #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ @@ -107,7 +107,7 @@ int pci_arbiter_enabled(void) unsigned long val; mfsdr(SDR0_PCI0, val); - return (val & 0x80000000); + return (val & SDR0_PCI0_PAE_MASK); #endif } #endif @@ -262,7 +262,7 @@ static int bootstrap_option(void) #endif /* SDR0_PINSTP_SHIFT */ -#if defined(CONFIG_440) +#if defined(CONFIG_440GP) static int do_chip_reset (unsigned long sys0, unsigned long sys1) { /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip @@ -276,7 +276,7 @@ static int do_chip_reset (unsigned long sys0, unsigned long sys1) return 1; } -#endif +#endif /* CONFIG_440GP */ int checkcpu (void) @@ -303,122 +303,113 @@ int checkcpu (void) get_sys_info(&sys_info); #if defined(CONFIG_XILINX_440) - puts("IBM PowerPC 4"); + puts("IBM PowerPC "); #else - puts("AMCC PowerPC 4"); -#endif - -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_405EX) - puts("05"); -#endif -#if defined(CONFIG_440) -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) - puts("60"); -#else - puts("40"); -#endif + puts("AMCC PowerPC "); #endif switch (pvr) { + +#if !defined(CONFIG_440) case PVR_405GP_RB: - puts("GP Rev. B"); + puts("405GP Rev. B"); break; case PVR_405GP_RC: - puts("GP Rev. C"); + puts("405GP Rev. C"); break; case PVR_405GP_RD: - puts("GP Rev. D"); + puts("405GP Rev. D"); break; #ifdef CONFIG_405GP case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */ - puts("GP Rev. E"); + puts("405GP Rev. E"); break; #endif case PVR_405CR_RA: - puts("CR Rev. A"); + puts("405CR Rev. A"); break; case PVR_405CR_RB: - puts("CR Rev. B"); + puts("405CR Rev. B"); break; #ifdef CONFIG_405CR case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */ - puts("CR Rev. C"); + puts("405CR Rev. C"); break; #endif case PVR_405GPR_RB: - puts("GPr Rev. B"); + puts("405GPr Rev. B"); break; case PVR_405EP_RB: - puts("EP Rev. B"); + puts("405EP Rev. B"); break; case PVR_405EZ_RA: - puts("EZ Rev. A"); + puts("405EZ Rev. A"); break; case PVR_405EX1_RA: - puts("EX Rev. A"); + puts("405EX Rev. A"); strcpy(addstr, "Security support"); break; case PVR_405EXR2_RA: - puts("EXr Rev. A"); + puts("405EXr Rev. A"); strcpy(addstr, "No Security support"); break; case PVR_405EX1_RC: - puts("EX Rev. C"); + puts("405EX Rev. C"); strcpy(addstr, "Security support"); break; case PVR_405EX2_RC: - puts("EX Rev. C"); + puts("405EX Rev. C"); strcpy(addstr, "No Security support"); break; case PVR_405EXR1_RC: - puts("EXr Rev. C"); + puts("405EXr Rev. C"); strcpy(addstr, "Security support"); break; case PVR_405EXR2_RC: - puts("EXr Rev. C"); + puts("405EXr Rev. C"); strcpy(addstr, "No Security support"); break; case PVR_405EX1_RD: - puts("EX Rev. D"); + puts("405EX Rev. D"); strcpy(addstr, "Security support"); break; case PVR_405EX2_RD: - puts("EX Rev. D"); + puts("405EX Rev. D"); strcpy(addstr, "No Security support"); break; case PVR_405EXR1_RD: - puts("EXr Rev. D"); + puts("405EXr Rev. D"); strcpy(addstr, "Security support"); break; case PVR_405EXR2_RD: - puts("EXr Rev. D"); + puts("405EXr Rev. D"); strcpy(addstr, "No Security support"); break; -#if defined(CONFIG_440) +#else /* CONFIG_440 */ + +#if defined(CONFIG_440GP) case PVR_440GP_RB: - puts("GP Rev. B"); + puts("440GP Rev. B"); /* See errata 1.12: CHIP_4 */ if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) || (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){ @@ -431,127 +422,127 @@ int checkcpu (void) break; case PVR_440GP_RC: - puts("GP Rev. C"); + puts("440GP Rev. C"); break; +#endif /* CONFIG_440GP */ case PVR_440GX_RA: - puts("GX Rev. A"); + puts("440GX Rev. A"); break; case PVR_440GX_RB: - puts("GX Rev. B"); + puts("440GX Rev. B"); break; case PVR_440GX_RC: - puts("GX Rev. C"); + puts("440GX Rev. C"); break; case PVR_440GX_RF: - puts("GX Rev. F"); + puts("440GX Rev. F"); break; case PVR_440EP_RA: - puts("EP Rev. A"); + puts("440EP Rev. A"); break; #ifdef CONFIG_440EP case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */ - puts("EP Rev. B"); + puts("440EP Rev. B"); break; case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */ - puts("EP Rev. C"); + puts("440EP Rev. C"); break; #endif /* CONFIG_440EP */ #ifdef CONFIG_440GR case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */ - puts("GR Rev. A"); + puts("440GR Rev. A"); break; case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */ - puts("GR Rev. B"); + puts("440GR Rev. B"); break; #endif /* CONFIG_440GR */ -#endif /* CONFIG_440 */ #ifdef CONFIG_440EPX case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ - puts("EPx Rev. A"); + puts("440EPx Rev. A"); strcpy(addstr, "Security/Kasumi support"); break; case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ - puts("EPx Rev. A"); + puts("440EPx Rev. A"); strcpy(addstr, "No Security/Kasumi support"); break; #endif /* CONFIG_440EPX */ #ifdef CONFIG_440GRX case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ - puts("GRx Rev. A"); + puts("440GRx Rev. A"); strcpy(addstr, "Security/Kasumi support"); break; case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ - puts("GRx Rev. A"); + puts("440GRx Rev. A"); strcpy(addstr, "No Security/Kasumi support"); break; #endif /* CONFIG_440GRX */ case PVR_440SP_6_RAB: - puts("SP Rev. A/B"); + puts("440SP Rev. A/B"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SP_RAB: - puts("SP Rev. A/B"); + puts("440SP Rev. A/B"); strcpy(addstr, "No RAID 6 support"); break; case PVR_440SP_6_RC: - puts("SP Rev. C"); + puts("440SP Rev. C"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SP_RC: - puts("SP Rev. C"); + puts("440SP Rev. C"); strcpy(addstr, "No RAID 6 support"); break; case PVR_440SPe_6_RA: - puts("SPe Rev. A"); + puts("440SPe Rev. A"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SPe_RA: - puts("SPe Rev. A"); + puts("440SPe Rev. A"); strcpy(addstr, "No RAID 6 support"); break; case PVR_440SPe_6_RB: - puts("SPe Rev. B"); + puts("440SPe Rev. B"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SPe_RB: - puts("SPe Rev. B"); + puts("440SPe Rev. B"); strcpy(addstr, "No RAID 6 support"); break; #if defined(CONFIG_460EX) || defined(CONFIG_460GT) case PVR_460EX_RA: - puts("EX Rev. A"); + puts("460EX Rev. A"); strcpy(addstr, "No Security/Kasumi support"); break; case PVR_460EX_SE_RA: - puts("EX Rev. A"); + puts("460EX Rev. A"); strcpy(addstr, "Security/Kasumi support"); break; case PVR_460EX_RB: - puts("EX Rev. B"); + puts("460EX Rev. B"); mfsdr(SDR0_ECID3, reg); if (reg & 0x00100000) strcpy(addstr, "No Security/Kasumi support"); @@ -560,17 +551,17 @@ int checkcpu (void) break; case PVR_460GT_RA: - puts("GT Rev. A"); + puts("460GT Rev. A"); strcpy(addstr, "No Security/Kasumi support"); break; case PVR_460GT_SE_RA: - puts("GT Rev. A"); + puts("460GT Rev. A"); strcpy(addstr, "Security/Kasumi support"); break; case PVR_460GT_RB: - puts("GT Rev. B"); + puts("460GT Rev. B"); mfsdr(SDR0_ECID3, reg); if (reg & 0x00100000) strcpy(addstr, "No Security/Kasumi support"); @@ -580,28 +571,29 @@ int checkcpu (void) #endif case PVR_460SX_RA: - puts("SX Rev. A"); + puts("460SX Rev. A"); strcpy(addstr, "Security support"); break; case PVR_460SX_RA_V1: - puts("SX Rev. A"); + puts("460SX Rev. A"); strcpy(addstr, "No Security support"); break; case PVR_460GX_RA: - puts("GX Rev. A"); + puts("460GX Rev. A"); strcpy(addstr, "Security support"); break; case PVR_460GX_RA_V1: - puts("GX Rev. A"); + puts("460GX Rev. A"); strcpy(addstr, "No Security support"); break; case PVR_VIRTEX5: - puts("x5 VIRTEX5"); + puts("440x5 VIRTEX5"); break; +#endif /* CONFIG_440 */ default: printf (" UNKNOWN (PVR=%08x)", pvr); diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index b31bd0bcc..d54b30e26 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -23,10 +23,10 @@ #include <common.h> #include <watchdog.h> -#include <ppc4xx_enet.h> +#include <asm/ppc4xx-emac.h> #include <asm/processor.h> -#include <asm/gpio.h> -#include <ppc4xx.h> +#include <asm/ppc4xx-gpio.h> +#include <asm/ppc4xx.h> #if defined(CONFIG_405GP) || defined(CONFIG_405EP) DECLARE_GLOBAL_DATA_PTR; @@ -266,7 +266,7 @@ cpu_init_f (void) /* * Set EMAC noise filter bits */ - mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); + mtdcr(CPC0_EPCTL, CPC0_EPCTL_E0NFE | CPC0_EPCTL_E1NFE); #endif /* CONFIG_405EP */ #if defined(CONFIG_SYS_4xx_GPIO_TABLE) @@ -397,10 +397,10 @@ cpu_init_f (void) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ - mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) | - PLB0_ACR_RDP_4DEEP); - mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) | - PLB1_ACR_RDP_4DEEP); + mtdcr(PLB4A0_ACR, (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_RDP_MASK) | + PLB4Ax_ACR_RDP_4DEEP); + mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) | + PLB4Ax_ACR_RDP_4DEEP); #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ } diff --git a/arch/powerpc/cpu/ppc4xx/dcr.S b/arch/powerpc/cpu/ppc4xx/dcr.S index 93465a3b5..e668e0536 100644 --- a/arch/powerpc/cpu/ppc4xx/dcr.S +++ b/arch/powerpc/cpu/ppc4xx/dcr.S @@ -24,7 +24,7 @@ #if defined(CONFIG_4xx) && defined(CONFIG_CMD_SETGETDCR) -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ diff --git a/arch/powerpc/cpu/ppc4xx/denali_data_eye.c b/arch/powerpc/cpu/ppc4xx/denali_data_eye.c index 03b8d3c61..9bba0caec 100644 --- a/arch/powerpc/cpu/ppc4xx/denali_data_eye.c +++ b/arch/powerpc/cpu/ppc4xx/denali_data_eye.c @@ -36,7 +36,7 @@ #include <common.h> #include <asm/processor.h> #include <asm/io.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /*-----------------------------------------------------------------------------+ diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c index 080ea0af4..c35b11348 100644 --- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c @@ -40,7 +40,7 @@ #include <common.h> #include <command.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <i2c.h> #include <asm/io.h> #include <asm/processor.h> diff --git a/arch/powerpc/cpu/ppc4xx/ecc.c b/arch/powerpc/cpu/ppc4xx/ecc.c index 49f28d93e..7fe5dbb7b 100644 --- a/arch/powerpc/cpu/ppc4xx/ecc.c +++ b/arch/powerpc/cpu/ppc4xx/ecc.c @@ -37,7 +37,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> #include <asm/processor.h> diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c index e99b2b03d..5ddb88024 100644 --- a/arch/powerpc/cpu/ppc4xx/fdt.c +++ b/arch/powerpc/cpu/ppc4xx/fdt.c @@ -25,7 +25,7 @@ #include <watchdog.h> #include <command.h> #include <asm/cache.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) #include <libfdt.h> diff --git a/arch/powerpc/cpu/ppc4xx/gpio.c b/arch/powerpc/cpu/ppc4xx/gpio.c index c0d351a95..20f057220 100644 --- a/arch/powerpc/cpu/ppc4xx/gpio.c +++ b/arch/powerpc/cpu/ppc4xx/gpio.c @@ -24,7 +24,10 @@ #include <common.h> #include <asm/processor.h> #include <asm/io.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> + +/* Only compile this file for boards with GPIO support */ +#if defined(GPIO0_BASE) #if defined(CONFIG_SYS_4xx_GPIO_TABLE) gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CONFIG_SYS_4xx_GPIO_TABLE; @@ -252,4 +255,6 @@ void gpio_set_chip_configuration(void) } } } + +#endif /* GPIO0_BASE */ #endif /* CONFIG_SYS_4xx_GPIO_TABLE */ diff --git a/arch/powerpc/cpu/ppc4xx/interrupts.c b/arch/powerpc/cpu/ppc4xx/interrupts.c index c89bf37a1..c2d497398 100644 --- a/arch/powerpc/cpu/ppc4xx/interrupts.c +++ b/arch/powerpc/cpu/ppc4xx/interrupts.c @@ -36,7 +36,7 @@ #include <command.h> #include <asm/processor.h> #include <asm/interrupt.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <ppc_asm.tmpl> #include <commproc.h> diff --git a/arch/powerpc/cpu/ppc4xx/kgdb.S b/arch/powerpc/cpu/ppc4xx/kgdb.S index 4227a4c15..417ba621a 100644 --- a/arch/powerpc/cpu/ppc4xx/kgdb.S +++ b/arch/powerpc/cpu/ppc4xx/kgdb.S @@ -22,7 +22,7 @@ #include <config.h> #include <command.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <version.h> #define CONFIG_405GP 1 /* needed for Linux kernel header files */ diff --git a/arch/powerpc/cpu/ppc4xx/miiphy.c b/arch/powerpc/cpu/ppc4xx/miiphy.c index 4fec126f4..3b2812201 100644 --- a/arch/powerpc/cpu/ppc4xx/miiphy.c +++ b/arch/powerpc/cpu/ppc4xx/miiphy.c @@ -41,8 +41,8 @@ #include <asm/io.h> #include <ppc_asm.tmpl> #include <commproc.h> -#include <ppc4xx_enet.h> -#include <405_mal.h> +#include <asm/ppc4xx-emac.h> +#include <asm/ppc4xx-mal.h> #include <miiphy.h> #if !defined(CONFIG_PHY_CLK_FREQ) diff --git a/arch/powerpc/cpu/ppc4xx/reginfo.c b/arch/powerpc/cpu/ppc4xx/reginfo.c index a9756672c..2f1ab9e96 100644 --- a/arch/powerpc/cpu/ppc4xx/reginfo.c +++ b/arch/powerpc/cpu/ppc4xx/reginfo.c @@ -28,7 +28,7 @@ #include <asm/processor.h> #include <asm/io.h> #include <asm/ppc4xx-uic.h> -#include <ppc4xx_enet.h> +#include <asm/ppc4xx-emac.h> enum REGISTER_TYPE { IDCR1, /* Indirectly Accessed DCR via SDRAM0_CFGADDR/SDRAM0_CFGDATA */ @@ -108,9 +108,9 @@ const struct cpu_register ppc4xx_reg[] = { {"SDR0_SDSTP3", IDCR6, SDR0_SDSTP3}, {"SDR0_CUST0", IDCR6, SDR0_CUST0}, {"SDR0_CUST1", IDCR6, SDR0_CUST1}, - {"SDR0_EBC0", IDCR6, SDR0_EBC0}, - {"SDR0_AMP0", IDCR6, SD0_AMP0}, - {"SDR0_AMP1", IDCR6, SD0_AMP1}, + {"SDR0_EBC", IDCR6, SDR0_EBC}, + {"SDR0_AMP0", IDCR6, SDR0_AMP0}, + {"SDR0_AMP1", IDCR6, SDR0_AMP1}, {"SDR0_CP440", IDCR6, SDR0_CP440}, {"SDR0_CRYP0", IDCR6, SDR0_CRYP0}, {"SDR0_DDRCFG", IDCR6, SDR0_DDRCFG}, diff --git a/arch/powerpc/cpu/ppc4xx/sdram.c b/arch/powerpc/cpu/ppc4xx/sdram.c index 30c6e0e38..b827daf66 100644 --- a/arch/powerpc/cpu/ppc4xx/sdram.c +++ b/arch/powerpc/cpu/ppc4xx/sdram.c @@ -28,7 +28,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include "sdram.h" #include "ecc.h" diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 906face03..abd4e910d 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -23,7 +23,7 @@ #include <common.h> #include <ppc_asm.tmpl> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> DECLARE_GLOBAL_DATA_PTR; @@ -902,7 +902,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) /* * Read CPR_PRIMAD register */ - mfcpr(CPC0_PRIMAD, cpr_primad); + mfcpr(CPR0_PRIMAD, cpr_primad); /* * Determine PLB_DIV. diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 4bad32f9f..7a65d9fcc 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -64,7 +64,7 @@ * address and (s)dram will be positioned at address 0 */ #include <config.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <timestamp.h> #include <version.h> @@ -340,6 +340,9 @@ _start_440: mfspr r1,SPRN_DBCR0 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */ bne skip_debug_init /* if set, don't clear debug register */ + mfspr r1,SPRN_CCR0 + ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */ + mtspr SPRN_CCR0,r1 mtspr SPRN_DBCR0,r0 mtspr SPRN_DBCR1,r0 mtspr SPRN_DBCR2,r0 diff --git a/arch/powerpc/cpu/ppc4xx/tlb.c b/arch/powerpc/cpu/ppc4xx/tlb.c index 24a9a9cc2..684da92a8 100644 --- a/arch/powerpc/cpu/ppc4xx/tlb.c +++ b/arch/powerpc/cpu/ppc4xx/tlb.c @@ -25,7 +25,7 @@ #if defined(CONFIG_440) -#include <ppc440.h> +#include <asm/ppc440.h> #include <asm/cache.h> #include <asm/io.h> #include <asm/mmu.h> diff --git a/arch/powerpc/cpu/ppc4xx/uic.c b/arch/powerpc/cpu/ppc4xx/uic.c index 8b1b259fa..324f0e95e 100644 --- a/arch/powerpc/cpu/ppc4xx/uic.c +++ b/arch/powerpc/cpu/ppc4xx/uic.c @@ -36,7 +36,7 @@ #include <command.h> #include <asm/processor.h> #include <asm/interrupt.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <ppc_asm.tmpl> #include <commproc.h> diff --git a/arch/powerpc/cpu/ppc4xx/xilinx_irq.c b/arch/powerpc/cpu/ppc4xx/xilinx_irq.c index 71087771c..eaa3de2d4 100644 --- a/arch/powerpc/cpu/ppc4xx/xilinx_irq.c +++ b/arch/powerpc/cpu/ppc4xx/xilinx_irq.c @@ -21,7 +21,7 @@ #include <command.h> #include <asm/processor.h> #include <asm/interrupt.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <ppc_asm.tmpl> #include <commproc.h> #include <asm/io.h> |