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-rw-r--r--arch/arm/include/asm/arch-spear/hardware.h55
-rw-r--r--arch/arm/include/asm/arch-spear/spr_defs.h30
-rw-r--r--arch/arm/include/asm/arch-spear/spr_misc.h136
-rw-r--r--arch/arm/include/asm/arch-spear/spr_ssp.h45
-rw-r--r--arch/arm/include/asm/arch-spear/spr_syscntl.h14
5 files changed, 260 insertions, 20 deletions
diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h
index 0012dd7e6..81509119d 100644
--- a/arch/arm/include/asm/arch-spear/hardware.h
+++ b/arch/arm/include/asm/arch-spear/hardware.h
@@ -24,37 +24,54 @@
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
-#define CONFIG_SYS_USBD_BASE (0xE1100000)
-#define CONFIG_SYS_PLUG_BASE (0xE1200000)
-#define CONFIG_SYS_FIFO_BASE (0xE1000800)
-#define CONFIG_SYS_SMI_BASE (0xFC000000)
-#define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000)
-#define CONFIG_SPEAR_TIMERBASE (0xFC800000)
-#define CONFIG_SPEAR_MISCBASE (0xFCA80000)
+#define CONFIG_SYS_USBD_BASE 0xE1100000
+#define CONFIG_SYS_PLUG_BASE 0xE1200000
+#define CONFIG_SYS_FIFO_BASE 0xE1000800
+#define CONFIG_SYS_SMI_BASE 0xFC000000
+#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000
+#define CONFIG_SPEAR_TIMERBASE 0xFC800000
+#define CONFIG_SPEAR_MISCBASE 0xFCA80000
#define CONFIG_SPEAR_ETHBASE 0xE0800000
+#define CONFIG_SPEAR_MPMCBASE 0xFC600000
+#define CONFIG_SSP1_BASE 0xD0100000
+#define CONFIG_SSP2_BASE 0xD0180000
+#define CONFIG_SSP3_BASE 0xD8180000
+#define CONFIG_GPIO_BASE 0xD8100000
#define CONFIG_SYS_NAND_CLE (1 << 16)
#define CONFIG_SYS_NAND_ALE (1 << 17)
#if defined(CONFIG_SPEAR600)
-#define CONFIG_SYS_I2C_BASE (0xD0200000)
-#define CONFIG_SYS_FSMC_BASE (0xD1800000)
+#define CONFIG_SYS_I2C_BASE 0xD0200000
+#define CONFIG_SYS_FSMC_BASE 0xD1800000
+#define CONFIG_FSMC_NAND_BASE 0xD2000000
+
+#define CONFIG_SPEAR_BOOTSTRAPCFG 0xFCA80000
+#define CONFIG_SPEAR_BOOTSTRAPSHFT 16
+#define CONFIG_SPEAR_BOOTSTRAPMASK 0xB
+#define CONFIG_SPEAR_ONLYSNORBOOT 0xA
+#define CONFIG_SPEAR_NORNANDBOOT 0xB
+#define CONFIG_SPEAR_NORNAND8BOOT 0x8
+#define CONFIG_SPEAR_NORNAND16BOOT 0x9
+#define CONFIG_SPEAR_USBBOOT 0x8
+
+#define CONFIG_SPEAR_MPMCREGS 100
#elif defined(CONFIG_SPEAR300)
-#define CONFIG_SYS_I2C_BASE (0xD0180000)
-#define CONFIG_SYS_FSMC_BASE (0x94000000)
+#define CONFIG_SYS_I2C_BASE 0xD0180000
+#define CONFIG_SYS_FSMC_BASE 0x94000000
#elif defined(CONFIG_SPEAR310)
-#define CONFIG_SYS_I2C_BASE (0xD0180000)
-#define CONFIG_SYS_FSMC_BASE (0x44000000)
+#define CONFIG_SYS_I2C_BASE 0xD0180000
+#define CONFIG_SYS_FSMC_BASE 0x44000000
#undef CONFIG_SYS_NAND_CLE
#undef CONFIG_SYS_NAND_ALE
#define CONFIG_SYS_NAND_CLE (1 << 17)
#define CONFIG_SYS_NAND_ALE (1 << 16)
-#define CONFIG_SPEAR_EMIBASE (0x4F000000)
-#define CONFIG_SPEAR_RASBASE (0xB4000000)
+#define CONFIG_SPEAR_EMIBASE 0x4F000000
+#define CONFIG_SPEAR_RASBASE 0xB4000000
#define CONFIG_SYS_MACB0_BASE 0xB0000000
#define CONFIG_SYS_MACB1_BASE 0xB0800000
@@ -62,11 +79,11 @@
#define CONFIG_SYS_MACB3_BASE 0xB1800000
#elif defined(CONFIG_SPEAR320)
-#define CONFIG_SYS_I2C_BASE (0xD0180000)
-#define CONFIG_SYS_FSMC_BASE (0x4C000000)
+#define CONFIG_SYS_I2C_BASE 0xD0180000
+#define CONFIG_SYS_FSMC_BASE 0x4C000000
-#define CONFIG_SPEAR_EMIBASE (0x40000000)
-#define CONFIG_SPEAR_RASBASE (0xB3000000)
+#define CONFIG_SPEAR_EMIBASE 0x40000000
+#define CONFIG_SPEAR_RASBASE 0xB3000000
#define CONFIG_SYS_MACB0_BASE 0xAA000000
diff --git a/arch/arm/include/asm/arch-spear/spr_defs.h b/arch/arm/include/asm/arch-spear/spr_defs.h
index 0ddce621e..71d64a199 100644
--- a/arch/arm/include/asm/arch-spear/spr_defs.h
+++ b/arch/arm/include/asm/arch-spear/spr_defs.h
@@ -28,6 +28,30 @@ extern int spear_board_init(ulong);
extern void setfreq(unsigned int, unsigned int);
extern unsigned int setfreq_sz;
+void plat_ddr_init(void);
+void soc_init(void);
+void spear_late_init(void);
+void plat_late_init(void);
+
+int snor_boot_selected(void);
+int nand_boot_selected(void);
+int pnor_boot_selected(void);
+int usb_boot_selected(void);
+int uart_boot_selected(void);
+int tftp_boot_selected(void);
+int i2c_boot_selected(void);
+int spi_boot_selected(void);
+int mmc_boot_selected(void);
+
+extern u32 mpmc_conf_vals[];
+
+struct chip_data {
+ int cpufreq;
+ int dramfreq;
+ int dramtype;
+ uchar version[32];
+};
+
/* HW mac id in i2c memory definitions */
#define MAGIC_OFF 0x0
#define MAGIC_LEN 0x2
@@ -36,4 +60,10 @@ extern unsigned int setfreq_sz;
#define MAC_OFF 0x2
#define MAC_LEN 0x6
+#define PNOR_WIDTH_8 0
+#define PNOR_WIDTH_16 1
+#define PNOR_WIDTH_32 2
+#define PNOR_WIDTH_NUM 3
+#define PNOR_WIDTH_SEARCH 0xff
+
#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h
index b8fcf49fe..5f67a5fa2 100644
--- a/arch/arm/include/asm/arch-spear/spr_misc.h
+++ b/arch/arm/include/asm/arch-spear/spr_misc.h
@@ -46,7 +46,7 @@ struct misc_regs {
u32 prsc2_clk_cfg; /* 0x48 */
u32 prsc3_clk_cfg; /* 0x4C */
u32 amem_cfg_ctrl; /* 0x50 */
- u32 port_cfg_ctrl; /* 0x54 */
+ u32 expi_clk_cfg; /* 0x54 */
u32 reserved_1; /* 0x58 */
u32 clcd_synth_clk; /* 0x5C */
u32 irda_synth_clk; /* 0x60 */
@@ -101,6 +101,37 @@ struct misc_regs {
u32 ras_gpp2_out; /* 0x800C */
};
+/* SYNTH_CLK value*/
+#define SYNTH23 0x00020003
+
+/* PLLx_FRQ value */
+#if defined(CONFIG_SPEAR3XX)
+#define FREQ_332 0xA600010C
+#define FREQ_266 0x8500010C
+#elif defined(CONFIG_SPEAR600)
+#define FREQ_332 0xA600010F
+#define FREQ_266 0x8500010F
+#endif
+
+/* PLL_CTR_REG */
+#define MEM_CLK_SEL_MSK 0x70000000
+#define MEM_CLK_HCLK 0x00000000
+#define MEM_CLK_2HCLK 0x10000000
+#define MEM_CLK_PLL2 0x30000000
+
+#define EXPI_CLK_CFG_LOW_COMPR 0x2000
+#define EXPI_CLK_CFG_CLK_EN 0x0400
+#define EXPI_CLK_CFG_RST 0x0200
+#define EXPI_CLK_SYNT_EN 0x0010
+#define EXPI_CLK_CFG_SEL_PLL2 0x0004
+#define EXPI_CLK_CFG_INT_CLK_EN 0x0001
+
+#define PLL2_CNTL_6UA 0x1c00
+#define PLL2_CNTL_SAMPLE 0x0008
+#define PLL2_CNTL_ENABLE 0x0004
+#define PLL2_CNTL_RESETN 0x0002
+#define PLL2_CNTL_LOCK 0x0001
+
/* AUTO_CFG_REG value */
#define MISC_SOCCFGMSK 0x0000003F
#define MISC_SOCCFG30 0x0000000C
@@ -131,9 +162,112 @@ struct misc_regs {
#define MISC_ETHENB 0x00800000
#define MISC_SMIENB 0x00200000
#define MISC_GPT3ENB 0x00010000
+#define MISC_GPIO4ENB 0x00002000
#define MISC_GPT2ENB 0x00000800
#define MISC_FSMCENB 0x00000200
#define MISC_I2CENB 0x00000080
+#define MISC_SSP2ENB 0x00000070
#define MISC_UART0ENB 0x00000008
+/* PERIPH_CLK_CFG */
+#define XTALTIMEEN 0x00000001
+#define PLLTIMEEN 0x00000002
+#define CLCDCLK_SYNTH 0x00000000
+#define CLCDCLK_48MHZ 0x00000004
+#define CLCDCLK_EXT 0x00000008
+#define UARTCLK_MASK (0x1 << 4)
+#define UARTCLK_48MHZ 0x00000000
+#define UARTCLK_SYNTH 0x00000010
+#define IRDACLK_48MHZ 0x00000000
+#define IRDACLK_SYNTH 0x00000020
+#define IRDACLK_EXT 0x00000040
+#define RTC_DISABLE 0x00000080
+#define GPT1CLK_48MHZ 0x00000000
+#define GPT1CLK_SYNTH 0x00000100
+#define GPT2CLK_48MHZ 0x00000000
+#define GPT2CLK_SYNTH 0x00000200
+#define GPT3CLK_48MHZ 0x00000000
+#define GPT3CLK_SYNTH 0x00000400
+#define GPT4CLK_48MHZ 0x00000000
+#define GPT4CLK_SYNTH 0x00000800
+#define GPT5CLK_48MHZ 0x00000000
+#define GPT5CLK_SYNTH 0x00001000
+#define GPT1_FREEZE 0x00002000
+#define GPT2_FREEZE 0x00004000
+#define GPT3_FREEZE 0x00008000
+#define GPT4_FREEZE 0x00010000
+#define GPT5_FREEZE 0x00020000
+
+/* PERIPH1_CLKEN bits */
+#define PERIPH_ARM1_WE 0x00000001
+#define PERIPH_ARM1 0x00000002
+#define PERIPH_ARM2 0x00000004
+#define PERIPH_UART1 0x00000008
+#define PERIPH_UART2 0x00000010
+#define PERIPH_SSP1 0x00000020
+#define PERIPH_SSP2 0x00000040
+#define PERIPH_I2C 0x00000080
+#define PERIPH_JPEG 0x00000100
+#define PERIPH_FSMC 0x00000200
+#define PERIPH_FIRDA 0x00000400
+#define PERIPH_GPT4 0x00000800
+#define PERIPH_GPT5 0x00001000
+#define PERIPH_GPIO4 0x00002000
+#define PERIPH_SSP3 0x00004000
+#define PERIPH_ADC 0x00008000
+#define PERIPH_GPT3 0x00010000
+#define PERIPH_RTC 0x00020000
+#define PERIPH_GPIO3 0x00040000
+#define PERIPH_DMA 0x00080000
+#define PERIPH_ROM 0x00100000
+#define PERIPH_SMI 0x00200000
+#define PERIPH_CLCD 0x00400000
+#define PERIPH_GMAC 0x00800000
+#define PERIPH_USBD 0x01000000
+#define PERIPH_USBH1 0x02000000
+#define PERIPH_USBH2 0x04000000
+#define PERIPH_MPMC 0x08000000
+#define PERIPH_RAMW 0x10000000
+#define PERIPH_MPMC_EN 0x20000000
+#define PERIPH_MPMC_WE 0x40000000
+#define PERIPH_MPMCMSK 0x60000000
+
+#define PERIPH_CLK_ALL 0x0FFFFFF8
+#define PERIPH_RST_ALL 0x00000004
+
+/* DDR_PAD values */
+#define DDR_PAD_CNF_MSK 0x0000ffff
+#define DDR_PAD_SW_CONF 0x00060000
+#define DDR_PAD_SSTL_SEL 0x00000001
+#define DDR_PAD_DRAM_TYPE 0x00008000
+
+/* DDR_COMP values */
+#define DDR_COMP_ACCURATE 0x00000010
+
+/* SoC revision stuff */
+#define SOC_PRI_SHFT 16
+#define SOC_SEC_SHFT 8
+
+/* Revision definitions */
+#define SOC_SPEAR_NA 0
+
+/*
+ * The definitons have started from
+ * 101 for SPEAr6xx
+ * 201 for SPEAr3xx
+ * 301 for SPEAr13xx
+ */
+#define SOC_SPEAR600_AA 101
+#define SOC_SPEAR600_AB 102
+#define SOC_SPEAR600_BA 103
+#define SOC_SPEAR600_BB 104
+#define SOC_SPEAR600_BC 105
+#define SOC_SPEAR600_BD 106
+
+#define SOC_SPEAR300 201
+#define SOC_SPEAR310 202
+#define SOC_SPEAR320 203
+
+extern int get_socrev(void);
+
#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_ssp.h b/arch/arm/include/asm/arch-spear/spr_ssp.h
new file mode 100644
index 000000000..4f144ee4d
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/spr_ssp.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPR_SSP_H
+#define _SPR_SSP_H
+
+struct ssp_regs {
+ u32 sspcr0;
+ u32 sspcr1;
+ u32 sspdr;
+ u32 sspsr;
+ u32 sspcpsr;
+ u32 sspimsc;
+ u32 sspicr;
+ u32 sspdmacr;
+};
+
+#define SSPCR0_FRF_MOT_SPI 0x0000
+#define SSPCR0_DSS_16BITS 0x000f
+
+#define SSPCR1_SSE 0x0002
+
+#define SSPSR_TNF 0x2
+#define SSPSR_TFE 0x1
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_syscntl.h b/arch/arm/include/asm/arch-spear/spr_syscntl.h
index 3c92f094c..2393d89c0 100644
--- a/arch/arm/include/asm/arch-spear/spr_syscntl.h
+++ b/arch/arm/include/asm/arch-spear/spr_syscntl.h
@@ -21,6 +21,9 @@
* MA 02111-1307 USA
*/
+#ifndef __SYSCTRL_H
+#define __SYSCTRL_H
+
struct syscntl_regs {
u32 scctrl;
u32 scsysstat;
@@ -36,3 +39,14 @@ struct syscntl_regs {
const u32 scperclken;
const u32 scperstat;
};
+
+#define MODE_SHIFT 0x00000003
+
+#define NORMAL 0x00000004
+#define SLOW 0x00000002
+#define DOZE 0x00000001
+#define SLEEP 0x00000000
+
+#define PLL_TIM 0x01FFFFFF
+
+#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-16 16:23:45 +0000