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-rw-r--r--arch/arm/cpu/arm1136/start.S8
-rw-r--r--arch/arm/cpu/arm1176/start.S10
-rw-r--r--arch/arm/cpu/arm720t/start.S10
-rw-r--r--arch/arm/cpu/arm920t/start.S10
-rw-r--r--arch/arm/cpu/arm925t/start.S10
-rw-r--r--arch/arm/cpu/arm926ejs/at91/cpu.c48
-rw-r--r--arch/arm/cpu/arm926ejs/kirkwood/cpu.c34
-rw-r--r--arch/arm/cpu/arm926ejs/kirkwood/dram.c38
-rw-r--r--arch/arm/cpu/arm926ejs/orion5x/cpu.c112
-rw-r--r--arch/arm/cpu/arm926ejs/orion5x/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/start.S10
-rw-r--r--arch/arm/cpu/arm946es/start.S8
-rw-r--r--arch/arm/cpu/arm_intcm/start.S10
-rw-r--r--arch/arm/cpu/armv7/start.S8
-rw-r--r--arch/arm/cpu/ixp/start.S10
-rw-r--r--arch/arm/cpu/lh7a40x/start.S11
-rw-r--r--arch/arm/cpu/pxa/start.S8
-rw-r--r--arch/arm/cpu/s3c44b0/start.S12
-rw-r--r--arch/arm/cpu/sa1100/start.S10
19 files changed, 231 insertions, 142 deletions
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 8b631920c..494768edf 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -235,8 +235,8 @@ stack_setup:
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
@@ -355,8 +355,8 @@ relocate: /* relocate U-Boot to RAM */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index e5e7913d9..6277ae092 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -284,8 +284,8 @@ stack_setup:
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
@@ -500,8 +500,8 @@ relocate: /* relocate U-Boot to RAM */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
#ifdef CONFIG_ENABLE_MMU
@@ -559,7 +559,7 @@ clbss_l:
str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
- ble clbss_l
+ blo clbss_l
#ifndef CONFIG_NAND_SPL
ldr pc, _start_armboot
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index 0f5f6c461..6a8d57b09 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -201,8 +201,8 @@ stack_setup:
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
@@ -318,8 +318,8 @@ relocate: /* relocate U-Boot to RAM */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
@@ -342,7 +342,7 @@ clear_bss:
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
- ble clbss_l
+ blo clbss_l
ldr pc, _start_armboot
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index a079bb272..09ee81527 100644
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -246,8 +246,8 @@ stack_setup:
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
@@ -406,8 +406,8 @@ relocate: /* relocate U-Boot to RAM */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
@@ -429,7 +429,7 @@ clear_bss:
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
- ble clbss_l
+ blo clbss_l
ldr pc, _start_armboot
diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S
index c0a856dfe..f173400ac 100644
--- a/arch/arm/cpu/arm925t/start.S
+++ b/arch/arm/cpu/arm925t/start.S
@@ -238,8 +238,8 @@ stack_setup:
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
@@ -377,8 +377,8 @@ relocate: /* relocate U-Boot to RAM */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
@@ -400,7 +400,7 @@ clear_bss:
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
- ble clbss_l
+ blo clbss_l
ldr pc, _start_armboot
diff --git a/arch/arm/cpu/arm926ejs/at91/cpu.c b/arch/arm/cpu/arm926ejs/at91/cpu.c
index 141a7d1ec..5e30f1dcc 100644
--- a/arch/arm/cpu/arm926ejs/at91/cpu.c
+++ b/arch/arm/cpu/arm926ejs/at91/cpu.c
@@ -1,4 +1,6 @@
/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
* (C) Copyright 2009
* Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
@@ -22,12 +24,11 @@
*/
#include <common.h>
-#ifdef CONFIG_AT91_LEGACY
-#warning Your board is using legacy SoC access. Please update!
-#endif
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_gpbr.h>
#include <asm/arch/clk.h>
#include <asm/arch/io.h>
@@ -35,18 +36,26 @@
#define CONFIG_SYS_AT91_MAIN_CLOCK 0
#endif
-/*
- * The at91sam9260 has 4 GPBR (0-3), we'll use the last one, nr 3,
- * to keep track of the bootcount.
- */
-#define AT91_GPBR_BOOTCOUNT_REGISTER 3
-#define AT91_BOOTCOUNT_ADDRESS (AT91_GPBR + 4*AT91_GPBR_BOOTCOUNT_REGISTER)
-
int arch_cpu_init(void)
{
return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
}
+void arch_preboot_os(void)
+{
+ ulong cpiv;
+ at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
+
+ cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
+
+ /*
+ * Disable PITC
+ * Add 0x1000 to current counter to stop it faster
+ * without waiting for wrapping back to 0
+ */
+ writel(cpiv + 0x1000, &pit->mr);
+}
+
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
@@ -66,27 +75,26 @@ int print_cpuinfo(void)
#ifdef CONFIG_BOOTCOUNT_LIMIT
/*
- * Just as the mpc5xxx, we combine the BOOTCOUNT_MAGIC and boocount
- * in one 32-bit register. This is done, as the AT91SAM9260 only has
- * 4 GPBR.
+ * We combine the BOOTCOUNT_MAGIC and bootcount in one 32-bit register.
+ * This is done so we need to use only one of the four GPBR registers.
*/
void bootcount_store (ulong a)
{
- volatile ulong *save_addr =
- (volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
+ at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE;
- *save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff);
+ writel((BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff),
+ &gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]);
}
ulong bootcount_load (void)
{
- volatile ulong *save_addr =
- (volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
+ at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE;
- if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
+ ulong val = readl(&gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]);
+ if ((val & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
return 0;
else
- return (*save_addr & 0x0000ffff);
+ return val & 0x0000ffff;
}
#endif /* CONFIG_BOOTCOUNT_LIMIT */
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index 82c978bd9..b4a4c0428 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -54,10 +54,11 @@ unsigned char get_random_hex(void)
u8 outbuf[BUFLEN];
/*
- * in case of 88F6281/88F6192 A0,
+ * in case of 88F6281/88F6282/88F6192 A0,
* Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
- * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are reserved regs and
- * Does not have names at this moment (no errata available)
+ * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
+ * reserved regs and does not have names at this moment
+ * (no errata available)
*/
writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
for (i = 0; i < BUFLEN; i++) {
@@ -271,20 +272,31 @@ static void kw_sysrst_check(void)
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
- char *name = "Unknown";
+ char *rev;
+ u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
+ u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
- switch (readl(KW_REG_DEVICE_ID) & 0x03) {
- case 1:
- name = "88F6192_A0";
+ if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
+ printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
+ return -1;
+ }
+
+ switch (revid) {
+ case 0:
+ rev = "Z0";
break;
case 2:
- name = "88F6281_A0";
+ rev = "A0";
+ break;
+ case 3:
+ rev = "A1";
break;
default:
- printf("SoC: Unsupported Kirkwood\n");
- return -1;
+ rev = "??";
+ break;
}
- printf("SoC: Kirkwood %s\n", name);
+
+ printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c
index 8f2a18af6..7439c87f6 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/dram.c
@@ -23,8 +23,11 @@
*/
#include <config.h>
+#include <common.h>
#include <asm/arch/kirkwood.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08))
#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08))
/*
@@ -56,3 +59,38 @@ u32 kw_sdram_bs(enum memory_bank bank)
result += 0x01000000;
return result;
}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+ int i;
+
+ gd->ram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = kw_sdram_bar(i);
+ gd->bd->bi_dram[i].size = kw_sdram_bs(i);
+ /*
+ * It is assumed that all memory banks are consecutive
+ * and without gaps.
+ * If the gap is found, ram_size will be reported for
+ * consecutive memory only
+ */
+ if (gd->bd->bi_dram[i].start != gd->ram_size)
+ break;
+
+ gd->ram_size += gd->bd->bi_dram[i].size;
+
+ }
+ return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+ dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
+
diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
index 260f88b46..1894b52fb 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
@@ -48,24 +48,34 @@ void reset_cpu(unsigned long ignored)
}
/*
- * Window Size
+ * Compute Window Size field value from size expressed in bytes
* Used with the Base register to set the address window size and location.
* Must be programmed from LSB to MSB as sequence of ones followed by
* sequence of zeros. The number of ones specifies the size of the window in
- * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
- * NOTE: A value of 0x0 specifies 64-KByte size.
+ * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
+ * NOTES:
+ * 1) A sizeval equal to 0x0 specifies 4 GiB.
+ * 2) A return value of 0x0 specifies 64 KiB.
*/
unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
{
- int i;
- unsigned int j = 0;
- u32 val = sizeval >> 1;
-
- for (i = 0; val >= 0x10000; i++) {
- j |= (1 << i);
- val = val >> 1;
- }
- return 0x0000ffff & j;
+ /*
+ * Calculate the number of 64 KiB blocks needed minus one (rounding up).
+ * For sizeval > 0 this is equivalent to:
+ * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1
+ */
+ sizeval = (sizeval - 1) >> 16;
+
+ /*
+ * Propagate 'one' bits to the right by 'oring' them.
+ * We need only treat bits 15-0.
+ */
+ sizeval |= sizeval >> 1; /* 'Or' bit 15 onto bit 14 */
+ sizeval |= sizeval >> 2; /* 'Or' bits 15-14 onto bits 13-12 */
+ sizeval |= sizeval >> 4; /* 'Or' bits 15-12 onto bits 11-8 */
+ sizeval |= sizeval >> 8; /* 'Or' bits 15-8 onto bits 7-0*/
+
+ return sizeval;
}
/*
@@ -77,6 +87,17 @@ unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
*
* If remap function not used, remap_lo must be set as base
*
+ * NOTES:
+ *
+ * 1) in order to avoid windows with inconsistent control and base values
+ * (which could prevent access to BOOTCS and hence execution from FLASH)
+ * always disable window before writing the base value then reenable it
+ * by writing the control value.
+ *
+ * 2) in order to avoid losing access to BOOTCS when disabling window 7,
+ * first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
+ * then configure windows 6 for its own target.
+ *
* Reference Documentation:
* Mbus-L to Mbus Bridge Registers Configuration.
* (Sec 25.1 and 25.3 of Datasheet)
@@ -86,57 +107,64 @@ int orion5x_config_adr_windows(void)
struct orion5x_win_registers *winregs =
(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
- /* Window 0: PCIE MEM address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
- ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
- ORION5X_WIN_ENABLE), &winregs[0].ctrl);
+/* Disable window 0, configure it for its intended target, enable it. */
+ writel(0, &winregs[0].ctrl);
writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
-
- /* Window 1: PCIE IO address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
- ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
- ORION5X_WIN_ENABLE), &winregs[1].ctrl);
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
+ ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
+ ORION5X_WIN_ENABLE), &winregs[0].ctrl);
+/* Disable window 1, configure it for its intended target, enable it. */
+ writel(0, &winregs[1].ctrl);
writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
-
- /* Window 2: PCI MEM address space */
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
+ ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
+ ORION5X_WIN_ENABLE), &winregs[1].ctrl);
+/* Disable window 2, configure it for its intended target, enable it. */
+ writel(0, &winregs[2].ctrl);
+ writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
ORION5X_WIN_ENABLE), &winregs[2].ctrl);
- writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
-
- /* Window 3: PCI IO address space */
+/* Disable window 3, configure it for its intended target, enable it. */
+ writel(0, &winregs[3].ctrl);
+ writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
ORION5X_WIN_ENABLE), &winregs[3].ctrl);
- writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
-
- /* Window 4: DEV_CS0 address space */
+/* Disable window 4, configure it for its intended target, enable it. */
+ writel(0, &winregs[4].ctrl);
+ writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
ORION5X_WIN_ENABLE), &winregs[4].ctrl);
- writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
-
- /* Window 5: DEV_CS1 address space */
+/* Disable window 5, configure it for its intended target, enable it. */
+ writel(0, &winregs[5].ctrl);
+ writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
ORION5X_WIN_ENABLE), &winregs[5].ctrl);
- writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
-
- /* Window 6: DEV_CS2 address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
- ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
+/* Disable window 6, configure it for FLASH, enable it. */
+ writel(0, &winregs[6].ctrl);
+ writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
+ ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
ORION5X_WIN_ENABLE), &winregs[6].ctrl);
- writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
-
- /* Window 7: BOOT Memory address space */
+/* Disable window 7, configure it for FLASH, enable it. */
+ writel(0, &winregs[7].ctrl);
+ writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
ORION5X_WIN_ENABLE), &winregs[7].ctrl);
- writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
+/* Disable window 6, configure it for its intended target, enable it. */
+ writel(0, &winregs[6].ctrl);
+ writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
+ ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
+ ORION5X_WIN_ENABLE), &winregs[6].ctrl);
return 0;
}
@@ -265,6 +293,8 @@ int arch_misc_init(void)
writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
+ /* initialize timer */
+ timer_init_r();
return 0;
}
#endif /* CONFIG_ARCH_MISC_INIT */
diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/cpu/arm926ejs/orion5x/timer.c
index 115448fa3..089ef47b3 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/timer.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/timer.c
@@ -173,9 +173,11 @@ int timer_init(void)
cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
writel(cntmrctrl, CNTMR_CTRL_REG);
+ return 0;
+}
+void timer_init_r(void)
+{
/* init the timestamp and lastdec value */
reset_timer_masked();
-
- return 0;
}
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 16ee972f2..a960689e7 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -236,8 +236,8 @@ stack_setup:
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
@@ -341,8 +341,8 @@ relocate: /* relocate U-Boot to RAM */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
@@ -368,7 +368,7 @@ clear_bss:
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
- ble clbss_l
+ blo clbss_l
bl coloured_LED_init
bl red_LED_on
diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
index 18ed0b2da..4f062e5ff 100644
--- a/arch/arm/cpu/arm946es/start.S
+++ b/arch/arm/cpu/arm946es/start.S
@@ -207,8 +207,8 @@ stack_setup:
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
@@ -309,8 +309,8 @@ relocate: /* relocate U-Boot to RAM */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
/* Set up the stack */
stack_setup:
diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S
index b39fdc64c..79ef51736 100644
--- a/arch/arm/cpu/arm_intcm/start.S
+++ b/arch/arm/cpu/arm_intcm/start.S
@@ -205,8 +205,8 @@ stack_setup:
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
@@ -305,8 +305,8 @@ relocate: /* relocate U-Boot to RAM */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
/* Set up the stack */
stack_setup:
@@ -327,7 +327,7 @@ clear_bss:
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
- ble clbss_l
+ blo clbss_l
ldr pc, _start_armboot
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index f411c0f4f..c392c5d9d 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -209,8 +209,8 @@ stack_setup:
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
@@ -324,8 +324,8 @@ relocate: @ relocate U-Boot to RAM
copy_loop: @ copy 32 bytes at a time
ldmia r0!, {r3 - r10} @ copy from source address [r0]
stmia r1!, {r3 - r10} @ copy to target address [r1]
- cmp r0, r2 @ until source end addreee [r2]
- ble copy_loop
+ cmp r0, r2 @ until source end address [r2]
+ blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S
index b2c825514..940d45d73 100644
--- a/arch/arm/cpu/ixp/start.S
+++ b/arch/arm/cpu/ixp/start.S
@@ -330,8 +330,8 @@ stack_setup:
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
@@ -547,8 +547,8 @@ relocate: /* relocate U-Boot to RAM */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
@@ -570,7 +570,7 @@ clear_bss:
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
- ble clbss_l
+ blo clbss_l
ldr pc, _start_armboot
diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S
index 002116a40..b8cf1b8b3 100644
--- a/arch/arm/cpu/lh7a40x/start.S
+++ b/arch/arm/cpu/lh7a40x/start.S
@@ -219,8 +219,8 @@ stack_setup:
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
@@ -341,9 +341,8 @@ relocate: /* relocate U-Boot to RAM */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- blt copy_loop /* a 'ble' here actually copies */
- /* four bytes of bss */
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
@@ -367,7 +366,7 @@ clear_bss:
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
- ble clbss_l
+ blo clbss_l
ldr pc, _start_armboot
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index 064ddbcf3..cfb94112d 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -204,8 +204,8 @@ stack_setup:
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
@@ -310,7 +310,7 @@ copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
- ble copy_loop
+ blo copy_loop
#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
@@ -337,7 +337,7 @@ clear_bss:
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
- ble clbss_l
+ blo clbss_l
#endif
ldr pc, _start_armboot
diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S
index e1ab5ccb3..c5a67dc66 100644
--- a/arch/arm/cpu/s3c44b0/start.S
+++ b/arch/arm/cpu/s3c44b0/start.S
@@ -191,8 +191,8 @@ stack_setup:
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
@@ -225,7 +225,7 @@ vector_copy_loop:
ldmia r0!, {r3-r10}
stmia r1!, {r3-r10}
cmp r0, r2
- ble vector_copy_loop
+ blo vector_copy_loop
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
@@ -310,8 +310,8 @@ relocate: /* relocate U-Boot to RAM */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
/*
now copy to sram the interrupt vector
@@ -324,7 +324,7 @@ vector_copy_loop:
ldmia r0!, {r3-r10}
stmia r1!, {r3-r10}
cmp r0, r2
- ble vector_copy_loop
+ blo vector_copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
index 4730e5a9a..d1262ada2 100644
--- a/arch/arm/cpu/sa1100/start.S
+++ b/arch/arm/cpu/sa1100/start.S
@@ -195,8 +195,8 @@ stack_setup:
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
@@ -293,8 +293,8 @@ relocate: /* relocate U-Boot to RAM */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
@@ -316,7 +316,7 @@ clear_bss:
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
- ble clbss_l
+ blo clbss_l
ldr pc, _start_armboot
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-27 01:46:26 +0000