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-rw-r--r--CHANGELOG1020
-rwxr-xr-xMAKEALL1
-rw-r--r--Makefile14
-rw-r--r--board/amcc/canyonlands/canyonlands.c26
-rw-r--r--board/cray/L1/init.S4
-rw-r--r--board/csb272/init.S2
-rw-r--r--board/csb472/init.S2
-rw-r--r--board/davinci/dm355evm/dm355evm.c10
-rw-r--r--board/digsy_mtc/cmd_mtc.c80
-rw-r--r--board/digsy_mtc/cmd_mtc.h1
-rw-r--r--board/eric/init.S4
-rw-r--r--board/esd/pci405/writeibm.S4
-rw-r--r--board/exbitgen/init.S2
-rw-r--r--board/freescale/m5208evbe/Makefile44
-rw-r--r--board/freescale/m5208evbe/config.mk (renamed from cpu/arm_cortexa8/omap3/config.mk)19
-rw-r--r--board/freescale/m5208evbe/m5208evbe.c94
-rw-r--r--board/freescale/m5208evbe/u-boot.lds142
-rw-r--r--board/freescale/m54451evb/u-boot.spa9
-rw-r--r--board/gdsys/compactcenter/compactcenter.c26
-rw-r--r--board/jse/init.S4
-rw-r--r--board/mimc/mimc200/mimc200.c2
-rw-r--r--board/mpl/common/pci.c2
-rw-r--r--board/mpl/mip405/init.S2
-rw-r--r--board/mpl/pip405/init.S2
-rw-r--r--board/omap3/beagle/beagle.c4
-rw-r--r--board/omap3/evm/evm.c19
-rw-r--r--board/omap3/pandora/pandora.c8
-rw-r--r--board/omap3/zoom2/zoom2.c13
-rw-r--r--board/sc3/init.S3
-rw-r--r--board/w7o/init.S2
-rw-r--r--common/cmd_sf.c2
-rw-r--r--common/env_common.c5
-rw-r--r--common/env_dataflash.c1
-rw-r--r--common/env_flash.c1
-rw-r--r--common/env_mgdisk.c1
-rw-r--r--common/env_nand.c1
-rw-r--r--common/env_nowhere.c1
-rw-r--r--common/env_nvram.c1
-rw-r--r--common/env_sf.c12
-rw-r--r--common/exports.c8
-rw-r--r--common/fdt_support.c4
-rw-r--r--common/hush.c2
-rw-r--r--cpu/arm920t/at91rm9200/lowlevel_init.S14
-rw-r--r--cpu/arm926ejs/at91/lowlevel_init.S2
-rw-r--r--cpu/arm926ejs/mx27/generic.c16
-rw-r--r--cpu/arm_cortexa8/config.mk3
-rw-r--r--cpu/arm_cortexa8/omap3/board.c16
-rw-r--r--cpu/arm_cortexa8/omap3/clock.c14
-rw-r--r--cpu/arm_cortexa8/omap3/lowlevel_init.S8
-rw-r--r--cpu/arm_cortexa8/omap3/mem.c56
-rw-r--r--cpu/arm_cortexa8/omap3/sys_info.c13
-rw-r--r--cpu/arm_cortexa8/omap3/timer.c2
-rw-r--r--cpu/i386/serial.c3
-rw-r--r--cpu/ixp/npe/miiphy.c2
-rw-r--r--cpu/mcf5227x/Makefile2
-rw-r--r--cpu/mcf5227x/cpu_init.c53
-rw-r--r--cpu/mcf5227x/dspi.c261
-rw-r--r--cpu/mcf52x2/config.mk4
-rw-r--r--cpu/mcf52x2/cpu.c66
-rw-r--r--cpu/mcf52x2/cpu_init.c89
-rw-r--r--cpu/mcf52x2/interrupts.c8
-rw-r--r--cpu/mcf52x2/speed.c13
-rw-r--r--cpu/mcf52x2/start.S33
-rw-r--r--cpu/mcf5445x/Makefile2
-rw-r--r--cpu/mcf5445x/cpu_init.c66
-rw-r--r--cpu/mcf5445x/dspi.c239
-rw-r--r--cpu/mcf5445x/start.S79
-rw-r--r--cpu/ppc4xx/4xx_pci.c2
-rw-r--r--cpu/ppc4xx/4xx_uart.c3
-rw-r--r--cpu/ppc4xx/cpu.c23
-rw-r--r--cpu/ppc4xx/miiphy.c2
-rw-r--r--cpu/ppc4xx/start.S2
-rw-r--r--disk/part_dos.c15
-rw-r--r--disk/part_efi.c2
-rw-r--r--disk/part_iso.c15
-rw-r--r--drivers/i2c/kirkwood_i2c.c1
-rw-r--r--drivers/mmc/Makefile1
-rw-r--r--drivers/mmc/mxcmmc.c522
-rw-r--r--drivers/mtd/nand/omap_gpmc.c41
-rw-r--r--drivers/mtd/spi/Makefile1
-rw-r--r--drivers/mtd/spi/eeprom_m95xxx.c117
-rw-r--r--drivers/net/4xx_enet.c2
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/e1000.c3096
-rw-r--r--drivers/net/e1000.h837
-rw-r--r--drivers/net/ftmac100.c278
-rw-r--r--drivers/net/ftmac100.h154
-rw-r--r--drivers/net/kirkwood_egiga.c15
-rw-r--r--drivers/net/phy/mv88e61xx.c23
-rw-r--r--drivers/qe/uec.c17
-rw-r--r--drivers/qe/uec_phy.c36
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/cf_spi.c357
-rw-r--r--drivers/video/bus_vcxk.c1
-rw-r--r--examples/standalone/Makefile2
-rw-r--r--include/405_mal.h2
-rw-r--r--include/_exports.h14
-rw-r--r--include/asm-arm/arch-kirkwood/gpio.h2
-rw-r--r--include/asm-arm/arch-mx27/mxcmmc.h25
-rw-r--r--include/asm-arm/arch-omap3/cpu.h476
-rw-r--r--include/asm-arm/arch-omap3/mem.h4
-rw-r--r--include/asm-arm/arch-omap3/omap3.h8
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h2
-rw-r--r--include/asm-m68k/coldfire/dspi.h229
-rw-r--r--include/asm-m68k/immap.h29
-rw-r--r--include/asm-m68k/immap_520x.h212
-rw-r--r--include/asm-m68k/m520x.h358
-rw-r--r--include/asm-ppc/processor.h2
-rw-r--r--include/configs/M5208EVBE.h223
-rw-r--r--include/configs/M52277EVB.h26
-rw-r--r--include/configs/M53017EVB.h7
-rw-r--r--include/configs/M54451EVB.h73
-rw-r--r--include/configs/M54455EVB.h27
-rw-r--r--include/configs/MPC8536DS.h1
-rw-r--r--include/configs/MPC8544DS.h1
-rw-r--r--include/configs/MPC8572DS.h1
-rw-r--r--include/configs/P2020DS.h1
-rw-r--r--include/configs/amcc-common.h13
-rw-r--r--include/configs/at91rm9200dk.h5
-rw-r--r--include/configs/at91rm9200ek.h5
-rw-r--r--include/configs/cmc_pu2.h5
-rw-r--r--include/configs/csb637.h5
-rw-r--r--include/configs/digsy_mtc.h120
-rw-r--r--include/configs/m501sk.h5
-rw-r--r--include/configs/mp2usb.h5
-rw-r--r--include/configs/omap3_beagle.h3
-rw-r--r--include/configs/omap3_evm.h3
-rw-r--r--include/configs/omap3_overo.h3
-rw-r--r--include/configs/omap3_pandora.h3
-rw-r--r--include/configs/omap3_zoom1.h3
-rw-r--r--include/configs/omap3_zoom2.h3
-rw-r--r--include/configs/sheevaplug.h1
-rw-r--r--include/exports.h3
-rw-r--r--include/miiphy.h2
-rw-r--r--include/net.h2
-rw-r--r--include/netdev.h1
-rw-r--r--include/pci_ids.h22
-rw-r--r--include/ppc405.h2
-rw-r--r--include/ppc440.h7
-rw-r--r--include/ppc4xx.h2
-rw-r--r--include/ppc4xx_enet.h2
-rw-r--r--lib_arm/_ashldi3.S2
-rw-r--r--lib_arm/_ashrdi3.S2
-rw-r--r--lib_arm/_divsi3.S2
-rw-r--r--lib_arm/_lshrdi3.S2
-rw-r--r--lib_arm/_udivsi3.S34
-rw-r--r--lib_generic/lzma/LzmaDec.c2
-rw-r--r--lib_generic/lzma/LzmaTools.c1
-rw-r--r--lib_generic/lzma/Makefile2
-rw-r--r--lib_m68k/board.c2
-rw-r--r--nand_spl/board/amcc/canyonlands/ddr2_fixed.c79
-rw-r--r--net/Makefile2
-rw-r--r--net/bootp.c81
-rw-r--r--net/eth.c56
-rw-r--r--net/net.c80
-rw-r--r--net/nfs.c42
-rw-r--r--net/rarp.c4
-rw-r--r--net/sntp.c6
-rw-r--r--net/tftp.c23
159 files changed, 8561 insertions, 2044 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 31955fe37..4b8d1328e 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,927 @@
+commit 53cc18c71b2b920cca171874c6663e274fa80556
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Aug 10 10:38:34 2009 +0200
+
+ Minor coding style cleanup.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit d371708a1beda0f529756e614af785b30461379e
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Aug 10 09:59:10 2009 +0200
+
+ net/tftp.c: fix warning: pointer targets differ in signedness
+
+ tftp.c:294: warning: pointer targets in passing argument 1 of 'strlen'
+ differ in signedness
+
+ This was only visible for the utx8245 board which seems to have DEBUG
+ enabled.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 3ed9e943fdfe51174b23989d48563b8c1b7d2ea8
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sat Aug 8 16:06:47 2009 +0200
+
+ ARM Cortex A8: Remove bogus config.mk entries
+
+ Remove bogus config.mk entry, fix newline and remove redundant
+ omap3/config.mk
+
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit cd3dcba1422d3441503251fbc69cf2437c440781
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sat Aug 8 12:46:09 2009 +0200
+
+ OMAP3: Fix missing GPMC_CONFIG_CS0_BASE
+
+ Applying two indepenent OMAP3 patches resulted in missing
+ GPMC_CONFIG_CS0_BASE. Patch "omap3: embedd gpmc_cs into gpmc
+ config struct" removes GPMC_CONFIG_CS0_BASE, independent patch
+ "omap3: bug fix for NOR boot support" introduces it's usage.
+ Re-introduce GPMC_CONFIG_CS0_BASE.
+
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit ba3dbaf281130029ecb970a922551902c1d80b50
+Author: Ilya Yanok <yanok@emcraft.com>
+Date: Mon Jun 8 04:12:49 2009 +0400
+
+ mxc-mmc: sdhc host driver for MX2 and MX3 proccessor
+
+ This is a port of Linux driver for SDHC host controller hardware
+ found on Freescale's MX2 and MX3 processors. Uses new generic MMC
+ framework (CONFIG_GENERIC_MMC) and it looks like there are some
+ problems with a framework (at least on LE cpus). Some of these
+ problems are addressed in the following patches.
+
+ Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+
+commit 642d7b63c343633dcafc4e23a20e32604a05ff13
+Author: Alessandro Rubini <rubini-list@gnudd.com>
+Date: Fri Aug 7 12:35:47 2009 +0200
+
+ kirkwood/gpio.h: remove duplicate definition
+
+ Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
+
+commit 3ac374c0f0b7d856f1a43317a286f2079106bd6a
+Author: Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Date: Fri Aug 7 12:37:36 2009 +0200
+
+ Add driver for the ST M95xxx SPI EEPROM
+
+ This chip is used in a number of boards manufactured by Calao-Systems
+ which should be supported soon. This driver provides the necessary
+ spi_read and spi_write functions necessary to communicate with the chip.
+
+ Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
+
+commit 30951960bae9a2c33e324a7165962a082e913f9e
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Fri Aug 7 22:27:32 2009 +0530
+
+ arm: Sheevaplug: Fixed NAND specific warning
+
+ It is recommended to define the macro CONFIG_SYS_64BIT_VSPRINTF
+ for NAND specific warning removal, same is done in this patch
+
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+commit 317734966e763fdee183898c0ed940c9bada2541
+Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
+Date: Fri Aug 7 13:53:20 2009 -0400
+
+ Dual-license IBM code contributions
+
+ It was brought to our attention that U-Boot contains code derived from the
+ IBM OpenBIOS source code originally provided with some of the older PowerPC
+ 4xx development boards. As a result, the original license of this code has
+ been carried in the various files for a number of years in the U-Boot project.
+
+ IBM is dual-licensing the IBM code contributions already present in U-Boot
+ under either the terms of the GNU General Public License version 2, or the
+ original code license already present.
+
+ Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
+
+commit cfd700be9f5ed289fd57a9bd61e266319badcb0d
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Wed Aug 5 09:03:54 2009 -0500
+
+ fdt: Fix fdt_pci_dma_ranges handling of 64-bit ranges
+
+ If the size of a region equal to 4G it can't be represnted in a 32-bit
+ BAR so we should have marked that case as MEM64.
+
+ Additionally bump the number of inbound windows up to 4 to handle the
+ fact that Freescale PPCs that have an implicit window for CCSRBAR.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 59b4d7471c42e955bd9846892a0cc7478171778d
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Aug 6 21:29:59 2009 +0200
+
+ ARM EABI: add new helper functions resp. function names
+
+ The ARM EABI defines new names for GCC helper functions,
+ and GCC seems to need some new functions as well.
+
+ This patch is a minimal-invasive approach to fix problems with EABI
+ conformant tool chains (to be used with "USE_PRIVATE_LIBGCC=yes").
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Tested-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 197324d7d998a791e5137b8176981b4af25220ae
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Wed Aug 5 16:18:44 2009 -0500
+
+ hush: Fix bogus free() call
+
+ An off-by-one error in hush.c resulted in an unintentional free() call
+ every time a command was executed
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit ff27650bb255e2275a212357b78c3b77cbf1d2e9
+Author: Detlev Zundel <dzu@denx.de>
+Date: Wed Aug 5 18:37:45 2009 +0200
+
+ digsy_mtc: Update default environment
+
+ Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit 0b40bd439a33bde9e3cccf1acb5744225d0c6103
+Author: Detlev Zundel <dzu@denx.de>
+Date: Wed Aug 5 18:37:44 2009 +0200
+
+ digsy_mtc: Add delay in SPI transfers to the companion controller.
+
+ While at it, remove initialization of variables which will be set
+ before usage in all cases.
+
+ Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit 0bf00750e082a004e5fb058925622ae72890cc56
+Author: Anatolij Gustschin <agust@denx.de>
+Date: Wed Aug 5 18:37:43 2009 +0200
+
+ digsy_mtc: minor fixes for mtc command help
+
+ Add mtc state subcommand description to the
+ help of mtc command.
+
+ Remove some newlines in description of commands
+ for proper help formating.
+
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 5cc69084189bf49aa99d13d57515be72d1844bdf
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Wed Aug 5 18:37:42 2009 +0200
+
+ digsy_mtc: Add mtc state command.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 716655288a53c95fad203ebf21d0b8ffdc2f7525
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Jul 28 22:35:39 2009 +0200
+
+ Partition support: remove newline from partition name
+
+ Remove bogus newline character that got added to the .name field of
+ the disk_partition_t structure.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 3f1649fb0dfb1e5c8890de154c332c394db5cdb5
+Author: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
+Date: Tue Jul 28 09:33:17 2009 +0200
+
+ Fix LZMA string.h header inclusion issue and remove unused variables.
+
+ Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
+
+commit 1c6232f1e2eae87e0e36d489611eb6891dff21e1
+Author: Jens Scharsig <esw@bus-elektronik.de>
+Date: Mon Jul 27 15:28:42 2009 +0200
+
+ bus_vcxk.c: fix warning: unused variable 'lineptr'
+
+ Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
+
+commit 18304f7675e84252965b4e24cba279071f1da472
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Fri Jul 24 17:51:27 2009 -0400
+
+ env: kill off default_environment_size
+
+ The only environment type that uses this variable is spi flash, and that is
+ only because it is reimplementing the common set_default_env() function.
+ So fix the spi flash code and kill off the default_environment_size in the
+ process.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit bedd8403f77f790e9876578885eab1200ba2f8d8
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Jul 23 16:37:48 2009 -0400
+
+ export SPI functions to standalone apps
+
+ While we're here, fix the broken #ifdef handling in _exports.h.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 3b9043a7c03290c9bdbef03848307263f5f3472c
+Author: Penda Naveen Kumar <pnaveen@ti.com>
+Date: Fri Jul 31 00:06:36 2009 +0530
+
+ omap3: bug fix for NOR boot support
+
+ This patch provides bug fix, when omap3 uses nor boot.
+
+ Signed-off-by: Penda Naveen Kumar<pnaveen@ti.com>
+ Acked-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 61c68ae0b43bb5d6ab32958c45289aa197b1a2d1
+Author: Michael Evans <horse_dung@hotmail.com>
+Date: Mon Jul 13 20:13:45 2009 +0100
+
+ Fix examples for OMAP3 boards...
+
+ The attached patch corrects an error in the examples/Makefile which
+ causes the applications in the examples directory to hang on OMAP3
+ based boards. The current Makefile sets -Ttext during linking to
+ 0x0c100000 which is outside of addressable SDRAM memory. The script
+ corrects the existing ifeq...else...endif logic to look at the VENDOR
+ tag rather than the CPU tag.
+
+ The patch affects the following configs: omap3_beagle_config,
+ omap3_overo_config, omap3_evm_config, omap3_pandora_config,
+ omap3_zoom1_config and omap3_zoom2_config.
+
+ Signed-off-by: Michael Evans <horse_dung@hotmail.com>
+
+ Edited commit message.
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit a3d1421dfd0bb1a729e171f8a093ac837f92cec6
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sat Aug 8 09:30:23 2009 +0200
+
+ omap3: use only fixed-size types inside ctrl_structs
+
+ replace variable types in ctrl_structs for omap3 by those with
+ fixed size (u8, u16, u32).
+ Additional ifndef-protection is needed by examples which do not
+ compile when including asm/types.h
+
+ Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 894113529e3a04871544dde977d6d7adee05d3bf
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sat Aug 8 09:30:22 2009 +0200
+
+ omap3: replace all instances of gpmc config struct by one global
+
+ Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 97a099eaa48d5c762c4f73c52c3090c513b8b877
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sat Aug 8 09:30:21 2009 +0200
+
+ omap3: remove typedefs for configuration structs
+
+ Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit aa0707897c49c330b7d6b8d8362e44f60f224732
+Author: Roy Zang <tie-fei.zang@freescale.com>
+Date: Fri Jul 31 13:34:02 2009 +0800
+
+ Add Intel E1000 PCIE card support
+
+ Based on Intel PRO/1000 Network Driver 7.3.20-k2
+ Add Intel E1000 PCIE card support. The following cards are added:
+ INTEL_82571EB_COPPER
+ INTEL_82571EB_FIBER,
+ INTEL_82571EB_SERDES
+ INTEL_82571EB_QUAD_COPPER
+ INTEL_82571PT_QUAD_COPPER
+ INTEL_82571EB_QUAD_FIBER
+ INTEL_82571EB_QUAD_COPPER_LOWPROFILE
+ INTEL_82571EB_SERDES_DUAL
+ INTEL_82571EB_SERDES_QUAD
+ INTEL_82572EI_COPPER
+ INTEL_82572EI_FIBER
+ INTEL_82572EI_SERDES
+ INTEL_82572EI
+ INTEL_82573E
+ INTEL_82573E_IAMT
+ INTEL_82573L
+ INTEL_82546GB_QUAD_COPPER_KSP3
+ INTEL_80003ES2LAN_COPPER_DPT
+ INTEL_80003ES2LAN_SERDES_DPT
+ INTEL_80003ES2LAN_COPPER_SPT
+ INTEL_80003ES2LAN_SERDES_SPT
+
+ 82571EB_COPPER dual ports,
+ 82572EI single port,
+ 82572EI_COPPER single port PCIE cards
+ and
+ 82545EM_COPPER,
+ 82541GI_LF
+ pci cards are tested on both P2020 board
+ and MPC8544DS board.
+
+ Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 86848a74c3c8eb2f8dd179d039ee604dc45288cf
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Jul 15 21:31:28 2009 -0400
+
+ net: sync env ethaddr to device enetaddr in eth_init()
+
+ In the previous enetaddr refactoring, the assumption with commit 56b555a644
+ was that the eth layer would handle the env -> device enetaddr syncing.
+ This was not the case as eth_initialize() is called only once and the sync
+ occurs there. So make sure the eth_init() function does the env -> device
+ sync with every network init.
+
+ Reported-by: Andrzej Wolski <awolski@poczta.fm>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 0ebf04c607b54a352629dcf7e76b76f1785dae54
+Author: Robin Getz <rgetz@blackfin.uclinux.org>
+Date: Thu Jul 23 03:01:03 2009 -0400
+
+ minor debug cleanups in ./net
+
+ Minor ./net cleanups - no functional changes
+ - change #ifdef DEBUG printf(); #endif to just debug()
+ - changed __FUNCTION__ to __func__
+ - got rid of extra whitespace between function and opening brace
+ - removed unnecessary braces on if statements
+
+ gcc dead code elimination should make this functionally/size equivalent
+ when DEBUG is not defined. (confirmed on Blackfin, with gcc 4.3.3).
+
+ Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 187af954cf7958c24efcf0fd62289bbdb4f1f24e
+Author: Matthias Ludwig <mludwig@ultratronik.de>
+Date: Tue May 19 09:09:31 2009 +0200
+
+ omap3: embedd gpmc_cs into gpmc config struct
+
+ Embedd chip select configuration into struct for gpmc config
+ instead of having it completely separated as suggested by
+ Wolfgang Denk on
+ http://lists.denx.de/pipermail/u-boot/2009-May/052247.html
+
+ Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
+
+commit 06bffc6ea52d4b390843d295d438b2037d12e5fd
+Author: David Brownell <david-b@pacbell.net>
+Date: Thu Jul 16 18:40:55 2009 -0700
+
+ rm9200 lowevel_init: don't touch reserved/readonly registers
+
+ For some reason the AT91rm9200 lowlevel init writes to a bunch of
+ reserved or read-only addresses. All the boards seem to define the
+ value-to-be-written values as zero ... but they shouldn't actually
+ be writing *anything* there.
+
+ No documented erratum justifies these accesses. It looks like maybe
+ some pre-release BDI-2000 setup code has been carried along by cargo
+ cult programming since at least late 2004 (per GIT history).
+
+ Here's a patch disabling what seems to be bogosity. Tested on a
+ csb337; there were no behavioral changes.
+
+ Signed-off-by: David Brownell <david-b@pacbell.net>
+
+ on RM9200ek
+ Tested-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 301b7db88fbdf7d118efb79b371b2527a2c31868
+Author: David Hunter <hunterd42@gmail.com>
+Date: Thu Jul 30 14:32:49 2009 -0700
+
+ pxa: Fix typo in GCDR(x)
+
+ Fix a typo in the GCDR(x) macro. It's a good thing no one was using it.
+
+ Signed-off-by: David Hunter <hunterd42@gmail.com>
+
+commit 3c448e648221879ae0e030e94508b4f9f63b7ab8
+Author: Eric Benard <eric@eukrea.com>
+Date: Sat Jul 18 23:45:15 2009 +0200
+
+ Add AT91SAM9260 to at91's lowlevel_init.S
+
+ Needed for AT91SAM9260 NOR Boot on Eukrea's CPU9260.
+
+ Signed-off-by: Eric Benard <eric@eukrea.com>
+
+commit 56bdfa961242fc6acaeebc800640a12b28db3899
+Author: Dirk Eibach <eibach@gdsys.de>
+Date: Thu Jul 30 09:36:33 2009 +0200
+
+ ppc4xx: Remove check for PPC460EX from CompactCenter
+
+ Signed-off-by: Dirk Eibach <eibach@gdsys.de>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c3fa4f0c8684c862ecd3fb622fab1e17e44e82e1
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Jul 29 08:46:10 2009 +0200
+
+ ppc4xx: Add support for PPC460EX/460GT rev B chip to AMCC Canyonlands
+
+ This patch is based on a diff created by Phong Vo from AMCC.
+
+ Signed-off-by: Phong Vo <pvo@amcc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 89bcc4875007ef6608297dc11e7a0d1fbd9900d2
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Jul 29 08:45:27 2009 +0200
+
+ ppc4xx: Add basic support for AMCC PPC460EX/460GT rev B chips
+
+ This patch is based on a diff created by Phong Vo from AMCC.
+
+ Signed-off-by: Phong Vo <pvo@amcc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 82a7edc7ea8f5fe55fed4ff7e127469569e539c4
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Jul 28 15:12:04 2009 +0200
+
+ ppc4xx: Canyonlands-NAND-boot: Support 2 Crucial 512MByte SODIMM's
+
+ Some Canyonlands boards are equipped with different SODIMM's. This is no
+ problem with the "normal" NOR booting Canyonlands U-Boot, since it
+ automatically detects the SODIMM's via SPD data and correctly configures
+ them. But the NAND booting version is different. Here we only have 4k
+ of image size to completely setup the hardware, including DDR2 setup.
+ So we need to use a fixed DDR2 setup here. This doesn't work for different
+ SODIMM's right now.
+
+ Currently only this Crucial SODIMM is support:
+ CT6464AC667.8FB (dual ranked)
+
+ Now some boards are shipped with this SODIMM:
+ CT6464AC667.4FE (single ranked)
+
+ This patch now supports both SODIMM's by configuring first for the dual
+ ranked DIMM. A quick shows, if this module is really installed. If this test
+ fails, the DDR2 controller is re-configured for the single
+ ranked SODIMM.
+
+ Tested with those SODIMM's:
+
+ CT6464AC667.8FB (dual ranked)
+ CT6464AC667.4FE (single ranked)
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 27dd5f8e1062684f1ba685760409d9b2ab6691bf
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Jul 28 10:56:03 2009 +0200
+
+ ppc4xx: amcc: Move "kernel_addr_r" etc to higher locations (> 16MB)
+
+ This patch moves the load addresses for kernel, fdt and ramdisk to higher
+ addresses (>= 16MB). This enables booting of bigger kernel images (e.g.
+ lockdep enabled).
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 6942efc2be1b90054fa4afa5cda7023469fe08b9
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Jul 28 10:50:32 2009 +0200
+
+ ppc4xx: amcc: Set CONFIG_SYS_BOOTMAPSZ to 16MB for big kernels
+
+ This patch changes CONFIG_SYS_BOOTMAPSZ from 8MB to 16MB which is the
+ initial TLB on 40x PPC's in the Linux kernel. With this change even bigger
+ Linux kernels (> 8MB) can be booted.
+
+ This patch also sets CONFIG_SYS_BOOTM_LEN to 16MB (default 8MB) to enable
+ decompression of bigger images.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4c2e3da82dc2b7f8b39b7f1d57f570e4bc5caa6d
+Author: Kumar Gala <kumar.gala@freescale.com>
+Date: Tue Jul 28 21:49:52 2009 -0500
+
+ Update Freescale copyrights to remove "All Rights Reserved"
+
+ "All Rights Reserved" conflicts with the GPL.
+
+ Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
+
+commit bb4291e62579dbc611e84eaaf973631e0bf129c7
+Author: Alessandro Rubini <rubini@unipv.it>
+Date: Fri Jul 24 11:27:14 2009 +0200
+
+ arm nomadik: add i2c
+
+ Signed-off-by: Alessandro Rubini <rubini@unipv.it>
+ Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
+ Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 60cbfbfd0fbebb4682f10ba96f622bfe17317598
+Author: Alessandro Rubini <rubini@unipv.it>
+Date: Fri Jul 24 11:27:03 2009 +0200
+
+ arm nomadik: add gpio support
+
+ Signed-off-by: Alessandro Rubini <rubini@unipv.it>
+ Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
+ Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 549b98306d897ae5991362d6096a36df50efe686
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Sun Jun 28 12:52:32 2009 -0500
+
+ OMAP3 Remove twl4030 defines
+
+ These defines have been subplanted by the equivelent defines in
+ include/twl4030.h
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+ Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Acked-by: Heiko Schocher <hs@denx.de>
+
+commit fccc0fcaaae5154612f8259365d26d04f204859f
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Sun Jun 28 12:52:31 2009 -0500
+
+ OMAP3 Move twl4030 mmc function
+
+ Because twl4030 now has its own device files, move and rename
+ twl4030_mmc_config.
+
+ twl4030_mmc_config initializes the twl4030 power setting to
+ the mmc device. Because it is in the twl4030 power domain, move
+ it out of drivers/mmc/omap3_mmc.c and into drivers/power/twl4030.c.
+
+ The function was renamed to twl4030_power_mmc_init because all
+ the functions in this file are to have the format
+
+ twl4030_power_<device>_<action>
+
+ In this case the suffix is mmc_init so
+ device : mmc
+ action : init
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+ Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Acked-by: Heiko Schocher <hs@denx.de>
+
+commit 2c15513010493435c78f83202940ac3be11de2c3
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Sun Jun 28 12:52:30 2009 -0500
+
+ OMAP3 Move twl4030 power and led functions
+
+ Because twl4030 now has its own device files, move exiting
+ omap3 power_init_r to a new location.
+
+ power_init_r is the only function in board/omap3/common.
+ It initializes the twl4030 power for the board and enables
+ the led.
+
+ The power part of the the function is moved to twl4030_power_init in
+ drivers/power/twl4030.c The power compilation is conditional on the
+ existing config variable CONFIG_TWL4030_POWER.
+
+ The led part is moved to twl4030_led_init in the new file
+ drivers/misc/twl4030_led.c The led compilation is conditional on
+ the new config variable CONFIG_TWL4030_LED
+
+ The directory board/omap3/common was removed because power_init_r
+ was the only function in it.
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+ Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Acked-by: Heiko Schocher <hs@denx.de>
+
+commit 3cb7a4805fc8fb4c09e4801e1c7d531186f20190
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Jul 28 22:13:52 2009 +0200
+
+ TQM8xx* boards: set larger SMC Rx buffer len
+
+ Commit 2b3f12c2 added support for configurable SMC Rx buffer length on
+ 8xx systems. Enable this feature on TQM8xx* based boards.
+
+ This fixes the problem that pasting text in the middle of a line
+ (i. e. inserting in edit mode) did not work - only the first two
+ characters got inserted, the rest was lost.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 4b7511478b62a539e5b066d19a986b75e5d9a527
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Jul 28 22:07:37 2009 +0200
+
+ Fix ext2load return code
+
+ Make the ext2load command return 0 on success (instead of the file
+ length).
+
+ Also fix output format (get rid of random newlines) and some coding
+ style issues (long lines etc.).
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 56fdaadc124a8ef9ec0fd8ff578233ec3b1137be
+Author: Weirich, Bernhard <Bernhard.Weirich@riedel.net>
+Date: Wed Jun 10 14:00:37 2009 +0200
+
+ ext2: fix inode size and calculations
+
+ Signed-off-by: unsik Kim <donari75@gmail.com>
+ Signed-off-by: Bernhard Weirich <bernhard.weirich@riedel.net>
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Tested-by: Wolfgang Denk <wd@denx.de>
+
+commit cd7826359ee71e8f6f3d68331930ab9cbe1c990e
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Sun Jun 28 12:52:29 2009 -0500
+
+ TWL4030 Add power reset button
+
+ The Zoom2 power reset button is on the top right side of the
+ main board. Press and hold for about to 8 seconds to completely
+ reset the board.
+
+ Some of the beta boards have a hardware problem that prevents
+ using this feature. If is difficult to further characterize the
+ boards that fail. So disable resetting for all beta boards.
+
+ The Zoom1 reset button is the red circle on the top right,
+ front of the board. Press and hold the button for 8 seconds to
+ completely reset the board.
+
+ After analyzing beagle, it was determined that other boards
+ that use the twl4030 for power managment can also make use
+ this function.
+
+ The resetting is done by the power management part of the twl4030.
+ Since there is no existing drivers/power, add one.
+
+ The compilation of power/twl4030.h is controlled by the config
+ variable CONFIG_TWL4030_POWER
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+ Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Acked-by: Heiko Schocher <hs@denx.de>
+
+commit 8966eb4c1c2d894b2a76174ba904c26c5af815b8
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Sun Jun 28 12:52:28 2009 -0500
+
+ TWL4030 Add initial support
+
+ The TWL4030 supplies many peripherals for OMAP3 boards. These include
+ power management, usb and, keyboard.
+
+ The product description is found here:
+
+ http://focus.ti.com/docs/prod/folders/print/tps65950.html
+
+ Product reference document, tps65950.pdf, is found here:
+
+ http://www.ti.com/lit/gpn/tps65950
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+ Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Acked-by: Heiko Schocher <hs@denx.de>
+
+commit 7f79dfb48b7419d5caa1cf932fcff4e2fb7040af
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Sun Jun 28 12:52:27 2009 -0500
+
+ OMAP I2C Fix the sampling clock.
+
+ This problem is seen on Zoom1 and Zoom2 in the startup and
+ when i2c probe is used
+
+ Before :
+
+ In: serial
+ Out: serial
+ Err: serial
+ timed out in wait_for_bb: I2C_STAT=1000
+ timed out in wait_for_bb: I2C_STAT=1000
+ timed out in wait_for_bb: I2C_STAT=1000
+ timed out in wait_for_pin: I2C_STAT=1000
+ I2C read: I/O error
+ timed out in wait_for_bb: I2C_STAT=1000
+ timed out in wait_for_bb: I2C_STAT=1000
+ Die ID #327c00020000000004013ddd05026013
+ Hit any key to stop autoboot: 0
+ OMAP3 Zoom1# i2c probe
+ Valid chip addresses:timed out in wait_for_bb: I2C_STAT=1000
+ 02 03 04 05 06 07 08 09 0A 0B 0C 0D <snip>
+
+ After :
+
+ In: serial
+ Out: serial
+ Err: serial
+ Die ID #327c00020000000004013ddd05026013
+ Hit any key to stop autoboot: 0
+ OMAP3 Zoom1# i2c probe
+ Valid chip addresses: 48 49 4A 4B
+
+ The addresses are for the twl4030.
+
+ The prescalar that converts the function clock to the sampling
+ clock is hardcoded to 0. The reference manual recommends 7
+ if the function clock is 96MHz.
+
+ Instead of just changing the hardcoded values, the prescalar
+ is calculated from the value I2C_IP_CLK.
+
+ The i2c #defines are in kHz. The speed passed into the
+ i2c init routine is in Hz. To be consistent, change the
+ defines to be in Hz.
+
+ The timing calculations are based on what is done in the
+ linux 2.6.30 kernel in drivers/i2c/buses/i2c_omap.c as
+ apposed to what is done in TRM.
+
+ The major variables in the timing caculations are
+ specified as #defines that can be overriden as required.
+
+ The variables and their defaults are
+
+ I2C_IP_CLK SYSTEM_CLOCK_96
+ I2C_INTERNAL_SAMPLING_CLK 19200000
+ I2C_FASTSPEED_SCLL_TRIM 6
+ I2C_FASTSPEED_SCLH_TRIM 6
+ I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
+ I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
+ I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
+ I2C_HIGHSPEED_PHASE_TWO_SCLH I2C_FASTSPEED_SCLH_TRIM
+
+ This was runtime verified on Zoom1, Zoom2, Beagle and Overo.
+ The 400kHz and 3.4M cases were verifed on test Zoom1,
+ Zoom2, Beagle and Overo configurations.
+
+ Testing for omap2 will be done in a second step as Nishanth
+ and Jean-Christophe commented.
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+ Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Acked-by: Heiko Schocher <hs@denx.de>
+
+commit 4ce5a72851ff2960543b125866c6132e0094e1ee
+Author: Heiko Schocher <hs@denx.de>
+Date: Mon Jul 20 09:59:37 2009 +0200
+
+ arm, i2c: added support for the TWSI I2C Interface
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 042d01c72e0ea95731708dd24bb8b6cf42e75c80
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jul 27 09:13:38 2009 +0200
+
+ ppc4xx: Fix problem with NOR range assignment in Canyonlands ft_board_setup
+
+ This patch fixes the problem, that the current fdt board fixup code only
+ set's one range, the one for NOR. By this it's overwriting the already
+ correctly configured values done in __ft_board_setup(). Just remove this
+ now unneeded NOR fixup and all the ranges are correctly defined.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Dirk Eibach <eibach@gdsys.de>
+ Cc: Felix Radensky <felix@embedded-sol.com>
+
+commit 11a1604f8d0a8d936b42f6435d004b4aa33a5d87
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jul 27 07:42:48 2009 +0200
+
+ ppc4xx: Add some NAND-booting bootstrap entries to Kilauea chip_config cmd
+
+ This patch adds some I2C bootstrap setting for NAND booting to the Kilauea
+ chip_config command ("533-nand" and "600-nand").
+
+ Additionally some incorrectly indented lines are fixed.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 5b34691ff87821891375b28ec5bcf5154575a735
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jul 27 07:42:37 2009 +0200
+
+ ppc4xx: Kilauea: Fix SDRAM init in NAND booting version
+
+ DDR2 Auto-calibration needs to be disabled on the NAND booting PPC4xx
+ targets. Otherwise the configured fixed init values for some DDR2
+ controller registers (e.g. RQDC) are not initialized at all resulting
+ in a non working SDRAM.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f3ed3c9b7441cde936d06a1ff7b1490ff0d600e6
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jul 27 10:53:43 2009 +0200
+
+ ppc4xx: Fix Arches DDR2 initialization
+
+ Testing on AMCC Arches with the latest U-Boot version yielded that DDR2
+ initialization is currently broken. U-Boot hangs upon relocation to SDRAM
+ or crashes with random traps. This patch fixes this problem. Arches now
+ uses a different WRDTR and CLKTR default setting than Canyonlands/Glacier.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ab4c62c1ba788bf7f673a985d99a76d9c2fd7eca
+Author: Dirk Eibach <eibach@gdsys.de>
+Date: Mon Jul 27 08:49:48 2009 +0200
+
+ ppc4xx: Add GDsys CompactCenter board support.
+
+ Board support for the Guntermann & Drunck CompactCenter and
+ DevCon-Center.
+ Based on the AMCC Canyonlands board support by Stefan Roese.
+
+ Signed-off-by: Dirk Eibach <eibach@gdsys.de>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c2e49f706ba13213f3c8da3a33e88010214e1997
+Author: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Date: Sat Jul 25 06:19:12 2009 +0200
+
+ mpc83xx: Add esd VME8349 board support
+
+ This patch adds support for the esd VME8349 board equipped with the
+ MPC8349. It's a VME PMC carrier board equipped with the Tundra
+ TSI148 VME-bridge.
+
+ Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit fe613cdd4eb2c5b257a60d8dfb7759742318c28a
+Author: Paul Gortmaker <paul.gortmaker@windriver.com>
+Date: Thu Jul 23 17:10:55 2009 -0400
+
+ sbc8349: combine HRCW flash and u-boot image flash
+
+ Up to this point in time, the sbc8349 board was storing the u-boot
+ image in flash 2x. One for the HRCW value at the beginning of
+ flash (0xff80_0000), and once close to the end of flash (0xfff8_0000)
+ for the actual image that got executed.
+
+ This moves the TEXT_BASE to be the beginning of flash, which makes
+ the second copy of the image redundant, and frees up the flash
+ from the end of the environment storage to the end of the flash
+ device itself.
+
+ Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit be9b56df02168ca97562d6b9ec791136e4cd925a
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Thu Jul 23 14:09:38 2009 -0500
+
+ mpc83xx: CONFIG_83XX_GENERIC_PCI is now synonymous with CONFIG_PCI; remove the former
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 94978e19f31d225b4f7d97c4acbac1ecfaeb8f69
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Jul 27 10:37:37 2009 +0200
+
+ Prepare 2009.08-rc1 (again, after fixing last minute issues).
+
+ Update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit 9689ddcca6e01f3637b4442fa8575f29ef4d7aa3
Author: Wolfgang Denk <wd@denx.de>
Date: Mon Jul 27 10:06:39 2009 +0200
@@ -2568,6 +3492,102 @@ Date: Mon Jun 15 11:51:47 2009 -0500
Cc: Ron Madrid <ron_madrid@sbcglobal.net>
Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
+commit 052c08916532d1d9c2f69eb9229709c7b2fc1f02
+Author: TsiChung Liew <tsicliew@gmail.com>
+Date: Wed Jul 8 07:41:24 2009 +0000
+
+ ColdFire: Update bootargs
+
+ Add a bootargs for M53017EVB and update bootargs
+ for M54451EVB
+
+ Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
+
+commit 6e8d58d36691520f8da74cd948661d28d5a5dc66
+Author: TsiChung Liew <tsicliew@gmail.com>
+Date: Tue Jun 30 14:30:19 2009 +0000
+
+ Command for accessing serial flash update
+
+ Change strtoul number base of argv 3 from 0 to 16
+
+ Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
+
+commit ee0a8462466dd284968536eb57c6eef4be0d6aad
+Author: TsiChung Liew <tsicliew@gmail.com>
+Date: Tue Jun 30 14:18:29 2009 +0000
+
+ ColdFire: Add DSPI support for MCF5227x and MCF5445x
+
+ Remove individual CPU specific DSPI driver.
+ Add required feature for the common DSPI driver in cpu_init and
+ in platform configuration file.
+
+ Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
+
+commit dec61c7851baa72151ef1d3657e7bb3b68907d48
+Author: TsiChung Liew <tsicliew@gmail.com>
+Date: Tue Jun 30 14:09:47 2009 +0000
+
+ Coldfire: Consolidate DSPI driver
+
+ Unify both MCF5227x and MCF5445x DSPI driver in CPU to
+ driver/spi folder for common use.
+
+ Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
+
+commit 11d88b26a68bd4bf98b1c962fde6257a50978231
+Author: TsiChung Liew <tsicliew@gmail.com>
+Date: Fri Jun 12 13:03:34 2009 +0000
+
+ ColdFire: Remove compiler warning messages
+
+ Remove unused variables and printf type mismatch in
+ lib_m68k/board.c
+
+ Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
+
+commit 4567c7bff2503fb1a7c738ff9b9f0bd00d274d9a
+Author: TsiChung Liew <tsicliew@gmail.com>
+Date: Fri Jun 12 11:31:31 2009 +0000
+
+ ColdFire: Fix M53017EVB flash size
+
+ Increase the flash size from 8MB to 16MB
+
+ Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
+
+commit bf9a521529e484b15e8fdb583a607cf7945d2f6b
+Author: TsiChung Liew <tsicliew@gmail.com>
+Date: Fri Jun 12 11:29:00 2009 +0000
+
+ ColdFire: Add M5208EVB and MCF520x CPU support
+
+ Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
+
+commit 709b384b6493d9726dce20663ebe31bf7cab2925
+Author: TsiChung Liew <tsicliew@gmail.com>
+Date: Thu Jun 11 15:39:57 2009 +0000
+
+ ColdFire: Update for M54451EVB
+
+ Update serial boot DRAM's Internal RAM, vector table and DRAM in
+ start.S, serial flash's read status command over SPI and NOR
+ flash.
+
+ Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
+
+commit bbf6bbffcaf694c03504c661e58fbd1aefe5bf64
+Author: TsiChung Liew <tsicliew@gmail.com>
+Date: Thu Jun 11 12:50:05 2009 +0000
+
+ ColdFire: Update configuration file to use flash buffer write
+
+ Update M52277EVB, M53017EVB and M54455EVB platform configuration
+ file to use flash buffer write
+
+ Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
+
commit 7d4450a9773673052fcd7fdf0a4a88c089126ac1
Author: Wolfgang Denk <wd@denx.de>
Date: Sun Jun 14 20:58:53 2009 +0200
diff --git a/MAKEALL b/MAKEALL
index dd0b761fe..edebaead3 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -777,6 +777,7 @@ LIST_coldfire=" \
EB+MCF-EV123 \
EB+MCF-EV123_internal \
idmr \
+ M5208EVBE \
M52277EVB \
M5235EVB \
M5249EVB \
diff --git a/Makefile b/Makefile
index 8096f91f0..329e0f5e6 100644
--- a/Makefile
+++ b/Makefile
@@ -24,7 +24,7 @@
VERSION = 2009
PATCHLEVEL = 08
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
@@ -1993,6 +1993,9 @@ ZPC1900_config: unconfig
## Coldfire
#########################################################################
+M5208EVBE_config : unconfig
+ @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5208evbe freescale
+
M52277EVB_config \
M52277EVB_spansion_config \
M52277EVB_stmicro_config : unconfig
@@ -2097,18 +2100,15 @@ M5373EVB_config : unconfig
@$(MKCONFIG) -a M5373EVB m68k mcf532x m5373evb freescale
M54451EVB_config \
-M54451EVB_spansion_config \
M54451EVB_stmicro_config : unconfig
@case "$@" in \
- M54451EVB_config) FLASH=SPANSION;; \
- M54451EVB_spansion_config) FLASH=SPANSION;; \
+ M54451EVB_config) FLASH=NOR;; \
M54451EVB_stmicro_config) FLASH=STMICRO;; \
esac; \
- if [ "$${FLASH}" = "SPANSION" ] ; then \
- echo "#define CONFIG_SYS_SPANSION_BOOT" >> $(obj)include/config.h ; \
+ if [ "$${FLASH}" = "NOR" ] ; then \
echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54451evb/config.tmp ; \
cp $(obj)board/freescale/m54451evb/u-boot.spa $(obj)board/freescale/m54451evb/u-boot.lds ; \
- $(XECHO) "... with SPANSION boot..." ; \
+ $(XECHO) "... with NOR boot..." ; \
fi; \
if [ "$${FLASH}" = "STMICRO" ] ; then \
echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 5071c8d4e..710a0af82 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -94,13 +94,23 @@ static inline void board_cpld_write(int offset, int data)
out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
}
+#else
+static int pvr_460ex(void)
+{
+ u32 pvr = get_pvr();
+
+ if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
+ (pvr == PVR_460EX_RB))
+ return 1;
+
+ return 0;
+}
#endif /* defined(CONFIG_ARCHES) */
int board_early_init_f(void)
{
#if !defined(CONFIG_ARCHES)
u32 sdr0_cust0;
- u32 pvr = get_pvr();
#endif
/*
@@ -175,7 +185,7 @@ int board_early_init_f(void)
mtdcr(AHB_TOP, 0x8000004B);
mtdcr(AHB_BOT, 0x8000004B);
- if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
+ if (pvr_460ex()) {
/*
* Configure USB-STP pins as alternate and not GPIO
* It seems to be neccessary to configure the STP pins as GPIO
@@ -234,17 +244,16 @@ int get_cpu_num(void)
int checkboard(void)
{
char *s = getenv("serial#");
- u32 pvr = get_pvr();
- if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) {
- printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
- gd->board_type = BOARD_GLACIER;
- } else {
+ if (pvr_460ex()) {
printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
gd->board_type = BOARD_CANYONLANDS_PCIE;
else
gd->board_type = BOARD_CANYONLANDS_SATA;
+ } else {
+ printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
+ gd->board_type = BOARD_GLACIER;
}
switch (gd->board_type) {
@@ -498,7 +507,6 @@ int misc_init_r(void)
{
u32 sdr0_srst1 = 0;
u32 eth_cfg;
- u32 pvr = get_pvr();
u8 val;
/*
@@ -513,7 +521,7 @@ int misc_init_r(void)
/* Set the for 2 RGMII mode */
/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
- if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
+ if (pvr_460ex())
eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
else
eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S
index 4b6b3f400..d700ea76c 100644
--- a/board/cray/L1/init.S
+++ b/board/cray/L1/init.S
@@ -1,5 +1,9 @@
/*------------------------------------------------------------------------------+ */
/* */
+/* This source code is dual-licensed. You may use it under the terms */
+/* of the GNU General Public License version 2, or under the license */
+/* below. */
+/* */
/* This source code has been made available to you by IBM on an AS-IS */
/* basis. Anyone receiving this source is licensed under IBM */
/* copyrights to use it in any way he or she deems fit, including */
diff --git a/board/csb272/init.S b/board/csb272/init.S
index ab371f20d..1cfef376a 100644
--- a/board/csb272/init.S
+++ b/board/csb272/init.S
@@ -1,4 +1,6 @@
/******************************************************************************
+ * This source code is dual-licensed. You may use it under the terms of the
+ * GNU General Public License version 2, or under the license below.
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
diff --git a/board/csb472/init.S b/board/csb472/init.S
index 4b6958aef..2cf8afc49 100644
--- a/board/csb472/init.S
+++ b/board/csb472/init.S
@@ -1,4 +1,6 @@
/******************************************************************************
+ * This source code is dual-licensed. You may use it under the terms of the
+ * GNU General Public License version 2, or under the license below.
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
diff --git a/board/davinci/dm355evm/dm355evm.c b/board/davinci/dm355evm/dm355evm.c
index 398f52775..0a4474832 100644
--- a/board/davinci/dm355evm/dm355evm.c
+++ b/board/davinci/dm355evm/dm355evm.c
@@ -23,7 +23,8 @@
#include <asm/arch/emif_defs.h>
#include <asm/arch/nand_defs.h>
#include "../common/misc.h"
-
+#include <net.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -79,6 +80,13 @@ int board_init(void)
return 0;
}
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
+
#ifdef CONFIG_NAND_DAVINCI
static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip)
diff --git a/board/digsy_mtc/cmd_mtc.c b/board/digsy_mtc/cmd_mtc.c
index 2ecb4f8c3..aa3961153 100644
--- a/board/digsy_mtc/cmd_mtc.c
+++ b/board/digsy_mtc/cmd_mtc.c
@@ -44,6 +44,19 @@ static const char *led_names[] = {
""
};
+static int msp430_xfer(const void *dout, void *din)
+{
+ int err;
+
+ err = spi_xfer(NULL, MTC_TRANSFER_SIZE, dout, din,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+
+ /* The MSP chip needs time to ready itself for the next command */
+ udelay(1000);
+
+ return err;
+}
+
static void mtc_calculate_checksum(tx_msp_cmd *packet)
{
int i;
@@ -59,7 +72,7 @@ static int do_mtc_led(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
tx_msp_cmd pcmd;
rx_msp_cmd prx;
- int err = 0;
+ int err;
int i;
if (argc < 2) {
@@ -102,8 +115,7 @@ static int do_mtc_led(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
pcmd.cmd_val2 = 0;
mtc_calculate_checksum(&pcmd);
- err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
- SPI_XFER_BEGIN | SPI_XFER_END);
+ err = msp430_xfer(&pcmd, &prx);
return err;
}
@@ -112,7 +124,7 @@ static int do_mtc_key(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
tx_msp_cmd pcmd;
rx_msp_cmd prx;
- int err = 0;
+ int err;
memset(&pcmd, 0, sizeof(pcmd));
memset(&prx, 0, sizeof(prx));
@@ -120,8 +132,7 @@ static int do_mtc_key(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
pcmd.cmd = CMD_GET_VIM;
mtc_calculate_checksum(&pcmd);
- err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
- SPI_XFER_BEGIN | SPI_XFER_END);
+ err = msp430_xfer(&pcmd, &prx);
if (!err) {
/* function returns '0' if key is pressed */
@@ -135,7 +146,7 @@ static int do_mtc_digout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
tx_msp_cmd pcmd;
rx_msp_cmd prx;
- int err = 0;
+ int err;
uchar channel_mask = 0;
if (argc < 3) {
@@ -155,8 +166,7 @@ static int do_mtc_digout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
pcmd.user_out = channel_mask;
mtc_calculate_checksum(&pcmd);
- err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
- SPI_XFER_BEGIN | SPI_XFER_END);
+ err = msp430_xfer(&pcmd, &prx);
return err;
}
@@ -165,7 +175,7 @@ static int do_mtc_digin(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
tx_msp_cmd pcmd;
rx_msp_cmd prx;
- int err = 0;
+ int err;
uchar channel_num = 0;
if (argc < 2) {
@@ -185,8 +195,7 @@ static int do_mtc_digin(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
pcmd.cmd = CMD_GET_VIM;
mtc_calculate_checksum(&pcmd);
- err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
- SPI_XFER_BEGIN | SPI_XFER_END);
+ err = msp430_xfer(&pcmd, &prx);
if (!err) {
/* function returns '0' when digin is on */
@@ -213,8 +222,8 @@ static int do_mtc_appreg(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
pcmd.cmd_val2 = 0; /* =0 means read appreg */
mtc_calculate_checksum(&pcmd);
- err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
- SPI_XFER_BEGIN | SPI_XFER_END);
+ err = msp430_xfer(&pcmd, &prx);
+
if (!err) {
sprintf(buf, "%d", prx.ack2);
setenv("appreg", buf);
@@ -227,7 +236,7 @@ static int do_mtc_version(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
tx_msp_cmd pcmd;
rx_msp_cmd prx;
- int err = 0;
+ int err;
memset(&pcmd, 0, sizeof(pcmd));
memset(&prx, 0, sizeof(prx));
@@ -235,8 +244,7 @@ static int do_mtc_version(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
pcmd.cmd = CMD_FW_VERSION;
mtc_calculate_checksum(&pcmd);
- err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
- SPI_XFER_BEGIN | SPI_XFER_END);
+ err = msp430_xfer(&pcmd, &prx);
if (!err) {
printf("FW V%d.%d.%d / HW %d\n",
@@ -246,6 +254,33 @@ static int do_mtc_version(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return err;
}
+static int do_mtc_state(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ tx_msp_cmd pcmd;
+ rx_msp_cmd prx;
+ int err;
+
+ memset(&pcmd, 0, sizeof(pcmd));
+ memset(&prx, 0, sizeof(prx));
+
+ pcmd.cmd = CMD_WD_WDSTATE;
+ pcmd.cmd_val2 = 1;
+
+ mtc_calculate_checksum(&pcmd);
+ err = msp430_xfer(&pcmd, &prx);
+
+ if (!err) {
+ printf("State %02Xh\n", prx.state);
+ printf("Input %02Xh\n", prx.input);
+ printf("UserWD %02Xh\n", prx.ack2);
+ printf("Sys WD %02Xh\n", prx.ack3);
+ printf("WD Timout %02Xh\n", prx.ack0);
+ printf("eSysState %02Xh\n", prx.ack1);
+ }
+
+ return err;
+}
+
static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
cmd_tbl_t cmd_mtc_sub[] = {
@@ -256,17 +291,19 @@ cmd_tbl_t cmd_mtc_sub[] = {
" - state: off red green orange\n"
" - blink: blink interval in 100ms steps (1 - 10; 0 = static)\n"),
U_BOOT_CMD_MKENT(key, 0, 1, do_mtc_key,
- "returns state of user key\n", ""),
+ "returns state of user key", ""),
U_BOOT_CMD_MKENT(version, 0, 1, do_mtc_version,
- "returns firmware version of supervisor uC\n", ""),
+ "returns firmware version of supervisor uC", ""),
U_BOOT_CMD_MKENT(appreg, 0, 1, do_mtc_appreg,
- "reads appreg value and stores in environment variable 'appreg'\n", ""),
+ "reads appreg value and stores in environment variable 'appreg'", ""),
U_BOOT_CMD_MKENT(digin, 1, 1, do_mtc_digin,
"returns state of digital input",
"<channel_num> - get state of digital input (1 or 2)\n"),
U_BOOT_CMD_MKENT(digout, 2, 1, do_mtc_digout,
"sets digital outputs",
"<on|off> <on|off>- set state of digital output 1 and 2\n"),
+ U_BOOT_CMD_MKENT(state, 0, 1, do_mtc_state,
+ "displays state", ""),
U_BOOT_CMD_MKENT(help, 4, 1, do_mtc_help, "get help",
"[command] - get help for command\n"),
};
@@ -333,7 +370,7 @@ int cmd_mtc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(mtc, 5, 1, cmd_mtc,
- "mtc - special commands for digsyMTC\n",
+ "special commands for digsyMTC",
"[subcommand] [args...]\n"
"Subcommands list:\n"
"led [ledname] [state] [blink] - set state of leds\n"
@@ -346,5 +383,6 @@ U_BOOT_CMD(mtc, 5, 1, cmd_mtc,
" 'appreg'\n"
"digin [channel] - returns state of digital input (1 or 2)\n"
"digout <on|off> <on|off> - sets state of two digital outputs\n"
+ "state - displays state\n"
"help [subcommand] - get help for subcommand\n"
);
diff --git a/board/digsy_mtc/cmd_mtc.h b/board/digsy_mtc/cmd_mtc.h
index db3aeed51..81714e34d 100644
--- a/board/digsy_mtc/cmd_mtc.h
+++ b/board/digsy_mtc/cmd_mtc.h
@@ -27,6 +27,7 @@
#define CMD_MTC_H
#define CMD_WD_PARA 0x02
+#define CMD_WD_WDSTATE 0x04
#define CMD_FW_VERSION 0x10
#define CMD_GET_VIM 0x30
#define CMD_SET_LED 0x40
diff --git a/board/eric/init.S b/board/eric/init.S
index 2304cc7bb..4820dd08c 100644
--- a/board/eric/init.S
+++ b/board/eric/init.S
@@ -1,5 +1,9 @@
/*------------------------------------------------------------------------------+ */
/* */
+/* This source code is dual-licensed. You may use it under the terms */
+/* of the GNU General Public License version 2, or under the license */
+/* below. */
+/* */
/* This source code has been made available to you by IBM on an AS-IS */
/* basis. Anyone receiving this source is licensed under IBM */
/* copyrights to use it in any way he or she deems fit, including */
diff --git a/board/esd/pci405/writeibm.S b/board/esd/pci405/writeibm.S
index 9f5c35b58..4e319c192 100644
--- a/board/esd/pci405/writeibm.S
+++ b/board/esd/pci405/writeibm.S
@@ -1,5 +1,9 @@
/*------------------------------------------------------------------------------+ */
/* */
+/* This source code is dual-licensed. You may use it under the terms */
+/* of the GNU General Public License version 2, or under the license */
+/* below. */
+/* */
/* This source code has been made available to you by IBM on an AS-IS */
/* basis. Anyone receiving this source is licensed under IBM */
/* copyrights to use it in any way he or she deems fit, including */
diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S
index 760835aab..cb5487461 100644
--- a/board/exbitgen/init.S
+++ b/board/exbitgen/init.S
@@ -1,4 +1,6 @@
/*----------------------------------------------------------------------+
+ * This source code is dual-licensed. You may use it under the terms of
+ * the GNU General Public License version 2, or under the license below.
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
diff --git a/board/freescale/m5208evbe/Makefile b/board/freescale/m5208evbe/Makefile
new file mode 100644
index 000000000..981763d20
--- /dev/null
+++ b/board/freescale/m5208evbe/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm_cortexa8/omap3/config.mk b/board/freescale/m5208evbe/config.mk
index 5fbec7a1b..ce014edca 100644
--- a/cpu/arm_cortexa8/omap3/config.mk
+++ b/board/freescale/m5208evbe/config.mk
@@ -1,6 +1,7 @@
#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -20,17 +21,5 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
- -msoft-float
-# Make ARMv5 to allow more compilers to work, even though its v7a.
-PLATFORM_CPPFLAGS += -march=armv5
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
- $(call cc-option,-malignment-traps,))
+TEXT_BASE = 0
diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c
new file mode 100644
index 000000000..5f99e2f24
--- /dev/null
+++ b/board/freescale/m5208evbe/m5208evbe.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale M5208EVBe\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ u32 dramsize, i;
+
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+
+ sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+#ifdef CONFIG_SYS_SDRAM_BASE1
+ sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+#endif
+ sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+ sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+
+ udelay(500);
+
+ /* Issue PALL */
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ asm("nop");
+
+ /* Perform two refresh cycles */
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ asm("nop");
+
+ /* Issue LEMR */
+ sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ asm("nop");
+ sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+ asm("nop");
+
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ asm("nop");
+
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ asm("nop");
+
+ udelay(100);
+
+ return dramsize;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/freescale/m5208evbe/u-boot.lds b/board/freescale/m5208evbe/u-boot.lds
new file mode 100644
index 000000000..bc9d5cd0d
--- /dev/null
+++ b/board/freescale/m5208evbe/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mcf52x2/start.o (.text)
+ cpu/mcf52x2/libmcf52x2.a (.text)
+ lib_m68k/libm68k.a (.text)
+ common/dlmalloc.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m54451evb/u-boot.spa b/board/freescale/m54451evb/u-boot.spa
index 08e184c1e..d8caefad6 100644
--- a/board/freescale/m54451evb/u-boot.spa
+++ b/board/freescale/m54451evb/u-boot.spa
@@ -56,10 +56,13 @@ SECTIONS
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf5445x/start.o (.text)
- lib_m68k/traps.o (.text)
- lib_m68k/interrupts.o (.text)
+ cpu/mcf5445x/libmcf5445x.a (.text)
+ lib_m68k/libm68k.a (.text)
+ common/cmd_flash.o (.text)
common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
+ common/main.o (.text)
+ common/image.o (.text)
+ lib_generic/libgeneric.a (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
diff --git a/board/gdsys/compactcenter/compactcenter.c b/board/gdsys/compactcenter/compactcenter.c
index 477ef7005..f448ef937 100644
--- a/board/gdsys/compactcenter/compactcenter.c
+++ b/board/gdsys/compactcenter/compactcenter.c
@@ -41,8 +41,6 @@ DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
- u32 pvr = get_pvr();
-
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
@@ -95,16 +93,14 @@ int board_early_init_f(void)
mtdcr(AHB_TOP, 0x8000004B);
mtdcr(AHB_BOT, 0x8000004B);
- if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
- /*
- * Configure USB-STP pins as alternate and not GPIO
- * It seems to be neccessary to configure the STP pins as GPIO
- * input at powerup (perhaps while USB reset is asserted). So
- * we configure those pins to their "real" function now.
- */
- gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
- gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
- }
+ /*
+ * Configure USB-STP pins as alternate and not GPIO
+ * It seems to be neccessary to configure the STP pins as GPIO
+ * input at powerup (perhaps while USB reset is asserted). So
+ * we configure those pins to their "real" function now.
+ */
+ gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+ gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
/* Trigger board component reset */
out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
@@ -250,7 +246,6 @@ int misc_init_r(void)
{
u32 sdr0_srst1 = 0;
u32 eth_cfg;
- u32 pvr = get_pvr();
/*
* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
@@ -264,10 +259,7 @@ int misc_init_r(void)
/* Set the for 2 RGMII mode */
/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
- if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
- eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
- else
- eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+ eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
mtsdr(SDR0_ETH_CFG, eth_cfg);
/*
diff --git a/board/jse/init.S b/board/jse/init.S
index c564ed3c9..7b932b25f 100644
--- a/board/jse/init.S
+++ b/board/jse/init.S
@@ -1,5 +1,9 @@
/*------------------------------------------------------------------------+ */
/* */
+/* This source code is dual-licensed. You may use it under the terms */
+/* of the GNU General Public License version 2, or under the license */
+/* below. */
+/* */
/* This source code has been made available to you by IBM on an AS-IS */
/* basis. Anyone receiving this source is licensed under IBM */
/* copyrights to use it in any way he or she deems fit, including */
diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c
index b773c1a36..0dcacb9f1 100644
--- a/board/mimc/mimc200/mimc200.c
+++ b/board/mimc/mimc200/mimc200.c
@@ -38,7 +38,7 @@
vidinfo_t panel_info = {
.vl_col = 480, /* Number of columns */
.vl_row = 272, /* Number of rows */
- .vl_clk = 10000000, /* pixel clock in ps */
+ .vl_clk = 5000000, /* pixel clock in ps */
.vl_sync = ATMEL_LCDC_INVCLK_INVERTED |
ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c
index bfd642892..e0ba620d1 100644
--- a/board/mpl/common/pci.c
+++ b/board/mpl/common/pci.c
@@ -1,4 +1,6 @@
/*-----------------------------------------------------------------------------+
+| This source code is dual-licensed. You may use it under the terms of
+| the GNU General Public License version 2, or under the license below.
|
| This source code has been made available to you by IBM on an AS-IS
| basis. Anyone receiving this source is licensed under IBM
diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S
index f00a871df..19d922051 100644
--- a/board/mpl/mip405/init.S
+++ b/board/mpl/mip405/init.S
@@ -1,4 +1,6 @@
/*------------------------------------------------------------------------------+
+ * This source code is dual-licensed. You may use it under the terms of
+ * the GNU General Public License version 2, or under the license below.
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S
index 838432525..61f37d74f 100644
--- a/board/mpl/pip405/init.S
+++ b/board/mpl/pip405/init.S
@@ -1,4 +1,6 @@
/*------------------------------------------------------------------------------+
+ * This source code is dual-licensed. You may use it under the terms of
+ * the GNU General Public License version 2, or under the license below.
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
diff --git a/board/omap3/beagle/beagle.c b/board/omap3/beagle/beagle.c
index 5423650df..32d501e22 100644
--- a/board/omap3/beagle/beagle.c
+++ b/board/omap3/beagle/beagle.c
@@ -103,8 +103,8 @@ void beagle_identify(void)
*/
int misc_init_r(void)
{
- gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
- gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+ struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
twl4030_power_init();
twl4030_led_init();
diff --git a/board/omap3/evm/evm.c b/board/omap3/evm/evm.c
index bfd2688d7..0718a0830 100644
--- a/board/omap3/evm/evm.c
+++ b/board/omap3/evm/evm.c
@@ -92,18 +92,17 @@ void set_muxconf_regs(void)
*/
static void setup_net_chip(void)
{
- gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE;
- gpmc_csx_t *gpmc_cs5_base = (gpmc_csx_t *)GPMC_CONFIG_CS5_BASE;
- ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
+ struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
/* Configure GPMC registers */
- writel(NET_GPMC_CONFIG1, &gpmc_cs5_base->config1);
- writel(NET_GPMC_CONFIG2, &gpmc_cs5_base->config2);
- writel(NET_GPMC_CONFIG3, &gpmc_cs5_base->config3);
- writel(NET_GPMC_CONFIG4, &gpmc_cs5_base->config4);
- writel(NET_GPMC_CONFIG5, &gpmc_cs5_base->config5);
- writel(NET_GPMC_CONFIG6, &gpmc_cs5_base->config6);
- writel(NET_GPMC_CONFIG7, &gpmc_cs5_base->config7);
+ writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
+ writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
+ writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
+ writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
+ writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
+ writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
+ writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
diff --git a/board/omap3/pandora/pandora.c b/board/omap3/pandora/pandora.c
index 1538efbb2..460ed1235 100644
--- a/board/omap3/pandora/pandora.c
+++ b/board/omap3/pandora/pandora.c
@@ -60,10 +60,10 @@ int board_init(void)
*/
int misc_init_r(void)
{
- gpio_t *gpio1_base = (gpio_t *)OMAP34XX_GPIO1_BASE;
- gpio_t *gpio4_base = (gpio_t *)OMAP34XX_GPIO4_BASE;
- gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
- gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
+ struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE;
+ struct gpio *gpio4_base = (struct gpio *)OMAP34XX_GPIO4_BASE;
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+ struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
twl4030_power_init();
twl4030_led_init();
diff --git a/board/omap3/zoom2/zoom2.c b/board/omap3/zoom2/zoom2.c
index 94a985dcb..d9e2ae502 100644
--- a/board/omap3/zoom2/zoom2.c
+++ b/board/omap3/zoom2/zoom2.c
@@ -50,8 +50,8 @@
* The details of the setting of the serial gpmc setup are not available.
* The values were provided by another party.
*/
-extern void enable_gpmc_config(u32 *gpmc_config, gpmc_csx_t *gpmc_cs_base,
- u32 base, u32 size);
+void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+ u32 size);
static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = {
0x00011000,
@@ -123,19 +123,14 @@ void zoom2_identify(void)
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
- gpmc_csx_t *serial_cs_base;
u32 *gpmc_config;
gpmc_init (); /* in SRAM or SDRAM, finish GPMC */
/* Configure console support on zoom2 */
gpmc_config = gpmc_serial_TL16CP754C;
- serial_cs_base = (gpmc_csx_t *) (GPMC_CONFIG_CS0_BASE +
- (3 * GPMC_CONFIG_WIDTH));
- enable_gpmc_config(gpmc_config,
- serial_cs_base,
- SERIAL_TL16CP754C_BASE,
- GPMC_SIZE_16M);
+ enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[4],
+ SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M);
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM2;
diff --git a/board/sc3/init.S b/board/sc3/init.S
index e7b3c8394..f97a5ea61 100644
--- a/board/sc3/init.S
+++ b/board/sc3/init.S
@@ -4,6 +4,9 @@
* (www.eurodsn.de). It's based on the original IBM source code, so
* this follows:
*
+ * This source code is dual-licensed. You may use it under the terms of the
+ * GNU General Public License version 2, or under the license below.
+ *
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
* copyrights to use it in any way he or she deems fit, including
diff --git a/board/w7o/init.S b/board/w7o/init.S
index 2fd84ba00..902c63113 100644
--- a/board/w7o/init.S
+++ b/board/w7o/init.S
@@ -1,4 +1,6 @@
/******************************************************************************
+ * This source code is dual-licensed. You may use it under the terms of the
+ * GNU General Public License version 2, or under the license below.
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 2d463a8c9..d571f60c0 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -48,7 +48,7 @@ static int do_spi_flash_probe(int argc, char *argv[])
goto usage;
}
if (argc >= 4) {
- mode = simple_strtoul(argv[3], &endp, 0);
+ mode = simple_strtoul(argv[3], &endp, 16);
if (*argv[3] == 0 || *endp != 0)
goto usage;
}
diff --git a/common/env_common.c b/common/env_common.c
index 6be3bb04a..be64d1307 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -139,11 +139,6 @@ uchar default_environment[] = {
"\0"
};
-#if defined(CONFIG_ENV_IS_IN_NAND) /* Environment is in Nand Flash */ \
- || defined(CONFIG_ENV_IS_IN_SPI_FLASH)
-int default_environment_size = sizeof(default_environment);
-#endif
-
void env_crc_update (void)
{
env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE);
diff --git a/common/env_dataflash.c b/common/env_dataflash.c
index fed919e67..27a3bbcca 100644
--- a/common/env_dataflash.c
+++ b/common/env_dataflash.c
@@ -35,7 +35,6 @@ extern int write_dataflash (unsigned long addr_dest, unsigned long addr_src,
unsigned long size);
extern int AT91F_DataflashInit (void);
extern uchar default_environment[];
-/* extern int default_environment_size; */
uchar env_get_char_spec (int index)
diff --git a/common/env_flash.c b/common/env_flash.c
index 00792cd38..b860c48db 100644
--- a/common/env_flash.c
+++ b/common/env_flash.c
@@ -83,7 +83,6 @@ static ulong end_addr_new = CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1;
#endif /* CONFIG_ENV_ADDR_REDUND */
extern uchar default_environment[];
-extern int default_environment_size;
uchar env_get_char_spec (int index)
diff --git a/common/env_mgdisk.c b/common/env_mgdisk.c
index 363ee68c2..b9de1ed0d 100644
--- a/common/env_mgdisk.c
+++ b/common/env_mgdisk.c
@@ -29,7 +29,6 @@
/* references to names in env_common.c */
extern uchar default_environment[];
-extern int default_environment_size;
char * env_name_spec = "MG_DISK";
diff --git a/common/env_nand.c b/common/env_nand.c
index 8052fb79e..ca631af19 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -59,7 +59,6 @@
/* references to names in env_common.c */
extern uchar default_environment[];
-extern int default_environment_size;
char * env_name_spec = "NAND";
diff --git a/common/env_nowhere.c b/common/env_nowhere.c
index 78e8f8eb4..ccc068b8e 100644
--- a/common/env_nowhere.c
+++ b/common/env_nowhere.c
@@ -34,7 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
env_t *env_ptr = NULL;
extern uchar default_environment[];
-extern int default_environment_size;
void env_relocate_spec (void)
diff --git a/common/env_nvram.c b/common/env_nvram.c
index 562edd049..2628fe434 100644
--- a/common/env_nvram.c
+++ b/common/env_nvram.c
@@ -58,7 +58,6 @@ env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR;
char * env_name_spec = "NVRAM";
extern uchar default_environment[];
-extern int default_environment_size;
#ifdef CONFIG_AMIGAONEG3SE
uchar env_get_char_spec (int index)
diff --git a/common/env_sf.c b/common/env_sf.c
index 2f52e2561..6575b6da3 100644
--- a/common/env_sf.c
+++ b/common/env_sf.c
@@ -47,7 +47,6 @@ DECLARE_GLOBAL_DATA_PTR;
/* references to names in env_common.c */
extern uchar default_environment[];
-extern int default_environment_size;
char * env_name_spec = "SPI Flash";
env_t *env_ptr;
@@ -143,16 +142,7 @@ err_probe:
err_crc:
puts("*** Warning - bad CRC, using default environment\n\n");
- if (default_environment_size > CONFIG_ENV_SIZE) {
- gd->env_valid = 0;
- puts("*** Error - default environment is too large\n\n");
- return;
- }
-
- memset(env_ptr, 0, sizeof(env_t));
- memcpy(env_ptr->data, default_environment, default_environment_size);
- env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE);
- gd->env_valid = 1;
+ set_default_env();
}
int env_init(void)
diff --git a/common/exports.c b/common/exports.c
index ec4656bfb..b3b6e1f9c 100644
--- a/common/exports.c
+++ b/common/exports.c
@@ -38,4 +38,12 @@ void jumptable_init (void)
gd->jt[XF_i2c_write] = (void *) i2c_write;
gd->jt[XF_i2c_read] = (void *) i2c_read;
#endif
+#ifdef CONFIG_CMD_SPI
+ gd->jt[XF_spi_init] = (void *) spi_init;
+ gd->jt[XF_spi_setup_slave] = (void *) spi_setup_slave;
+ gd->jt[XF_spi_free_slave] = (void *) spi_free_slave;
+ gd->jt[XF_spi_claim_bus] = (void *) spi_claim_bus;
+ gd->jt[XF_spi_release_bus] = (void *) spi_release_bus;
+ gd->jt[XF_spi_xfer] = (void *) spi_xfer;
+#endif
}
diff --git a/common/fdt_support.c b/common/fdt_support.c
index fc077e829..89164a12d 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -625,7 +625,7 @@ int fdt_resize(void *blob)
}
#ifdef CONFIG_PCI
-#define CONFIG_SYS_PCI_NR_INBOUND_WIN 3
+#define CONFIG_SYS_PCI_NR_INBOUND_WIN 4
#define FDT_PCI_PREFETCH (0x40000000)
#define FDT_PCI_MEM32 (0x02000000)
@@ -655,7 +655,7 @@ int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose) {
size = (u64)hose->regions[r].size;
dma_range[0] = 0;
- if (size > 0x100000000ull)
+ if (size >= 0x100000000ull)
dma_range[0] |= FDT_PCI_MEM64;
else
dma_range[0] |= FDT_PCI_MEM32;
diff --git a/common/hush.c b/common/hush.c
index 97fd07067..528dd254a 100644
--- a/common/hush.c
+++ b/common/hush.c
@@ -2002,7 +2002,7 @@ static int free_pipe(struct pipe *pi, int indent)
#ifndef __U_BOOT__
globfree(&child->glob_result);
#else
- for (a = child->argc;a >= 0;a--) {
+ for (a = 0; a < child->argc; a++) {
free(child->argv[a]);
}
free(child->argv);
diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S
index 0913284e7..d8bb96004 100644
--- a/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ b/cpu/arm920t/at91rm9200/lowlevel_init.S
@@ -81,6 +81,7 @@ LoopOsc:
bne 0b
/* delay - this is all done by guess */
ldr r0, =0x00010000
+ /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
1:
subs r0, r0, #1
bhi 1b
@@ -108,16 +109,6 @@ LoopOsc:
.ltorg
SMRDATA:
- .word AT91C_MC_PUIA
- .word CONFIG_SYS_MC_PUIA_VAL
- .word AT91C_MC_PUP
- .word CONFIG_SYS_MC_PUP_VAL
- .word AT91C_MC_PUER
- .word CONFIG_SYS_MC_PUER_VAL
- .word AT91C_MC_ASR
- .word CONFIG_SYS_MC_ASR_VAL
- .word AT91C_MC_AASR
- .word CONFIG_SYS_MC_AASR_VAL
.word AT91C_EBI_CFGR
.word CONFIG_SYS_EBI_CFGR_VAL
.word AT91C_SMC_CSR0
@@ -128,8 +119,7 @@ SMRDATA:
.word CONFIG_SYS_PLLBR_VAL
.word AT91C_MCKR
.word CONFIG_SYS_MCKR_VAL
- /* SMRDATA is 80 bytes long */
- /* here there's a delay of 100 */
+ /* here there's a delay */
SMRDATA1:
.word AT91C_PIOC_ASR
.word CONFIG_SYS_PIOC_ASR_VAL
diff --git a/cpu/arm926ejs/at91/lowlevel_init.S b/cpu/arm926ejs/at91/lowlevel_init.S
index 5ed518cc2..9962ae9be 100644
--- a/cpu/arm926ejs/at91/lowlevel_init.S
+++ b/cpu/arm926ejs/at91/lowlevel_init.S
@@ -194,7 +194,7 @@ SMRDATA:
.word CONFIG_SYS_PIOD_PPUDR_VAL
.word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
.word CONFIG_SYS_PIOD_PPUDR_VAL
-#elif defined(CONFIG_AT91SAM9261)
+#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261)
.word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR)
.word CONFIG_SYS_PIOC_PDR_VAL1
.word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR)
diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c
index 47fa4b48e..9b4ff0261 100644
--- a/cpu/arm926ejs/mx27/generic.c
+++ b/cpu/arm926ejs/mx27/generic.c
@@ -23,6 +23,9 @@
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
+#ifdef CONFIG_MXC_MMC
+#include <asm/arch/mxcmmc.h>
+#endif
/*
* get the system pll clock in Hz
@@ -169,6 +172,19 @@ int cpu_eth_init(bd_t *bis)
#endif
}
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_MXC_MMC
+ return mxc_mmc_init(bis);
+#else
+ return 0;
+#endif
+}
+
void imx_gpio_mode(int gpio_mode)
{
struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
diff --git a/cpu/arm_cortexa8/config.mk b/cpu/arm_cortexa8/config.mk
index 580559692..3bfe3db20 100644
--- a/cpu/arm_cortexa8/config.mk
+++ b/cpu/arm_cortexa8/config.mk
@@ -30,7 +30,6 @@ PLATFORM_CPPFLAGS += -march=armv5
# Supply options according to compiler version
#
# =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option)
PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
- $(call cc-option,-malignment-traps,)) \ No newline at end of file
+ $(call cc-option,-malignment-traps,))
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index b665ec9ed..233728762 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -59,11 +59,11 @@ static inline void delay(unsigned long loops)
*****************************************************************************/
void secure_unlock_mem(void)
{
- pm_t *pm_rt_ape_base = (pm_t *)PM_RT_APE_BASE_ADDR_ARM;
- pm_t *pm_gpmc_base = (pm_t *)PM_GPMC_BASE_ADDR_ARM;
- pm_t *pm_ocm_ram_base = (pm_t *)PM_OCM_RAM_BASE_ADDR_ARM;
- pm_t *pm_iva2_base = (pm_t *)PM_IVA2_BASE_ADDR_ARM;
- sms_t *sms_base = (sms_t *)OMAP34XX_SMS_BASE;
+ struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
+ struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
+ struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
+ struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
+ struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
/* Protection Module Register Target APE (PM_RT) */
writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
@@ -234,7 +234,7 @@ void s_init(void)
* Routine: wait_for_command_complete
* Description: Wait for posting to finish on watchdog
*****************************************************************************/
-void wait_for_command_complete(watchdog_t *wd_base)
+void wait_for_command_complete(struct watchdog *wd_base)
{
int pending = 1;
do {
@@ -248,8 +248,8 @@ void wait_for_command_complete(watchdog_t *wd_base)
*****************************************************************************/
void watchdog_init(void)
{
- watchdog_t *wd2_base = (watchdog_t *)WD2_BASE;
- prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+ struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
/*
* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c
index 0306b6c06..174c45311 100644
--- a/cpu/arm_cortexa8/omap3/clock.c
+++ b/cpu/arm_cortexa8/omap3/clock.c
@@ -41,10 +41,10 @@
u32 get_osc_clk_speed(void)
{
u32 start, cstart, cend, cdiff, val;
- prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
- prm_t *prm_base = (prm_t *)PRM_BASE;
- gptimer_t *gpt1_base = (gptimer_t *)OMAP34XX_GPT1;
- s32ktimer_t *s32k_base = (s32ktimer_t *)SYNC_32KTIMER_BASE;
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ struct prm *prm_base = (struct prm *)PRM_BASE;
+ struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
+ struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
val = readl(&prm_base->clksrc_ctrl);
@@ -133,8 +133,8 @@ void prcm_init(void)
int xip_safe, p0, p1, p2, p3;
u32 osc_clk = 0, sys_clkin_sel;
u32 clk_index, sil_index = 0;
- prm_t *prm_base = (prm_t *)PRM_BASE;
- prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+ struct prm *prm_base = (struct prm *)PRM_BASE;
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
dpll_param *dpll_param_p;
f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
@@ -341,7 +341,7 @@ void prcm_init(void)
*****************************************************************************/
void per_clocks_enable(void)
{
- prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
/* Enable GP2 timer. */
sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */
diff --git a/cpu/arm_cortexa8/omap3/lowlevel_init.S b/cpu/arm_cortexa8/omap3/lowlevel_init.S
index cf1f927cf..73063ec8e 100644
--- a/cpu/arm_cortexa8/omap3/lowlevel_init.S
+++ b/cpu/arm_cortexa8/omap3/lowlevel_init.S
@@ -135,19 +135,19 @@ _go_to_speed: .word go_to_speed
/* these constants need to be close for PIC code */
/* The Nor has to be in the Flash Base CS0 for this condition to happen */
flash_cfg1_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
+ .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
flash_cfg3_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
+ .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
flash_cfg3_val:
.word STNOR_GPMC_CONFIG3
flash_cfg4_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
+ .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
flash_cfg4_val:
.word STNOR_GPMC_CONFIG4
flash_cfg5_val:
.word STNOR_GPMC_CONFIG5
flash_cfg5_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
+ .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
pll_ctl_add:
.word CM_CLKEN_PLL
pll_div_add1:
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index 3cc22c498..079c84870 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -41,6 +41,8 @@ unsigned int boot_flash_sec;
unsigned int boot_flash_type;
volatile unsigned int boot_flash_env_addr;
+struct gpmc *gpmc_cfg;
+
#if defined(CONFIG_CMD_NAND)
static u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG1,
@@ -51,9 +53,6 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG6, 0
};
-gpmc_csx_t *nand_cs_base;
-gpmc_t *gpmc_cfg_base;
-
#if defined(CONFIG_ENV_IS_IN_NAND)
#define GPMC_CS 0
#else
@@ -72,8 +71,6 @@ static u32 gpmc_onenand[GPMC_MAX_REG] = {
ONENAND_GPMC_CONFIG6, 0
};
-gpmc_csx_t *onenand_cs_base;
-
#if defined(CONFIG_ENV_IS_IN_ONENAND)
#define GPMC_CS 0
#else
@@ -82,7 +79,7 @@ gpmc_csx_t *onenand_cs_base;
#endif
-static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
+static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
/**************************************************************************
* make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
@@ -149,12 +146,12 @@ void sdrc_init(void)
void do_sdrc_init(u32 cs, u32 early)
{
- sdrc_actim_t *sdrc_actim_base;
+ struct sdrc_actim *sdrc_actim_base;
if(cs)
- sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL1_BASE;
+ sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
else
- sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL0_BASE;
+ sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
if (early) {
/* reset sdrc controller */
@@ -195,21 +192,21 @@ void do_sdrc_init(u32 cs, u32 early)
writel(0, &sdrc_base->cs[cs].mcfg);
}
-void enable_gpmc_config(u32 *gpmc_config, gpmc_csx_t *gpmc_cs_base, u32 base,
+void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size)
{
- writel(0, &gpmc_cs_base->config7);
+ writel(0, &cs->config7);
sdelay(1000);
/* Delay for settling */
- writel(gpmc_config[0], &gpmc_cs_base->config1);
- writel(gpmc_config[1], &gpmc_cs_base->config2);
- writel(gpmc_config[2], &gpmc_cs_base->config3);
- writel(gpmc_config[3], &gpmc_cs_base->config4);
- writel(gpmc_config[4], &gpmc_cs_base->config5);
- writel(gpmc_config[5], &gpmc_cs_base->config6);
+ writel(gpmc_config[0], &cs->config1);
+ writel(gpmc_config[1], &cs->config2);
+ writel(gpmc_config[2], &cs->config3);
+ writel(gpmc_config[3], &cs->config4);
+ writel(gpmc_config[4], &cs->config5);
+ writel(gpmc_config[5], &cs->config6);
/* Enable the config */
writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
- (1 << 6)), &gpmc_cs_base->config7);
+ (1 << 6)), &cs->config7);
sdelay(2000);
}
@@ -222,8 +219,7 @@ void gpmc_init(void)
{
/* putting a blanket check on GPMC based on ZeBu for now */
u32 *gpmc_config = NULL;
- gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
- gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
+ gpmc_cfg = (struct gpmc *)GPMC_BASE;
u32 base = 0;
u32 size = 0;
u32 f_off = CONFIG_SYS_MONITOR_LEN;
@@ -231,28 +227,26 @@ void gpmc_init(void)
u32 config = 0;
/* global settings */
- writel(0, &gpmc_base->irqenable); /* isr's sources masked */
- writel(0, &gpmc_base->timeout_control);/* timeout disable */
+ writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
+ writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
- config = readl(&gpmc_base->config);
+ config = readl(&gpmc_cfg->config);
config &= (~0xf00);
- writel(config, &gpmc_base->config);
+ writel(config, &gpmc_cfg->config);
/*
* Disable the GPMC0 config set by ROM code
* It conflicts with our MPDB (both at 0x08000000)
*/
- writel(0, &gpmc_cs_base->config7);
+ writel(0, &gpmc_cfg->cs[0].config7);
sdelay(1000);
#if defined(CONFIG_CMD_NAND) /* CS 0 */
gpmc_config = gpmc_m_nand;
- gpmc_cfg_base = gpmc_base;
- nand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
- (GPMC_CS * GPMC_CONFIG_WIDTH));
+
base = PISMO1_NAND_BASE;
size = PISMO1_NAND_SIZE;
- enable_gpmc_config(gpmc_config, nand_cs_base, base, size);
+ enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
#if defined(CONFIG_ENV_IS_IN_NAND)
f_off = SMNAND_ENV_OFFSET;
f_sec = SZ_128K;
@@ -266,11 +260,9 @@ void gpmc_init(void)
#if defined(CONFIG_CMD_ONENAND)
gpmc_config = gpmc_onenand;
- onenand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
- (GPMC_CS * GPMC_CONFIG_WIDTH));
base = PISMO1_ONEN_BASE;
size = PISMO1_ONEN_SIZE;
- enable_gpmc_config(gpmc_config, onenand_cs_base, base, size);
+ enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
#if defined(CONFIG_ENV_IS_IN_ONENAND)
f_off = ONENAND_ENV_OFFSET;
f_sec = SZ_128K;
diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c
index 2f04cd6d9..765aaf2b3 100644
--- a/cpu/arm_cortexa8/omap3/sys_info.c
+++ b/cpu/arm_cortexa8/omap3/sys_info.c
@@ -32,9 +32,8 @@
#include <i2c.h>
extern omap3_sysinfo sysinfo;
-static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
-static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
-static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
+static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
+static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
static char *rev_s[CPU_3XX_MAX_REV] = {
"1.0",
"2.0",
@@ -47,7 +46,7 @@ static char *rev_s[CPU_3XX_MAX_REV] = {
*****************************************************************/
void dieid_num_r(void)
{
- ctrl_id_t *id_base = (ctrl_id_t *)OMAP34XX_ID_L4_IO_BASE;
+ struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
char *uid_s, die_id[34];
u32 id[4];
@@ -82,7 +81,7 @@ u32 get_cpu_type(void)
u32 get_cpu_rev(void)
{
u32 cpuid = 0;
- ctrl_id_t *id_base;
+ struct ctrl_id *id_base;
/*
* On ES1.0 the IDCODE register is not exposed on L4
@@ -93,7 +92,7 @@ u32 get_cpu_rev(void)
return CPU_3XX_ES10;
else {
/* Decode the IDs on > ES1.0 */
- id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE;
+ id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf;
@@ -160,7 +159,7 @@ u32 get_gpmc0_base(void)
{
u32 b;
- b = readl(&gpmc_cs_base->config7);
+ b = readl(&gpmc_cfg->cs[0].config7);
b &= 0x1F; /* keep base [5:0] */
b = b << 24; /* ret 0x0b000000 */
return b;
diff --git a/cpu/arm_cortexa8/omap3/timer.c b/cpu/arm_cortexa8/omap3/timer.c
index 05cfe763a..12a16b321 100644
--- a/cpu/arm_cortexa8/omap3/timer.c
+++ b/cpu/arm_cortexa8/omap3/timer.c
@@ -37,7 +37,7 @@
static ulong timestamp;
static ulong lastinc;
-static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE;
+static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
/*
* Nothing really to do with interrupts, just starts up a counter.
diff --git a/cpu/i386/serial.c b/cpu/i386/serial.c
index 8b5f8fa11..e7025a3cd 100644
--- a/cpu/i386/serial.c
+++ b/cpu/i386/serial.c
@@ -26,6 +26,9 @@
/*------------------------------------------------------------------------------+ */
/*
+ * This source code is dual-licensed. You may use it under the terms of the
+ * GNU General Public License version 2, or under the license below.
+ *
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
* copyrights to use it in any way he or she deems fit, including
diff --git a/cpu/ixp/npe/miiphy.c b/cpu/ixp/npe/miiphy.c
index 20fee2d39..b208c51ea 100644
--- a/cpu/ixp/npe/miiphy.c
+++ b/cpu/ixp/npe/miiphy.c
@@ -1,4 +1,6 @@
/*-----------------------------------------------------------------------------+
+ | This source code is dual-licensed. You may use it under the terms of the
+ | GNU General Public License version 2, or under the license below.
|
| This source code has been made available to you by IBM on an AS-IS
| basis. Anyone receiving this source is licensed under IBM
diff --git a/cpu/mcf5227x/Makefile b/cpu/mcf5227x/Makefile
index 44f93850e..d0e9b4550 100644
--- a/cpu/mcf5227x/Makefile
+++ b/cpu/mcf5227x/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START = start.o
-COBJS = cpu.o speed.o cpu_init.o interrupts.o dspi.o
+COBJS = cpu.o speed.o cpu_init.o interrupts.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c
index 8945ef316..d8bcf375c 100644
--- a/cpu/mcf5227x/cpu_init.c
+++ b/cpu/mcf5227x/cpu_init.c
@@ -152,3 +152,56 @@ void uart_port_conf(void)
break;
}
}
+
+#ifdef CONFIG_CF_DSPI
+void cfspi_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ gpio->par_dspi =
+ GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK;
+}
+
+int cfspi_claim_bus(uint bus, uint cs)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+ return -1;
+
+ /* Clear FIFO and resume transfer */
+ dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+
+ switch (cs) {
+ case 0:
+ gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_MASK;
+ gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+ break;
+ case 2:
+ gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+ gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
+ break;
+ }
+
+ return 0;
+}
+
+void cfspi_release_bus(uint bus, uint cs)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */
+
+ switch (cs) {
+ case 0:
+ gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+ break;
+ case 2:
+ gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+ break;
+ }
+}
+#endif
diff --git a/cpu/mcf5227x/dspi.c b/cpu/mcf5227x/dspi.c
deleted file mode 100644
index 7f48f9184..000000000
--- a/cpu/mcf5227x/dspi.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- *
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <spi.h>
-#include <malloc.h>
-
-#if defined(CONFIG_CF_DSPI)
-#include <asm/immap.h>
-
-void dspi_init(void)
-{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
- gpio->par_dspi =
- GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK;
-
- dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
- DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
- DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
- DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
-
-#ifdef CONFIG_SYS_DSPI_DCTAR0
- dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR1
- dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR2
- dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR3
- dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR4
- dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR5
- dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR6
- dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR7
- dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
-#endif
-}
-
-void dspi_tx(int chipsel, u8 attrib, u16 data)
-{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
- while ((dspi->dsr & 0x0000F000) >= 4) ;
-
- dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
-}
-
-u16 dspi_rx(void)
-{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
- while ((dspi->dsr & 0x000000F0) == 0) ;
-
- return (dspi->drfr & 0xFFFF);
-}
-
-#if defined(CONFIG_CMD_SPI)
-void spi_init_f(void)
-{
-}
-
-void spi_init_r(void)
-{
-}
-
-void spi_init(void)
-{
- dspi_init();
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- struct spi_slave *slave;
-
- slave = malloc(sizeof(struct spi_slave));
- if (!slave)
- return NULL;
-
- switch (cs) {
- case 0:
- gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
- gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
- break;
- case 2:
- gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
- gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
- break;
- }
-
- slave->bus = bus;
- slave->cs = cs;
-
- return slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- switch (slave->cs) {
- case 0:
- gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
- break;
- case 2:
- gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
- break;
- }
-
- free(slave);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- static int bWrite = 0;
- u8 *spi_rd, *spi_wr;
- int len = bitlen >> 3;
-
- spi_rd = (u8 *) din;
- spi_wr = (u8 *) dout;
-
- /* command handling */
- if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) {
- switch (*spi_wr) {
- case 0x02: /* Page Prog */
- bWrite = 1;
- dspi_tx(slave->cs, 0x80, spi_wr[0]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[1]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[2]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[3]);
- dspi_rx();
- return 0;
- case 0x05: /* Read Status */
- if (len == 4)
- if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
- && (spi_wr[3] == 0xFF)) {
- dspi_tx(slave->cs, 0x80, *spi_wr);
- dspi_rx();
- }
- return 0;
- case 0x06: /* WREN */
- dspi_tx(slave->cs, 0x00, *spi_wr);
- dspi_rx();
- return 0;
- case 0x0B: /* Fast read */
- if ((len == 5) && (spi_wr[4] == 0)) {
- dspi_tx(slave->cs, 0x80, spi_wr[0]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[1]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[2]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[3]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[4]);
- dspi_rx();
- }
- return 0;
- case 0x9F: /* RDID */
- dspi_tx(slave->cs, 0x80, *spi_wr);
- dspi_rx();
- return 0;
- case 0xD8: /* Sector erase */
- if (len == 4)
- if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) {
- dspi_tx(slave->cs, 0x80, spi_wr[0]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[1]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[2]);
- dspi_rx();
- dspi_tx(slave->cs, 0x00, spi_wr[3]);
- dspi_rx();
- }
- return 0;
- }
- }
-
- if (bWrite)
- len--;
-
- while (len--) {
- if (dout != NULL) {
- dspi_tx(slave->cs, 0x80, *spi_wr);
- dspi_rx();
- spi_wr++;
- }
-
- if (din != NULL) {
- dspi_tx(slave->cs, 0x80, 0);
- *spi_rd = dspi_rx();
- spi_rd++;
- }
- }
-
- if (flags == SPI_XFER_END) {
- if (bWrite) {
- dspi_tx(slave->cs, 0x00, *spi_wr);
- dspi_rx();
- bWrite = 0;
- } else {
- dspi_tx(slave->cs, 0x00, 0);
- dspi_rx();
- }
- }
-
- return 0;
-}
-#endif /* CONFIG_CMD_SPI */
-
-#endif /* CONFIG_CF_DSPI */
diff --git a/cpu/mcf52x2/config.mk b/cpu/mcf52x2/config.mk
index 829273617..52751be3e 100644
--- a/cpu/mcf52x2/config.mk
+++ b/cpu/mcf52x2/config.mk
@@ -26,6 +26,7 @@
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5208:=$(shell grep CONFIG_M5208 $(TOPDIR)/include/$(cfg))
is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
@@ -36,6 +37,9 @@ is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
+ifneq (,$(findstring CONFIG_M5208,$(is5208)))
+PLATFORM_CPPFLAGS += -mcpu=5208
+endif
ifneq (,$(findstring CONFIG_M5249,$(is5249)))
PLATFORM_CPPFLAGS += -mcpu=5249
endif
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
index 32d6c40da..2cfe6311d 100644
--- a/cpu/mcf52x2/cpu.c
+++ b/cpu/mcf52x2/cpu.c
@@ -34,6 +34,72 @@
#include <asm/immap.h>
#include <netdev.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_M5208
+int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+
+ udelay(1000);
+
+ rcm->rcr = RCM_RCR_SOFTRST;
+
+ /* we don't return! */
+ return 0;
+};
+
+int checkcpu(void)
+{
+ char buf1[32], buf2[32];
+
+ printf("CPU: Freescale Coldfire MCF5208\n"
+ " CPU CLK %s MHz BUS CLK %s MHz\n",
+ strmhz(buf1, gd->cpu_clk),
+ strmhz(buf2, gd->bus_clk));
+ return 0;
+};
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+ wdt->sr = 0x5555;
+ wdt->sr = 0xAAAA;
+}
+
+int watchdog_disable(void)
+{
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+ wdt->sr = 0x5555; /* reset watchdog counteDECLARE_GLOBAL_DATA_PTR;
+r */
+ wdt->sr = 0xAAAA;
+ wdt->cr = 0; /* disable watchdog timer */
+
+ puts("WATCHDOG:disabled\n");
+ return (0);
+}
+
+int watchdog_init(void)
+{
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+ wdt->cr = 0; /* disable watchdog */
+
+ /* set timeout and enable watchdog */
+ wdt->mr =
+ ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
+ wdt->sr = 0x5555; /* reset watchdog counter */
+ wdt->sr = 0xAAAA;
+
+ puts("WATCHDOG:enabled\n");
+ return (0);
+}
+#endif /* #ifdef CONFIG_WATCHDOG */
+#endif /* #ifdef CONFIG_M5208 */
+
#ifdef CONFIG_M5271
/*
* Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 11f70b0db..7cea6558f 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -101,6 +101,95 @@ void init_fbcs(void)
}
#endif
+#if defined(CONFIG_M5208)
+void cpu_init_f(void)
+{
+ volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+
+#ifndef CONFIG_WATCHDOG
+ volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
+
+ /* Disable the watchdog if we aren't using it */
+ wdg->cr = 0;
+#endif
+
+ scm1->mpr = 0x77777777;
+ scm1->pacra = 0;
+ scm1->pacrb = 0;
+ scm1->pacrc = 0;
+ scm1->pacrd = 0;
+ scm1->pacre = 0;
+ scm1->pacrf = 0;
+
+ /* FlexBus Chipselect */
+ init_fbcs();
+
+ icache_enable();
+}
+
+/* initialize higher level parts of CPU like timers */
+int cpu_init_r(void)
+{
+ return (0);
+}
+
+void uart_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ /* Setup Ports: */
+ switch (CONFIG_SYS_UART_PORT) {
+ case 0:
+ gpio->par_uart &= GPIO_PAR_UART0_MASK;
+ gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+ break;
+ case 1:
+ gpio->par_uart &= GPIO_PAR_UART0_MASK;
+ gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
+ break;
+ case 2:
+#ifdef CONFIG_SYS_UART2_PRI_GPIO
+ gpio->par_timer &=
+ (GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK);
+ gpio->par_timer |=
+ (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
+#endif
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
+ gpio->par_feci2c &=
+ (GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK);
+ gpio->par_feci2c |=
+ (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
+#endif
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
+ gpio->par_feci2c &=
+ (GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
+ gpio->par_feci2c |=
+ (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+#endif
+ break;
+ }
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ if (setclear) {
+ gpio->par_fec |=
+ GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
+ gpio->par_feci2c |=
+ GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
+ } else {
+ gpio->par_fec &=
+ (GPIO_PAR_FEC_7W_MASK & GPIO_PAR_FEC_MII_MASK);
+ gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_MASK;
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
+#endif /* CONFIG_M5208 */
+
#if defined(CONFIG_M5253)
/*
* Breath some life into the CPU...
diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c
index 0181e4b41..dff8c6aa8 100644
--- a/cpu/mcf52x2/interrupts.c
+++ b/cpu/mcf52x2/interrupts.c
@@ -59,13 +59,19 @@ void dtimer_intr_setup(void)
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5272 */
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275)
+#if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
+ defined(CONFIG_M5271) || defined(CONFIG_M5275)
int interrupt_init(void)
{
volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
+#if defined(CONFIG_M5208)
+ intp->imrl0 = 0xFFFFFFFF;
+ intp->imrh0 = 0xFFFFFFFF;
+#else
intp->imrl0 |= 0x1;
+#endif
enable_interrupts();
return 0;
diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index c93a5180e..b485e1ccc 100644
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -30,11 +30,16 @@
DECLARE_GLOBAL_DATA_PTR;
-/*
- * get_clocks() fills in gd->cpu_clock and gd->bus_clk
- */
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
int get_clocks (void)
{
+#if defined(CONFIG_M5208)
+ volatile pll_t *pll = (pll_t *) MMAP_PLL;
+
+ pll->odr = CONFIG_SYS_PLL_ODR;
+ pll->fdr = CONFIG_SYS_PLL_FDR;
+#endif
+
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
unsigned long pllcr;
@@ -77,7 +82,7 @@ int get_clocks (void)
#endif
gd->cpu_clk = CONFIG_SYS_CLK;
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
+#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
defined(CONFIG_M5271) || defined(CONFIG_M5275)
gd->bus_clk = gd->cpu_clk / 2;
#else
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index ba6b8843e..0dd4de516 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -120,6 +120,12 @@ _start:
nop
move.w #0x2700,%sr
+#if defined(CONFIG_M5208)
+ /* Initialize RAMBAR: locate SRAM and validate it */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ movec %d0, %RAMBAR1
+#endif
+
#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set MBAR address + valid flag */
move.c %d0, %MBAR
@@ -195,15 +201,6 @@ _after_flashbar_copy:
movec %d0, %RAMBAR1
#endif
-#if 0
- /* invalidate and disable cache */
- move.l #0x01000000, %d0 /* Invalidate cache cmd */
- movec %d0, %CACR /* Invalidate cache */
- move.l #0, %d0
- movec %d0, %ACR0
- movec %d0, %ACR1
-#endif
-
/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
@@ -340,6 +337,24 @@ _int_handler:
/*------------------------------------------------------------------------------*/
/* cache functions */
+#ifdef CONFIG_M5208
+ .globl icache_enable
+icache_enable:
+ move.l #0x01000000, %d0 /* Invalidate cache cmd */
+ movec %d0, %CACR /* Invalidate cache */
+ move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup cache mask */
+ movec %d0, %ACR0 /* Enable cache */
+
+ move.l #0x80000200, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Enable cache */
+ nop
+
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
+ moveq #1, %d0
+ move.l %d0, (%a1)
+ rts
+#endif
+
#ifdef CONFIG_M5271
.globl icache_enable
icache_enable:
diff --git a/cpu/mcf5445x/Makefile b/cpu/mcf5445x/Makefile
index a549fdd2a..26ec29895 100644
--- a/cpu/mcf5445x/Makefile
+++ b/cpu/mcf5445x/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START = start.o
-COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o
+COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c
index 7e04e32c7..48b37dfe7 100644
--- a/cpu/mcf5445x/cpu_init.c
+++ b/cpu/mcf5445x/cpu_init.c
@@ -171,3 +171,69 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
return 0;
}
#endif
+
+#ifdef CONFIG_CF_DSPI
+void cfspi_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK;
+}
+
+int cfspi_claim_bus(uint bus, uint cs)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+ return -1;
+
+ /* Clear FIFO and resume transfer */
+ dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+
+ switch (cs) {
+ case 0:
+ gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+ gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+ break;
+ case 1:
+ gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
+ gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1;
+ break;
+ case 2:
+ gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
+ gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2;
+ break;
+ case 5:
+ gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
+ gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5;
+ break;
+ }
+
+ return 0;
+}
+
+void cfspi_release_bus(uint bus, uint cs)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */
+
+ switch (cs) {
+ case 0:
+ gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+ break;
+ case 1:
+ gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
+ break;
+ case 2:
+ gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
+ break;
+ case 5:
+ gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
+ break;
+ }
+}
+#endif
diff --git a/cpu/mcf5445x/dspi.c b/cpu/mcf5445x/dspi.c
deleted file mode 100644
index 6d3ebab6e..000000000
--- a/cpu/mcf5445x/dspi.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- *
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <spi.h>
-#include <malloc.h>
-
-#if defined(CONFIG_CF_DSPI)
-#include <asm/immap.h>
-
-void dspi_init(void)
-{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
- gpio->par_dspi = GPIO_PAR_DSPI_PCS5_PCS5 | GPIO_PAR_DSPI_PCS2_PCS2 |
- GPIO_PAR_DSPI_PCS1_PCS1 | GPIO_PAR_DSPI_PCS0_PCS0 |
- GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK;
-
- dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
- DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
- DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
- DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
-
-#ifdef CONFIG_SYS_DSPI_DCTAR0
- dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR1
- dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR2
- dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR3
- dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR4
- dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR5
- dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR6
- dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR7
- dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
-#endif
-}
-
-void dspi_tx(int chipsel, u8 attrib, u16 data)
-{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
- while ((dspi->dsr & 0x0000F000) >= 4) ;
-
- dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
-}
-
-u16 dspi_rx(void)
-{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
- while ((dspi->dsr & 0x000000F0) == 0) ;
-
- return (dspi->drfr & 0xFFFF);
-}
-
-#if defined(CONFIG_CMD_SPI)
-void spi_init_f(void)
-{
-}
-
-void spi_init_r(void)
-{
-}
-
-void spi_init(void)
-{
- dspi_init();
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct spi_slave *slave;
-
- slave = malloc(sizeof(struct spi_slave));
- if (!slave)
- return NULL;
-
- slave->bus = bus;
- slave->cs = cs;
-
- return slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- free(slave);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- static int bWrite = 0;
- u8 *spi_rd, *spi_wr;
- int len = bitlen >> 3;
-
- spi_rd = (u8 *) din;
- spi_wr = (u8 *) dout;
-
- /* command handling */
- if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) {
- switch (*spi_wr) {
- case 0x02: /* Page Prog */
- bWrite = 1;
- dspi_tx(slave->cs, 0x80, spi_wr[0]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[1]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[2]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[3]);
- dspi_rx();
- return 0;
- case 0x05: /* Read Status */
- if (len == 4)
- if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
- && (spi_wr[3] == 0xFF)) {
- dspi_tx(slave->cs, 0x80, *spi_wr);
- dspi_rx();
- }
- return 0;
- case 0x06: /* WREN */
- dspi_tx(slave->cs, 0x00, *spi_wr);
- dspi_rx();
- return 0;
- case 0x0B: /* Fast read */
- if ((len == 5) && (spi_wr[4] == 0)) {
- dspi_tx(slave->cs, 0x80, spi_wr[0]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[1]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[2]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[3]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[4]);
- dspi_rx();
- }
- return 0;
- case 0x9F: /* RDID */
- dspi_tx(slave->cs, 0x80, *spi_wr);
- dspi_rx();
- return 0;
- case 0xD8: /* Sector erase */
- if (len == 4)
- if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) {
- dspi_tx(slave->cs, 0x80, spi_wr[0]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[1]);
- dspi_rx();
- dspi_tx(slave->cs, 0x80, spi_wr[2]);
- dspi_rx();
- dspi_tx(slave->cs, 0x00, spi_wr[3]);
- dspi_rx();
- }
- return 0;
- }
- }
-
- if (bWrite)
- len--;
-
- while (len--) {
- if (dout != NULL) {
- dspi_tx(slave->cs, 0x80, *spi_wr);
- dspi_rx();
- spi_wr++;
- }
-
- if (din != NULL) {
- dspi_tx(slave->cs, 0x80, 0);
- *spi_rd = dspi_rx();
- spi_rd++;
- }
- }
-
- if (flags == SPI_XFER_END) {
- if (bWrite) {
- dspi_tx(slave->cs, 0x00, *spi_wr);
- dspi_rx();
- bWrite = 0;
- } else {
- dspi_tx(slave->cs, 0x00, 0);
- dspi_rx();
- }
- }
-
- return 0;
-}
-#endif /* CONFIG_CMD_SPI */
-
-#endif /* CONFIG_CF_DSPI */
diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S
index 26fb2ce0c..d2d443915 100644
--- a/cpu/mcf5445x/start.S
+++ b/cpu/mcf5445x/start.S
@@ -150,8 +150,32 @@ asm_sbf_img_hdr:
.long TEXT_BASE /* image to be relocated at */
asm_dram_init:
+ move.w #0x2700,%sr /* Mask off Interrupt */
+
+ move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
+ movec %d0, %VBR
+
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
- movec %d0, %RAMBAR1 /* init Rambar */
+ movec %d0, %RAMBAR1
+
+ /* initialize general use internal ram */
+ move.l #0, %d0
+ move.l #(CACR_STATUS), %a1 /* CACR */
+ move.l #(ICACHE_STATUS), %a2 /* icache */
+ move.l #(DCACHE_STATUS), %a3 /* dcache */
+ move.l %d0, (%a1)
+ move.l %d0, (%a2)
+ move.l %d0, (%a3)
+
+ /* invalidate and disable cache */
+ move.l #0x01004100, %d0 /* Invalidate cache cmd */
+ movec %d0, %CACR /* Invalidate cache */
+ move.l #0, %d0
+ movec %d0, %ACR0
+ movec %d0, %ACR1
+ movec %d0, %ACR2
+ movec %d0, %ACR3
+
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
@@ -163,10 +187,7 @@ asm_dram_init:
move.l #0xFC008004, %a1
move.l #(CONFIG_SYS_CS0_MASK), (%a1)
- /*
- * Dram Initialization
- * a1, a2, and d0
- */
+ /* Dram Initialization a1, a2, and d0 */
/* mscr sdram */
move.l #0xFC0A4074, %a1
move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
@@ -209,24 +230,21 @@ dramsz_loop:
move.l #0xFC0B8000, %a1 /* Mode */
move.l #0xFC0B8004, %a2 /* Ctrl */
-#ifdef CONFIG_M54455EVB
/* Issue PALL */
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
nop
+#ifdef CONFIG_M54455EVB
/* Issue LEMR */
move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
nop
move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
nop
-
- move.l #1000, %d0
-wait1000:
- nop
- subq.l #1, %d0
- bne wait1000
#endif
+ move.l #1000, %d1
+ jsr asm_delay
+
/* Issue PALL */
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
nop
@@ -246,25 +264,24 @@ wait1000:
move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
nop
move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
- nop
#endif
- move.l #500, %d0
-wait500:
- nop
- subq.l #1, %d0
- bne wait500
+ move.l #500, %d1
+ jsr asm_delay
- move.l #(CONFIG_SYS_SDRAM_CTRL), %d0
- and.l #0x7FFFFFFF, %d0
+ move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
+ and.l #0x7FFFFFFF, %d1
#ifdef CONFIG_M54455EVB
- or.l #0x10000c00, %d0
+ or.l #0x10000C00, %d1
#elif defined(CONFIG_M54451EVB)
- or.l #0x10000000, %d0
+ or.l #0x10000C00, %d1
#endif
- move.l %d0, (%a2)
+ move.l %d1, (%a2)
nop
+ move.l #2000, %d1
+ jsr asm_delay
+
/*
* DSPI Initialization
* a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
@@ -274,6 +291,7 @@ wait500:
* a4 - Dst addr
*/
/* Enable pins for DSPI mode - chip-selects are enabled later */
+asm_dspi_init:
move.l #0xFC0A4063, %a0
move.b #0x7F, (%a0)
@@ -367,27 +385,29 @@ asm_dspi_rd_status:
move.b (%a3), %d1
rts
+
+asm_delay:
+ nop
+ subq.l #1, %d1
+ bne asm_delay
+ rts
#endif /* CONFIG_CF_SBF */
.text
. = 0x400
.globl _start
_start:
+#if !defined(CONFIG_CF_SBF)
nop
nop
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
-#if defined(CONFIG_CF_SBF)
- move.l #TEXT_BASE, %d0
- movec %d0, %VBR
-#else
move.l #CONFIG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
-#endif
/* initialize general use internal ram */
move.l #0, %d0
@@ -411,6 +431,7 @@ _start:
the first c-code */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
+#endif
move.l #__got_start, %a5 /* put relocation table address to a5 */
@@ -532,7 +553,7 @@ icache_enable:
move.l #0x00040100, %d0 /* Invalidate icache */
movec %d0, %CACR
- move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 /* Setup icache */
+ move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup icache */
movec %d0, %ACR2
move.l #0x04088020, %d0 /* Enable bcache and icache */
diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c
index 4b5d636bd..5d7d59c0e 100644
--- a/cpu/ppc4xx/4xx_pci.c
+++ b/cpu/ppc4xx/4xx_pci.c
@@ -1,4 +1,6 @@
/*-----------------------------------------------------------------------------+
+ * This source code is dual-licensed. You may use it under the terms of
+ * the GNU General Public license version 2, or under the license below.
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c
index c106ac223..0780624e4 100644
--- a/cpu/ppc4xx/4xx_uart.c
+++ b/cpu/ppc4xx/4xx_uart.c
@@ -22,6 +22,9 @@
*/
/*
+ * This source code is dual-licensed. You may use it under the terms of the
+ * GNU General Public License version 2, or under the license below.
+ *
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
* copyrights to use it in any way he or she deems fit, including
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index e12a78481..e9861abe7 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -285,6 +285,9 @@ int checkcpu (void)
uint pvr = get_pvr();
ulong clock = gd->cpu_clk;
char buf[32];
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ u32 reg;
+#endif
#if !defined(CONFIG_IOP480)
char addstr[64] = "";
@@ -526,6 +529,7 @@ int checkcpu (void)
strcpy(addstr, "No RAID 6 support");
break;
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
case PVR_460EX_RA:
puts("EX Rev. A");
strcpy(addstr, "No Security/Kasumi support");
@@ -536,6 +540,15 @@ int checkcpu (void)
strcpy(addstr, "Security/Kasumi support");
break;
+ case PVR_460EX_RB:
+ puts("EX Rev. B");
+ mfsdr(SDR0_ECID3, reg);
+ if (reg & 0x00100000)
+ strcpy(addstr, "No Security/Kasumi support");
+ else
+ strcpy(addstr, "Security/Kasumi support");
+ break;
+
case PVR_460GT_RA:
puts("GT Rev. A");
strcpy(addstr, "No Security/Kasumi support");
@@ -546,6 +559,16 @@ int checkcpu (void)
strcpy(addstr, "Security/Kasumi support");
break;
+ case PVR_460GT_RB:
+ puts("GT Rev. B");
+ mfsdr(SDR0_ECID3, reg);
+ if (reg & 0x00100000)
+ strcpy(addstr, "No Security/Kasumi support");
+ else
+ strcpy(addstr, "Security/Kasumi support");
+ break;
+#endif
+
case PVR_460SX_RA:
puts("SX Rev. A");
strcpy(addstr, "Security support");
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index 01710e71d..6a92bf836 100644
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -1,4 +1,6 @@
/*-----------------------------------------------------------------------------+
+ | This source code is dual-licensed. You may use it under the terms of the
+ | GNU General Public License version 2, or under the license below.
|
| This source code has been made available to you by IBM on an AS-IS
| basis. Anyone receiving this source is licensed under IBM
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 60756c3df..f967d8464 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -25,6 +25,8 @@
* MA 02111-1307 USA
*/
/*------------------------------------------------------------------------------+
+ * This source code is dual-licensed. You may use it under the terms of the
+ * GNU General Public License version 2, or under the license below.
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
diff --git a/disk/part_dos.c b/disk/part_dos.c
index 93bf3dd4e..b915eb748 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -198,19 +198,24 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part
case IF_TYPE_IDE:
case IF_TYPE_SATA:
case IF_TYPE_ATAPI:
- sprintf ((char *)info->name, "hd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "hd%c%d",
+ 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_SCSI:
- sprintf ((char *)info->name, "sd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "sd%c%d",
+ 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_USB:
- sprintf ((char *)info->name, "usbd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "usbd%c%d",
+ 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_DOC:
- sprintf ((char *)info->name, "docd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "docd%c%d",
+ 'a' + dev_desc->dev, part_num);
break;
default:
- sprintf ((char *)info->name, "xx%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "xx%c%d",
+ 'a' + dev_desc->dev, part_num);
break;
}
/* sprintf(info->type, "%d, pt->sys_ind); */
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 626f022f9..1b04c27ce 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -169,7 +169,7 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part,
- info->start;
info->blksz = GPT_BLOCK_SIZE;
- sprintf((char *)info->name, "%s%d\n", GPT_ENTRY_NAME, part);
+ sprintf((char *)info->name, "%s%d", GPT_ENTRY_NAME, part);
sprintf((char *)info->type, "U-Boot");
debug("%s: start 0x%lX, size 0x%lX, name %s", __FUNCTION__,
diff --git a/disk/part_iso.c b/disk/part_iso.c
index 8fe6148c2..990da956c 100644
--- a/disk/part_iso.c
+++ b/disk/part_iso.c
@@ -161,19 +161,24 @@ int get_partition_info_iso_verb(block_dev_desc_t * dev_desc, int part_num, disk_
case IF_TYPE_IDE:
case IF_TYPE_SATA:
case IF_TYPE_ATAPI:
- sprintf ((char *)info->name, "hd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "hd%c%d",
+ 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_SCSI:
- sprintf ((char *)info->name, "sd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "sd%c%d",
+ 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_USB:
- sprintf ((char *)info->name, "usbd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "usbd%c%d",
+ 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_DOC:
- sprintf ((char *)info->name, "docd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "docd%c%d",
+ 'a' + dev_desc->dev, part_num);
break;
default:
- sprintf ((char *)info->name, "xx%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "xx%c%d",
+ 'a' + dev_desc->dev, part_num);
break;
}
/* the bootcatalog (including validation Entry) is limited to 2048Bytes
diff --git a/drivers/i2c/kirkwood_i2c.c b/drivers/i2c/kirkwood_i2c.c
index dd30499b3..37b7d99bd 100644
--- a/drivers/i2c/kirkwood_i2c.c
+++ b/drivers/i2c/kirkwood_i2c.c
@@ -481,4 +481,3 @@ unsigned int i2c_get_bus_num(void)
return i2c_bus_num;
#endif
}
-
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 1b0af12a7..6fa04b84f 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -30,6 +30,7 @@ COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
+COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o
COBJS := $(COBJS-y)
diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c
new file mode 100644
index 000000000..d30717661
--- /dev/null
+++ b/drivers/mmc/mxcmmc.c
@@ -0,0 +1,522 @@
+/*
+ * This is a driver for the SDHC controller found in Freescale MX2/MX3
+ * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
+ * Unlike the hardware found on MX1, this hardware just works and does
+ * not need all the quirks found in imxmmc.c, hence the seperate driver.
+ *
+ * Copyright (C) 2009 Ilya Yanok, <yanok@emcraft.com>
+ * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
+ *
+ * derived from pxamci.c by Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <mmc.h>
+#include <part.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#ifdef CONFIG_MX27
+#include <asm/arch/clock.h>
+#endif
+
+#define DRIVER_NAME "mxc-mmc"
+
+struct mxcmci_regs {
+ u32 str_stp_clk;
+ u32 status;
+ u32 clk_rate;
+ u32 cmd_dat_cont;
+ u32 res_to;
+ u32 read_to;
+ u32 blk_len;
+ u32 nob;
+ u32 rev_no;
+ u32 int_cntr;
+ u32 cmd;
+ u32 arg;
+ u32 pad;
+ u32 res_fifo;
+ u32 buffer_access;
+};
+
+#define STR_STP_CLK_RESET (1 << 3)
+#define STR_STP_CLK_START_CLK (1 << 1)
+#define STR_STP_CLK_STOP_CLK (1 << 0)
+
+#define STATUS_CARD_INSERTION (1 << 31)
+#define STATUS_CARD_REMOVAL (1 << 30)
+#define STATUS_YBUF_EMPTY (1 << 29)
+#define STATUS_XBUF_EMPTY (1 << 28)
+#define STATUS_YBUF_FULL (1 << 27)
+#define STATUS_XBUF_FULL (1 << 26)
+#define STATUS_BUF_UND_RUN (1 << 25)
+#define STATUS_BUF_OVFL (1 << 24)
+#define STATUS_SDIO_INT_ACTIVE (1 << 14)
+#define STATUS_END_CMD_RESP (1 << 13)
+#define STATUS_WRITE_OP_DONE (1 << 12)
+#define STATUS_DATA_TRANS_DONE (1 << 11)
+#define STATUS_READ_OP_DONE (1 << 11)
+#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
+#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
+#define STATUS_BUF_READ_RDY (1 << 7)
+#define STATUS_BUF_WRITE_RDY (1 << 6)
+#define STATUS_RESP_CRC_ERR (1 << 5)
+#define STATUS_CRC_READ_ERR (1 << 3)
+#define STATUS_CRC_WRITE_ERR (1 << 2)
+#define STATUS_TIME_OUT_RESP (1 << 1)
+#define STATUS_TIME_OUT_READ (1 << 0)
+#define STATUS_ERR_MASK 0x2f
+
+#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
+#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
+#define CMD_DAT_CONT_START_READWAIT (1 << 10)
+#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
+#define CMD_DAT_CONT_INIT (1 << 7)
+#define CMD_DAT_CONT_WRITE (1 << 4)
+#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
+#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
+#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
+#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
+
+#define INT_SDIO_INT_WKP_EN (1 << 18)
+#define INT_CARD_INSERTION_WKP_EN (1 << 17)
+#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
+#define INT_CARD_INSERTION_EN (1 << 15)
+#define INT_CARD_REMOVAL_EN (1 << 14)
+#define INT_SDIO_IRQ_EN (1 << 13)
+#define INT_DAT0_EN (1 << 12)
+#define INT_BUF_READ_EN (1 << 4)
+#define INT_BUF_WRITE_EN (1 << 3)
+#define INT_END_CMD_RES_EN (1 << 2)
+#define INT_WRITE_OP_DONE_EN (1 << 1)
+#define INT_READ_OP_EN (1 << 0)
+
+struct mxcmci_host {
+ struct mmc *mmc;
+ struct mxcmci_regs *base;
+ int irq;
+ int detect_irq;
+ int dma;
+ int do_dma;
+ unsigned int power_mode;
+
+ struct mmc_cmd *cmd;
+ struct mmc_data *data;
+
+ unsigned int dma_nents;
+ unsigned int datasize;
+ unsigned int dma_dir;
+
+ u16 rev_no;
+ unsigned int cmdat;
+
+ int clock;
+};
+
+static struct mxcmci_host mxcmci_host;
+static struct mxcmci_host *host = &mxcmci_host;
+
+static inline int mxcmci_use_dma(struct mxcmci_host *host)
+{
+ return host->do_dma;
+}
+
+static void mxcmci_softreset(struct mxcmci_host *host)
+{
+ int i;
+
+ /* reset sequence */
+ writew(STR_STP_CLK_RESET, &host->base->str_stp_clk);
+ writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
+ &host->base->str_stp_clk);
+
+ for (i = 0; i < 8; i++)
+ writew(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
+
+ writew(0xff, &host->base->res_to);
+}
+
+static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
+{
+ unsigned int nob = data->blocks;
+ unsigned int blksz = data->blocksize;
+ unsigned int datasize = nob * blksz;
+
+ host->data = data;
+
+ writew(nob, &host->base->nob);
+ writew(blksz, &host->base->blk_len);
+ host->datasize = datasize;
+}
+
+static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_cmd *cmd,
+ unsigned int cmdat)
+{
+ if (host->cmd != NULL)
+ printf("mxcmci: error!\n");
+ host->cmd = cmd;
+
+ switch (cmd->resp_type) {
+ case MMC_RSP_R1: /* short CRC, OPCODE */
+ case MMC_RSP_R1b:/* short CRC, OPCODE, BUSY */
+ cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
+ break;
+ case MMC_RSP_R2: /* long 136 bit + CRC */
+ cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
+ break;
+ case MMC_RSP_R3: /* short */
+ cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
+ break;
+ case MMC_RSP_NONE:
+ break;
+ default:
+ printf("mxcmci: unhandled response type 0x%x\n",
+ cmd->resp_type);
+ return -EINVAL;
+ }
+
+ writew(cmd->cmdidx, &host->base->cmd);
+ writel(cmd->cmdarg, &host->base->arg);
+ writew(cmdat, &host->base->cmd_dat_cont);
+
+ return 0;
+}
+
+static void mxcmci_finish_request(struct mxcmci_host *host,
+ struct mmc_cmd *cmd, struct mmc_data *data)
+{
+ host->cmd = NULL;
+ host->data = NULL;
+}
+
+static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
+{
+ int data_error = 0;
+
+ if (stat & STATUS_ERR_MASK) {
+ printf("request failed. status: 0x%08x\n",
+ stat);
+ if (stat & STATUS_CRC_READ_ERR) {
+ data_error = -EILSEQ;
+ } else if (stat & STATUS_CRC_WRITE_ERR) {
+ u32 err_code = (stat >> 9) & 0x3;
+ if (err_code == 2) /* No CRC response */
+ data_error = TIMEOUT;
+ else
+ data_error = -EILSEQ;
+ } else if (stat & STATUS_TIME_OUT_READ) {
+ data_error = TIMEOUT;
+ } else {
+ data_error = -EIO;
+ }
+ }
+
+ host->data = NULL;
+
+ return data_error;
+}
+
+static int mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
+{
+ struct mmc_cmd *cmd = host->cmd;
+ int i;
+ u32 a, b, c;
+ u32 *resp = (u32 *)cmd->response;
+
+ if (!cmd)
+ return 0;
+
+ if (stat & STATUS_TIME_OUT_RESP) {
+ printf("CMD TIMEOUT\n");
+ return TIMEOUT;
+ } else if (stat & STATUS_RESP_CRC_ERR && cmd->resp_type & MMC_RSP_CRC) {
+ printf("cmd crc error\n");
+ return -EILSEQ;
+ }
+
+ if (cmd->resp_type & MMC_RSP_PRESENT) {
+ if (cmd->resp_type & MMC_RSP_136) {
+ for (i = 0; i < 4; i++) {
+ a = readw(&host->base->res_fifo);
+ b = readw(&host->base->res_fifo);
+ resp[i] = a << 16 | b;
+ }
+ } else {
+ a = readw(&host->base->res_fifo);
+ b = readw(&host->base->res_fifo);
+ c = readw(&host->base->res_fifo);
+ resp[0] = a << 24 | b << 8 | c >> 8;
+ }
+ }
+ return 0;
+}
+
+static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
+{
+ u32 stat;
+ unsigned long timeout = get_ticks() + CONFIG_SYS_HZ;
+
+ do {
+ stat = readl(&host->base->status);
+ if (stat & STATUS_ERR_MASK)
+ return stat;
+ if (timeout < get_ticks())
+ return STATUS_TIME_OUT_READ;
+ if (stat & mask)
+ return 0;
+ } while (1);
+}
+
+static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
+{
+ unsigned int stat;
+ u32 *buf = _buf;
+
+ while (bytes > 3) {
+ stat = mxcmci_poll_status(host,
+ STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
+ if (stat)
+ return stat;
+ *buf++ = readl(&host->base->buffer_access);
+ bytes -= 4;
+ }
+
+ if (bytes) {
+ u8 *b = (u8 *)buf;
+ u32 tmp;
+
+ stat = mxcmci_poll_status(host,
+ STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
+ if (stat)
+ return stat;
+ tmp = readl(&host->base->buffer_access);
+ memcpy(b, &tmp, bytes);
+ }
+
+ return 0;
+}
+
+static int mxcmci_push(struct mxcmci_host *host, const void *_buf, int bytes)
+{
+ unsigned int stat;
+ const u32 *buf = _buf;
+
+ while (bytes > 3) {
+ stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
+ if (stat)
+ return stat;
+ writel(*buf++, &host->base->buffer_access);
+ bytes -= 4;
+ }
+
+ if (bytes) {
+ const u8 *b = (u8 *)buf;
+ u32 tmp;
+
+ stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
+ if (stat)
+ return stat;
+
+ memcpy(&tmp, b, bytes);
+ writel(tmp, &host->base->buffer_access);
+ }
+
+ stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
+ if (stat)
+ return stat;
+
+ return 0;
+}
+
+static int mxcmci_transfer_data(struct mxcmci_host *host)
+{
+ struct mmc_data *data = host->data;
+ int stat;
+ unsigned long length;
+
+ length = data->blocks * data->blocksize;
+ host->datasize = 0;
+
+ if (data->flags & MMC_DATA_READ) {
+ stat = mxcmci_pull(host, data->dest, length);
+ if (stat)
+ return stat;
+ host->datasize += length;
+ } else {
+ stat = mxcmci_push(host, (const void *)(data->src), length);
+ if (stat)
+ return stat;
+ host->datasize += length;
+ stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
+ if (stat)
+ return stat;
+ }
+ return 0;
+}
+
+static int mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
+{
+ int datastat;
+ int ret;
+
+ ret = mxcmci_read_response(host, stat);
+
+ if (ret) {
+ mxcmci_finish_request(host, host->cmd, host->data);
+ return ret;
+ }
+
+ if (!host->data) {
+ mxcmci_finish_request(host, host->cmd, host->data);
+ return 0;
+ }
+
+ datastat = mxcmci_transfer_data(host);
+ ret = mxcmci_finish_data(host, datastat);
+ mxcmci_finish_request(host, host->cmd, host->data);
+ return ret;
+}
+
+static int mxcmci_request(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct mxcmci_host *host = mmc->priv;
+ unsigned int cmdat = host->cmdat;
+ u32 stat;
+ int ret;
+
+ host->cmdat &= ~CMD_DAT_CONT_INIT;
+ if (data) {
+ mxcmci_setup_data(host, data);
+
+ cmdat |= CMD_DAT_CONT_DATA_ENABLE;
+
+ if (data->flags & MMC_DATA_WRITE)
+ cmdat |= CMD_DAT_CONT_WRITE;
+ }
+
+ if ((ret = mxcmci_start_cmd(host, cmd, cmdat))) {
+ mxcmci_finish_request(host, cmd, data);
+ return ret;
+ }
+
+ do {
+ stat = readl(&host->base->status);
+ writel(stat, &host->base->status);
+ } while (!(stat & STATUS_END_CMD_RESP));
+
+ return mxcmci_cmd_done(host, stat);
+}
+
+static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
+{
+ unsigned int divider;
+ int prescaler = 0;
+ unsigned long clk_in = imx_get_perclk2();
+
+ while (prescaler <= 0x800) {
+ for (divider = 1; divider <= 0xF; divider++) {
+ int x;
+
+ x = (clk_in / (divider + 1));
+
+ if (prescaler)
+ x /= (prescaler * 2);
+
+ if (x <= clk_ios)
+ break;
+ }
+ if (divider < 0x10)
+ break;
+
+ if (prescaler == 0)
+ prescaler = 1;
+ else
+ prescaler <<= 1;
+ }
+
+ writew((prescaler << 4) | divider, &host->base->clk_rate);
+}
+
+static void mxcmci_set_ios(struct mmc *mmc)
+{
+ struct mxcmci_host *host = mmc->priv;
+ if (mmc->bus_width == 4)
+ host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
+ else
+ host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
+
+ if (mmc->clock) {
+ mxcmci_set_clk_rate(host, mmc->clock);
+ writew(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
+ } else {
+ writew(STR_STP_CLK_STOP_CLK, &host->base->str_stp_clk);
+ }
+
+ host->clock = mmc->clock;
+}
+
+static int mxcmci_init(struct mmc *mmc)
+{
+ struct mxcmci_host *host = mmc->priv;
+
+ mxcmci_softreset(host);
+
+ host->rev_no = readw(&host->base->rev_no);
+ if (host->rev_no != 0x400) {
+ printf("wrong rev.no. 0x%08x. aborting.\n",
+ host->rev_no);
+ return -ENODEV;
+ }
+
+ /* recommended in data sheet */
+ writew(0x2db4, &host->base->read_to);
+
+ writel(0, &host->base->int_cntr);
+
+ return 0;
+}
+
+static int mxcmci_initialize(bd_t *bis)
+{
+ struct mmc *mmc = NULL;
+
+ mmc = malloc(sizeof(struct mmc));
+
+ if (!mmc)
+ return -ENOMEM;
+
+ sprintf(mmc->name, "MXC MCI");
+ mmc->send_cmd = mxcmci_request;
+ mmc->set_ios = mxcmci_set_ios;
+ mmc->init = mxcmci_init;
+ mmc->host_caps = MMC_MODE_4BIT;
+
+ host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE;
+ mmc->priv = host;
+ host->mmc = mmc;
+
+ mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+ mmc->f_min = imx_get_perclk2() >> 7;
+ mmc->f_max = imx_get_perclk2() >> 1;
+
+ mmc_register(mmc);
+
+ return 0;
+}
+
+int mxc_mmc_init(bd_t *bis)
+{
+ return mxcmci_initialize(bis);
+}
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 5f8ed3984..99b9cef17 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -30,8 +30,6 @@
#include <nand.h>
static uint8_t cs;
-static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
-static gpmc_csx_t *gpmc_cs_base;
static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
/*
@@ -49,13 +47,13 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
*/
switch (ctrl) {
case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
- this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_cmd;
+ this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
break;
case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
- this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_adr;
+ this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
break;
case NAND_CTRL_CHANGE | NAND_NCE:
- this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_dat;
+ this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
break;
}
@@ -75,8 +73,8 @@ static void omap_hwecc_init(struct nand_chip *chip)
* Init ECC Control Register
* Clear all ECC | Enable Reg1
*/
- writel(ECCCLEAR | ECCRESULTREG1, &gpmc_base->ecc_control);
- writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_base->ecc_size_config);
+ writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
+ writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config);
}
/*
@@ -179,7 +177,7 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
u_int32_t val;
/* Start Reading from HW ECC1_Result = 0x200 */
- val = readl(&gpmc_base->ecc1_result);
+ val = readl(&gpmc_cfg->ecc1_result);
ecc_code[0] = val & 0xFF;
ecc_code[1] = (val >> 16) & 0xFF;
@@ -189,7 +187,7 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
* Stop reading anymore ECC vals and clear old results
* enable will be called if more reads are required
*/
- writel(0x000, &gpmc_base->ecc_config);
+ writel(0x000, &gpmc_cfg->ecc_config);
return 0;
}
@@ -208,7 +206,7 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
case NAND_ECC_READ:
case NAND_ECC_WRITE:
/* Clear the ecc result registers, select ecc reg as 1 */
- writel(ECCCLEAR | ECCRESULTREG1, &gpmc_base->ecc_control);
+ writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
/*
* Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
@@ -216,9 +214,9 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
* we just have a single ECC engine for all CS
*/
writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
- &gpmc_base->ecc_size_config);
+ &gpmc_cfg->ecc_size_config);
val = (dev_width << 7) | (cs << 1) | (0x1);
- writel(val, &gpmc_base->ecc_config);
+ writel(val, &gpmc_cfg->ecc_config);
break;
default:
printf("Error: Unrecognized Mode[%d]!\n", mode);
@@ -311,15 +309,8 @@ int board_nand_init(struct nand_chip *nand)
* devices.
*/
while (cs < GPMC_MAX_CS) {
- /*
- * Each GPMC set for a single CS is at offset 0x30
- * - already remapped for us
- */
- gpmc_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
- (cs * GPMC_CONFIG_WIDTH));
/* Check if NAND type is set */
- if ((readl(&gpmc_cs_base->config1) & 0xC00) ==
- 0x800) {
+ if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
/* Found it!! */
break;
}
@@ -331,18 +322,18 @@ int board_nand_init(struct nand_chip *nand)
return -ENODEV;
}
- gpmc_config = readl(&gpmc_base->config);
+ gpmc_config = readl(&gpmc_cfg->config);
/* Disable Write protect */
gpmc_config |= 0x10;
- writel(gpmc_config, &gpmc_base->config);
+ writel(gpmc_config, &gpmc_cfg->config);
- nand->IO_ADDR_R = (void __iomem *)&gpmc_cs_base->nand_dat;
- nand->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_cmd;
+ nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
+ nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
nand->cmd_ctrl = omap_nand_hwcontrol;
nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR;
/* If we are 16 bit dev, our gpmc config tells us that */
- if ((readl(gpmc_cs_base) & 0x3000) == 0x1000)
+ if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
nand->options |= NAND_BUSWIDTH_16;
nand->chip_delay = 100;
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 27dcbffab..e3e029280 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -31,6 +31,7 @@ COBJS-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.o
COBJS-$(CONFIG_SPI_FLASH_SPANSION) += spansion.o
COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o
COBJS-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.o
+COBJS-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/mtd/spi/eeprom_m95xxx.c b/drivers/mtd/spi/eeprom_m95xxx.c
new file mode 100644
index 000000000..59f80e39f
--- /dev/null
+++ b/drivers/mtd/spi/eeprom_m95xxx.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+
+#define SPI_EEPROM_WREN 0x06
+#define SPI_EEPROM_RDSR 0x05
+#define SPI_EEPROM_READ 0x03
+#define SPI_EEPROM_WRITE 0x02
+
+#ifndef CONFIG_DEFAULT_SPI_BUS
+#define CONFIG_DEFAULT_SPI_BUS 0
+#endif
+
+#ifndef CONFIG_DEFAULT_SPI_MODE
+#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
+#endif
+
+ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
+{
+ struct spi_slave *slave;
+ u8 cmd = SPI_EEPROM_READ;
+
+ slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000,
+ CONFIG_DEFAULT_SPI_MODE);
+ spi_claim_bus(slave);
+
+ /* command */
+ if(spi_xfer(slave, 8, &cmd, NULL, SPI_XFER_BEGIN))
+ return -1;
+
+ /*
+ * if alen == 3, addr[0] is the block number, we never use it here. All we
+ * need are the lower 16 bits
+ */
+ if (alen == 3)
+ addr++;
+
+ /* address, and data */
+ if(spi_xfer(slave, 16, addr, NULL, 0))
+ return -1;
+ if(spi_xfer(slave, 8 * len, NULL, buffer, SPI_XFER_END))
+ return -1;
+
+ spi_release_bus(slave);
+ spi_free_slave(slave);
+ return len;
+}
+
+ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
+{
+ struct spi_slave *slave;
+ int i;
+ char buf[3];
+
+ slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000,
+ CONFIG_DEFAULT_SPI_MODE);
+ spi_claim_bus(slave);
+
+ buf[0] = SPI_EEPROM_WREN;
+ if(spi_xfer(slave, 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END))
+ return -1;
+
+ buf[0] = SPI_EEPROM_WRITE;
+
+ /* As for reading, drop addr[0] if alen is 3 */
+ if (alen == 3) {
+ alen--;
+ addr++;
+ }
+
+ memcpy(buf + 1, addr, alen);
+ /* command + addr, then data */
+ if(spi_xfer(slave, 24, buf, NULL, SPI_XFER_BEGIN))
+ return -1;
+ if(spi_xfer(slave, len * 8, buffer, NULL, SPI_XFER_END))
+ return -1;
+
+ reset_timer_masked();
+ do {
+ buf[0] = SPI_EEPROM_RDSR;
+ buf[1] = 0;
+ spi_xfer(slave, 16, buf, buf, SPI_XFER_BEGIN | SPI_XFER_END);
+
+ if (!(buf[1] & 1))
+ break;
+
+ } while (get_timer_masked() < CONFIG_SYS_SPI_WRITE_TOUT);
+
+ if (buf[1] & 1)
+ printf ("*** spi_write: Time out while writing!\n");
+
+ spi_release_bus(slave);
+ spi_free_slave(slave);
+ return len;
+}
diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c
index c0200481c..329eef07d 100644
--- a/drivers/net/4xx_enet.c
+++ b/drivers/net/4xx_enet.c
@@ -1,4 +1,6 @@
/*-----------------------------------------------------------------------------+
+ * This source code is dual-licensed. You may use it under the terms of the
+ * GNU General Public License version 2, or under the license below.
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 34b56d825..1c6e40224 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_EEPRO100) += eepro100.o
COBJS-$(CONFIG_ENC28J60) += enc28j60.o
COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
+COBJS-$(CONFIG_FTMAC100) += ftmac100.o
COBJS-$(CONFIG_GRETH) += greth.o
COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index a52749d78..777783a91 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -51,7 +51,7 @@ tested on both gig copper and gig fiber boards
#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
#define mdelay(n) udelay((n)*1000)
-#define E1000_DEFAULT_PBA 0x00000030
+#define E1000_DEFAULT_PBA 0x000a0026
/* NIC specific static variables go here */
@@ -82,6 +82,28 @@ static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
+ /* E1000 PCIe card */
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER },
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES },
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
{}
};
@@ -95,16 +117,20 @@ static int e1000_config_mac_to_phy(struct e1000_hw *hw);
static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
static int e1000_check_for_link(struct eth_device *nic);
static int e1000_wait_autoneg(struct e1000_hw *hw);
-static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
+static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
uint16_t * duplex);
static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
uint16_t * phy_data);
static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
uint16_t phy_data);
-static void e1000_phy_hw_reset(struct e1000_hw *hw);
+static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
static int e1000_phy_reset(struct e1000_hw *hw);
static int e1000_detect_gig_phy(struct e1000_hw *hw);
+static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
+static void e1000_set_media_type(struct e1000_hw *hw);
+static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
+static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
#define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg)))
#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg))
#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\
@@ -114,6 +140,9 @@ static int e1000_detect_gig_phy(struct e1000_hw *hw);
#define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
#ifndef CONFIG_AP1000 /* remove for warnings */
+static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
+ uint16_t words,
+ uint16_t *data);
/******************************************************************************
* Raises the EEPROM's clock input.
*
@@ -204,17 +233,17 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static uint16_t
-e1000_shift_in_ee_bits(struct e1000_hw *hw)
+e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
{
uint32_t eecd;
uint32_t i;
uint16_t data;
- /* In order to read a register from the EEPROM, we need to shift 16 bits
- * in from the EEPROM. Bits are "shifted in" by raising the clock input to
- * the EEPROM (setting the SK bit), and then reading the value of the "DO"
- * bit. During this "shifting in" process the "DI" bit should always be
- * clear..
+ /* In order to read a register from the EEPROM, we need to shift 'count'
+ * bits in from the EEPROM. Bits are "shifted in" by raising the clock
+ * input to the EEPROM (setting the SK bit), and then reading the
+ * value of the "DO" bit. During this "shifting in" process the
+ * "DI" bit should always be clear.
*/
eecd = E1000_READ_REG(hw, EECD);
@@ -222,7 +251,7 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw)
eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
data = 0;
- for (i = 0; i < 16; i++) {
+ for (i = 0; i < count; i++) {
data = data << 1;
e1000_raise_ee_clk(hw, &eecd);
@@ -239,213 +268,600 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw)
}
/******************************************************************************
- * Prepares EEPROM for access
+ * Returns EEPROM to a "standby" state
*
* hw - Struct containing variables accessed by shared code
- *
- * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
- * function should be called before issuing a command to the EEPROM.
*****************************************************************************/
static void
-e1000_setup_eeprom(struct e1000_hw *hw)
+e1000_standby_eeprom(struct e1000_hw *hw)
{
+ struct e1000_eeprom_info *eeprom = &hw->eeprom;
uint32_t eecd;
eecd = E1000_READ_REG(hw, EECD);
- /* Clear SK and DI */
- eecd &= ~(E1000_EECD_SK | E1000_EECD_DI);
- E1000_WRITE_REG(hw, EECD, eecd);
+ if (eeprom->type == e1000_eeprom_microwire) {
+ eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
+ E1000_WRITE_REG(hw, EECD, eecd);
+ E1000_WRITE_FLUSH(hw);
+ udelay(eeprom->delay_usec);
- /* Set CS */
- eecd |= E1000_EECD_CS;
- E1000_WRITE_REG(hw, EECD, eecd);
+ /* Clock high */
+ eecd |= E1000_EECD_SK;
+ E1000_WRITE_REG(hw, EECD, eecd);
+ E1000_WRITE_FLUSH(hw);
+ udelay(eeprom->delay_usec);
+
+ /* Select EEPROM */
+ eecd |= E1000_EECD_CS;
+ E1000_WRITE_REG(hw, EECD, eecd);
+ E1000_WRITE_FLUSH(hw);
+ udelay(eeprom->delay_usec);
+
+ /* Clock low */
+ eecd &= ~E1000_EECD_SK;
+ E1000_WRITE_REG(hw, EECD, eecd);
+ E1000_WRITE_FLUSH(hw);
+ udelay(eeprom->delay_usec);
+ } else if (eeprom->type == e1000_eeprom_spi) {
+ /* Toggle CS to flush commands */
+ eecd |= E1000_EECD_CS;
+ E1000_WRITE_REG(hw, EECD, eecd);
+ E1000_WRITE_FLUSH(hw);
+ udelay(eeprom->delay_usec);
+ eecd &= ~E1000_EECD_CS;
+ E1000_WRITE_REG(hw, EECD, eecd);
+ E1000_WRITE_FLUSH(hw);
+ udelay(eeprom->delay_usec);
+ }
+}
+
+/***************************************************************************
+* Description: Determines if the onboard NVM is FLASH or EEPROM.
+*
+* hw - Struct containing variables accessed by shared code
+****************************************************************************/
+static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
+{
+ uint32_t eecd = 0;
+
+ DEBUGFUNC();
+
+ if (hw->mac_type == e1000_ich8lan)
+ return FALSE;
+
+ if (hw->mac_type == e1000_82573) {
+ eecd = E1000_READ_REG(hw, EECD);
+
+ /* Isolate bits 15 & 16 */
+ eecd = ((eecd >> 15) & 0x03);
+
+ /* If both bits are set, device is Flash type */
+ if (eecd == 0x03)
+ return FALSE;
+ }
+ return TRUE;
}
/******************************************************************************
- * Returns EEPROM to a "standby" state
+ * Prepares EEPROM for access
*
* hw - Struct containing variables accessed by shared code
+ *
+ * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
+ * function should be called before issuing a command to the EEPROM.
*****************************************************************************/
-static void
-e1000_standby_eeprom(struct e1000_hw *hw)
+static int32_t
+e1000_acquire_eeprom(struct e1000_hw *hw)
{
- uint32_t eecd;
+ struct e1000_eeprom_info *eeprom = &hw->eeprom;
+ uint32_t eecd, i = 0;
+
+ DEBUGOUT();
+ if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
+ return -E1000_ERR_SWFW_SYNC;
eecd = E1000_READ_REG(hw, EECD);
- /* Deselct EEPROM */
- eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
- E1000_WRITE_REG(hw, EECD, eecd);
- E1000_WRITE_FLUSH(hw);
- udelay(50);
+ if (hw->mac_type != e1000_82573) {
+ /* Request EEPROM Access */
+ if (hw->mac_type > e1000_82544) {
+ eecd |= E1000_EECD_REQ;
+ E1000_WRITE_REG(hw, EECD, eecd);
+ eecd = E1000_READ_REG(hw, EECD);
+ while ((!(eecd & E1000_EECD_GNT)) &&
+ (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
+ i++;
+ udelay(5);
+ eecd = E1000_READ_REG(hw, EECD);
+ }
+ if (!(eecd & E1000_EECD_GNT)) {
+ eecd &= ~E1000_EECD_REQ;
+ E1000_WRITE_REG(hw, EECD, eecd);
+ DEBUGOUT("Could not acquire EEPROM grant\n");
+ return -E1000_ERR_EEPROM;
+ }
+ }
+ }
- /* Clock high */
- eecd |= E1000_EECD_SK;
- E1000_WRITE_REG(hw, EECD, eecd);
- E1000_WRITE_FLUSH(hw);
- udelay(50);
+ /* Setup EEPROM for Read/Write */
- /* Select EEPROM */
- eecd |= E1000_EECD_CS;
- E1000_WRITE_REG(hw, EECD, eecd);
- E1000_WRITE_FLUSH(hw);
- udelay(50);
+ if (eeprom->type == e1000_eeprom_microwire) {
+ /* Clear SK and DI */
+ eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
+ E1000_WRITE_REG(hw, EECD, eecd);
- /* Clock low */
- eecd &= ~E1000_EECD_SK;
- E1000_WRITE_REG(hw, EECD, eecd);
- E1000_WRITE_FLUSH(hw);
- udelay(50);
+ /* Set CS */
+ eecd |= E1000_EECD_CS;
+ E1000_WRITE_REG(hw, EECD, eecd);
+ } else if (eeprom->type == e1000_eeprom_spi) {
+ /* Clear SK and CS */
+ eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
+ E1000_WRITE_REG(hw, EECD, eecd);
+ udelay(1);
+ }
+
+ return E1000_SUCCESS;
}
/******************************************************************************
- * Reads a 16 bit word from the EEPROM.
+ * Sets up eeprom variables in the hw struct. Must be called after mac_type
+ * is configured. Additionally, if this is ICH8, the flash controller GbE
+ * registers must be mapped, or this will crash.
*
* hw - Struct containing variables accessed by shared code
- * offset - offset of word in the EEPROM to read
- * data - word read from the EEPROM
*****************************************************************************/
-static int
-e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t * data)
+static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
{
- uint32_t eecd;
- uint32_t i = 0;
- int large_eeprom = FALSE;
+ struct e1000_eeprom_info *eeprom = &hw->eeprom;
+ uint32_t eecd = E1000_READ_REG(hw, EECD);
+ int32_t ret_val = E1000_SUCCESS;
+ uint16_t eeprom_size;
- /* Request EEPROM Access */
- if (hw->mac_type > e1000_82544) {
- eecd = E1000_READ_REG(hw, EECD);
- if (eecd & E1000_EECD_SIZE)
- large_eeprom = TRUE;
- eecd |= E1000_EECD_REQ;
- E1000_WRITE_REG(hw, EECD, eecd);
- eecd = E1000_READ_REG(hw, EECD);
- while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) {
- i++;
- udelay(10);
- eecd = E1000_READ_REG(hw, EECD);
+ DEBUGOUT();
+
+ switch (hw->mac_type) {
+ case e1000_82542_rev2_0:
+ case e1000_82542_rev2_1:
+ case e1000_82543:
+ case e1000_82544:
+ eeprom->type = e1000_eeprom_microwire;
+ eeprom->word_size = 64;
+ eeprom->opcode_bits = 3;
+ eeprom->address_bits = 6;
+ eeprom->delay_usec = 50;
+ eeprom->use_eerd = FALSE;
+ eeprom->use_eewr = FALSE;
+ break;
+ case e1000_82540:
+ case e1000_82545:
+ case e1000_82545_rev_3:
+ case e1000_82546:
+ case e1000_82546_rev_3:
+ eeprom->type = e1000_eeprom_microwire;
+ eeprom->opcode_bits = 3;
+ eeprom->delay_usec = 50;
+ if (eecd & E1000_EECD_SIZE) {
+ eeprom->word_size = 256;
+ eeprom->address_bits = 8;
+ } else {
+ eeprom->word_size = 64;
+ eeprom->address_bits = 6;
}
- if (!(eecd & E1000_EECD_GNT)) {
- eecd &= ~E1000_EECD_REQ;
+ eeprom->use_eerd = FALSE;
+ eeprom->use_eewr = FALSE;
+ break;
+ case e1000_82541:
+ case e1000_82541_rev_2:
+ case e1000_82547:
+ case e1000_82547_rev_2:
+ if (eecd & E1000_EECD_TYPE) {
+ eeprom->type = e1000_eeprom_spi;
+ eeprom->opcode_bits = 8;
+ eeprom->delay_usec = 1;
+ if (eecd & E1000_EECD_ADDR_BITS) {
+ eeprom->page_size = 32;
+ eeprom->address_bits = 16;
+ } else {
+ eeprom->page_size = 8;
+ eeprom->address_bits = 8;
+ }
+ } else {
+ eeprom->type = e1000_eeprom_microwire;
+ eeprom->opcode_bits = 3;
+ eeprom->delay_usec = 50;
+ if (eecd & E1000_EECD_ADDR_BITS) {
+ eeprom->word_size = 256;
+ eeprom->address_bits = 8;
+ } else {
+ eeprom->word_size = 64;
+ eeprom->address_bits = 6;
+ }
+ }
+ eeprom->use_eerd = FALSE;
+ eeprom->use_eewr = FALSE;
+ break;
+ case e1000_82571:
+ case e1000_82572:
+ eeprom->type = e1000_eeprom_spi;
+ eeprom->opcode_bits = 8;
+ eeprom->delay_usec = 1;
+ if (eecd & E1000_EECD_ADDR_BITS) {
+ eeprom->page_size = 32;
+ eeprom->address_bits = 16;
+ } else {
+ eeprom->page_size = 8;
+ eeprom->address_bits = 8;
+ }
+ eeprom->use_eerd = FALSE;
+ eeprom->use_eewr = FALSE;
+ break;
+ case e1000_82573:
+ eeprom->type = e1000_eeprom_spi;
+ eeprom->opcode_bits = 8;
+ eeprom->delay_usec = 1;
+ if (eecd & E1000_EECD_ADDR_BITS) {
+ eeprom->page_size = 32;
+ eeprom->address_bits = 16;
+ } else {
+ eeprom->page_size = 8;
+ eeprom->address_bits = 8;
+ }
+ eeprom->use_eerd = TRUE;
+ eeprom->use_eewr = TRUE;
+ if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
+ eeprom->type = e1000_eeprom_flash;
+ eeprom->word_size = 2048;
+
+ /* Ensure that the Autonomous FLASH update bit is cleared due to
+ * Flash update issue on parts which use a FLASH for NVM. */
+ eecd &= ~E1000_EECD_AUPDEN;
E1000_WRITE_REG(hw, EECD, eecd);
- DEBUGOUT("Could not acquire EEPROM grant\n");
- return -E1000_ERR_EEPROM;
}
- }
+ break;
+ case e1000_80003es2lan:
+ eeprom->type = e1000_eeprom_spi;
+ eeprom->opcode_bits = 8;
+ eeprom->delay_usec = 1;
+ if (eecd & E1000_EECD_ADDR_BITS) {
+ eeprom->page_size = 32;
+ eeprom->address_bits = 16;
+ } else {
+ eeprom->page_size = 8;
+ eeprom->address_bits = 8;
+ }
+ eeprom->use_eerd = TRUE;
+ eeprom->use_eewr = FALSE;
+ break;
- /* Prepare the EEPROM for reading */
- e1000_setup_eeprom(hw);
+ /* ich8lan does not support currently. if needed, please
+ * add corresponding code and functions.
+ */
+#if 0
+ case e1000_ich8lan:
+ {
+ int32_t i = 0;
+
+ eeprom->type = e1000_eeprom_ich8;
+ eeprom->use_eerd = FALSE;
+ eeprom->use_eewr = FALSE;
+ eeprom->word_size = E1000_SHADOW_RAM_WORDS;
+ uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
+ ICH_FLASH_GFPREG);
+ /* Zero the shadow RAM structure. But don't load it from NVM
+ * so as to save time for driver init */
+ if (hw->eeprom_shadow_ram != NULL) {
+ for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
+ hw->eeprom_shadow_ram[i].modified = FALSE;
+ hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
+ }
+ }
- /* Send the READ command (opcode + addr) */
- e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE, 3);
- e1000_shift_out_ee_bits(hw, offset, (large_eeprom) ? 8 : 6);
+ hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
+ ICH_FLASH_SECTOR_SIZE;
- /* Read the data */
- *data = e1000_shift_in_ee_bits(hw);
+ hw->flash_bank_size = ((flash_size >> 16)
+ & ICH_GFPREG_BASE_MASK) + 1;
+ hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
- /* End this read operation */
- e1000_standby_eeprom(hw);
+ hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
- /* Stop requesting EEPROM access */
- if (hw->mac_type > e1000_82544) {
- eecd = E1000_READ_REG(hw, EECD);
- eecd &= ~E1000_EECD_REQ;
- E1000_WRITE_REG(hw, EECD, eecd);
+ hw->flash_bank_size /= 2 * sizeof(uint16_t);
+ break;
+ }
+#endif
+ default:
+ break;
}
- return 0;
+ if (eeprom->type == e1000_eeprom_spi) {
+ /* eeprom_size will be an enum [0..8] that maps
+ * to eeprom sizes 128B to
+ * 32KB (incremented by powers of 2).
+ */
+ if (hw->mac_type <= e1000_82547_rev_2) {
+ /* Set to default value for initial eeprom read. */
+ eeprom->word_size = 64;
+ ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
+ &eeprom_size);
+ if (ret_val)
+ return ret_val;
+ eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
+ >> EEPROM_SIZE_SHIFT;
+ /* 256B eeprom size was not supported in earlier
+ * hardware, so we bump eeprom_size up one to
+ * ensure that "1" (which maps to 256B) is never
+ * the result used in the shifting logic below. */
+ if (eeprom_size)
+ eeprom_size++;
+ } else {
+ eeprom_size = (uint16_t)((eecd &
+ E1000_EECD_SIZE_EX_MASK) >>
+ E1000_EECD_SIZE_EX_SHIFT);
+ }
+
+ eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
+ }
+ return ret_val;
}
-#if 0
-static void
-e1000_eeprom_cleanup(struct e1000_hw *hw)
+/******************************************************************************
+ * Polls the status bit (bit 1) of the EERD to determine when the read is done.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static int32_t
+e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
{
- uint32_t eecd;
+ uint32_t attempts = 100000;
+ uint32_t i, reg = 0;
+ int32_t done = E1000_ERR_EEPROM;
- eecd = E1000_READ_REG(hw, EECD);
- eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
- E1000_WRITE_REG(hw, EECD, eecd);
- e1000_raise_ee_clk(hw, &eecd);
- e1000_lower_ee_clk(hw, &eecd);
+ for (i = 0; i < attempts; i++) {
+ if (eerd == E1000_EEPROM_POLL_READ)
+ reg = E1000_READ_REG(hw, EERD);
+ else
+ reg = E1000_READ_REG(hw, EEWR);
+
+ if (reg & E1000_EEPROM_RW_REG_DONE) {
+ done = E1000_SUCCESS;
+ break;
+ }
+ udelay(5);
+ }
+
+ return done;
}
-static uint16_t
-e1000_wait_eeprom_done(struct e1000_hw *hw)
+/******************************************************************************
+ * Reads a 16 bit word from the EEPROM using the EERD register.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * offset - offset of word in the EEPROM to read
+ * data - word read from the EEPROM
+ * words - number of words to read
+ *****************************************************************************/
+static int32_t
+e1000_read_eeprom_eerd(struct e1000_hw *hw,
+ uint16_t offset,
+ uint16_t words,
+ uint16_t *data)
{
- uint32_t eecd;
- uint32_t i;
+ uint32_t i, eerd = 0;
+ int32_t error = 0;
+
+ for (i = 0; i < words; i++) {
+ eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
+ E1000_EEPROM_RW_REG_START;
+
+ E1000_WRITE_REG(hw, EERD, eerd);
+ error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
+
+ if (error)
+ break;
+ data[i] = (E1000_READ_REG(hw, EERD) >>
+ E1000_EEPROM_RW_REG_DATA);
- e1000_standby_eeprom(hw);
- for (i = 0; i < 200; i++) {
- eecd = E1000_READ_REG(hw, EECD);
- if (eecd & E1000_EECD_DO)
- return (TRUE);
- udelay(5);
}
- return (FALSE);
+
+ return error;
}
-static int
-e1000_write_eeprom(struct e1000_hw *hw, uint16_t Reg, uint16_t Data)
+static void
+e1000_release_eeprom(struct e1000_hw *hw)
{
uint32_t eecd;
- int large_eeprom = FALSE;
- int i = 0;
- /* Request EEPROM Access */
- if (hw->mac_type > e1000_82544) {
- eecd = E1000_READ_REG(hw, EECD);
- if (eecd & E1000_EECD_SIZE)
- large_eeprom = TRUE;
- eecd |= E1000_EECD_REQ;
+ DEBUGFUNC();
+
+ eecd = E1000_READ_REG(hw, EECD);
+
+ if (hw->eeprom.type == e1000_eeprom_spi) {
+ eecd |= E1000_EECD_CS; /* Pull CS high */
+ eecd &= ~E1000_EECD_SK; /* Lower SCK */
+
E1000_WRITE_REG(hw, EECD, eecd);
- eecd = E1000_READ_REG(hw, EECD);
- while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) {
- i++;
- udelay(5);
- eecd = E1000_READ_REG(hw, EECD);
- }
- if (!(eecd & E1000_EECD_GNT)) {
- eecd &= ~E1000_EECD_REQ;
- E1000_WRITE_REG(hw, EECD, eecd);
- DEBUGOUT("Could not acquire EEPROM grant\n");
- return FALSE;
- }
- }
- e1000_setup_eeprom(hw);
- e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE, 5);
- e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4);
- e1000_standby_eeprom(hw);
- e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE, 3);
- e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 8 : 6);
- e1000_shift_out_ee_bits(hw, Data, 16);
- if (!e1000_wait_eeprom_done(hw)) {
- return FALSE;
+
+ udelay(hw->eeprom.delay_usec);
+ } else if (hw->eeprom.type == e1000_eeprom_microwire) {
+ /* cleanup eeprom */
+
+ /* CS on Microwire is active-high */
+ eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
+
+ E1000_WRITE_REG(hw, EECD, eecd);
+
+ /* Rising edge of clock */
+ eecd |= E1000_EECD_SK;
+ E1000_WRITE_REG(hw, EECD, eecd);
+ E1000_WRITE_FLUSH(hw);
+ udelay(hw->eeprom.delay_usec);
+
+ /* Falling edge of clock */
+ eecd &= ~E1000_EECD_SK;
+ E1000_WRITE_REG(hw, EECD, eecd);
+ E1000_WRITE_FLUSH(hw);
+ udelay(hw->eeprom.delay_usec);
}
- e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE, 5);
- e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4);
- e1000_eeprom_cleanup(hw);
/* Stop requesting EEPROM access */
if (hw->mac_type > e1000_82544) {
- eecd = E1000_READ_REG(hw, EECD);
eecd &= ~E1000_EECD_REQ;
E1000_WRITE_REG(hw, EECD, eecd);
}
- i = 0;
- eecd = E1000_READ_REG(hw, EECD);
- while (((eecd & E1000_EECD_GNT)) && (i < 500)) {
- i++;
- udelay(10);
- eecd = E1000_READ_REG(hw, EECD);
- }
- if ((eecd & E1000_EECD_GNT)) {
- DEBUGOUT("Could not release EEPROM grant\n");
+}
+/******************************************************************************
+ * Reads a 16 bit word from the EEPROM.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static int32_t
+e1000_spi_eeprom_ready(struct e1000_hw *hw)
+{
+ uint16_t retry_count = 0;
+ uint8_t spi_stat_reg;
+
+ DEBUGFUNC();
+
+ /* Read "Status Register" repeatedly until the LSB is cleared. The
+ * EEPROM will signal that the command has been completed by clearing
+ * bit 0 of the internal status register. If it's not cleared within
+ * 5 milliseconds, then error out.
+ */
+ retry_count = 0;
+ do {
+ e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
+ hw->eeprom.opcode_bits);
+ spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
+ if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
+ break;
+
+ udelay(5);
+ retry_count += 5;
+
+ e1000_standby_eeprom(hw);
+ } while (retry_count < EEPROM_MAX_RETRY_SPI);
+
+ /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
+ * only 0-5mSec on 5V devices)
+ */
+ if (retry_count >= EEPROM_MAX_RETRY_SPI) {
+ DEBUGOUT("SPI EEPROM Status error\n");
+ return -E1000_ERR_EEPROM;
}
- return TRUE;
+
+ return E1000_SUCCESS;
}
+
+/******************************************************************************
+ * Reads a 16 bit word from the EEPROM.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * offset - offset of word in the EEPROM to read
+ * data - word read from the EEPROM
+ *****************************************************************************/
+static int32_t
+e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
+ uint16_t words, uint16_t *data)
+{
+ struct e1000_eeprom_info *eeprom = &hw->eeprom;
+ uint32_t i = 0;
+
+ DEBUGFUNC();
+
+ /* If eeprom is not yet detected, do so now */
+ if (eeprom->word_size == 0)
+ e1000_init_eeprom_params(hw);
+
+ /* A check for invalid values: offset too large, too many words,
+ * and not enough words.
+ */
+ if ((offset >= eeprom->word_size) ||
+ (words > eeprom->word_size - offset) ||
+ (words == 0)) {
+ DEBUGOUT("\"words\" parameter out of bounds."
+ "Words = %d, size = %d\n", offset, eeprom->word_size);
+ return -E1000_ERR_EEPROM;
+ }
+
+ /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
+ * directly. In this case, we need to acquire the EEPROM so that
+ * FW or other port software does not interrupt.
+ */
+ if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
+ hw->eeprom.use_eerd == FALSE) {
+
+ /* Prepare the EEPROM for bit-bang reading */
+ if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
+ return -E1000_ERR_EEPROM;
+ }
+
+ /* Eerd register EEPROM access requires no eeprom aquire/release */
+ if (eeprom->use_eerd == TRUE)
+ return e1000_read_eeprom_eerd(hw, offset, words, data);
+
+ /* ich8lan does not support currently. if needed, please
+ * add corresponding code and functions.
+ */
+#if 0
+ /* ICH EEPROM access is done via the ICH flash controller */
+ if (eeprom->type == e1000_eeprom_ich8)
+ return e1000_read_eeprom_ich8(hw, offset, words, data);
#endif
+ /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
+ * acquired the EEPROM at this point, so any returns should relase it */
+ if (eeprom->type == e1000_eeprom_spi) {
+ uint16_t word_in;
+ uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
+
+ if (e1000_spi_eeprom_ready(hw)) {
+ e1000_release_eeprom(hw);
+ return -E1000_ERR_EEPROM;
+ }
+
+ e1000_standby_eeprom(hw);
+
+ /* Some SPI eeproms use the 8th address bit embedded in
+ * the opcode */
+ if ((eeprom->address_bits == 8) && (offset >= 128))
+ read_opcode |= EEPROM_A8_OPCODE_SPI;
+
+ /* Send the READ command (opcode + addr) */
+ e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
+ e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
+ eeprom->address_bits);
+
+ /* Read the data. The address of the eeprom internally
+ * increments with each byte (spi) being read, saving on the
+ * overhead of eeprom setup and tear-down. The address
+ * counter will roll over if reading beyond the size of
+ * the eeprom, thus allowing the entire memory to be read
+ * starting from any offset. */
+ for (i = 0; i < words; i++) {
+ word_in = e1000_shift_in_ee_bits(hw, 16);
+ data[i] = (word_in >> 8) | (word_in << 8);
+ }
+ } else if (eeprom->type == e1000_eeprom_microwire) {
+ for (i = 0; i < words; i++) {
+ /* Send the READ command (opcode + addr) */
+ e1000_shift_out_ee_bits(hw,
+ EEPROM_READ_OPCODE_MICROWIRE,
+ eeprom->opcode_bits);
+ e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
+ eeprom->address_bits);
+
+ /* Read the data. For microwire, each word requires
+ * the overhead of eeprom setup and tear-down. */
+ data[i] = e1000_shift_in_ee_bits(hw, 16);
+ e1000_standby_eeprom(hw);
+ }
+ }
+
+ /* End this read operation */
+ e1000_release_eeprom(hw);
+
+ return E1000_SUCCESS;
+}
/******************************************************************************
* Verifies that the EEPROM has a valid checksum
@@ -466,7 +882,7 @@ e1000_validate_eeprom_checksum(struct eth_device *nic)
DEBUGFUNC();
for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
- if (e1000_read_eeprom(hw, i, &eeprom_data) < 0) {
+ if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
DEBUGOUT("EEPROM Read Error\n");
return -E1000_ERR_EEPROM;
}
@@ -480,8 +896,205 @@ e1000_validate_eeprom_checksum(struct eth_device *nic)
return -E1000_ERR_EEPROM;
}
}
+
+/*****************************************************************************
+ * Set PHY to class A mode
+ * Assumes the following operations will follow to enable the new class mode.
+ * 1. Do a PHY soft reset
+ * 2. Restart auto-negotiation or force link.
+ *
+ * hw - Struct containing variables accessed by shared code
+ ****************************************************************************/
+static int32_t
+e1000_set_phy_mode(struct e1000_hw *hw)
+{
+ int32_t ret_val;
+ uint16_t eeprom_data;
+
+ DEBUGFUNC();
+
+ if ((hw->mac_type == e1000_82545_rev_3) &&
+ (hw->media_type == e1000_media_type_copper)) {
+ ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
+ 1, &eeprom_data);
+ if (ret_val)
+ return ret_val;
+
+ if ((eeprom_data != EEPROM_RESERVED_WORD) &&
+ (eeprom_data & EEPROM_PHY_CLASS_A)) {
+ ret_val = e1000_write_phy_reg(hw,
+ M88E1000_PHY_PAGE_SELECT, 0x000B);
+ if (ret_val)
+ return ret_val;
+ ret_val = e1000_write_phy_reg(hw,
+ M88E1000_PHY_GEN_CONTROL, 0x8104);
+ if (ret_val)
+ return ret_val;
+
+ hw->phy_reset_disable = FALSE;
+ }
+ }
+
+ return E1000_SUCCESS;
+}
#endif /* #ifndef CONFIG_AP1000 */
+/***************************************************************************
+ *
+ * Obtaining software semaphore bit (SMBI) before resetting PHY.
+ *
+ * hw: Struct containing variables accessed by shared code
+ *
+ * returns: - E1000_ERR_RESET if fail to obtain semaphore.
+ * E1000_SUCCESS at any other case.
+ *
+ ***************************************************************************/
+static int32_t
+e1000_get_software_semaphore(struct e1000_hw *hw)
+{
+ int32_t timeout = hw->eeprom.word_size + 1;
+ uint32_t swsm;
+
+ DEBUGFUNC();
+
+ if (hw->mac_type != e1000_80003es2lan)
+ return E1000_SUCCESS;
+
+ while (timeout) {
+ swsm = E1000_READ_REG(hw, SWSM);
+ /* If SMBI bit cleared, it is now set and we hold
+ * the semaphore */
+ if (!(swsm & E1000_SWSM_SMBI))
+ break;
+ mdelay(1);
+ timeout--;
+ }
+
+ if (!timeout) {
+ DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
+ return -E1000_ERR_RESET;
+ }
+
+ return E1000_SUCCESS;
+}
+
+/***************************************************************************
+ * This function clears HW semaphore bits.
+ *
+ * hw: Struct containing variables accessed by shared code
+ *
+ * returns: - None.
+ *
+ ***************************************************************************/
+static void
+e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
+{
+ uint32_t swsm;
+
+ DEBUGFUNC();
+
+ if (!hw->eeprom_semaphore_present)
+ return;
+
+ swsm = E1000_READ_REG(hw, SWSM);
+ if (hw->mac_type == e1000_80003es2lan) {
+ /* Release both semaphores. */
+ swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
+ } else
+ swsm &= ~(E1000_SWSM_SWESMBI);
+ E1000_WRITE_REG(hw, SWSM, swsm);
+}
+
+/***************************************************************************
+ *
+ * Using the combination of SMBI and SWESMBI semaphore bits when resetting
+ * adapter or Eeprom access.
+ *
+ * hw: Struct containing variables accessed by shared code
+ *
+ * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
+ * E1000_SUCCESS at any other case.
+ *
+ ***************************************************************************/
+static int32_t
+e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
+{
+ int32_t timeout;
+ uint32_t swsm;
+
+ DEBUGFUNC();
+
+ if (!hw->eeprom_semaphore_present)
+ return E1000_SUCCESS;
+
+ if (hw->mac_type == e1000_80003es2lan) {
+ /* Get the SW semaphore. */
+ if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
+ return -E1000_ERR_EEPROM;
+ }
+
+ /* Get the FW semaphore. */
+ timeout = hw->eeprom.word_size + 1;
+ while (timeout) {
+ swsm = E1000_READ_REG(hw, SWSM);
+ swsm |= E1000_SWSM_SWESMBI;
+ E1000_WRITE_REG(hw, SWSM, swsm);
+ /* if we managed to set the bit we got the semaphore. */
+ swsm = E1000_READ_REG(hw, SWSM);
+ if (swsm & E1000_SWSM_SWESMBI)
+ break;
+
+ udelay(50);
+ timeout--;
+ }
+
+ if (!timeout) {
+ /* Release semaphores */
+ e1000_put_hw_eeprom_semaphore(hw);
+ DEBUGOUT("Driver can't access the Eeprom - "
+ "SWESMBI bit is set.\n");
+ return -E1000_ERR_EEPROM;
+ }
+
+ return E1000_SUCCESS;
+}
+
+static int32_t
+e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
+{
+ uint32_t swfw_sync = 0;
+ uint32_t swmask = mask;
+ uint32_t fwmask = mask << 16;
+ int32_t timeout = 200;
+
+ DEBUGFUNC();
+ while (timeout) {
+ if (e1000_get_hw_eeprom_semaphore(hw))
+ return -E1000_ERR_SWFW_SYNC;
+
+ swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
+ if (!(swfw_sync & (fwmask | swmask)))
+ break;
+
+ /* firmware currently using resource (fwmask) */
+ /* or other software thread currently using resource (swmask) */
+ e1000_put_hw_eeprom_semaphore(hw);
+ mdelay(5);
+ timeout--;
+ }
+
+ if (!timeout) {
+ DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
+ return -E1000_ERR_SWFW_SYNC;
+ }
+
+ swfw_sync |= swmask;
+ E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
+
+ e1000_put_hw_eeprom_semaphore(hw);
+ return E1000_SUCCESS;
+}
+
/******************************************************************************
* Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
* second function of dual function devices
@@ -501,7 +1114,7 @@ e1000_read_mac_addr(struct eth_device *nic)
for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
offset = i >> 1;
- if (e1000_read_eeprom(hw, offset, &eeprom_data) < 0) {
+ if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
DEBUGOUT("EEPROM Read Error\n");
return -E1000_ERR_EEPROM;
}
@@ -605,7 +1218,7 @@ e1000_clear_vfta(struct e1000_hw *hw)
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
-static int
+int32_t
e1000_set_mac_type(struct e1000_hw *hw)
{
DEBUGFUNC();
@@ -636,21 +1249,88 @@ e1000_set_mac_type(struct e1000_hw *hw)
break;
case E1000_DEV_ID_82540EM:
case E1000_DEV_ID_82540EM_LOM:
+ case E1000_DEV_ID_82540EP:
+ case E1000_DEV_ID_82540EP_LOM:
+ case E1000_DEV_ID_82540EP_LP:
hw->mac_type = e1000_82540;
break;
case E1000_DEV_ID_82545EM_COPPER:
- case E1000_DEV_ID_82545GM_COPPER:
case E1000_DEV_ID_82545EM_FIBER:
hw->mac_type = e1000_82545;
break;
+ case E1000_DEV_ID_82545GM_COPPER:
+ case E1000_DEV_ID_82545GM_FIBER:
+ case E1000_DEV_ID_82545GM_SERDES:
+ hw->mac_type = e1000_82545_rev_3;
+ break;
case E1000_DEV_ID_82546EB_COPPER:
case E1000_DEV_ID_82546EB_FIBER:
+ case E1000_DEV_ID_82546EB_QUAD_COPPER:
hw->mac_type = e1000_82546;
break;
+ case E1000_DEV_ID_82546GB_COPPER:
+ case E1000_DEV_ID_82546GB_FIBER:
+ case E1000_DEV_ID_82546GB_SERDES:
+ case E1000_DEV_ID_82546GB_PCIE:
+ case E1000_DEV_ID_82546GB_QUAD_COPPER:
+ case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
+ hw->mac_type = e1000_82546_rev_3;
+ break;
+ case E1000_DEV_ID_82541EI:
+ case E1000_DEV_ID_82541EI_MOBILE:
+ case E1000_DEV_ID_82541ER_LOM:
+ hw->mac_type = e1000_82541;
+ break;
case E1000_DEV_ID_82541ER:
+ case E1000_DEV_ID_82541GI:
case E1000_DEV_ID_82541GI_LF:
+ case E1000_DEV_ID_82541GI_MOBILE:
hw->mac_type = e1000_82541_rev_2;
break;
+ case E1000_DEV_ID_82547EI:
+ case E1000_DEV_ID_82547EI_MOBILE:
+ hw->mac_type = e1000_82547;
+ break;
+ case E1000_DEV_ID_82547GI:
+ hw->mac_type = e1000_82547_rev_2;
+ break;
+ case E1000_DEV_ID_82571EB_COPPER:
+ case E1000_DEV_ID_82571EB_FIBER:
+ case E1000_DEV_ID_82571EB_SERDES:
+ case E1000_DEV_ID_82571EB_SERDES_DUAL:
+ case E1000_DEV_ID_82571EB_SERDES_QUAD:
+ case E1000_DEV_ID_82571EB_QUAD_COPPER:
+ case E1000_DEV_ID_82571PT_QUAD_COPPER:
+ case E1000_DEV_ID_82571EB_QUAD_FIBER:
+ case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
+ hw->mac_type = e1000_82571;
+ break;
+ case E1000_DEV_ID_82572EI_COPPER:
+ case E1000_DEV_ID_82572EI_FIBER:
+ case E1000_DEV_ID_82572EI_SERDES:
+ case E1000_DEV_ID_82572EI:
+ hw->mac_type = e1000_82572;
+ break;
+ case E1000_DEV_ID_82573E:
+ case E1000_DEV_ID_82573E_IAMT:
+ case E1000_DEV_ID_82573L:
+ hw->mac_type = e1000_82573;
+ break;
+ case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
+ case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
+ case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
+ case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
+ hw->mac_type = e1000_80003es2lan;
+ break;
+ case E1000_DEV_ID_ICH8_IGP_M_AMT:
+ case E1000_DEV_ID_ICH8_IGP_AMT:
+ case E1000_DEV_ID_ICH8_IGP_C:
+ case E1000_DEV_ID_ICH8_IFE:
+ case E1000_DEV_ID_ICH8_IFE_GT:
+ case E1000_DEV_ID_ICH8_IFE_G:
+ case E1000_DEV_ID_ICH8_IGP_M:
+ hw->mac_type = e1000_ich8lan;
+ break;
default:
/* Should never have loaded on this device */
return -E1000_ERR_MAC_TYPE;
@@ -677,8 +1357,7 @@ e1000_reset_hw(struct e1000_hw *hw)
if (hw->mac_type == e1000_82542_rev2_0) {
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
pci_write_config_word(hw->pdev, PCI_COMMAND,
- hw->
- pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
+ hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
}
/* Clear interrupt mask to stop board from generating interrupts */
@@ -709,12 +1388,7 @@ e1000_reset_hw(struct e1000_hw *hw)
DEBUGOUT("Issuing a global reset to MAC\n");
ctrl = E1000_READ_REG(hw, CTRL);
-#if 0
- if (hw->mac_type > e1000_82543)
- E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
- else
-#endif
- E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
+ E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
/* Force a reload from the EEPROM if necessary */
if (hw->mac_type < e1000_82540) {
@@ -746,6 +1420,127 @@ e1000_reset_hw(struct e1000_hw *hw)
if (hw->mac_type == e1000_82542_rev2_0) {
pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
}
+ E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA);
+}
+
+/******************************************************************************
+ *
+ * Initialize a number of hardware-dependent bits
+ *
+ * hw: Struct containing variables accessed by shared code
+ *
+ * This function contains hardware limitation workarounds for PCI-E adapters
+ *
+ *****************************************************************************/
+static void
+e1000_initialize_hardware_bits(struct e1000_hw *hw)
+{
+ if ((hw->mac_type >= e1000_82571) &&
+ (!hw->initialize_hw_bits_disable)) {
+ /* Settings common to all PCI-express silicon */
+ uint32_t reg_ctrl, reg_ctrl_ext;
+ uint32_t reg_tarc0, reg_tarc1;
+ uint32_t reg_tctl;
+ uint32_t reg_txdctl, reg_txdctl1;
+
+ /* link autonegotiation/sync workarounds */
+ reg_tarc0 = E1000_READ_REG(hw, TARC0);
+ reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
+
+ /* Enable not-done TX descriptor counting */
+ reg_txdctl = E1000_READ_REG(hw, TXDCTL);
+ reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
+ E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
+
+ reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
+ reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
+ E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
+
+ switch (hw->mac_type) {
+ case e1000_82571:
+ case e1000_82572:
+ /* Clear PHY TX compatible mode bits */
+ reg_tarc1 = E1000_READ_REG(hw, TARC1);
+ reg_tarc1 &= ~((1 << 30)|(1 << 29));
+
+ /* link autonegotiation/sync workarounds */
+ reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
+
+ /* TX ring control fixes */
+ reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
+
+ /* Multiple read bit is reversed polarity */
+ reg_tctl = E1000_READ_REG(hw, TCTL);
+ if (reg_tctl & E1000_TCTL_MULR)
+ reg_tarc1 &= ~(1 << 28);
+ else
+ reg_tarc1 |= (1 << 28);
+
+ E1000_WRITE_REG(hw, TARC1, reg_tarc1);
+ break;
+ case e1000_82573:
+ reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
+ reg_ctrl_ext &= ~(1 << 23);
+ reg_ctrl_ext |= (1 << 22);
+
+ /* TX byte count fix */
+ reg_ctrl = E1000_READ_REG(hw, CTRL);
+ reg_ctrl &= ~(1 << 29);
+
+ E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
+ E1000_WRITE_REG(hw, CTRL, reg_ctrl);
+ break;
+ case e1000_80003es2lan:
+ /* improve small packet performace for fiber/serdes */
+ if ((hw->media_type == e1000_media_type_fiber)
+ || (hw->media_type ==
+ e1000_media_type_internal_serdes)) {
+ reg_tarc0 &= ~(1 << 20);
+ }
+
+ /* Multiple read bit is reversed polarity */
+ reg_tctl = E1000_READ_REG(hw, TCTL);
+ reg_tarc1 = E1000_READ_REG(hw, TARC1);
+ if (reg_tctl & E1000_TCTL_MULR)
+ reg_tarc1 &= ~(1 << 28);
+ else
+ reg_tarc1 |= (1 << 28);
+
+ E1000_WRITE_REG(hw, TARC1, reg_tarc1);
+ break;
+ case e1000_ich8lan:
+ /* Reduce concurrent DMA requests to 3 from 4 */
+ if ((hw->revision_id < 3) ||
+ ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
+ (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
+ reg_tarc0 |= ((1 << 29)|(1 << 28));
+
+ reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
+ reg_ctrl_ext |= (1 << 22);
+ E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
+
+ /* workaround TX hang with TSO=on */
+ reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
+
+ /* Multiple read bit is reversed polarity */
+ reg_tctl = E1000_READ_REG(hw, TCTL);
+ reg_tarc1 = E1000_READ_REG(hw, TARC1);
+ if (reg_tctl & E1000_TCTL_MULR)
+ reg_tarc1 &= ~(1 << 28);
+ else
+ reg_tarc1 |= (1 << 28);
+
+ /* workaround TX hang with TSO=on */
+ reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
+
+ E1000_WRITE_REG(hw, TARC1, reg_tarc1);
+ break;
+ default:
+ break;
+ }
+
+ E1000_WRITE_REG(hw, TARC0, reg_tarc0);
+ }
}
/******************************************************************************
@@ -763,49 +1558,43 @@ static int
e1000_init_hw(struct eth_device *nic)
{
struct e1000_hw *hw = nic->priv;
- uint32_t ctrl, status;
+ uint32_t ctrl;
uint32_t i;
int32_t ret_val;
uint16_t pcix_cmd_word;
uint16_t pcix_stat_hi_word;
uint16_t cmd_mmrbc;
uint16_t stat_mmrbc;
- e1000_bus_type bus_type = e1000_bus_type_unknown;
-
+ uint32_t mta_size;
+ uint32_t reg_data;
+ uint32_t ctrl_ext;
DEBUGFUNC();
-#if 0
- /* Initialize Identification LED */
- ret_val = e1000_id_led_init(hw);
- if (ret_val < 0) {
- DEBUGOUT("Error Initializing Identification LED\n");
- return ret_val;
- }
-#endif
- /* Set the Media Type and exit with error if it is not valid. */
- if (hw->mac_type != e1000_82543) {
- /* tbi_compatibility is only valid on 82543 */
- hw->tbi_compatibility_en = FALSE;
+ /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
+ if ((hw->mac_type == e1000_ich8lan) &&
+ ((hw->revision_id < 3) ||
+ ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
+ (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
+ reg_data = E1000_READ_REG(hw, STATUS);
+ reg_data &= ~0x80000000;
+ E1000_WRITE_REG(hw, STATUS, reg_data);
}
+ /* Do not need initialize Identification LED */
- if (hw->mac_type >= e1000_82543) {
- status = E1000_READ_REG(hw, STATUS);
- if (status & E1000_STATUS_TBIMODE) {
- hw->media_type = e1000_media_type_fiber;
- /* tbi_compatibility not valid on fiber */
- hw->tbi_compatibility_en = FALSE;
- } else {
- hw->media_type = e1000_media_type_copper;
- }
- } else {
- /* This is an 82542 (fiber only) */
- hw->media_type = e1000_media_type_fiber;
- }
+ /* Set the media type and TBI compatibility */
+ e1000_set_media_type(hw);
+
+ /* Must be called after e1000_set_media_type
+ * because media_type is used */
+ e1000_initialize_hardware_bits(hw);
/* Disabling VLAN filtering. */
DEBUGOUT("Initializing the IEEE VLAN\n");
- E1000_WRITE_REG(hw, VET, 0);
-
- e1000_clear_vfta(hw);
+ /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
+ if (hw->mac_type != e1000_ich8lan) {
+ if (hw->mac_type < e1000_82545_rev_3)
+ E1000_WRITE_REG(hw, VET, 0);
+ e1000_clear_vfta(hw);
+ }
/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
if (hw->mac_type == e1000_82542_rev2_0) {
@@ -833,26 +1622,33 @@ e1000_init_hw(struct eth_device *nic)
/* Zero out the Multicast HASH table */
DEBUGOUT("Zeroing the MTA\n");
- for (i = 0; i < E1000_MC_TBL_SIZE; i++)
+ mta_size = E1000_MC_TBL_SIZE;
+ if (hw->mac_type == e1000_ich8lan)
+ mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
+ for (i = 0; i < mta_size; i++) {
E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
-
+ /* use write flush to prevent Memory Write Block (MWB) from
+ * occuring when accessing our register space */
+ E1000_WRITE_FLUSH(hw);
+ }
#if 0
/* Set the PCI priority bit correctly in the CTRL register. This
* determines if the adapter gives priority to receives, or if it
- * gives equal priority to transmits and receives.
+ * gives equal priority to transmits and receives. Valid only on
+ * 82542 and 82543 silicon.
*/
- if (hw->dma_fairness) {
+ if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
ctrl = E1000_READ_REG(hw, CTRL);
E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
}
#endif
- if (hw->mac_type >= e1000_82543) {
- status = E1000_READ_REG(hw, STATUS);
- bus_type = (status & E1000_STATUS_PCIX_MODE) ?
- e1000_bus_type_pcix : e1000_bus_type_pci;
- }
+ switch (hw->mac_type) {
+ case e1000_82545_rev_3:
+ case e1000_82546_rev_3:
+ break;
+ default:
/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
- if (bus_type == e1000_bus_type_pcix) {
+ if (hw->bus_type == e1000_bus_type_pcix) {
pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
&pcix_cmd_word);
pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
@@ -872,6 +1668,12 @@ e1000_init_hw(struct eth_device *nic)
pcix_cmd_word);
}
}
+ break;
+ }
+
+ /* More time needed for PHY to initialize */
+ if (hw->mac_type == e1000_ich8lan)
+ mdelay(15);
/* Call a subroutine to configure the link and setup flow control. */
ret_val = e1000_setup_link(nic);
@@ -884,6 +1686,48 @@ e1000_init_hw(struct eth_device *nic)
E1000_TXDCTL_FULL_TX_DESC_WB;
E1000_WRITE_REG(hw, TXDCTL, ctrl);
}
+
+ switch (hw->mac_type) {
+ default:
+ break;
+ case e1000_80003es2lan:
+ /* Enable retransmit on late collisions */
+ reg_data = E1000_READ_REG(hw, TCTL);
+ reg_data |= E1000_TCTL_RTLC;
+ E1000_WRITE_REG(hw, TCTL, reg_data);
+
+ /* Configure Gigabit Carry Extend Padding */
+ reg_data = E1000_READ_REG(hw, TCTL_EXT);
+ reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
+ reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
+ E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
+
+ /* Configure Transmit Inter-Packet Gap */
+ reg_data = E1000_READ_REG(hw, TIPG);
+ reg_data &= ~E1000_TIPG_IPGT_MASK;
+ reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
+ E1000_WRITE_REG(hw, TIPG, reg_data);
+
+ reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
+ reg_data &= ~0x00100000;
+ E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
+ /* Fall through */
+ case e1000_82571:
+ case e1000_82572:
+ case e1000_ich8lan:
+ ctrl = E1000_READ_REG(hw, TXDCTL1);
+ ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
+ | E1000_TXDCTL_FULL_TX_DESC_WB;
+ E1000_WRITE_REG(hw, TXDCTL1, ctrl);
+ break;
+ }
+
+ if (hw->mac_type == e1000_82573) {
+ uint32_t gcr = E1000_READ_REG(hw, GCR);
+ gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
+ E1000_WRITE_REG(hw, GCR, gcr);
+ }
+
#if 0
/* Clear all of the statistics registers (clear on read). It is
* important that we do this after we have tried to establish link
@@ -891,8 +1735,22 @@ e1000_init_hw(struct eth_device *nic)
* is no link.
*/
e1000_clear_hw_cntrs(hw);
+
+ /* ICH8 No-snoop bits are opposite polarity.
+ * Set to snoop by default after reset. */
+ if (hw->mac_type == e1000_ich8lan)
+ e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
#endif
+ if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
+ hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
+ ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
+ /* Relaxed ordering must be disabled to avoid a parity
+ * error crash in a PCI slot. */
+ ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
+ E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+ }
+
return ret_val;
}
@@ -917,6 +1775,11 @@ e1000_setup_link(struct eth_device *nic)
DEBUGFUNC();
+ /* In the case of the phy reset being blocked, we already have a link.
+ * We do not have to set it up again. */
+ if (e1000_check_phy_reset_block(hw))
+ return E1000_SUCCESS;
+
#ifndef CONFIG_AP1000
/* Read and store word 0x0F of the EEPROM. This word contains bits
* that determine the hardware's default PAUSE (flow control) mode,
@@ -926,7 +1789,8 @@ e1000_setup_link(struct eth_device *nic)
* control setting, then the variable hw->fc will
* be initialized based on a value in the EEPROM.
*/
- if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) {
+ if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
+ &eeprom_data) < 0) {
DEBUGOUT("EEPROM Read Error\n");
return -E1000_ERR_EEPROM;
}
@@ -937,13 +1801,31 @@ e1000_setup_link(struct eth_device *nic)
#endif
if (hw->fc == e1000_fc_default) {
- if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
- hw->fc = e1000_fc_none;
- else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
- EEPROM_WORD0F_ASM_DIR)
- hw->fc = e1000_fc_tx_pause;
- else
+ switch (hw->mac_type) {
+ case e1000_ich8lan:
+ case e1000_82573:
hw->fc = e1000_fc_full;
+ break;
+ default:
+#ifndef CONFIG_AP1000
+ ret_val = e1000_read_eeprom(hw,
+ EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
+ if (ret_val) {
+ DEBUGOUT("EEPROM Read Error\n");
+ return -E1000_ERR_EEPROM;
+ }
+#else
+ eeprom_data = 0xb220;
+#endif
+ if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
+ hw->fc = e1000_fc_none;
+ else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
+ EEPROM_WORD0F_ASM_DIR)
+ hw->fc = e1000_fc_tx_pause;
+ else
+ hw->fc = e1000_fc_full;
+ break;
+ }
}
/* We want to save off the original Flow Control configuration just
@@ -985,12 +1867,16 @@ e1000_setup_link(struct eth_device *nic)
* control is disabled, because it does not hurt anything to
* initialize these registers.
*/
- DEBUGOUT
- ("Initializing the Flow Control address, type and timer regs\n");
+ DEBUGOUT("Initializing the Flow Control address, type"
+ "and timer regs\n");
+
+ /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
+ if (hw->mac_type != e1000_ich8lan) {
+ E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
+ E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
+ E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
+ }
- E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
- E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
- E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
/* Set the flow control receive threshold registers. Normally,
@@ -1155,17 +2041,15 @@ e1000_setup_fiber_link(struct eth_device *nic)
}
/******************************************************************************
-* Detects which PHY is present and the speed and duplex
+* Make sure we have a valid PHY and change PHY mode before link setup.
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
-static int
-e1000_setup_copper_link(struct eth_device *nic)
+static int32_t
+e1000_copper_link_preconfig(struct e1000_hw *hw)
{
- struct e1000_hw *hw = nic->priv;
uint32_t ctrl;
int32_t ret_val;
- uint16_t i;
uint16_t phy_data;
DEBUGFUNC();
@@ -1180,28 +2064,684 @@ e1000_setup_copper_link(struct eth_device *nic)
ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
E1000_WRITE_REG(hw, CTRL, ctrl);
} else {
- ctrl |=
- (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
+ ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
+ | E1000_CTRL_SLU);
E1000_WRITE_REG(hw, CTRL, ctrl);
- e1000_phy_hw_reset(hw);
+ ret_val = e1000_phy_hw_reset(hw);
+ if (ret_val)
+ return ret_val;
}
/* Make sure we have a valid PHY */
ret_val = e1000_detect_gig_phy(hw);
- if (ret_val < 0) {
+ if (ret_val) {
DEBUGOUT("Error, did not detect valid phy.\n");
return ret_val;
}
DEBUGOUT("Phy ID = %x \n", hw->phy_id);
- /* Enable CRS on TX. This must be set for half-duplex operation. */
- if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
+#ifndef CONFIG_AP1000
+ /* Set PHY to class A mode (if necessary) */
+ ret_val = e1000_set_phy_mode(hw);
+ if (ret_val)
+ return ret_val;
+#endif
+ if ((hw->mac_type == e1000_82545_rev_3) ||
+ (hw->mac_type == e1000_82546_rev_3)) {
+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
+ &phy_data);
+ phy_data |= 0x00000008;
+ ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
+ phy_data);
+ }
+
+ if (hw->mac_type <= e1000_82543 ||
+ hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
+ hw->mac_type == e1000_82541_rev_2
+ || hw->mac_type == e1000_82547_rev_2)
+ hw->phy_reset_disable = FALSE;
+
+ return E1000_SUCCESS;
+}
+
+/*****************************************************************************
+ *
+ * This function sets the lplu state according to the active flag. When
+ * activating lplu this function also disables smart speed and vise versa.
+ * lplu will not be activated unless the device autonegotiation advertisment
+ * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
+ * hw: Struct containing variables accessed by shared code
+ * active - true to enable lplu false to disable lplu.
+ *
+ * returns: - E1000_ERR_PHY if fail to read/write the PHY
+ * E1000_SUCCESS at any other case.
+ *
+ ****************************************************************************/
+
+static int32_t
+e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active)
+{
+ uint32_t phy_ctrl = 0;
+ int32_t ret_val;
+ uint16_t phy_data;
+ DEBUGFUNC();
+
+ if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
+ && hw->phy_type != e1000_phy_igp_3)
+ return E1000_SUCCESS;
+
+ /* During driver activity LPLU should not be used or it will attain link
+ * from the lowest speeds starting from 10Mbps. The capability is used
+ * for Dx transitions and states */
+ if (hw->mac_type == e1000_82541_rev_2
+ || hw->mac_type == e1000_82547_rev_2) {
+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
+ &phy_data);
+ if (ret_val)
+ return ret_val;
+ } else if (hw->mac_type == e1000_ich8lan) {
+ /* MAC writes into PHY register based on the state transition
+ * and start auto-negotiation. SW driver can overwrite the
+ * settings in CSR PHY power control E1000_PHY_CTRL register. */
+ phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
+ } else {
+ ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
+ &phy_data);
+ if (ret_val)
+ return ret_val;
+ }
+
+ if (!active) {
+ if (hw->mac_type == e1000_82541_rev_2 ||
+ hw->mac_type == e1000_82547_rev_2) {
+ phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
+ ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
+ phy_data);
+ if (ret_val)
+ return ret_val;
+ } else {
+ if (hw->mac_type == e1000_ich8lan) {
+ phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
+ E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
+ } else {
+ phy_data &= ~IGP02E1000_PM_D3_LPLU;
+ ret_val = e1000_write_phy_reg(hw,
+ IGP02E1000_PHY_POWER_MGMT, phy_data);
+ if (ret_val)
+ return ret_val;
+ }
+ }
+
+ /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
+ * Dx states where the power conservation is most important. During
+ * driver activity we should enable SmartSpeed, so performance is
+ * maintained. */
+ if (hw->smart_speed == e1000_smart_speed_on) {
+ ret_val = e1000_read_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
+ ret_val = e1000_write_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG, phy_data);
+ if (ret_val)
+ return ret_val;
+ } else if (hw->smart_speed == e1000_smart_speed_off) {
+ ret_val = e1000_read_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+ ret_val = e1000_write_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG, phy_data);
+ if (ret_val)
+ return ret_val;
+ }
+
+ } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
+ || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
+ (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
+
+ if (hw->mac_type == e1000_82541_rev_2 ||
+ hw->mac_type == e1000_82547_rev_2) {
+ phy_data |= IGP01E1000_GMII_FLEX_SPD;
+ ret_val = e1000_write_phy_reg(hw,
+ IGP01E1000_GMII_FIFO, phy_data);
+ if (ret_val)
+ return ret_val;
+ } else {
+ if (hw->mac_type == e1000_ich8lan) {
+ phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
+ E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
+ } else {
+ phy_data |= IGP02E1000_PM_D3_LPLU;
+ ret_val = e1000_write_phy_reg(hw,
+ IGP02E1000_PHY_POWER_MGMT, phy_data);
+ if (ret_val)
+ return ret_val;
+ }
+ }
+
+ /* When LPLU is enabled we should disable SmartSpeed */
+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+ &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+ ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+ phy_data);
+ if (ret_val)
+ return ret_val;
+ }
+ return E1000_SUCCESS;
+}
+
+/*****************************************************************************
+ *
+ * This function sets the lplu d0 state according to the active flag. When
+ * activating lplu this function also disables smart speed and vise versa.
+ * lplu will not be activated unless the device autonegotiation advertisment
+ * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
+ * hw: Struct containing variables accessed by shared code
+ * active - true to enable lplu false to disable lplu.
+ *
+ * returns: - E1000_ERR_PHY if fail to read/write the PHY
+ * E1000_SUCCESS at any other case.
+ *
+ ****************************************************************************/
+
+static int32_t
+e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active)
+{
+ uint32_t phy_ctrl = 0;
+ int32_t ret_val;
+ uint16_t phy_data;
+ DEBUGFUNC();
+
+ if (hw->mac_type <= e1000_82547_rev_2)
+ return E1000_SUCCESS;
+
+ if (hw->mac_type == e1000_ich8lan) {
+ phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
+ } else {
+ ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
+ &phy_data);
+ if (ret_val)
+ return ret_val;
+ }
+
+ if (!active) {
+ if (hw->mac_type == e1000_ich8lan) {
+ phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
+ E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
+ } else {
+ phy_data &= ~IGP02E1000_PM_D0_LPLU;
+ ret_val = e1000_write_phy_reg(hw,
+ IGP02E1000_PHY_POWER_MGMT, phy_data);
+ if (ret_val)
+ return ret_val;
+ }
+
+ /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
+ * Dx states where the power conservation is most important. During
+ * driver activity we should enable SmartSpeed, so performance is
+ * maintained. */
+ if (hw->smart_speed == e1000_smart_speed_on) {
+ ret_val = e1000_read_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
+ ret_val = e1000_write_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG, phy_data);
+ if (ret_val)
+ return ret_val;
+ } else if (hw->smart_speed == e1000_smart_speed_off) {
+ ret_val = e1000_read_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+ ret_val = e1000_write_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG, phy_data);
+ if (ret_val)
+ return ret_val;
+ }
+
+
+ } else {
+
+ if (hw->mac_type == e1000_ich8lan) {
+ phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
+ E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
+ } else {
+ phy_data |= IGP02E1000_PM_D0_LPLU;
+ ret_val = e1000_write_phy_reg(hw,
+ IGP02E1000_PHY_POWER_MGMT, phy_data);
+ if (ret_val)
+ return ret_val;
+ }
+
+ /* When LPLU is enabled we should disable SmartSpeed */
+ ret_val = e1000_read_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+ ret_val = e1000_write_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG, phy_data);
+ if (ret_val)
+ return ret_val;
+
+ }
+ return E1000_SUCCESS;
+}
+
+/********************************************************************
+* Copper link setup for e1000_phy_igp series.
+*
+* hw - Struct containing variables accessed by shared code
+*********************************************************************/
+static int32_t
+e1000_copper_link_igp_setup(struct e1000_hw *hw)
+{
+ uint32_t led_ctrl;
+ int32_t ret_val;
+ uint16_t phy_data;
+
+ DEBUGOUT();
+
+ if (hw->phy_reset_disable)
+ return E1000_SUCCESS;
+
+ ret_val = e1000_phy_reset(hw);
+ if (ret_val) {
+ DEBUGOUT("Error Resetting the PHY\n");
+ return ret_val;
}
+
+ /* Wait 15ms for MAC to configure PHY from eeprom settings */
+ mdelay(15);
+ if (hw->mac_type != e1000_ich8lan) {
+ /* Configure activity LED after PHY reset */
+ led_ctrl = E1000_READ_REG(hw, LEDCTL);
+ led_ctrl &= IGP_ACTIVITY_LED_MASK;
+ led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
+ E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
+ }
+
+ /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
+ if (hw->phy_type == e1000_phy_igp) {
+ /* disable lplu d3 during driver init */
+ ret_val = e1000_set_d3_lplu_state(hw, FALSE);
+ if (ret_val) {
+ DEBUGOUT("Error Disabling LPLU D3\n");
+ return ret_val;
+ }
+ }
+
+ /* disable lplu d0 during driver init */
+ ret_val = e1000_set_d0_lplu_state(hw, FALSE);
+ if (ret_val) {
+ DEBUGOUT("Error Disabling LPLU D0\n");
+ return ret_val;
+ }
+ /* Configure mdi-mdix settings */
+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+ hw->dsp_config_state = e1000_dsp_config_disabled;
+ /* Force MDI for earlier revs of the IGP PHY */
+ phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
+ | IGP01E1000_PSCR_FORCE_MDI_MDIX);
+ hw->mdix = 1;
+
+ } else {
+ hw->dsp_config_state = e1000_dsp_config_enabled;
+ phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
+
+ switch (hw->mdix) {
+ case 1:
+ phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
+ break;
+ case 2:
+ phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
+ break;
+ case 0:
+ default:
+ phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
+ break;
+ }
+ }
+ ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
+ if (ret_val)
+ return ret_val;
+
+ /* set auto-master slave resolution settings */
+ if (hw->autoneg) {
+ e1000_ms_type phy_ms_setting = hw->master_slave;
+
+ if (hw->ffe_config_state == e1000_ffe_config_active)
+ hw->ffe_config_state = e1000_ffe_config_enabled;
+
+ if (hw->dsp_config_state == e1000_dsp_config_activated)
+ hw->dsp_config_state = e1000_dsp_config_enabled;
+
+ /* when autonegotiation advertisment is only 1000Mbps then we
+ * should disable SmartSpeed and enable Auto MasterSlave
+ * resolution as hardware default. */
+ if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
+ /* Disable SmartSpeed */
+ ret_val = e1000_read_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG, &phy_data);
+ if (ret_val)
+ return ret_val;
+ phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+ ret_val = e1000_write_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG, phy_data);
+ if (ret_val)
+ return ret_val;
+ /* Set auto Master/Slave resolution process */
+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
+ &phy_data);
+ if (ret_val)
+ return ret_val;
+ phy_data &= ~CR_1000T_MS_ENABLE;
+ ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
+ phy_data);
+ if (ret_val)
+ return ret_val;
+ }
+
+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ /* load defaults for future use */
+ hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
+ ((phy_data & CR_1000T_MS_VALUE) ?
+ e1000_ms_force_master :
+ e1000_ms_force_slave) :
+ e1000_ms_auto;
+
+ switch (phy_ms_setting) {
+ case e1000_ms_force_master:
+ phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
+ break;
+ case e1000_ms_force_slave:
+ phy_data |= CR_1000T_MS_ENABLE;
+ phy_data &= ~(CR_1000T_MS_VALUE);
+ break;
+ case e1000_ms_auto:
+ phy_data &= ~CR_1000T_MS_ENABLE;
+ default:
+ break;
+ }
+ ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
+ if (ret_val)
+ return ret_val;
+ }
+
+ return E1000_SUCCESS;
+}
+
+/*****************************************************************************
+ * This function checks the mode of the firmware.
+ *
+ * returns - TRUE when the mode is IAMT or FALSE.
+ ****************************************************************************/
+boolean_t
+e1000_check_mng_mode(struct e1000_hw *hw)
+{
+ uint32_t fwsm;
+ DEBUGFUNC();
+
+ fwsm = E1000_READ_REG(hw, FWSM);
+
+ if (hw->mac_type == e1000_ich8lan) {
+ if ((fwsm & E1000_FWSM_MODE_MASK) ==
+ (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
+ return TRUE;
+ } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
+ (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
+ return TRUE;
+
+ return FALSE;
+}
+
+static int32_t
+e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
+{
+ uint32_t reg_val;
+ uint16_t swfw;
+ DEBUGFUNC();
+
+ if ((hw->mac_type == e1000_80003es2lan) &&
+ (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
+ swfw = E1000_SWFW_PHY1_SM;
+ } else {
+ swfw = E1000_SWFW_PHY0_SM;
+ }
+ if (e1000_swfw_sync_acquire(hw, swfw))
+ return -E1000_ERR_SWFW_SYNC;
+
+ reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
+ & E1000_KUMCTRLSTA_OFFSET) | data;
+ E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
+ udelay(2);
+
+ return E1000_SUCCESS;
+}
+
+static int32_t
+e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
+{
+ uint32_t reg_val;
+ uint16_t swfw;
+ DEBUGFUNC();
+
+ if ((hw->mac_type == e1000_80003es2lan) &&
+ (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
+ swfw = E1000_SWFW_PHY1_SM;
+ } else {
+ swfw = E1000_SWFW_PHY0_SM;
+ }
+ if (e1000_swfw_sync_acquire(hw, swfw))
+ return -E1000_ERR_SWFW_SYNC;
+
+ /* Write register address */
+ reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
+ E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
+ E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
+ udelay(2);
+
+ /* Read the data returned */
+ reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
+ *data = (uint16_t)reg_val;
+
+ return E1000_SUCCESS;
+}
+
+/********************************************************************
+* Copper link setup for e1000_phy_gg82563 series.
+*
+* hw - Struct containing variables accessed by shared code
+*********************************************************************/
+static int32_t
+e1000_copper_link_ggp_setup(struct e1000_hw *hw)
+{
+ int32_t ret_val;
+ uint16_t phy_data;
+ uint32_t reg_data;
+
+ DEBUGFUNC();
+
+ if (!hw->phy_reset_disable) {
+ /* Enable CRS on TX for half-duplex operation. */
+ ret_val = e1000_read_phy_reg(hw,
+ GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
+ /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
+ phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
+
+ ret_val = e1000_write_phy_reg(hw,
+ GG82563_PHY_MAC_SPEC_CTRL, phy_data);
+ if (ret_val)
+ return ret_val;
+
+ /* Options:
+ * MDI/MDI-X = 0 (default)
+ * 0 - Auto for all speeds
+ * 1 - MDI mode
+ * 2 - MDI-X mode
+ * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
+ */
+ ret_val = e1000_read_phy_reg(hw,
+ GG82563_PHY_SPEC_CTRL, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
+
+ switch (hw->mdix) {
+ case 1:
+ phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
+ break;
+ case 2:
+ phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
+ break;
+ case 0:
+ default:
+ phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
+ break;
+ }
+
+ /* Options:
+ * disable_polarity_correction = 0 (default)
+ * Automatic Correction for Reversed Cable Polarity
+ * 0 - Disabled
+ * 1 - Enabled
+ */
+ phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
+ ret_val = e1000_write_phy_reg(hw,
+ GG82563_PHY_SPEC_CTRL, phy_data);
+
+ if (ret_val)
+ return ret_val;
+
+ /* SW Reset the PHY so all changes take effect */
+ ret_val = e1000_phy_reset(hw);
+ if (ret_val) {
+ DEBUGOUT("Error Resetting the PHY\n");
+ return ret_val;
+ }
+ } /* phy_reset_disable */
+
+ if (hw->mac_type == e1000_80003es2lan) {
+ /* Bypass RX and TX FIFO's */
+ ret_val = e1000_write_kmrn_reg(hw,
+ E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
+ E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
+ | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
+ if (ret_val)
+ return ret_val;
+
+ ret_val = e1000_read_phy_reg(hw,
+ GG82563_PHY_SPEC_CTRL_2, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
+ ret_val = e1000_write_phy_reg(hw,
+ GG82563_PHY_SPEC_CTRL_2, phy_data);
+
+ if (ret_val)
+ return ret_val;
+
+ reg_data = E1000_READ_REG(hw, CTRL_EXT);
+ reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
+ E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
+
+ ret_val = e1000_read_phy_reg(hw,
+ GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ /* Do not init these registers when the HW is in IAMT mode, since the
+ * firmware will have already initialized them. We only initialize
+ * them if the HW is not in IAMT mode.
+ */
+ if (e1000_check_mng_mode(hw) == FALSE) {
+ /* Enable Electrical Idle on the PHY */
+ phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
+ ret_val = e1000_write_phy_reg(hw,
+ GG82563_PHY_PWR_MGMT_CTRL, phy_data);
+ if (ret_val)
+ return ret_val;
+
+ ret_val = e1000_read_phy_reg(hw,
+ GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
+ ret_val = e1000_write_phy_reg(hw,
+ GG82563_PHY_KMRN_MODE_CTRL, phy_data);
+
+ if (ret_val)
+ return ret_val;
+ }
+
+ /* Workaround: Disable padding in Kumeran interface in the MAC
+ * and in the PHY to avoid CRC errors.
+ */
+ ret_val = e1000_read_phy_reg(hw,
+ GG82563_PHY_INBAND_CTRL, &phy_data);
+ if (ret_val)
+ return ret_val;
+ phy_data |= GG82563_ICR_DIS_PADDING;
+ ret_val = e1000_write_phy_reg(hw,
+ GG82563_PHY_INBAND_CTRL, phy_data);
+ if (ret_val)
+ return ret_val;
+ }
+ return E1000_SUCCESS;
+}
+
+/********************************************************************
+* Copper link setup for e1000_phy_m88 series.
+*
+* hw - Struct containing variables accessed by shared code
+*********************************************************************/
+static int32_t
+e1000_copper_link_mgp_setup(struct e1000_hw *hw)
+{
+ int32_t ret_val;
+ uint16_t phy_data;
+
+ DEBUGFUNC();
+
+ if (hw->phy_reset_disable)
+ return E1000_SUCCESS;
+
+ /* Enable CRS on TX. This must be set for half-duplex operation. */
+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+ if (ret_val)
+ return ret_val;
+
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
-#if 0
/* Options:
* MDI/MDI-X = 0 (default)
* 0 - Auto for all speeds
@@ -1210,6 +2750,7 @@ e1000_setup_copper_link(struct eth_device *nic)
* 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
*/
phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
+
switch (hw->mdix) {
case 1:
phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
@@ -1225,68 +2766,75 @@ e1000_setup_copper_link(struct eth_device *nic)
phy_data |= M88E1000_PSCR_AUTO_X_MODE;
break;
}
-#else
- phy_data |= M88E1000_PSCR_AUTO_X_MODE;
-#endif
-#if 0
/* Options:
* disable_polarity_correction = 0 (default)
- * Automatic Correction for Reversed Cable Polarity
+ * Automatic Correction for Reversed Cable Polarity
* 0 - Disabled
* 1 - Enabled
*/
phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
- if (hw->disable_polarity_correction == 1)
- phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
-#else
- phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
-#endif
- if (e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
- }
+ ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+ if (ret_val)
+ return ret_val;
- /* Force TX_CLK in the Extended PHY Specific Control Register
- * to 25MHz clock.
- */
- if (e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- phy_data |= M88E1000_EPSCR_TX_CLK_25;
- /* Configure Master and Slave downshift values */
- phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
- M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
- phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
- M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
- if (e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
+ if (hw->phy_revision < M88E1011_I_REV_4) {
+ /* Force TX_CLK in the Extended PHY Specific Control Register
+ * to 25MHz clock.
+ */
+ ret_val = e1000_read_phy_reg(hw,
+ M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ phy_data |= M88E1000_EPSCR_TX_CLK_25;
+
+ if ((hw->phy_revision == E1000_REVISION_2) &&
+ (hw->phy_id == M88E1111_I_PHY_ID)) {
+ /* Vidalia Phy, set the downshift counter to 5x */
+ phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
+ phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
+ ret_val = e1000_write_phy_reg(hw,
+ M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
+ if (ret_val)
+ return ret_val;
+ } else {
+ /* Configure Master and Slave downshift values */
+ phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
+ | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
+ phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
+ | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
+ ret_val = e1000_write_phy_reg(hw,
+ M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
+ if (ret_val)
+ return ret_val;
+ }
}
/* SW Reset the PHY so all changes take effect */
ret_val = e1000_phy_reset(hw);
- if (ret_val < 0) {
+ if (ret_val) {
DEBUGOUT("Error Resetting the PHY\n");
return ret_val;
}
- /* Options:
- * autoneg = 1 (default)
- * PHY will advertise value(s) parsed from
- * autoneg_advertised and fc
- * autoneg = 0
- * PHY will be set to 10H, 10F, 100H, or 100F
- * depending on value parsed from forced_speed_duplex.
- */
+ return E1000_SUCCESS;
+}
+
+/********************************************************************
+* Setup auto-negotiation and flow control advertisements,
+* and then perform auto-negotiation.
+*
+* hw - Struct containing variables accessed by shared code
+*********************************************************************/
+static int32_t
+e1000_copper_link_autoneg(struct e1000_hw *hw)
+{
+ int32_t ret_val;
+ uint16_t phy_data;
+
+ DEBUGFUNC();
- /* Is autoneg enabled? This is enabled by default or by software override.
- * If so, call e1000_phy_setup_autoneg routine to parse the
- * autoneg_advertised and fc options. If autoneg is NOT enabled, then the
- * user should have provided a speed/duplex override. If so, then call
- * e1000_phy_force_speed_duplex to parse and set this up.
- */
/* Perform some bounds checking on the hw->autoneg_advertised
* parameter. If this variable is zero, then set it to the default.
*/
@@ -1298,9 +2846,13 @@ e1000_setup_copper_link(struct eth_device *nic)
if (hw->autoneg_advertised == 0)
hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+ /* IFE phy only supports 10/100 */
+ if (hw->phy_type == e1000_phy_ife)
+ hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
+
DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
ret_val = e1000_phy_setup_autoneg(hw);
- if (ret_val < 0) {
+ if (ret_val) {
DEBUGOUT("Error Setting up Auto-Negotiation\n");
return ret_val;
}
@@ -1309,82 +2861,177 @@ e1000_setup_copper_link(struct eth_device *nic)
/* Restart auto-negotiation by setting the Auto Neg Enable bit and
* the Auto Neg Restart bit in the PHY control register.
*/
- if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
+ if (ret_val)
+ return ret_val;
+
phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
- if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
- }
-#if 0
+ ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
+ if (ret_val)
+ return ret_val;
+
/* Does the user want to wait for Auto-Neg to complete here, or
* check at a later time (for example, callback routine).
*/
+ /* If we do not wait for autonegtation to complete I
+ * do not see a valid link status.
+ * wait_autoneg_complete = 1 .
+ */
if (hw->wait_autoneg_complete) {
ret_val = e1000_wait_autoneg(hw);
- if (ret_val < 0) {
- DEBUGOUT
- ("Error while waiting for autoneg to complete\n");
+ if (ret_val) {
+ DEBUGOUT("Error while waiting for autoneg"
+ "to complete\n");
return ret_val;
}
}
-#else
- /* If we do not wait for autonegtation to complete I
- * do not see a valid link status.
- */
- ret_val = e1000_wait_autoneg(hw);
- if (ret_val < 0) {
- DEBUGOUT("Error while waiting for autoneg to complete\n");
+
+ hw->get_link_status = TRUE;
+
+ return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Config the MAC and the PHY after link is up.
+* 1) Set up the MAC to the current PHY speed/duplex
+* if we are on 82543. If we
+* are on newer silicon, we only need to configure
+* collision distance in the Transmit Control Register.
+* 2) Set up flow control on the MAC to that established with
+* the link partner.
+* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+static int32_t
+e1000_copper_link_postconfig(struct e1000_hw *hw)
+{
+ int32_t ret_val;
+ DEBUGFUNC();
+
+ if (hw->mac_type >= e1000_82544) {
+ e1000_config_collision_dist(hw);
+ } else {
+ ret_val = e1000_config_mac_to_phy(hw);
+ if (ret_val) {
+ DEBUGOUT("Error configuring MAC to PHY settings\n");
+ return ret_val;
+ }
+ }
+ ret_val = e1000_config_fc_after_link_up(hw);
+ if (ret_val) {
+ DEBUGOUT("Error Configuring Flow Control\n");
return ret_val;
}
-#endif
+ return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Detects which PHY is present and setup the speed and duplex
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+static int
+e1000_setup_copper_link(struct eth_device *nic)
+{
+ struct e1000_hw *hw = nic->priv;
+ int32_t ret_val;
+ uint16_t i;
+ uint16_t phy_data;
+ uint16_t reg_data;
+
+ DEBUGFUNC();
+
+ switch (hw->mac_type) {
+ case e1000_80003es2lan:
+ case e1000_ich8lan:
+ /* Set the mac to wait the maximum time between each
+ * iteration and increase the max iterations when
+ * polling the phy; this fixes erroneous timeouts at 10Mbps. */
+ ret_val = e1000_write_kmrn_reg(hw,
+ GG82563_REG(0x34, 4), 0xFFFF);
+ if (ret_val)
+ return ret_val;
+ ret_val = e1000_read_kmrn_reg(hw,
+ GG82563_REG(0x34, 9), &reg_data);
+ if (ret_val)
+ return ret_val;
+ reg_data |= 0x3F;
+ ret_val = e1000_write_kmrn_reg(hw,
+ GG82563_REG(0x34, 9), reg_data);
+ if (ret_val)
+ return ret_val;
+ default:
+ break;
+ }
+
+ /* Check if it is a valid PHY and set PHY mode if necessary. */
+ ret_val = e1000_copper_link_preconfig(hw);
+ if (ret_val)
+ return ret_val;
+ switch (hw->mac_type) {
+ case e1000_80003es2lan:
+ /* Kumeran registers are written-only */
+ reg_data =
+ E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
+ reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
+ ret_val = e1000_write_kmrn_reg(hw,
+ E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
+ if (ret_val)
+ return ret_val;
+ break;
+ default:
+ break;
+ }
+
+ if (hw->phy_type == e1000_phy_igp ||
+ hw->phy_type == e1000_phy_igp_3 ||
+ hw->phy_type == e1000_phy_igp_2) {
+ ret_val = e1000_copper_link_igp_setup(hw);
+ if (ret_val)
+ return ret_val;
+ } else if (hw->phy_type == e1000_phy_m88) {
+ ret_val = e1000_copper_link_mgp_setup(hw);
+ if (ret_val)
+ return ret_val;
+ } else if (hw->phy_type == e1000_phy_gg82563) {
+ ret_val = e1000_copper_link_ggp_setup(hw);
+ if (ret_val)
+ return ret_val;
+ }
+
+ /* always auto */
+ /* Setup autoneg and flow control advertisement
+ * and perform autonegotiation */
+ ret_val = e1000_copper_link_autoneg(hw);
+ if (ret_val)
+ return ret_val;
/* Check link status. Wait up to 100 microseconds for link to become
* valid.
*/
for (i = 0; i < 10; i++) {
- if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if (ret_val)
+ return ret_val;
+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if (ret_val)
+ return ret_val;
+
if (phy_data & MII_SR_LINK_STATUS) {
- /* We have link, so we need to finish the config process:
- * 1) Set up the MAC to the current PHY speed/duplex
- * if we are on 82543. If we
- * are on newer silicon, we only need to configure
- * collision distance in the Transmit Control Register.
- * 2) Set up flow control on the MAC to that established with
- * the link partner.
- */
- if (hw->mac_type >= e1000_82544) {
- e1000_config_collision_dist(hw);
- } else {
- ret_val = e1000_config_mac_to_phy(hw);
- if (ret_val < 0) {
- DEBUGOUT
- ("Error configuring MAC to PHY settings\n");
- return ret_val;
- }
- }
- ret_val = e1000_config_fc_after_link_up(hw);
- if (ret_val < 0) {
- DEBUGOUT("Error Configuring Flow Control\n");
+ /* Config the MAC and PHY after link is up */
+ ret_val = e1000_copper_link_postconfig(hw);
+ if (ret_val)
return ret_val;
- }
+
DEBUGOUT("Valid link established!!!\n");
- return 0;
+ return E1000_SUCCESS;
}
udelay(10);
}
DEBUGOUT("Unable to establish link!!!\n");
- return -E1000_ERR_NOLINK;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -1392,25 +3039,28 @@ e1000_setup_copper_link(struct eth_device *nic)
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
-static int
+int32_t
e1000_phy_setup_autoneg(struct e1000_hw *hw)
{
+ int32_t ret_val;
uint16_t mii_autoneg_adv_reg;
uint16_t mii_1000t_ctrl_reg;
DEBUGFUNC();
/* Read the MII Auto-Neg Advertisement Register (Address 4). */
- if (e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
+ if (ret_val)
+ return ret_val;
- /* Read the MII 1000Base-T Control Register (Address 9). */
- if (e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if (hw->phy_type != e1000_phy_ife) {
+ /* Read the MII 1000Base-T Control Register (Address 9). */
+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
+ &mii_1000t_ctrl_reg);
+ if (ret_val)
+ return ret_val;
+ } else
+ mii_1000t_ctrl_reg = 0;
/* Need to parse both autoneg_advertised and fc and set up
* the appropriate PHY registers. First we will parse for
@@ -1421,7 +3071,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
/* First we clear all the 10/100 mb speed bits in the Auto-Neg
* Advertisement Register (Address 4) and the 1000 mb speed bits in
- * the 1000Base-T Control Register (Address 9).
+ * the 1000Base-T Control Register (Address 9).
*/
mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
@@ -1517,18 +3167,20 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
return -E1000_ERR_CONFIG;
}
- if (e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
- }
+ ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
+ if (ret_val)
+ return ret_val;
DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
- if (e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
+ if (hw->phy_type != e1000_phy_ife) {
+ ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
+ mii_1000t_ctrl_reg);
+ if (ret_val)
+ return ret_val;
}
- return 0;
+
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -1542,12 +3194,19 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
static void
e1000_config_collision_dist(struct e1000_hw *hw)
{
- uint32_t tctl;
+ uint32_t tctl, coll_dist;
+
+ DEBUGFUNC();
+
+ if (hw->mac_type < e1000_82543)
+ coll_dist = E1000_COLLISION_DISTANCE_82542;
+ else
+ coll_dist = E1000_COLLISION_DISTANCE;
tctl = E1000_READ_REG(hw, TCTL);
tctl &= ~E1000_TCTL_COLD;
- tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
+ tctl |= coll_dist << E1000_COLD_SHIFT;
E1000_WRITE_REG(hw, TCTL, tctl);
E1000_WRITE_FLUSH(hw);
@@ -1681,7 +3340,7 @@ e1000_force_mac_fc(struct e1000_hw *hw)
* based on the flow control negotiated by the PHY. In TBI mode, the TFCE
* and RFCE bits will be automaticaly set to the negotiated flow control mode.
*****************************************************************************/
-static int
+static int32_t
e1000_config_fc_after_link_up(struct e1000_hw *hw)
{
int32_t ret_val;
@@ -1697,7 +3356,11 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
* so we had to force link. In this case, we need to force the
* configuration of the MAC to match the "fc" parameter.
*/
- if ((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) {
+ if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
+ || ((hw->media_type == e1000_media_type_internal_serdes)
+ && (hw->autoneg_failed))
+ || ((hw->media_type == e1000_media_type_copper)
+ && (!hw->autoneg))) {
ret_val = e1000_force_mac_fc(hw);
if (ret_val < 0) {
DEBUGOUT("Error forcing flow control settings\n");
@@ -1881,7 +3544,7 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
("Copper PHY and Auto Neg has not completed.\r\n");
}
}
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -2070,17 +3733,92 @@ e1000_check_for_link(struct eth_device *nic)
}
/******************************************************************************
+* Configure the MAC-to-PHY interface for 10/100Mbps
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+static int32_t
+e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
+{
+ int32_t ret_val = E1000_SUCCESS;
+ uint32_t tipg;
+ uint16_t reg_data;
+
+ DEBUGFUNC();
+
+ reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
+ ret_val = e1000_write_kmrn_reg(hw,
+ E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
+ if (ret_val)
+ return ret_val;
+
+ /* Configure Transmit Inter-Packet Gap */
+ tipg = E1000_READ_REG(hw, TIPG);
+ tipg &= ~E1000_TIPG_IPGT_MASK;
+ tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
+ E1000_WRITE_REG(hw, TIPG, tipg);
+
+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
+
+ if (ret_val)
+ return ret_val;
+
+ if (duplex == HALF_DUPLEX)
+ reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
+ else
+ reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
+
+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
+
+ return ret_val;
+}
+
+static int32_t
+e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
+{
+ int32_t ret_val = E1000_SUCCESS;
+ uint16_t reg_data;
+ uint32_t tipg;
+
+ DEBUGFUNC();
+
+ reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
+ ret_val = e1000_write_kmrn_reg(hw,
+ E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
+ if (ret_val)
+ return ret_val;
+
+ /* Configure Transmit Inter-Packet Gap */
+ tipg = E1000_READ_REG(hw, TIPG);
+ tipg &= ~E1000_TIPG_IPGT_MASK;
+ tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
+ E1000_WRITE_REG(hw, TIPG, tipg);
+
+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
+
+ if (ret_val)
+ return ret_val;
+
+ reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
+
+ return ret_val;
+}
+
+/******************************************************************************
* Detects the current speed and duplex settings of the hardware.
*
* hw - Struct containing variables accessed by shared code
* speed - Speed of the connection
* duplex - Duplex setting of the connection
*****************************************************************************/
-static void
-e1000_get_speed_and_duplex(struct e1000_hw *hw,
- uint16_t * speed, uint16_t * duplex)
+static int
+e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
+ uint16_t *duplex)
{
uint32_t status;
+ int32_t ret_val;
+ uint16_t phy_data;
DEBUGFUNC();
@@ -2109,6 +3847,41 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
*speed = SPEED_1000;
*duplex = FULL_DUPLEX;
}
+
+ /* IGP01 PHY may advertise full duplex operation after speed downgrade
+ * even if it is operating at half duplex. Here we set the duplex
+ * settings to match the duplex in the link partner's capabilities.
+ */
+ if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
+ ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
+ *duplex = HALF_DUPLEX;
+ else {
+ ret_val = e1000_read_phy_reg(hw,
+ PHY_LP_ABILITY, &phy_data);
+ if (ret_val)
+ return ret_val;
+ if ((*speed == SPEED_100 &&
+ !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
+ || (*speed == SPEED_10
+ && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
+ *duplex = HALF_DUPLEX;
+ }
+ }
+
+ if ((hw->mac_type == e1000_80003es2lan) &&
+ (hw->media_type == e1000_media_type_copper)) {
+ if (*speed == SPEED_1000)
+ ret_val = e1000_configure_kmrn_for_1000(hw);
+ else
+ ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
+ if (ret_val)
+ return ret_val;
+ }
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -2429,30 +4202,132 @@ e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
}
/******************************************************************************
+ * Checks if PHY reset is blocked due to SOL/IDER session, for example.
+ * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
+ * the caller to figure out how to deal with it.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * returns: - E1000_BLK_PHY_RESET
+ * E1000_SUCCESS
+ *
+ *****************************************************************************/
+int32_t
+e1000_check_phy_reset_block(struct e1000_hw *hw)
+{
+ uint32_t manc = 0;
+ uint32_t fwsm = 0;
+
+ if (hw->mac_type == e1000_ich8lan) {
+ fwsm = E1000_READ_REG(hw, FWSM);
+ return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
+ : E1000_BLK_PHY_RESET;
+ }
+
+ if (hw->mac_type > e1000_82547_rev_2)
+ manc = E1000_READ_REG(hw, MANC);
+ return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
+ E1000_BLK_PHY_RESET : E1000_SUCCESS;
+}
+
+/***************************************************************************
+ * Checks if the PHY configuration is done
+ *
+ * hw: Struct containing variables accessed by shared code
+ *
+ * returns: - E1000_ERR_RESET if fail to reset MAC
+ * E1000_SUCCESS at any other case.
+ *
+ ***************************************************************************/
+static int32_t
+e1000_get_phy_cfg_done(struct e1000_hw *hw)
+{
+ int32_t timeout = PHY_CFG_TIMEOUT;
+ uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
+
+ DEBUGFUNC();
+
+ switch (hw->mac_type) {
+ default:
+ mdelay(10);
+ break;
+ case e1000_80003es2lan:
+ /* Separate *_CFG_DONE_* bit for each port */
+ if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
+ cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
+ /* Fall Through */
+ case e1000_82571:
+ case e1000_82572:
+ while (timeout) {
+ if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
+ break;
+ else
+ mdelay(1);
+ timeout--;
+ }
+ if (!timeout) {
+ DEBUGOUT("MNG configuration cycle has not "
+ "completed.\n");
+ return -E1000_ERR_RESET;
+ }
+ break;
+ }
+
+ return E1000_SUCCESS;
+}
+
+/******************************************************************************
* Returns the PHY to the power-on reset state
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
-static void
+int32_t
e1000_phy_hw_reset(struct e1000_hw *hw)
{
- uint32_t ctrl;
- uint32_t ctrl_ext;
+ uint32_t ctrl, ctrl_ext;
+ uint32_t led_ctrl;
+ int32_t ret_val;
+ uint16_t swfw;
DEBUGFUNC();
+ /* In the case of the phy reset being blocked, it's not an error, we
+ * simply return success without performing the reset. */
+ ret_val = e1000_check_phy_reset_block(hw);
+ if (ret_val)
+ return E1000_SUCCESS;
+
DEBUGOUT("Resetting Phy...\n");
if (hw->mac_type > e1000_82543) {
+ if ((hw->mac_type == e1000_80003es2lan) &&
+ (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
+ swfw = E1000_SWFW_PHY1_SM;
+ } else {
+ swfw = E1000_SWFW_PHY0_SM;
+ }
+ if (e1000_swfw_sync_acquire(hw, swfw)) {
+ DEBUGOUT("Unable to acquire swfw sync\n");
+ return -E1000_ERR_SWFW_SYNC;
+ }
/* Read the device control register and assert the E1000_CTRL_PHY_RST
* bit. Then, take it out of reset.
*/
ctrl = E1000_READ_REG(hw, CTRL);
E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
E1000_WRITE_FLUSH(hw);
- mdelay(10);
+
+ if (hw->mac_type < e1000_82571)
+ udelay(10);
+ else
+ udelay(100);
+
E1000_WRITE_REG(hw, CTRL, ctrl);
E1000_WRITE_FLUSH(hw);
+
+ if (hw->mac_type >= e1000_82571)
+ mdelay(10);
+
} else {
/* Read the Extended Device Control Register, assert the PHY_RESET_DIR
* bit to put the PHY into reset. Then, take it out of reset.
@@ -2468,6 +4343,127 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
E1000_WRITE_FLUSH(hw);
}
udelay(150);
+
+ if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+ /* Configure activity LED after PHY reset */
+ led_ctrl = E1000_READ_REG(hw, LEDCTL);
+ led_ctrl &= IGP_ACTIVITY_LED_MASK;
+ led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
+ E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
+ }
+
+ /* Wait for FW to finish PHY configuration. */
+ ret_val = e1000_get_phy_cfg_done(hw);
+ if (ret_val != E1000_SUCCESS)
+ return ret_val;
+
+ return ret_val;
+}
+
+/******************************************************************************
+ * IGP phy init script - initializes the GbE PHY
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static void
+e1000_phy_init_script(struct e1000_hw *hw)
+{
+ uint32_t ret_val;
+ uint16_t phy_saved_data;
+ DEBUGFUNC();
+
+ if (hw->phy_init_script) {
+ mdelay(20);
+
+ /* Save off the current value of register 0x2F5B to be
+ * restored at the end of this routine. */
+ ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
+
+ /* Disabled the PHY transmitter */
+ e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
+
+ mdelay(20);
+
+ e1000_write_phy_reg(hw, 0x0000, 0x0140);
+
+ mdelay(5);
+
+ switch (hw->mac_type) {
+ case e1000_82541:
+ case e1000_82547:
+ e1000_write_phy_reg(hw, 0x1F95, 0x0001);
+
+ e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
+
+ e1000_write_phy_reg(hw, 0x1F79, 0x0018);
+
+ e1000_write_phy_reg(hw, 0x1F30, 0x1600);
+
+ e1000_write_phy_reg(hw, 0x1F31, 0x0014);
+
+ e1000_write_phy_reg(hw, 0x1F32, 0x161C);
+
+ e1000_write_phy_reg(hw, 0x1F94, 0x0003);
+
+ e1000_write_phy_reg(hw, 0x1F96, 0x003F);
+
+ e1000_write_phy_reg(hw, 0x2010, 0x0008);
+ break;
+
+ case e1000_82541_rev_2:
+ case e1000_82547_rev_2:
+ e1000_write_phy_reg(hw, 0x1F73, 0x0099);
+ break;
+ default:
+ break;
+ }
+
+ e1000_write_phy_reg(hw, 0x0000, 0x3300);
+
+ mdelay(20);
+
+ /* Now enable the transmitter */
+ e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
+
+ if (hw->mac_type == e1000_82547) {
+ uint16_t fused, fine, coarse;
+
+ /* Move to analog registers page */
+ e1000_read_phy_reg(hw,
+ IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
+
+ if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
+ e1000_read_phy_reg(hw,
+ IGP01E1000_ANALOG_FUSE_STATUS, &fused);
+
+ fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
+ coarse = fused
+ & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
+
+ if (coarse >
+ IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
+ coarse -=
+ IGP01E1000_ANALOG_FUSE_COARSE_10;
+ fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
+ } else if (coarse
+ == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
+ fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
+
+ fused = (fused
+ & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
+ (fine
+ & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
+ (coarse
+ & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
+
+ e1000_write_phy_reg(hw,
+ IGP01E1000_ANALOG_FUSE_CONTROL, fused);
+ e1000_write_phy_reg(hw,
+ IGP01E1000_ANALOG_FUSE_BYPASS,
+ IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
+ }
+ }
+ }
}
/******************************************************************************
@@ -2475,26 +4471,49 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
*
* hw - Struct containing variables accessed by shared code
*
-* Sets bit 15 of the MII Control regiser
+* Sets bit 15 of the MII Control register
******************************************************************************/
-static int
+int32_t
e1000_phy_reset(struct e1000_hw *hw)
{
+ int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC();
- if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- phy_data |= MII_CR_RESET;
- if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
+ /* In the case of the phy reset being blocked, it's not an error, we
+ * simply return success without performing the reset. */
+ ret_val = e1000_check_phy_reset_block(hw);
+ if (ret_val)
+ return E1000_SUCCESS;
+
+ switch (hw->phy_type) {
+ case e1000_phy_igp:
+ case e1000_phy_igp_2:
+ case e1000_phy_igp_3:
+ case e1000_phy_ife:
+ ret_val = e1000_phy_hw_reset(hw);
+ if (ret_val)
+ return ret_val;
+ break;
+ default:
+ ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ phy_data |= MII_CR_RESET;
+ ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
+ if (ret_val)
+ return ret_val;
+
+ udelay(1);
+ break;
}
- udelay(1);
- return 0;
+
+ if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
+ e1000_phy_init_script(hw);
+
+ return E1000_SUCCESS;
}
static int e1000_set_phy_type (struct e1000_hw *hw)
@@ -2508,14 +4527,31 @@ static int e1000_set_phy_type (struct e1000_hw *hw)
case M88E1000_E_PHY_ID:
case M88E1000_I_PHY_ID:
case M88E1011_I_PHY_ID:
+ case M88E1111_I_PHY_ID:
hw->phy_type = e1000_phy_m88;
break;
case IGP01E1000_I_PHY_ID:
if (hw->mac_type == e1000_82541 ||
- hw->mac_type == e1000_82541_rev_2) {
+ hw->mac_type == e1000_82541_rev_2 ||
+ hw->mac_type == e1000_82547 ||
+ hw->mac_type == e1000_82547_rev_2) {
+ hw->phy_type = e1000_phy_igp;
hw->phy_type = e1000_phy_igp;
break;
}
+ case IGP03E1000_E_PHY_ID:
+ hw->phy_type = e1000_phy_igp_3;
+ break;
+ case IFE_E_PHY_ID:
+ case IFE_PLUS_E_PHY_ID:
+ case IFE_C_E_PHY_ID:
+ hw->phy_type = e1000_phy_ife;
+ break;
+ case GG82563_E_PHY_ID:
+ if (hw->mac_type == e1000_80003es2lan) {
+ hw->phy_type = e1000_phy_gg82563;
+ break;
+ }
/* Fall Through */
default:
/* Should never have loaded on this device */
@@ -2531,27 +4567,47 @@ static int e1000_set_phy_type (struct e1000_hw *hw)
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
-static int
+static int32_t
e1000_detect_gig_phy(struct e1000_hw *hw)
{
- int32_t phy_init_status;
+ int32_t phy_init_status, ret_val;
uint16_t phy_id_high, phy_id_low;
- int match = FALSE;
+ boolean_t match = FALSE;
DEBUGFUNC();
- /* Read the PHY ID Registers to identify which PHY is onboard. */
- if (e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
+ /* The 82571 firmware may still be configuring the PHY. In this
+ * case, we cannot access the PHY until the configuration is done. So
+ * we explicitly set the PHY values. */
+ if (hw->mac_type == e1000_82571 ||
+ hw->mac_type == e1000_82572) {
+ hw->phy_id = IGP01E1000_I_PHY_ID;
+ hw->phy_type = e1000_phy_igp_2;
+ return E1000_SUCCESS;
}
+
+ /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
+ * work- around that forces PHY page 0 to be set or the reads fail.
+ * The rest of the code in this routine uses e1000_read_phy_reg to
+ * read the PHY ID. So for ESB-2 we need to have this set so our
+ * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
+ * the routines below will figure this out as well. */
+ if (hw->mac_type == e1000_80003es2lan)
+ hw->phy_type = e1000_phy_gg82563;
+
+ /* Read the PHY ID Registers to identify which PHY is onboard. */
+ ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
+ if (ret_val)
+ return ret_val;
+
hw->phy_id = (uint32_t) (phy_id_high << 16);
- udelay(2);
- if (e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ udelay(20);
+ ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
+ if (ret_val)
+ return ret_val;
+
hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
+ hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
switch (hw->mac_type) {
case e1000_82543:
@@ -2564,15 +4620,38 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
break;
case e1000_82540:
case e1000_82545:
+ case e1000_82545_rev_3:
case e1000_82546:
+ case e1000_82546_rev_3:
if (hw->phy_id == M88E1011_I_PHY_ID)
match = TRUE;
break;
+ case e1000_82541:
case e1000_82541_rev_2:
+ case e1000_82547:
+ case e1000_82547_rev_2:
if(hw->phy_id == IGP01E1000_I_PHY_ID)
match = TRUE;
break;
+ case e1000_82573:
+ if (hw->phy_id == M88E1111_I_PHY_ID)
+ match = TRUE;
+ break;
+ case e1000_80003es2lan:
+ if (hw->phy_id == GG82563_E_PHY_ID)
+ match = TRUE;
+ break;
+ case e1000_ich8lan:
+ if (hw->phy_id == IGP03E1000_E_PHY_ID)
+ match = TRUE;
+ if (hw->phy_id == IFE_E_PHY_ID)
+ match = TRUE;
+ if (hw->phy_id == IFE_PLUS_E_PHY_ID)
+ match = TRUE;
+ if (hw->phy_id == IFE_C_E_PHY_ID)
+ match = TRUE;
+ break;
default:
DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
return -E1000_ERR_CONFIG;
@@ -2588,6 +4667,60 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
return -E1000_ERR_PHY;
}
+/*****************************************************************************
+ * Set media type and TBI compatibility.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * **************************************************************************/
+void
+e1000_set_media_type(struct e1000_hw *hw)
+{
+ uint32_t status;
+
+ DEBUGFUNC();
+
+ if (hw->mac_type != e1000_82543) {
+ /* tbi_compatibility is only valid on 82543 */
+ hw->tbi_compatibility_en = FALSE;
+ }
+
+ switch (hw->device_id) {
+ case E1000_DEV_ID_82545GM_SERDES:
+ case E1000_DEV_ID_82546GB_SERDES:
+ case E1000_DEV_ID_82571EB_SERDES:
+ case E1000_DEV_ID_82571EB_SERDES_DUAL:
+ case E1000_DEV_ID_82571EB_SERDES_QUAD:
+ case E1000_DEV_ID_82572EI_SERDES:
+ case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
+ hw->media_type = e1000_media_type_internal_serdes;
+ break;
+ default:
+ switch (hw->mac_type) {
+ case e1000_82542_rev2_0:
+ case e1000_82542_rev2_1:
+ hw->media_type = e1000_media_type_fiber;
+ break;
+ case e1000_ich8lan:
+ case e1000_82573:
+ /* The STATUS_TBIMODE bit is reserved or reused
+ * for the this device.
+ */
+ hw->media_type = e1000_media_type_copper;
+ break;
+ default:
+ status = E1000_READ_REG(hw, STATUS);
+ if (status & E1000_STATUS_TBIMODE) {
+ hw->media_type = e1000_media_type_fiber;
+ /* tbi_compatibility not valid on fiber */
+ hw->tbi_compatibility_en = FALSE;
+ } else {
+ hw->media_type = e1000_media_type_copper;
+ }
+ break;
+ }
+ }
+}
+
/**
* e1000_sw_init - Initialize general software structures (struct e1000_adapter)
*
@@ -2619,6 +4752,17 @@ e1000_sw_init(struct eth_device *nic, int cardnum)
return result;
}
+ switch (hw->mac_type) {
+ default:
+ break;
+ case e1000_82541:
+ case e1000_82547:
+ case e1000_82541_rev_2:
+ case e1000_82547_rev_2:
+ hw->phy_init_script = 1;
+ break;
+ }
+
/* lan a vs. lan b settings */
if (hw->mac_type == e1000_82546)
/*this also works w/ multiple 82546 cards */
@@ -2634,6 +4778,7 @@ e1000_sw_init(struct eth_device *nic, int cardnum)
hw->fc_send_xon = 1;
/* Media type - copper or fiber */
+ e1000_set_media_type(hw);
if (hw->mac_type >= e1000_82543) {
uint32_t status = E1000_READ_REG(hw, STATUS);
@@ -2649,22 +4794,13 @@ e1000_sw_init(struct eth_device *nic, int cardnum)
hw->media_type = e1000_media_type_fiber;
}
+ hw->tbi_compatibility_en = TRUE;
+ hw->wait_autoneg_complete = TRUE;
if (hw->mac_type < e1000_82543)
hw->report_tx_early = 0;
else
hw->report_tx_early = 1;
- hw->tbi_compatibility_en = TRUE;
-#if 0
- hw->wait_autoneg_complete = FALSE;
- hw->adaptive_ifs = TRUE;
-
- /* Copper options */
- if (hw->media_type == e1000_media_type_copper) {
- hw->mdix = AUTO_ALL_MODES;
- hw->disable_polarity_correction = FALSE;
- }
-#endif
return E1000_SUCCESS;
}
@@ -2693,7 +4829,8 @@ e1000_configure_tx(struct e1000_hw *hw)
{
unsigned long ptr;
unsigned long tctl;
- unsigned long tipg;
+ unsigned long tipg, tarc;
+ uint32_t ipgr1, ipgr2;
ptr = (u32) tx_pool;
if (ptr & 0xf)
@@ -2712,45 +4849,64 @@ e1000_configure_tx(struct e1000_hw *hw)
tx_tail = 0;
/* Set the default values for the Tx Inter Packet Gap timer */
+ if (hw->mac_type <= e1000_82547_rev_2 &&
+ (hw->media_type == e1000_media_type_fiber ||
+ hw->media_type == e1000_media_type_internal_serdes))
+ tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
+ else
+ tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
+
+ /* Set the default values for the Tx Inter Packet Gap timer */
switch (hw->mac_type) {
case e1000_82542_rev2_0:
case e1000_82542_rev2_1:
tipg = DEFAULT_82542_TIPG_IPGT;
- tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
- tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
+ ipgr1 = DEFAULT_82542_TIPG_IPGR1;
+ ipgr2 = DEFAULT_82542_TIPG_IPGR2;
+ break;
+ case e1000_80003es2lan:
+ ipgr1 = DEFAULT_82543_TIPG_IPGR1;
+ ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
break;
default:
- if (hw->media_type == e1000_media_type_fiber)
- tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
- else
- tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
- tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
- tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
+ ipgr1 = DEFAULT_82543_TIPG_IPGR1;
+ ipgr2 = DEFAULT_82543_TIPG_IPGR2;
+ break;
}
+ tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
+ tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
E1000_WRITE_REG(hw, TIPG, tipg);
-#if 0
- /* Set the Tx Interrupt Delay register */
- E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
- if (hw->mac_type >= e1000_82540)
- E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
-#endif
/* Program the Transmit Control Register */
tctl = E1000_READ_REG(hw, TCTL);
tctl &= ~E1000_TCTL_CT;
tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
- E1000_WRITE_REG(hw, TCTL, tctl);
+
+ if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
+ tarc = E1000_READ_REG(hw, TARC0);
+ /* set the speed mode bit, we'll clear it if we're not at
+ * gigabit link later */
+ /* git bit can be set to 1*/
+ } else if (hw->mac_type == e1000_80003es2lan) {
+ tarc = E1000_READ_REG(hw, TARC0);
+ tarc |= 1;
+ E1000_WRITE_REG(hw, TARC0, tarc);
+ tarc = E1000_READ_REG(hw, TARC1);
+ tarc |= 1;
+ E1000_WRITE_REG(hw, TARC1, tarc);
+ }
+
e1000_config_collision_dist(hw);
-#if 0
- /* Setup Transmit Descriptor Settings for this adapter */
- adapter->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_IDE;
+ /* Setup Transmit Descriptor Settings for eop descriptor */
+ hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
- if (adapter->hw.report_tx_early == 1)
- adapter->txd_cmd |= E1000_TXD_CMD_RS;
+ /* Need to set up RS bit */
+ if (hw->mac_type < e1000_82543)
+ hw->txd_cmd |= E1000_TXD_CMD_RPS;
else
- adapter->txd_cmd |= E1000_TXD_CMD_RPS;
-#endif
+ hw->txd_cmd |= E1000_TXD_CMD_RS;
+ E1000_WRITE_REG(hw, TCTL, tctl);
}
/**
@@ -2766,8 +4922,9 @@ e1000_setup_rctl(struct e1000_hw *hw)
rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
- rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF; /* |
- (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
+ rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
+ | E1000_RCTL_RDMTS_HALF; /* |
+ (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
if (hw->tbi_compatibility_on == 1)
rctl |= E1000_RCTL_SBP;
@@ -2775,26 +4932,8 @@ e1000_setup_rctl(struct e1000_hw *hw)
rctl &= ~E1000_RCTL_SBP;
rctl &= ~(E1000_RCTL_SZ_4096);
-#if 0
- switch (adapter->rx_buffer_len) {
- case E1000_RXBUFFER_2048:
- default:
-#endif
rctl |= E1000_RCTL_SZ_2048;
rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
-#if 0
- break;
- case E1000_RXBUFFER_4096:
- rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
- break;
- case E1000_RXBUFFER_8192:
- rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
- break;
- case E1000_RXBUFFER_16384:
- rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
- break;
- }
-#endif
E1000_WRITE_REG(hw, RCTL, rctl);
}
@@ -2808,23 +4947,12 @@ static void
e1000_configure_rx(struct e1000_hw *hw)
{
unsigned long ptr;
- unsigned long rctl;
-#if 0
- unsigned long rxcsum;
-#endif
+ unsigned long rctl, ctrl_ext;
rx_tail = 0;
/* make sure receives are disabled while setting up the descriptors */
rctl = E1000_READ_REG(hw, RCTL);
E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
-#if 0
- /* set the Receive Delay Timer Register */
-
- E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
-#endif
if (hw->mac_type >= e1000_82540) {
-#if 0
- E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
-#endif
/* Set the interrupt throttling rate. Value is calculated
* as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
#define MAX_INTS_PER_SEC 8000
@@ -2832,6 +4960,13 @@ e1000_configure_rx(struct e1000_hw *hw)
E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
}
+ if (hw->mac_type >= e1000_82571) {
+ ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
+ /* Reset delay timers after every interrupt */
+ ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
+ E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+ E1000_WRITE_FLUSH(hw);
+ }
/* Setup the Base and Length of the Rx Descriptor Ring */
ptr = (u32) rx_pool;
if (ptr & 0xf)
@@ -2845,14 +4980,6 @@ e1000_configure_rx(struct e1000_hw *hw)
/* Setup the HW Rx Head and Tail Descriptor Pointers */
E1000_WRITE_REG(hw, RDH, 0);
E1000_WRITE_REG(hw, RDT, 0);
-#if 0
- /* Enable 82543 Receive Checksum Offload for TCP and UDP */
- if ((adapter->hw.mac_type >= e1000_82543) && (adapter->rx_csum == TRUE)) {
- rxcsum = E1000_READ_REG(hw, RXCSUM);
- rxcsum |= E1000_RXCSUM_TUOFL;
- E1000_WRITE_REG(hw, RXCSUM, rxcsum);
- }
-#endif
/* Enable Receives */
E1000_WRITE_REG(hw, RCTL, rctl);
@@ -2891,11 +5018,11 @@ e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
tx_tail = (tx_tail + 1) % 8;
txp->buffer_addr = cpu_to_le64(virt_to_bus(packet));
- txp->lower.data = cpu_to_le32(E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP |
- E1000_TXD_CMD_IFCS | length);
+ txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
txp->upper.data = 0;
E1000_WRITE_REG(hw, TDT, tx_tail);
+ E1000_WRITE_FLUSH(hw);
while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
if (i++ > TOUT_LOOP) {
DEBUGOUT("e1000: tx timeout\n");
@@ -2972,6 +5099,37 @@ e1000_init(struct eth_device *nic, bd_t * bis)
return 1;
}
+/******************************************************************************
+ * Gets the current PCI bus type of hardware
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+void e1000_get_bus_type(struct e1000_hw *hw)
+{
+ uint32_t status;
+
+ switch (hw->mac_type) {
+ case e1000_82542_rev2_0:
+ case e1000_82542_rev2_1:
+ hw->bus_type = e1000_bus_type_pci;
+ break;
+ case e1000_82571:
+ case e1000_82572:
+ case e1000_82573:
+ case e1000_80003es2lan:
+ hw->bus_type = e1000_bus_type_pci_express;
+ break;
+ case e1000_ich8lan:
+ hw->bus_type = e1000_bus_type_pci_express;
+ break;
+ default:
+ status = E1000_READ_REG(hw, STATUS);
+ hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
+ e1000_bus_type_pcix : e1000_bus_type_pci;
+ break;
+ }
+}
+
/**************************************************************************
PROBE - Look for an adapter, this routine's visible to the outside
You should omit the last argument struct pci_device * for a non-PCI NIC
@@ -3017,14 +5175,10 @@ e1000_initialize(bd_t * bis)
sprintf(nic->name, "e1000#%d", card_number);
/* Are these variables needed? */
-#if 0
- hw->fc = e1000_fc_none;
- hw->original_fc = e1000_fc_none;
-#else
hw->fc = e1000_fc_default;
hw->original_fc = e1000_fc_default;
-#endif
hw->autoneg_failed = 0;
+ hw->autoneg = 1;
hw->get_link_status = TRUE;
hw->hw_addr = (typeof(hw->hw_addr)) iobase;
hw->mac_type = e1000_undefined;
@@ -3035,7 +5189,16 @@ e1000_initialize(bd_t * bis)
free(nic);
return 0;
}
+ if (e1000_check_phy_reset_block(hw))
+ printf("phy reset block error \n");
+ e1000_reset_hw(hw);
#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
+ if (e1000_init_eeprom_params(hw)) {
+ printf("The EEPROM Checksum Is Not Valid\n");
+ free(hw);
+ free(nic);
+ return 0;
+ }
if (e1000_validate_eeprom_checksum(nic) < 0) {
printf("The EEPROM Checksum Is Not Valid\n");
free(hw);
@@ -3045,7 +5208,8 @@ e1000_initialize(bd_t * bis)
#endif
e1000_read_mac_addr(nic);
- E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA);
+ /* get the bus type information */
+ e1000_get_bus_type(hw);
printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n",
nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index 08042a8cc..eb0804b41 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -71,9 +71,18 @@ typedef enum {
e1000_82544,
e1000_82540,
e1000_82545,
+ e1000_82545_rev_3,
e1000_82546,
+ e1000_82546_rev_3,
e1000_82541,
e1000_82541_rev_2,
+ e1000_82547,
+ e1000_82547_rev_2,
+ e1000_82571,
+ e1000_82572,
+ e1000_82573,
+ e1000_80003es2lan,
+ e1000_ich8lan,
e1000_num_macs
} e1000_mac_type;
@@ -81,10 +90,21 @@ typedef enum {
typedef enum {
e1000_media_type_copper = 0,
e1000_media_type_fiber = 1,
+ e1000_media_type_internal_serdes = 2,
e1000_num_media_types
} e1000_media_type;
typedef enum {
+ e1000_eeprom_uninitialized = 0,
+ e1000_eeprom_spi,
+ e1000_eeprom_microwire,
+ e1000_eeprom_flash,
+ e1000_eeprom_ich8,
+ e1000_eeprom_none, /* No NVM support */
+ e1000_num_eeprom_types
+} e1000_eeprom_type;
+
+typedef enum {
e1000_10_half = 0,
e1000_10_full = 1,
e1000_100_half = 2,
@@ -109,7 +129,9 @@ typedef enum {
typedef enum {
e1000_bus_type_unknown = 0,
e1000_bus_type_pci,
- e1000_bus_type_pcix
+ e1000_bus_type_pcix,
+ e1000_bus_type_pci_express,
+ e1000_bus_type_reserved
} e1000_bus_type;
/* PCI bus speeds */
@@ -172,10 +194,13 @@ typedef enum {
} e1000_1000t_rx_status;
typedef enum {
- e1000_phy_m88 = 0,
- e1000_phy_igp,
- e1000_phy_igp_2,
- e1000_phy_undefined = 0xFF
+ e1000_phy_m88 = 0,
+ e1000_phy_igp,
+ e1000_phy_igp_2,
+ e1000_phy_gg82563,
+ e1000_phy_igp_3,
+ e1000_phy_ife,
+ e1000_phy_undefined = 0xFF
} e1000_phy_type;
struct e1000_phy_info {
@@ -207,6 +232,7 @@ struct e1000_phy_stats {
#define E1000_ERR_MASTER_REQUESTS_PENDING 10
#define E1000_ERR_HOST_INTERFACE_COMMAND 11
#define E1000_BLK_PHY_RESET 12
+#define E1000_ERR_SWFW_SYNC 13
/* PCI Device IDs */
#define E1000_DEV_ID_82542 0x1000
@@ -217,14 +243,151 @@ struct e1000_phy_stats {
#define E1000_DEV_ID_82544GC_COPPER 0x100C
#define E1000_DEV_ID_82544GC_LOM 0x100D
#define E1000_DEV_ID_82540EM 0x100E
-#define E1000_DEV_ID_82540EM_LOM 0x1015
-#define E1000_DEV_ID_82545GM_COPPER 0x1026
-#define E1000_DEV_ID_82545EM_COPPER 0x100F
-#define E1000_DEV_ID_82545EM_FIBER 0x1011
-#define E1000_DEV_ID_82546EB_COPPER 0x1010
-#define E1000_DEV_ID_82546EB_FIBER 0x1012
-#define E1000_DEV_ID_82541ER 0x1078
-#define E1000_DEV_ID_82541GI_LF 0x107C
+#define E1000_DEV_ID_82540EM_LOM 0x1015
+#define E1000_DEV_ID_82540EP_LOM 0x1016
+#define E1000_DEV_ID_82540EP 0x1017
+#define E1000_DEV_ID_82540EP_LP 0x101E
+#define E1000_DEV_ID_82545EM_COPPER 0x100F
+#define E1000_DEV_ID_82545EM_FIBER 0x1011
+#define E1000_DEV_ID_82545GM_COPPER 0x1026
+#define E1000_DEV_ID_82545GM_FIBER 0x1027
+#define E1000_DEV_ID_82545GM_SERDES 0x1028
+#define E1000_DEV_ID_82546EB_COPPER 0x1010
+#define E1000_DEV_ID_82546EB_FIBER 0x1012
+#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
+#define E1000_DEV_ID_82541EI 0x1013
+#define E1000_DEV_ID_82541EI_MOBILE 0x1018
+#define E1000_DEV_ID_82541ER_LOM 0x1014
+#define E1000_DEV_ID_82541ER 0x1078
+#define E1000_DEV_ID_82547GI 0x1075
+#define E1000_DEV_ID_82541GI 0x1076
+#define E1000_DEV_ID_82541GI_MOBILE 0x1077
+#define E1000_DEV_ID_82541GI_LF 0x107C
+#define E1000_DEV_ID_82546GB_COPPER 0x1079
+#define E1000_DEV_ID_82546GB_FIBER 0x107A
+#define E1000_DEV_ID_82546GB_SERDES 0x107B
+#define E1000_DEV_ID_82546GB_PCIE 0x108A
+#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
+#define E1000_DEV_ID_82547EI 0x1019
+#define E1000_DEV_ID_82547EI_MOBILE 0x101A
+#define E1000_DEV_ID_82571EB_COPPER 0x105E
+#define E1000_DEV_ID_82571EB_FIBER 0x105F
+#define E1000_DEV_ID_82571EB_SERDES 0x1060
+#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
+#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
+#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
+#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
+#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
+#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
+#define E1000_DEV_ID_82572EI_COPPER 0x107D
+#define E1000_DEV_ID_82572EI_FIBER 0x107E
+#define E1000_DEV_ID_82572EI_SERDES 0x107F
+#define E1000_DEV_ID_82572EI 0x10B9
+#define E1000_DEV_ID_82573E 0x108B
+#define E1000_DEV_ID_82573E_IAMT 0x108C
+#define E1000_DEV_ID_82573L 0x109A
+#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
+#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
+#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
+#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
+#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
+
+#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
+#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
+#define E1000_DEV_ID_ICH8_IGP_C 0x104B
+#define E1000_DEV_ID_ICH8_IFE 0x104C
+#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
+#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
+#define E1000_DEV_ID_ICH8_IGP_M 0x104D
+
+#define IGP03E1000_E_PHY_ID 0x02A80390
+#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
+#define IFE_PLUS_E_PHY_ID 0x02A80320
+#define IFE_C_E_PHY_ID 0x02A80310
+
+#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status,
+ Control and Address */
+#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special
+ control register */
+#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False
+ Carrier Counter */
+#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet
+ Counter */
+#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error
+ Frame Counter */
+#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error
+ Counter */
+#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive
+ Premature End Of Frame
+ Error Counter */
+#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of
+ Frame Error Counter */
+#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber
+ Detect Counter */
+#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and
+ Status */
+#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and
+ LED configuration */
+#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
+#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control
+ (HWI) */
+
+#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto
+ reduced power down */
+#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power
+ state of 100BASE-TX */
+#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power
+ state of 10BASE-T */
+#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T
+ polarity */
+#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY
+ address */
+#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed
+ result 1=100Mbs, 0=10Mbs */
+#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation
+ duplex result 1=Full, 0=Half */
+#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
+
+#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down
+ disabled */
+#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity,
+ 0=Normal */
+#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity
+ Disabled, 0=Enabled */
+#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled,
+ 0=Normal Jabber Operation */
+#define IFE_PSC_FORCE_POLARITY_SHIFT 5
+#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
+
+#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X
+ feature, default 0=disabled */
+#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X,
+ 0=force MDI */
+#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
+#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm
+ is completed */
+#define IFE_PMC_MDIX_MODE_SHIFT 6
+#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
+
+#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI
+ feature */
+#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed,
+ 0=failed */
+#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses
+ on the wire */
+#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
+#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
+#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication
+ type of problem on the line */
+#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to
+ the cable problem, in 80cm granularity */
+#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
+#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
+#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2
+ off */
+#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
+
+
#define NUM_DEV_IDS 16
#define NODE_ADDRESS_SIZE 6
@@ -235,6 +398,10 @@ struct e1000_phy_stats {
#define E1000_82542_2_0_REV_ID 2
#define E1000_82542_2_1_REV_ID 3
+#define E1000_REVISION_0 0
+#define E1000_REVISION_1 1
+#define E1000_REVISION_2 2
+#define E1000_REVISION_3 3
#define SPEED_10 10
#define SPEED_100 100
@@ -522,11 +689,27 @@ struct e1000_ffvt_entry {
#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
#define E1000_TCTL 0x00400 /* TX Control - RW */
+#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
+#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
+#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
+#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
+#define FEXTNVM_SW_CONFIG 0x0001
#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
+#define E1000_PBS 0x01008 /* Packet Buffer Size */
+#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
+#define E1000_FLASH_UPDATES 1000
+#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
+#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
+#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
+#define E1000_FLSWCTL 0x01030 /* FLASH control register */
+#define E1000_FLSWDATA 0x01034 /* FLASH data register */
+#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
+#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
+#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
@@ -539,6 +722,11 @@ struct e1000_ffvt_entry {
#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
+#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
+#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
+#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
+#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
+#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
@@ -548,6 +736,14 @@ struct e1000_ffvt_entry {
#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
+#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
+#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
+#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
+#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
+#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
+#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
+#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
+#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
@@ -812,6 +1008,44 @@ struct e1000_hw_stats {
uint64_t tsctfc;
};
+struct e1000_eeprom_info {
+ e1000_eeprom_type type;
+ uint16_t word_size;
+ uint16_t opcode_bits;
+ uint16_t address_bits;
+ uint16_t delay_usec;
+ uint16_t page_size;
+ boolean_t use_eerd;
+ boolean_t use_eewr;
+};
+
+typedef enum {
+ e1000_smart_speed_default = 0,
+ e1000_smart_speed_on,
+ e1000_smart_speed_off
+} e1000_smart_speed;
+
+typedef enum {
+ e1000_dsp_config_disabled = 0,
+ e1000_dsp_config_enabled,
+ e1000_dsp_config_activated,
+ e1000_dsp_config_undefined = 0xFF
+} e1000_dsp_config;
+
+typedef enum {
+ e1000_ms_hw_default = 0,
+ e1000_ms_force_master,
+ e1000_ms_force_slave,
+ e1000_ms_auto
+} e1000_ms_type;
+
+typedef enum {
+ e1000_ffe_config_enabled = 0,
+ e1000_ffe_config_active,
+ e1000_ffe_config_blocked
+} e1000_ffe_config;
+
+
/* Structure containing variables used by the shared code (e1000_hw.c) */
struct e1000_hw {
pci_dev_t pdev;
@@ -819,16 +1053,26 @@ struct e1000_hw {
e1000_mac_type mac_type;
e1000_phy_type phy_type;
uint32_t phy_init_script;
+ uint32_t txd_cmd;
e1000_media_type media_type;
e1000_lan_loc lan_loc;
e1000_fc_type fc;
+ e1000_bus_type bus_type;
#if 0
e1000_bus_speed bus_speed;
e1000_bus_width bus_width;
- e1000_bus_type bus_type;
uint32_t io_base;
#endif
+ uint32_t asf_firmware_present;
+ uint32_t eeprom_semaphore_present;
+ uint32_t swfw_sync_present;
+ uint32_t swfwhw_semaphore_present;
+ struct e1000_eeprom_info eeprom;
+ e1000_ms_type master_slave;
+ e1000_ms_type original_master_slave;
+ e1000_ffe_config ffe_config_state;
uint32_t phy_id;
+ uint32_t phy_revision;
uint32_t phy_addr;
uint32_t original_fc;
uint32_t txcw;
@@ -861,31 +1105,45 @@ struct e1000_hw {
uint16_t subsystem_id;
uint16_t subsystem_vendor_id;
uint8_t revision_id;
-#if 0
uint8_t autoneg;
uint8_t mdix;
uint8_t forced_speed_duplex;
uint8_t wait_autoneg_complete;
uint8_t dma_fairness;
-#endif
#if 0
uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
- boolean_t disable_polarity_correction;
#endif
+ boolean_t disable_polarity_correction;
+ boolean_t speed_downgraded;
boolean_t get_link_status;
boolean_t tbi_compatibility_en;
boolean_t tbi_compatibility_on;
+ boolean_t fc_strict_ieee;
boolean_t fc_send_xon;
boolean_t report_tx_early;
+ boolean_t phy_reset_disable;
+ boolean_t initialize_hw_bits_disable;
#if 0
boolean_t adaptive_ifs;
boolean_t ifs_params_forced;
boolean_t in_ifs_mode;
#endif
+ e1000_smart_speed smart_speed;
+ e1000_dsp_config dsp_config_state;
};
#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
+#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM
+ read/write registers */
+#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
+#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start
+ operation */
+#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
+#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write
+ complete */
+#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
+#define EEPROM_RESERVED_WORD 0xFFFF
/* Register Bit Masks */
/* Device Control */
@@ -957,6 +1215,30 @@ struct e1000_hw {
#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
+#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
+ * (0-small, 1-large) */
+
+#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
+#ifndef E1000_EEPROM_GRANT_ATTEMPTS
+#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
+#endif
+#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
+#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
+#define E1000_EECD_SIZE_EX_SHIFT 11
+#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
+#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
+#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
+#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
+#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
+#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
+#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
+#define E1000_EECD_SECVAL_SHIFT 22
+#define E1000_STM_OPCODE 0xDB00
+#define E1000_HICR_FW_RESET 0xC0
+
+#define E1000_SHADOW_RAM_WORDS 2048
+#define E1000_ICH_NVM_SIG_WORD 0x13
+#define E1000_ICH_NVM_SIG_MASK 0xC0
/* EEPROM Read */
#define E1000_EERD_START 0x00000001 /* Start Read */
@@ -966,14 +1248,62 @@ struct e1000_hw {
#define E1000_EERD_DATA_SHIFT 16
#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
+/* EEPROM Commands - Microwire */
+#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
+#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
+#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
+#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
+#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
+
+/* EEPROM Commands - SPI */
+#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
+#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
+#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
+#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
+#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
+#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
+#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
+#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
+#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
+#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
+#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
+
+/* EEPROM Size definitions */
+#define EEPROM_WORD_SIZE_SHIFT 6
+#define EEPROM_SIZE_SHIFT 10
+#define EEPROM_SIZE_MASK 0x1C00
+
+/* EEPROM Word Offsets */
+#define EEPROM_COMPAT 0x0003
+#define EEPROM_ID_LED_SETTINGS 0x0004
+#define EEPROM_VERSION 0x0005
+#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude
+ adjustment. */
+#define EEPROM_PHY_CLASS_WORD 0x0007
+#define EEPROM_INIT_CONTROL1_REG 0x000A
+#define EEPROM_INIT_CONTROL2_REG 0x000F
+#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
+#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
+#define EEPROM_INIT_3GIO_3 0x001A
+#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
+#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
+#define EEPROM_CFG 0x0012
+#define EEPROM_FLASH_VERSION 0x0032
+#define EEPROM_CHECKSUM_REG 0x003F
+
+#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
+#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
+
/* Extended Device Control */
#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
-#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
-#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
+#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable
+ Pin 4 */
+#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable
+ Pin 5 */
#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
#define E1000_CTRL_EXT_SWDPIN6 0x00000040 /* SWDPIN 6 value */
@@ -989,6 +1319,7 @@ struct e1000_hw {
#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
+#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
@@ -1010,6 +1341,12 @@ struct e1000_hw {
#define E1000_MDIC_INT_EN 0x20000000
#define E1000_MDIC_ERROR 0x40000000
+#define E1000_PHY_CTRL_SPD_EN 0x00000001
+#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
+#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
+#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
+#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
+#define E1000_PHY_CTRL_B2B_EN 0x00000080
/* LED Control */
#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
#define E1000_LEDCTL_LED0_MODE_SHIFT 0
@@ -1153,6 +1490,12 @@ struct e1000_hw {
#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
+/* SW_W_SYNC definitions */
+#define E1000_SWFW_EEP_SM 0x0001
+#define E1000_SWFW_PHY0_SM 0x0002
+#define E1000_SWFW_PHY1_SM 0x0004
+#define E1000_SWFW_MAC_CSR_SM 0x0008
+
/* Receive Descriptor */
#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
@@ -1173,12 +1516,14 @@ struct e1000_hw {
#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
/* Transmit Descriptor Control */
-#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
-#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
-#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
+#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
+#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
+#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
+#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
+ still to be processed. */
/* Transmit Configuration Word */
#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
@@ -1212,6 +1557,7 @@ struct e1000_hw {
#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
+#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
/* Receive Checksum Control */
#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
@@ -1349,9 +1695,10 @@ struct e1000_hw {
#define PBA_SIZE 4
/* Collision related configuration parameters */
-#define E1000_COLLISION_THRESHOLD 16
+#define E1000_COLLISION_THRESHOLD 0xF
#define E1000_CT_SHIFT 4
-#define E1000_COLLISION_DISTANCE 64
+#define E1000_COLLISION_DISTANCE 63
+#define E1000_COLLISION_DISTANCE_82542 64
#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
#define E1000_GB_HDX_COLLISION_DISTANCE 512
@@ -1376,6 +1723,7 @@ struct e1000_hw {
#define DEFAULT_82542_TIPG_IPGR2 10
#define DEFAULT_82543_TIPG_IPGR2 6
+#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
#define E1000_TIPG_IPGR2_SHIFT 20
#define E1000_TXDMAC_DPP 0x00000001
@@ -1396,6 +1744,7 @@ struct e1000_hw {
/* PBA constants */
#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
#define E1000_PBA_24K 0x0018
+#define E1000_PBA_38K 0x0026
#define E1000_PBA_40K 0x0028
#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
@@ -1537,8 +1886,22 @@ struct e1000_hw {
#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
+#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
+#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
+
#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
+/* M88EC018 Rev 2 specific DownShift settings */
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
+
/* IGP01E1000 specifics */
#define IGP01E1000_IEEE_REGS_PAGE 0x0000
#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
@@ -1554,6 +1917,290 @@ struct e1000_hw {
#define IGP02E1000_PHY_POWER_MGMT 0x19
#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
+/* IGP01E1000 AGC Registers - stores the cable length values*/
+#define IGP01E1000_PHY_AGC_A 0x1172
+#define IGP01E1000_PHY_AGC_B 0x1272
+#define IGP01E1000_PHY_AGC_C 0x1472
+#define IGP01E1000_PHY_AGC_D 0x1872
+
+/* IGP01E1000 Specific Port Config Register - R/W */
+#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
+#define IGP01E1000_PSCFR_PRE_EN 0x0020
+#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
+#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
+#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
+#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
+/* IGP02E1000 AGC Registers for cable length values */
+#define IGP02E1000_PHY_AGC_A 0x11B1
+#define IGP02E1000_PHY_AGC_B 0x12B1
+#define IGP02E1000_PHY_AGC_C 0x14B1
+#define IGP02E1000_PHY_AGC_D 0x18B1
+
+#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
+#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in
+ non-D0a modes */
+#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in
+ D0a mode */
+
+/* IGP01E1000 DSP Reset Register */
+#define IGP01E1000_PHY_DSP_RESET 0x1F33
+#define IGP01E1000_PHY_DSP_SET 0x1F71
+#define IGP01E1000_PHY_DSP_FFE 0x1F35
+
+#define IGP01E1000_PHY_CHANNEL_NUM 4
+#define IGP02E1000_PHY_CHANNEL_NUM 4
+
+#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
+#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
+#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
+#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
+
+#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
+#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
+
+#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
+#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
+#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
+#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
+
+#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
+/* IGP01E1000 PCS Initialization register - stores the polarity status when
+ * speed = 1000 Mbps. */
+#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
+#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
+
+#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
+
+/* IGP01E1000 GMII FIFO Register */
+#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
+ * on Link-Up */
+#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
+
+/* IGP01E1000 Analog Register */
+#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
+#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
+#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
+#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
+
+#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
+#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
+#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
+#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
+#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
+
+#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
+#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
+#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
+#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
+
+/* IGP01E1000 Specific Port Control Register - R/W */
+#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
+#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
+#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
+#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
+#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
+#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
+/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
+#define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */
+#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal
+ Disabled */
+#define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */
+#define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter
+ Disabled */
+#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
+#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI
+ configuration */
+#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX
+ configuration */
+#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic
+ crossover */
+#define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended
+ Distance */
+#define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300
+#define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */
+#define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only
+ (Energy Detect) */
+#define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */
+#define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */
+#define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */
+#define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000
+#define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12
+
+/* PHY Specific Status Register (Page 0, Register 17) */
+#define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */
+#define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */
+#define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */
+#define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */
+#define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */
+#define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */
+#define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */
+#define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */
+#define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */
+#define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */
+#define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */
+#define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */
+#define GG82563_PSSR_SPEED_MASK 0xC000
+#define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */
+#define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */
+#define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */
+
+/* PHY Specific Status Register 2 (Page 0, Register 19) */
+#define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */
+#define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */
+#define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
+#define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */
+#define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */
+#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */
+#define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */
+#define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */
+#define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
+#define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */
+#define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */
+#define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */
+#define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */
+
+/* PHY Specific Control Register 2 (Page 0, Register 26) */
+#define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative
+ Polarity */
+#define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C
+#define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal
+ Operation */
+#define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns
+ Sequence */
+#define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns
+ Sequence */
+#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse
+ Auto-Negotiation */
+#define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable
+ 1000BASE-T */
+#define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000
+#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */
+#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */
+
+/* MAC Specific Control Register (Page 2, Register 21) */
+/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
+#define GG82563_MSCR_TX_CLK_MASK 0x0007
+#define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004
+#define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005
+#define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006
+#define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007
+
+#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
+
+/* DSP Distance Register (Page 5, Register 26) */
+#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
+ 1 = 50-80M;
+ 2 = 80-110M;
+ 3 = 110-140M;
+ 4 = >140M */
+
+/* Kumeran Mode Control Register (Page 193, Register 16) */
+#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs,
+ 0=Kumeran Inband LEDs */
+#define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */
+#define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080
+#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400
+#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz,
+ 0=0.8MHz */
+#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
+
+/* Power Management Control Register (Page 193, Register 20) */
+#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES
+ Electrical Idle */
+#define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */
+#define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */
+#define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse
+ Auto-Negotiation */
+#define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps
+ Auto-Neg in non D0 */
+#define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps
+ Auto-Neg Always */
+#define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a
+ Reverse Auto-Negotiation */
+#define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */
+#define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300
+#define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */
+#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */
+#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */
+#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */
+
+/* In-Band Control Register (Page 194, Register 18) */
+#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */
+
+
+/* Bits...
+ * 15-5: page
+ * 4-0: register offset
+ */
+#define GG82563_PAGE_SHIFT 5
+#define GG82563_REG(page, reg) \
+ (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
+#define GG82563_MIN_ALT_REG 30
+
+/* GG82563 Specific Registers */
+#define GG82563_PHY_SPEC_CTRL \
+ GG82563_REG(0, 16) /* PHY Specific Control */
+#define GG82563_PHY_SPEC_STATUS \
+ GG82563_REG(0, 17) /* PHY Specific Status */
+#define GG82563_PHY_INT_ENABLE \
+ GG82563_REG(0, 18) /* Interrupt Enable */
+#define GG82563_PHY_SPEC_STATUS_2 \
+ GG82563_REG(0, 19) /* PHY Specific Status 2 */
+#define GG82563_PHY_RX_ERR_CNTR \
+ GG82563_REG(0, 21) /* Receive Error Counter */
+#define GG82563_PHY_PAGE_SELECT \
+ GG82563_REG(0, 22) /* Page Select */
+#define GG82563_PHY_SPEC_CTRL_2 \
+ GG82563_REG(0, 26) /* PHY Specific Control 2 */
+#define GG82563_PHY_PAGE_SELECT_ALT \
+ GG82563_REG(0, 29) /* Alternate Page Select */
+#define GG82563_PHY_TEST_CLK_CTRL \
+ GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
+
+#define GG82563_PHY_MAC_SPEC_CTRL \
+ GG82563_REG(2, 21) /* MAC Specific Control Register */
+#define GG82563_PHY_MAC_SPEC_CTRL_2 \
+ GG82563_REG(2, 26) /* MAC Specific Control 2 */
+
+#define GG82563_PHY_DSP_DISTANCE \
+ GG82563_REG(5, 26) /* DSP Distance */
+
+/* Page 193 - Port Control Registers */
+#define GG82563_PHY_KMRN_MODE_CTRL \
+ GG82563_REG(193, 16) /* Kumeran Mode Control */
+#define GG82563_PHY_PORT_RESET \
+ GG82563_REG(193, 17) /* Port Reset */
+#define GG82563_PHY_REVISION_ID \
+ GG82563_REG(193, 18) /* Revision ID */
+#define GG82563_PHY_DEVICE_ID \
+ GG82563_REG(193, 19) /* Device ID */
+#define GG82563_PHY_PWR_MGMT_CTRL \
+ GG82563_REG(193, 20) /* Power Management Control */
+#define GG82563_PHY_RATE_ADAPT_CTRL \
+ GG82563_REG(193, 25) /* Rate Adaptation Control */
+
+/* Page 194 - KMRN Registers */
+#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
+ GG82563_REG(194, 16) /* FIFO's Control/Status */
+#define GG82563_PHY_KMRN_CTRL \
+ GG82563_REG(194, 17) /* Control */
+#define GG82563_PHY_INBAND_CTRL \
+ GG82563_REG(194, 18) /* Inband Control */
+#define GG82563_PHY_KMRN_DIAGNOSTIC \
+ GG82563_REG(194, 19) /* Diagnostic */
+#define GG82563_PHY_ACK_TIMEOUTS \
+ GG82563_REG(194, 20) /* Acknowledge Timeouts */
+#define GG82563_PHY_ADV_ABILITY \
+ GG82563_REG(194, 21) /* Advertised Ability */
+#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
+ GG82563_REG(194, 23) /* Link Partner Advertised Ability */
+#define GG82563_PHY_ADV_NEXT_PAGE \
+ GG82563_REG(194, 24) /* Advertised Next Page */
+#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
+ GG82563_REG(194, 25) /* Link Partner Advertised Next page */
+#define GG82563_PHY_KMRN_MISC \
+ GG82563_REG(194, 26) /* Misc. */
+
/* PHY Control Register */
#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
@@ -1765,6 +2412,10 @@ struct e1000_hw {
#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
#define IGP01E1000_I_PHY_ID 0x02A80380
+#define M88E1011_I_REV_4 0x04
+#define M88E1111_I_PHY_ID 0x01410CC0
+#define L1LXT971A_PHY_ID 0x001378E0
+#define GG82563_E_PHY_ID 0x01410CA0
/* Miscellaneous PHY bit definitions. */
#define PHY_PREAMBLE 0xFFFFFFFF
@@ -1791,4 +2442,142 @@ struct e1000_hw {
#define ADVERTISE_1000_FULL 0x0020
#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
+#define ICH_FLASH_GFPREG 0x0000
+#define ICH_FLASH_HSFSTS 0x0004
+#define ICH_FLASH_HSFCTL 0x0006
+#define ICH_FLASH_FADDR 0x0008
+#define ICH_FLASH_FDATA0 0x0010
+#define ICH_FLASH_FRACC 0x0050
+#define ICH_FLASH_FREG0 0x0054
+#define ICH_FLASH_FREG1 0x0058
+#define ICH_FLASH_FREG2 0x005C
+#define ICH_FLASH_FREG3 0x0060
+#define ICH_FLASH_FPR0 0x0074
+#define ICH_FLASH_FPR1 0x0078
+#define ICH_FLASH_SSFSTS 0x0090
+#define ICH_FLASH_SSFCTL 0x0092
+#define ICH_FLASH_PREOP 0x0094
+#define ICH_FLASH_OPTYPE 0x0096
+#define ICH_FLASH_OPMENU 0x0098
+
+#define ICH_FLASH_REG_MAPSIZE 0x00A0
+#define ICH_FLASH_SECTOR_SIZE 4096
+#define ICH_GFPREG_BASE_MASK 0x1FFF
+#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
+
+#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
+#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
+
+/* SPI EEPROM Status Register */
+#define EEPROM_STATUS_RDY_SPI 0x01
+#define EEPROM_STATUS_WEN_SPI 0x02
+#define EEPROM_STATUS_BP0_SPI 0x04
+#define EEPROM_STATUS_BP1_SPI 0x08
+#define EEPROM_STATUS_WPEN_SPI 0x80
+
+/* SW Semaphore Register */
+#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
+#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
+#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
+#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
+
+/* FW Semaphore Register */
+#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
+#define E1000_FWSM_MODE_SHIFT 1
+#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
+
+#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
+#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
+#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
+#define E1000_FWSM_SKUEL_SHIFT 29
+#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
+#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
+#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
+#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
+
+#define E1000_GCR 0x05B00 /* PCI-Ex Control */
+#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
+#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
+#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
+#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
+#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
+#define E1000_SWSM 0x05B50 /* SW Semaphore */
+#define E1000_FWSM 0x05B54 /* FW Semaphore */
+#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
+#define E1000_HICR 0x08F00 /* Host Inteface Control */
+
+#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
+#define IGP_ACTIVITY_LED_ENABLE 0x0300
+#define IGP_LED3_MODE 0x07000000
+
+/* Mask bit for PHY class in Word 7 of the EEPROM */
+#define EEPROM_PHY_CLASS_A 0x8000
+#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
+#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
+#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
+
+#define E1000_KUMCTRLSTA_MASK 0x0000FFFF
+#define E1000_KUMCTRLSTA_OFFSET 0x001F0000
+#define E1000_KUMCTRLSTA_OFFSET_SHIFT 16
+#define E1000_KUMCTRLSTA_REN 0x00200000
+
+#define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
+#define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001
+#define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
+#define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003
+#define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
+#define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
+#define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
+#define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
+#define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
+
+/* FIFO Control */
+#define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
+#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
+
+/* In-Band Control */
+#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
+#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
+
+/* Half-Duplex Control */
+#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
+#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
+
+#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
+
+#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
+#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
+
+#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
+#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
+#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
+
+#define E1000_MNG_ICH_IAMT_MODE 0x2
+#define E1000_MNG_IAMT_MODE 0x3
+#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
+#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
+/* Number of milliseconds we wait for PHY configuration done after MAC reset */
+#define PHY_CFG_TIMEOUT 100
+#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
+#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008
+#define E1000_TXDMAC_DPP 0x00000001
+#define AUTO_ALL_MODES 0
+
+#ifndef E1000_MASTER_SLAVE
+/* Switch to override PHY master/slave setting */
+#define E1000_MASTER_SLAVE e1000_ms_hw_default
+#endif
+/* Extended Transmit Control */
+#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
+#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
+
+#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
+
+#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
+
+#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
+#define E1000_MC_TBL_SIZE_ICH8LAN 32
+
+#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers
+ after IMS clear */
#endif /* _E1000_HW_H_ */
diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c
new file mode 100644
index 000000000..2328cb51d
--- /dev/null
+++ b/drivers/net/ftmac100.c
@@ -0,0 +1,278 @@
+/*
+ * Faraday FTMAC100 Ethernet
+ *
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+
+#include "ftmac100.h"
+
+#define ETH_ZLEN 60
+
+struct ftmac100_data {
+ volatile struct ftmac100_txdes txdes[1];
+ volatile struct ftmac100_rxdes rxdes[PKTBUFSRX];
+ int rx_index;
+};
+
+/*
+ * Reset MAC
+ */
+static void ftmac100_reset (struct eth_device *dev)
+{
+ struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
+
+ debug ("%s()\n", __func__);
+
+ writel (FTMAC100_MACCR_SW_RST, &ftmac100->maccr);
+
+ while (readl (&ftmac100->maccr) & FTMAC100_MACCR_SW_RST)
+ ;
+}
+
+/*
+ * Set MAC address
+ */
+static void ftmac100_set_mac (struct eth_device *dev, const unsigned char *mac)
+{
+ struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
+ unsigned int maddr = mac[0] << 8 | mac[1];
+ unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
+
+ debug ("%s(%x %x)\n", __func__, maddr, laddr);
+
+ writel (maddr, &ftmac100->mac_madr);
+ writel (laddr, &ftmac100->mac_ladr);
+}
+
+static void ftmac100_set_mac_from_env (struct eth_device *dev)
+{
+ eth_getenv_enetaddr ("ethaddr", dev->enetaddr);
+
+ ftmac100_set_mac (dev, dev->enetaddr);
+}
+
+/*
+ * disable transmitter, receiver
+ */
+static void ftmac100_halt (struct eth_device *dev)
+{
+ struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
+
+ debug ("%s()\n", __func__);
+
+ writel (0, &ftmac100->maccr);
+}
+
+static int ftmac100_init (struct eth_device *dev, bd_t *bd)
+{
+ struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
+ struct ftmac100_data *priv = dev->priv;
+ volatile struct ftmac100_txdes *txdes = priv->txdes;
+ volatile struct ftmac100_rxdes *rxdes = priv->rxdes;
+ unsigned int maccr;
+ int i;
+
+ debug ("%s()\n", __func__);
+
+ ftmac100_reset (dev);
+
+ /* set the ethernet address */
+
+ ftmac100_set_mac_from_env (dev);
+
+ /* disable all interrupts */
+
+ writel (0, &ftmac100->imr);
+
+ /* initialize descriptors */
+
+ priv->rx_index = 0;
+
+ txdes[0].txdes1 = FTMAC100_TXDES1_EDOTR;
+ rxdes[PKTBUFSRX - 1].rxdes1 = FTMAC100_RXDES1_EDORR;
+
+ for (i = 0; i < PKTBUFSRX; i++) {
+ /* RXBUF_BADR */
+ rxdes[i].rxdes2 = (unsigned int)NetRxPackets[i];
+ rxdes[i].rxdes1 |= FTMAC100_RXDES1_RXBUF_SIZE (PKTSIZE_ALIGN);
+ rxdes[i].rxdes0 = FTMAC100_RXDES0_RXDMA_OWN;
+ }
+
+ /* transmit ring */
+
+ writel ((unsigned int)txdes, &ftmac100->txr_badr);
+
+ /* receive ring */
+
+ writel ((unsigned int)rxdes, &ftmac100->rxr_badr);
+
+ /* poll receive descriptor automatically */
+
+ writel (FTMAC100_APTC_RXPOLL_CNT (1), &ftmac100->aptc);
+
+ /* enable transmitter, receiver */
+
+ maccr = FTMAC100_MACCR_XMT_EN |
+ FTMAC100_MACCR_RCV_EN |
+ FTMAC100_MACCR_XDMA_EN |
+ FTMAC100_MACCR_RDMA_EN |
+ FTMAC100_MACCR_CRC_APD |
+ FTMAC100_MACCR_ENRX_IN_HALFTX |
+ FTMAC100_MACCR_RX_RUNT |
+ FTMAC100_MACCR_RX_BROADPKT;
+
+ writel (maccr, &ftmac100->maccr);
+
+ return 0;
+}
+
+/*
+ * Get a data block via Ethernet
+ */
+static int ftmac100_recv (struct eth_device *dev)
+{
+ struct ftmac100_data *priv = dev->priv;
+ volatile struct ftmac100_rxdes *curr_des;
+ unsigned short rxlen;
+
+ curr_des = &priv->rxdes[priv->rx_index];
+
+ if (curr_des->rxdes0 & FTMAC100_RXDES0_RXDMA_OWN)
+ return -1;
+
+ if (curr_des->rxdes0 & (FTMAC100_RXDES0_RX_ERR |
+ FTMAC100_RXDES0_CRC_ERR |
+ FTMAC100_RXDES0_FTL |
+ FTMAC100_RXDES0_RUNT |
+ FTMAC100_RXDES0_RX_ODD_NB)) {
+ return -1;
+ }
+
+ rxlen = FTMAC100_RXDES0_RFL (curr_des->rxdes0);
+
+ debug ("%s(): RX buffer %d, %x received\n",
+ __func__, priv->rx_index, rxlen);
+
+ /* pass the packet up to the protocol layers. */
+
+ NetReceive ((void *)curr_des->rxdes2, rxlen);
+
+ /* release buffer to DMA */
+
+ curr_des->rxdes0 |= FTMAC100_RXDES0_RXDMA_OWN;
+
+ priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
+
+ return 0;
+}
+
+/*
+ * Send a data block via Ethernet
+ */
+static int
+ftmac100_send (struct eth_device *dev, volatile void *packet, int length)
+{
+ struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
+ struct ftmac100_data *priv = dev->priv;
+ volatile struct ftmac100_txdes *curr_des = priv->txdes;
+ int tmo;
+
+ if (curr_des->txdes0 & FTMAC100_TXDES0_TXDMA_OWN) {
+ debug ("%s(): no TX descriptor available\n", __func__);
+ return -1;
+ }
+
+ debug ("%s(%x, %x)\n", __func__, (int)packet, length);
+
+ length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
+
+ /* initiate a transmit sequence */
+
+ curr_des->txdes2 = (unsigned int)packet; /* TXBUF_BADR */
+
+ curr_des->txdes1 &= FTMAC100_TXDES1_EDOTR;
+ curr_des->txdes1 |= FTMAC100_TXDES1_FTS |
+ FTMAC100_TXDES1_LTS |
+ FTMAC100_TXDES1_TXBUF_SIZE (length);
+
+ curr_des->txdes0 = FTMAC100_TXDES0_TXDMA_OWN;
+
+ /* start transmit */
+
+ writel (1, &ftmac100->txpd);
+
+ /* wait for transfer to succeed */
+
+ tmo = get_timer (0) + 5 * CONFIG_SYS_HZ;
+ while (curr_des->txdes0 & FTMAC100_TXDES0_TXDMA_OWN) {
+ if (get_timer (0) >= tmo) {
+ debug ("%s(): timed out\n", __func__);
+ return -1;
+ }
+ }
+
+ debug ("%s(): packet sent\n", __func__);
+
+ return 0;
+}
+
+int ftmac100_initialize (bd_t *bd)
+{
+ struct eth_device *dev;
+ struct ftmac100_data *priv;
+
+ dev = malloc (sizeof *dev);
+ if (!dev) {
+ printf ("%s(): failed to allocate dev\n", __func__);
+ goto out;
+ }
+
+ /* Transmit and receive descriptors should align to 16 bytes */
+
+ priv = memalign (16, sizeof (struct ftmac100_data));
+ if (!priv) {
+ printf ("%s(): failed to allocate priv\n", __func__);
+ goto free_dev;
+ }
+
+ memset (dev, 0, sizeof (*dev));
+ memset (priv, 0, sizeof (*priv));
+
+ sprintf (dev->name, "FTMAC100");
+ dev->iobase = CONFIG_FTMAC100_BASE;
+ dev->init = ftmac100_init;
+ dev->halt = ftmac100_halt;
+ dev->send = ftmac100_send;
+ dev->recv = ftmac100_recv;
+ dev->priv = priv;
+
+ eth_register (dev);
+
+ return 1;
+
+free_dev:
+ free (dev);
+out:
+ return 0;
+}
diff --git a/drivers/net/ftmac100.h b/drivers/net/ftmac100.h
new file mode 100644
index 000000000..21142d966
--- /dev/null
+++ b/drivers/net/ftmac100.h
@@ -0,0 +1,154 @@
+/*
+ * Faraday FTMAC100 Ethernet
+ *
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __FTMAC100_H
+#define __FTMAC100_H
+
+struct ftmac100 {
+ unsigned int isr; /* 0x00 */
+ unsigned int imr; /* 0x04 */
+ unsigned int mac_madr; /* 0x08 */
+ unsigned int mac_ladr; /* 0x0c */
+ unsigned int maht0; /* 0x10 */
+ unsigned int maht1; /* 0x14 */
+ unsigned int txpd; /* 0x18 */
+ unsigned int rxpd; /* 0x1c */
+ unsigned int txr_badr; /* 0x20 */
+ unsigned int rxr_badr; /* 0x24 */
+ unsigned int itc; /* 0x28 */
+ unsigned int aptc; /* 0x2c */
+ unsigned int dblac; /* 0x30 */
+ unsigned int pad1[3]; /* 0x34 - 0x3c */
+ unsigned int pad2[16]; /* 0x40 - 0x7c */
+ unsigned int pad3[2]; /* 0x80 - 0x84 */
+ unsigned int maccr; /* 0x88 */
+ unsigned int macsr; /* 0x8c */
+ unsigned int phycr; /* 0x90 */
+ unsigned int phywdata; /* 0x94 */
+ unsigned int fcr; /* 0x98 */
+ unsigned int bpr; /* 0x9c */
+ unsigned int pad4[8]; /* 0xa0 - 0xbc */
+ unsigned int pad5; /* 0xc0 */
+ unsigned int ts; /* 0xc4 */
+ unsigned int dmafifos; /* 0xc8 */
+ unsigned int tm; /* 0xcc */
+ unsigned int pad6; /* 0xd0 */
+ unsigned int tx_mcol_scol; /* 0xd4 */
+ unsigned int rpf_aep; /* 0xd8 */
+ unsigned int xm_pg; /* 0xdc */
+ unsigned int runt_tlcc; /* 0xe0 */
+ unsigned int crcer_ftl; /* 0xe4 */
+ unsigned int rlc_rcc; /* 0xe8 */
+ unsigned int broc; /* 0xec */
+ unsigned int mulca; /* 0xf0 */
+ unsigned int rp; /* 0xf4 */
+ unsigned int xp; /* 0xf8 */
+};
+
+/*
+ * Interrupt status register & interrupt mask register
+ */
+#define FTMAC100_INT_RPKT_FINISH (1 << 0)
+#define FTMAC100_INT_NORXBUF (1 << 1)
+#define FTMAC100_INT_XPKT_FINISH (1 << 2)
+#define FTMAC100_INT_NOTXBUF (1 << 3)
+#define FTMAC100_INT_XPKT_OK (1 << 4)
+#define FTMAC100_INT_XPKT_LOST (1 << 5)
+#define FTMAC100_INT_RPKT_SAV (1 << 6)
+#define FTMAC100_INT_RPKT_LOST (1 << 7)
+#define FTMAC100_INT_AHB_ERR (1 << 8)
+#define FTMAC100_INT_PHYSTS_CHG (1 << 9)
+
+/*
+ * Automatic polling timer control register
+ */
+#define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
+#define FTMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
+#define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
+#define FTMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
+
+/*
+ * MAC control register
+ */
+#define FTMAC100_MACCR_XDMA_EN (1 << 0)
+#define FTMAC100_MACCR_RDMA_EN (1 << 1)
+#define FTMAC100_MACCR_SW_RST (1 << 2)
+#define FTMAC100_MACCR_LOOP_EN (1 << 3)
+#define FTMAC100_MACCR_CRC_DIS (1 << 4)
+#define FTMAC100_MACCR_XMT_EN (1 << 5)
+#define FTMAC100_MACCR_ENRX_IN_HALFTX (1 << 6)
+#define FTMAC100_MACCR_RCV_EN (1 << 8)
+#define FTMAC100_MACCR_HT_MULTI_EN (1 << 9)
+#define FTMAC100_MACCR_RX_RUNT (1 << 10)
+#define FTMAC100_MACCR_RX_FTL (1 << 11)
+#define FTMAC100_MACCR_RCV_ALL (1 << 12)
+#define FTMAC100_MACCR_CRC_APD (1 << 14)
+#define FTMAC100_MACCR_FULLDUP (1 << 15)
+#define FTMAC100_MACCR_RX_MULTIPKT (1 << 16)
+#define FTMAC100_MACCR_RX_BROADPKT (1 << 17)
+
+/*
+ * Transmit descriptor, aligned to 16 bytes
+ */
+struct ftmac100_txdes {
+ unsigned int txdes0;
+ unsigned int txdes1;
+ unsigned int txdes2; /* TXBUF_BADR */
+ unsigned int txdes3; /* not used by HW */
+} __attribute__ ((aligned(16)));
+
+#define FTMAC100_TXDES0_TXPKT_LATECOL (1 << 0)
+#define FTMAC100_TXDES0_TXPKT_EXSCOL (1 << 1)
+#define FTMAC100_TXDES0_TXDMA_OWN (1 << 31)
+
+#define FTMAC100_TXDES1_TXBUF_SIZE(x) ((x) & 0x7ff)
+#define FTMAC100_TXDES1_LTS (1 << 27)
+#define FTMAC100_TXDES1_FTS (1 << 28)
+#define FTMAC100_TXDES1_TX2FIC (1 << 29)
+#define FTMAC100_TXDES1_TXIC (1 << 30)
+#define FTMAC100_TXDES1_EDOTR (1 << 31)
+
+/*
+ * Receive descriptor, aligned to 16 bytes
+ */
+struct ftmac100_rxdes {
+ unsigned int rxdes0;
+ unsigned int rxdes1;
+ unsigned int rxdes2; /* RXBUF_BADR */
+ unsigned int rxdes3; /* not used by HW */
+} __attribute__ ((aligned(16)));
+
+#define FTMAC100_RXDES0_RFL(des) ((des) & 0x7ff)
+#define FTMAC100_RXDES0_MULTICAST (1 << 16)
+#define FTMAC100_RXDES0_BROADCAST (1 << 17)
+#define FTMAC100_RXDES0_RX_ERR (1 << 18)
+#define FTMAC100_RXDES0_CRC_ERR (1 << 19)
+#define FTMAC100_RXDES0_FTL (1 << 20)
+#define FTMAC100_RXDES0_RUNT (1 << 21)
+#define FTMAC100_RXDES0_RX_ODD_NB (1 << 22)
+#define FTMAC100_RXDES0_LRS (1 << 28)
+#define FTMAC100_RXDES0_FRS (1 << 29)
+#define FTMAC100_RXDES0_RXDMA_OWN (1 << 31)
+
+#define FTMAC100_RXDES1_RXBUF_SIZE(x) ((x) & 0x7ff)
+#define FTMAC100_RXDES1_EDORR (1 << 31)
+
+#endif /* __FTMAC100_H */
diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c
index 701812bf1..f31fefcb0 100644
--- a/drivers/net/kirkwood_egiga.c
+++ b/drivers/net/kirkwood_egiga.c
@@ -592,7 +592,7 @@ int kirkwood_egiga_initialize(bd_t * bis)
struct kwgbe_device *dkwgbe;
struct eth_device *dev;
int devnum;
- char *s, buf[NAMESIZE * 2];
+ char *s;
u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
@@ -650,11 +650,14 @@ int kirkwood_egiga_initialize(bd_t * bis)
}
while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
- /* Generate Ramdom MAC addresses if not set */
- sprintf(buf, "00:50:43:%02x:%02x:%02x",
- get_random_hex(), get_random_hex(),
- get_random_hex());
- setenv(s, buf);
+ /* Generate Random Private MAC addr if not set */
+ dev->enetaddr[0] = 0x02;
+ dev->enetaddr[1] = 0x50;
+ dev->enetaddr[2] = 0x43;
+ dev->enetaddr[3] = get_random_hex();
+ dev->enetaddr[4] = get_random_hex();
+ dev->enetaddr[5] = get_random_hex();
+ eth_setenv_enetaddr(s, dev->enetaddr);
}
dev->init = (void *)kwgbe_init;
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
index 29630f5bf..3754e8bdc 100644
--- a/drivers/net/phy/mv88e61xx.c
+++ b/drivers/net/phy/mv88e61xx.c
@@ -38,7 +38,7 @@
*/
static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
{
- u32 reg = 0;
+ u16 reg = 0;
u32 timeout = MV88E61XX_PHY_TIMEOUT;
/* Poll till SMIBusy bit is clear */
@@ -54,8 +54,7 @@ static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
{
- u16 reg;
- u32 mii_dev_addr;
+ u16 mii_dev_addr;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
@@ -73,8 +72,7 @@ static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data)
{
- u16 reg;
- u32 mii_dev_addr;
+ u16 mii_dev_addr;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
@@ -357,15 +355,22 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
}
RD_PHY(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, &reg);
- reg &= 0xfff0;
- if (reg == 0x1610)
+ switch (reg &= 0xfff0) {
+ case 0x1610:
idstr = "88E6161";
- if (reg == 0x1650)
+ break;
+ case 0x1650:
idstr = "88E6165";
- if (reg == 0x1210) {
+ break;
+ case 0x1210:
idstr = "88E6123";
/* ports 2,3,4 not available */
swconfig->ports_enabled &= 0x023;
+ break;
+ default:
+ /* Could not detect switch id */
+ idstr = "88E61??";
+ break;
}
/* Port based VLANs configuration */
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index d48d22b61..db95adaee 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -31,6 +31,11 @@
#include "uec_phy.h"
#include "miiphy.h"
+/* Default UTBIPAR SMI address */
+#ifndef CONFIG_UTBIPAR_INIT_TBIPA
+#define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
+#endif
+
static uec_info_t uec_info[] = {
#ifdef CONFIG_UEC_ETH1
STD_UEC_INFO(1), /* UEC1 */
@@ -1071,15 +1076,11 @@ static int uec_startup(uec_private_t *uec)
utbipar = in_be32(&uec_regs->utbipar);
utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
enet_interface = uec->uec_info->enet_interface;
- if (enet_interface == ENET_1000_TBI ||
- enet_interface == ENET_1000_RTBI) {
- utbipar |= (uec_info->phy_address + uec_info->uf_info.ucc_num)
- << UTBIPAR_PHY_ADDRESS_SHIFT;
- } else {
- utbipar |= (0x10 + uec_info->uf_info.ucc_num)
- << UTBIPAR_PHY_ADDRESS_SHIFT;
- }
+ /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
+ * This frees up the remaining SMI addresses for use.
+ */
+ utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
out_be32(&uec_regs->utbipar, utbipar);
/* Configure the TBI for SGMII operation */
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index d613f3e4c..aa4eb5e38 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -51,27 +51,28 @@
*--------------------------------------------------------------------*/
/*
- * Some boards do not have a PHY for each ethernet port. These ports
- * are known as Fixed PHY (or PHY-less) ports. For such ports, set
- * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
- * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and
- * duplex should be for these ports in the board configuration
- * file.
+ * Some boards do not have a PHY for each ethernet port. These ports are known
+ * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
+ * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
+ * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
+ * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
+ * speed and duplex should be for the port.
*
- * For Example:
+ * Example board header configuration file:
* #define CONFIG_FIXED_PHY 0xFFFFFFFF
+ * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
*
- * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
- * #define CONFIG_PHY1_ADDR 1
- * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY
- * #define CONFIG_PHY3_ADDR 3
+ * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
+ * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02
+ * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
+ * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04
*
- * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \
- * {devnum, speed, duplex},
+ * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
+ * {name, speed, duplex},
*
* #define CONFIG_SYS_FIXED_PHY_PORTS \
- * CONFIG_SYS_FIXED_PHY_PORT(0,SPEED_100,DUPLEX_FULL) \
- * CONFIG_SYS_FIXED_PHY_PORT(2,SPEED_100,DUPLEX_HALF)
+ * CONFIG_SYS_FIXED_PHY_PORT("FSL UEC0",SPEED_100,DUPLEX_FULL) \
+ * CONFIG_SYS_FIXED_PHY_PORT("FSL UEC2",SPEED_100,DUPLEX_HALF)
*/
#ifndef CONFIG_FIXED_PHY
@@ -83,7 +84,7 @@
#endif
struct fixed_phy_port {
- unsigned int devnum; /* ethernet port */
+ char name[NAMESIZE]; /* ethernet port name */
unsigned int speed; /* specified speed 10,100 or 1000 */
unsigned int duplex; /* specified duplex FULL or HALF */
};
@@ -592,7 +593,8 @@ static int fixed_phy_read_status (struct uec_mii_info *mii_info)
int i = 0;
for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
- if (mii_info->mii_id == fixed_phy_port[i].devnum) {
+ if (strncmp(mii_info->dev->name, fixed_phy_port[i].name,
+ strlen(mii_info->dev->name)) == 0) {
mii_info->speed = fixed_phy_port[i].speed;
mii_info->duplex = fixed_phy_port[i].duplex;
mii_info->link = 1; /* Link is always UP */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index a9f67a0ac..824d8e740 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -28,6 +28,7 @@ LIB := $(obj)libspi.a
COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
+COBJS-$(CONFIG_CF_SPI) += cf_spi.o
COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
new file mode 100644
index 000000000..722aafc73
--- /dev/null
+++ b/drivers/spi/cf_spi.c
@@ -0,0 +1,357 @@
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <malloc.h>
+#include <asm/immap.h>
+
+struct cf_spi_slave {
+ struct spi_slave slave;
+ uint baudrate;
+ int charbit;
+};
+
+int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
+ void *din, ulong flags);
+struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode);
+void cfspi_init(void);
+void cfspi_tx(u32 ctrl, u16 data);
+u16 cfspi_rx(void);
+
+extern void cfspi_port_conf(void);
+extern int cfspi_claim_bus(uint bus, uint cs);
+extern void cfspi_release_bus(uint bus, uint cs);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CF_DSPI)
+/* DSPI specific mode */
+#define SPI_MODE_MOD 0x00200000
+#define SPI_DBLRATE 0x00100000
+
+void cfspi_init(void)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ cfspi_port_conf(); /* port configuration */
+
+ dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
+ DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
+ DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
+ DSPI_MCR_CRXF | DSPI_MCR_CTXF;
+
+ /* Default setting in platform configuration */
+#ifdef CONFIG_SYS_DSPI_CTAR0
+ dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
+#endif
+#ifdef CONFIG_SYS_DSPI_CTAR1
+ dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;
+#endif
+#ifdef CONFIG_SYS_DSPI_CTAR2
+ dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;
+#endif
+#ifdef CONFIG_SYS_DSPI_CTAR3
+ dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;
+#endif
+#ifdef CONFIG_SYS_DSPI_CTAR4
+ dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;
+#endif
+#ifdef CONFIG_SYS_DSPI_CTAR5
+ dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;
+#endif
+#ifdef CONFIG_SYS_DSPI_CTAR6
+ dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;
+#endif
+#ifdef CONFIG_SYS_DSPI_CTAR7
+ dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;
+#endif
+}
+
+void cfspi_tx(u32 ctrl, u16 data)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ while ((dspi->sr & 0x0000F000) >= 4) ;
+
+ dspi->tfr = (ctrl | data);
+}
+
+u16 cfspi_rx(void)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ while ((dspi->sr & 0x000000F0) == 0) ;
+
+ return (dspi->rfr & 0xFFFF);
+}
+
+int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
+ void *din, ulong flags)
+{
+ struct cf_spi_slave *cfslave = (struct cf_spi_slave *)slave;
+ u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
+ u8 *spi_rd = NULL, *spi_wr = NULL;
+ static u32 ctrl = 0;
+ uint len = bitlen >> 3;
+
+ if (cfslave->charbit == 16) {
+ bitlen >>= 1;
+ spi_wr16 = (u16 *) dout;
+ spi_rd16 = (u16 *) din;
+ } else {
+ spi_wr = (u8 *) dout;
+ spi_rd = (u8 *) din;
+ }
+
+ if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
+ ctrl |= DSPI_TFR_CONT;
+
+ ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16);
+
+ if (len > 1) {
+ int tmp_len = len - 1;
+ while (tmp_len--) {
+ if (dout != NULL) {
+ if (cfslave->charbit == 16)
+ cfspi_tx(ctrl, *spi_wr16++);
+ else
+ cfspi_tx(ctrl, *spi_wr++);
+ cfspi_rx();
+ }
+
+ if (din != NULL) {
+ cfspi_tx(ctrl, 0);
+ if (cfslave->charbit == 16)
+ *spi_rd16++ = cfspi_rx();
+ else
+ *spi_rd++ = cfspi_rx();
+ }
+ }
+
+ len = 1; /* remaining byte */
+ }
+
+ if ((flags & SPI_XFER_END) == SPI_XFER_END)
+ ctrl &= ~DSPI_TFR_CONT;
+
+ if (len) {
+ if (dout != NULL) {
+ if (cfslave->charbit == 16)
+ cfspi_tx(ctrl, *spi_wr16);
+ else
+ cfspi_tx(ctrl, *spi_wr);
+ cfspi_rx();
+ }
+
+ if (din != NULL) {
+ cfspi_tx(ctrl, 0);
+ if (cfslave->charbit == 16)
+ *spi_rd16 = cfspi_rx();
+ else
+ *spi_rd = cfspi_rx();
+ }
+ } else {
+ /* dummy read */
+ cfspi_tx(ctrl, 0);
+ cfspi_rx();
+ }
+
+ return 0;
+}
+
+struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode)
+{
+ /*
+ * bit definition for mode:
+ * bit 31 - 28: Transfer size 3 to 16 bits
+ * 27 - 26: PCS to SCK delay prescaler
+ * 25 - 24: After SCK delay prescaler
+ * 23 - 22: Delay after transfer prescaler
+ * 21 : Allow overwrite for bit 31-22 and bit 20-8
+ * 20 : Double baud rate
+ * 19 - 16: PCS to SCK delay scaler
+ * 15 - 12: After SCK delay scaler
+ * 11 - 8: Delay after transfer scaler
+ * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
+ */
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ int prescaler[] = { 2, 3, 5, 7 };
+ int scaler[] = {
+ 2, 4, 6, 8,
+ 16, 32, 64, 128,
+ 256, 512, 1024, 2048,
+ 4096, 8192, 16384, 32768
+ };
+ int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
+ int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
+ u32 bus_setup = 0;
+
+ tmp = (prescaler[3] * scaler[15]);
+ /* Maximum and minimum baudrate it can handle */
+ if ((cfslave->baudrate > (gd->bus_clk >> 1)) ||
+ (cfslave->baudrate < (gd->bus_clk / tmp))) {
+ printf("Exceed baudrate limitation: Max %d - Min %d\n",
+ (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
+ return NULL;
+ }
+
+ /* Activate Double Baud when it exceed 1/4 the bus clk */
+ if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||
+ (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
+ bus_setup |= DSPI_CTAR_DBR;
+ dbr = 1;
+ }
+
+ if (mode & SPI_CPOL)
+ bus_setup |= DSPI_CTAR_CPOL;
+ if (mode & SPI_CPHA)
+ bus_setup |= DSPI_CTAR_CPHA;
+ if (mode & SPI_LSB_FIRST)
+ bus_setup |= DSPI_CTAR_LSBFE;
+
+ /* Overwrite default value set in platform configuration file */
+ if (mode & SPI_MODE_MOD) {
+
+ if ((mode & 0xF0000000) == 0)
+ bus_setup |=
+ dspi->ctar[cfslave->slave.bus] & 0x78000000;
+ else
+ bus_setup |= ((mode & 0xF0000000) >> 1);
+
+ /*
+ * Check to see if it is enabled by default in platform
+ * config, or manual setting passed by mode parameter
+ */
+ if (mode & SPI_DBLRATE) {
+ bus_setup |= DSPI_CTAR_DBR;
+ dbr = 1;
+ }
+ bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */
+ bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */
+ } else
+ bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0);
+
+ cfslave->charbit =
+ ((dspi->ctar[cfslave->slave.bus] & 0x78000000) ==
+ 0x78000000) ? 16 : 8;
+
+ pbrcnt = sizeof(prescaler) / sizeof(int);
+ brcnt = sizeof(scaler) / sizeof(int);
+
+ /* baudrate calculation - to closer value, may not be exact match */
+ for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
+ baud_speed = gd->bus_clk / prescaler[i];
+ for (j = 0; j < brcnt; j++) {
+ tmp = (baud_speed / scaler[j]) * (1 + dbr);
+
+ if (tmp > cfslave->baudrate)
+ diff = tmp - cfslave->baudrate;
+ else
+ diff = cfslave->baudrate - tmp;
+
+ if (diff < bestmatch) {
+ bestmatch = diff;
+ best_i = i;
+ best_j = j;
+ }
+ }
+ }
+ bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
+ dspi->ctar[cfslave->slave.bus] = bus_setup;
+
+ return &cfslave->slave;
+}
+#endif /* CONFIG_CF_DSPI */
+
+#ifdef CONFIG_CF_QSPI
+/* 52xx, 53xx */
+#endif /* CONFIG_CF_QSPI */
+
+#ifdef CONFIG_CMD_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
+ return 1;
+ else
+ return 0;
+}
+
+void spi_init_f(void)
+{
+}
+
+void spi_init_r(void)
+{
+}
+
+void spi_init(void)
+{
+ cfspi_init();
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct cf_spi_slave *cfslave;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ cfslave = malloc(sizeof(struct cf_spi_slave));
+ if (!cfslave)
+ return NULL;
+
+ cfslave->slave.bus = bus;
+ cfslave->slave.cs = cs;
+ cfslave->baudrate = max_hz;
+
+ /* specific setup */
+ return cfspi_setup_slave(cfslave, mode);
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ free(slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return cfspi_claim_bus(slave->bus, slave->cs);
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ cfspi_release_bus(slave->bus, slave->cs);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ return cfspi_xfer(slave, bitlen, dout, din, flags);
+}
+#endif /* CONFIG_CMD_SPI */
diff --git a/drivers/video/bus_vcxk.c b/drivers/video/bus_vcxk.c
index b3b53e12b..7726bb319 100644
--- a/drivers/video/bus_vcxk.c
+++ b/drivers/video/bus_vcxk.c
@@ -380,7 +380,6 @@ int vcxk_display_bitmap(ulong addr, int x, int y)
unsigned long c_width;
unsigned long c_height;
unsigned char *dataptr;
- unsigned char *lineptr;
bmp = (bmp_image_t *) addr;
if ((bmp->header.signature[0] == 'B') &&
diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile
index dbcfa920e..d2e811a8b 100644
--- a/examples/standalone/Makefile
+++ b/examples/standalone/Makefile
@@ -33,7 +33,7 @@ ifeq ($(ARCH),arm)
ifeq ($(BOARD),omap2420h4)
LOAD_ADDR = 0x80300000
else
-ifeq ($(CPU),omap3)
+ifeq ($(SOC),omap3)
LOAD_ADDR = 0x80300000
else
LOAD_ADDR = 0xc100000
diff --git a/include/405_mal.h b/include/405_mal.h
index 1415cbe1b..1ca9429e2 100644
--- a/include/405_mal.h
+++ b/include/405_mal.h
@@ -1,5 +1,7 @@
/* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */
/*----------------------------------------------------------------------------+
+| This source code is dual-licensed. You may use it under the terms of the
+| GNU General Public License version 2, or under the license below.
|
| This source code has been made available to you by IBM on an AS-IS
| basis. Anyone receiving this source is licensed under IBM
diff --git a/include/_exports.h b/include/_exports.h
index af43885c5..f3df56827 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -1,3 +1,7 @@
+/*
+ * You do not need to use #ifdef around functions that may not exist
+ * in the final configuration (such as i2c).
+ */
EXPORT_FUNC(get_version)
EXPORT_FUNC(getc)
EXPORT_FUNC(tstc)
@@ -14,13 +18,15 @@ EXPORT_FUNC(vprintf)
EXPORT_FUNC(do_reset)
EXPORT_FUNC(getenv)
EXPORT_FUNC(setenv)
-#ifdef CONFIG_HAS_UID
EXPORT_FUNC(forceenv)
-#endif
EXPORT_FUNC(simple_strtoul)
EXPORT_FUNC(simple_strtol)
EXPORT_FUNC(strcmp)
-#if defined(CONFIG_CMD_I2C)
EXPORT_FUNC(i2c_write)
EXPORT_FUNC(i2c_read)
-#endif
+EXPORT_FUNC(spi_init)
+EXPORT_FUNC(spi_setup_slave)
+EXPORT_FUNC(spi_free_slave)
+EXPORT_FUNC(spi_claim_bus)
+EXPORT_FUNC(spi_release_bus)
+EXPORT_FUNC(spi_xfer)
diff --git a/include/asm-arm/arch-kirkwood/gpio.h b/include/asm-arm/arch-kirkwood/gpio.h
index a79102ba5..b5bacde34 100644
--- a/include/asm-arm/arch-kirkwood/gpio.h
+++ b/include/asm-arm/arch-kirkwood/gpio.h
@@ -17,8 +17,6 @@
#ifndef __KIRKWOOD_GPIO_H
#define __KIRKWOOD_GPIO_H
-/* got from kernel include/linux/kernel.h */
-#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
/* got from kernel include/linux/bitops.h */
#define BITS_PER_BYTE 8
#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
diff --git a/include/asm-arm/arch-mx27/mxcmmc.h b/include/asm-arm/arch-mx27/mxcmmc.h
new file mode 100644
index 000000000..4c83cc7cb
--- /dev/null
+++ b/include/asm-arm/arch-mx27/mxcmmc.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef ASM_ARCH_MXCMMC_H
+#define ASM_ARCH_MXCMMC_H
+
+int mxc_mmc_init(bd_t *bis);
+
+#endif
diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
index a4ce45ab2..7a032b828 100644
--- a/include/asm-arm/arch-omap3/cpu.h
+++ b/include/asm-arm/arch-omap3/cpu.h
@@ -25,34 +25,40 @@
#ifndef _CPU_H
#define _CPU_H
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
/* Register offsets of common modules */
/* Control */
+#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-typedef struct ctrl {
- unsigned char res1[0xC0];
- unsigned short gpmc_nadv_ale; /* 0xC0 */
- unsigned short gpmc_noe; /* 0xC2 */
- unsigned short gpmc_nwe; /* 0xC4 */
- unsigned char res2[0x22A];
- unsigned int status; /* 0x2F0 */
- unsigned int gpstatus; /* 0x2F4 */
- unsigned char res3[0x08];
- unsigned int rpubkey_0; /* 0x300 */
- unsigned int rpubkey_1; /* 0x304 */
- unsigned int rpubkey_2; /* 0x308 */
- unsigned int rpubkey_3; /* 0x30C */
- unsigned int rpubkey_4; /* 0x310 */
- unsigned char res4[0x04];
- unsigned int randkey_0; /* 0x318 */
- unsigned int randkey_1; /* 0x31C */
- unsigned int randkey_2; /* 0x320 */
- unsigned int randkey_3; /* 0x324 */
- unsigned char res5[0x124];
- unsigned int ctrl_omap_stat; /* 0x44C */
-} ctrl_t;
+struct ctrl {
+ u8 res1[0xC0];
+ u16 gpmc_nadv_ale; /* 0xC0 */
+ u16 gpmc_noe; /* 0xC2 */
+ u16 gpmc_nwe; /* 0xC4 */
+ u8 res2[0x22A];
+ u32 status; /* 0x2F0 */
+ u32 gpstatus; /* 0x2F4 */
+ u8 res3[0x08];
+ u32 rpubkey_0; /* 0x300 */
+ u32 rpubkey_1; /* 0x304 */
+ u32 rpubkey_2; /* 0x308 */
+ u32 rpubkey_3; /* 0x30C */
+ u32 rpubkey_4; /* 0x310 */
+ u8 res4[0x04];
+ u32 randkey_0; /* 0x318 */
+ u32 randkey_1; /* 0x31C */
+ u32 randkey_2; /* 0x320 */
+ u32 randkey_3; /* 0x324 */
+ u8 res5[0x124];
+ u32 ctrl_omap_stat; /* 0x44C */
+};
#else /* __ASSEMBLY__ */
#define CONTROL_STATUS 0x2F0
#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
/* cpu type */
#define OMAP3503 0x5c00
@@ -60,18 +66,20 @@ typedef struct ctrl {
#define OMAP3525 0x4c00
#define OMAP3530 0x0c00
+#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-typedef struct ctrl_id {
- unsigned char res1[0x4];
- unsigned int idcode; /* 0x04 */
- unsigned int prod_id; /* 0x08 */
- unsigned char res2[0x0C];
- unsigned int die_id_0; /* 0x18 */
- unsigned int die_id_1; /* 0x1C */
- unsigned int die_id_2; /* 0x20 */
- unsigned int die_id_3; /* 0x24 */
-} ctrl_id_t;
+struct ctrl_id {
+ u8 res1[0x4];
+ u32 idcode; /* 0x04 */
+ u32 prod_id; /* 0x08 */
+ u8 res2[0x0C];
+ u32 die_id_0; /* 0x18 */
+ u32 die_id_1; /* 0x1C */
+ u32 die_id_2; /* 0x20 */
+ u32 die_id_3; /* 0x24 */
+};
#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
/* device type */
#define DEVICE_MASK (0x7 << 8)
@@ -81,56 +89,53 @@ typedef struct ctrl_id {
#define HS_DEVICE 0x2
#define GP_DEVICE 0x3
-/* GPMC CS3/cs4/cs6 not avaliable */
#define GPMC_BASE (OMAP34XX_GPMC_BASE)
#define GPMC_CONFIG_CS0 0x60
-#define GPMC_CONFIG_CS5 0x150
-
#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
-#define GPMC_CONFIG_CS5_BASE (GPMC_BASE + GPMC_CONFIG_CS5)
-#define GPMC_CONFIG_WP 0x10
-
-#define GPMC_CONFIG_WIDTH 0x30
+#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-typedef struct gpmc {
- unsigned char res1[0x10];
- unsigned int sysconfig; /* 0x10 */
- unsigned char res2[0x4];
- unsigned int irqstatus; /* 0x18 */
- unsigned int irqenable; /* 0x1C */
- unsigned char res3[0x20];
- unsigned int timeout_control; /* 0x40 */
- unsigned char res4[0xC];
- unsigned int config; /* 0x50 */
- unsigned int status; /* 0x54 */
- unsigned char res5[0x19C];
- unsigned int ecc_config; /* 0x1F4 */
- unsigned int ecc_control; /* 0x1F8 */
- unsigned int ecc_size_config; /* 0x1FC */
- unsigned int ecc1_result; /* 0x200 */
- unsigned int ecc2_result; /* 0x204 */
- unsigned int ecc3_result; /* 0x208 */
- unsigned int ecc4_result; /* 0x20C */
- unsigned int ecc5_result; /* 0x210 */
- unsigned int ecc6_result; /* 0x214 */
- unsigned int ecc7_result; /* 0x218 */
- unsigned int ecc8_result; /* 0x21C */
- unsigned int ecc9_result; /* 0x220 */
-} gpmc_t;
-
-typedef struct gpmc_csx {
- unsigned int config1; /* 0x00 */
- unsigned int config2; /* 0x04 */
- unsigned int config3; /* 0x08 */
- unsigned int config4; /* 0x0C */
- unsigned int config5; /* 0x10 */
- unsigned int config6; /* 0x14 */
- unsigned int config7; /* 0x18 */
- unsigned int nand_cmd; /* 0x1C */
- unsigned int nand_adr; /* 0x20 */
- unsigned int nand_dat; /* 0x24 */
-} gpmc_csx_t;
+struct gpmc_cs {
+ u32 config1; /* 0x00 */
+ u32 config2; /* 0x04 */
+ u32 config3; /* 0x08 */
+ u32 config4; /* 0x0C */
+ u32 config5; /* 0x10 */
+ u32 config6; /* 0x14 */
+ u32 config7; /* 0x18 */
+ u32 nand_cmd; /* 0x1C */
+ u32 nand_adr; /* 0x20 */
+ u32 nand_dat; /* 0x24 */
+ u8 res[8]; /* blow up to 0x30 byte */
+};
+
+struct gpmc {
+ u8 res1[0x10];
+ u32 sysconfig; /* 0x10 */
+ u8 res2[0x4];
+ u32 irqstatus; /* 0x18 */
+ u32 irqenable; /* 0x1C */
+ u8 res3[0x20];
+ u32 timeout_control; /* 0x40 */
+ u8 res4[0xC];
+ u32 config; /* 0x50 */
+ u32 status; /* 0x54 */
+ u8 res5[0x8];
+ struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
+ u8 res6[0x18];
+ u32 ecc_config; /* 0x1F4 */
+ u32 ecc_control; /* 0x1F8 */
+ u32 ecc_size_config; /* 0x1FC */
+ u32 ecc1_result; /* 0x200 */
+ u32 ecc2_result; /* 0x204 */
+ u32 ecc3_result; /* 0x208 */
+ u32 ecc4_result; /* 0x20C */
+ u32 ecc5_result; /* 0x210 */
+ u32 ecc6_result; /* 0x214 */
+ u32 ecc7_result; /* 0x218 */
+ u32 ecc8_result; /* 0x21C */
+ u32 ecc9_result; /* 0x220 */
+};
#else /* __ASSEMBLY__ */
#define GPMC_CONFIG1 0x00
#define GPMC_CONFIG2 0x04
@@ -140,6 +145,7 @@ typedef struct gpmc_csx {
#define GPMC_CONFIG6 0x14
#define GPMC_CONFIG7 0x18
#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
/* GPMC Mapping */
#define FLASH_BASE 0x10000000 /* NOR flash, */
@@ -155,54 +161,58 @@ typedef struct gpmc_csx {
#define ONENAND_MAP 0x20000000 /* OneNand addr */
/* (actual size small port) */
/* SMS */
+#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-typedef struct sms {
- unsigned char res1[0x10];
- unsigned int sysconfig; /* 0x10 */
- unsigned char res2[0x34];
- unsigned int rg_att0; /* 0x48 */
- unsigned char res3[0x84];
- unsigned int class_arb0; /* 0xD0 */
-} sms_t;
+struct sms {
+ u8 res1[0x10];
+ u32 sysconfig; /* 0x10 */
+ u8 res2[0x34];
+ u32 rg_att0; /* 0x48 */
+ u8 res3[0x84];
+ u32 class_arb0; /* 0xD0 */
+};
#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
#define BURSTCOMPLETE_GROUP7 (0x1 << 31)
/* SDRC */
+#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-typedef struct sdrc_cs {
- unsigned int mcfg; /* 0x80 || 0xB0 */
- unsigned int mr; /* 0x84 || 0xB4 */
- unsigned char res1[0x4];
- unsigned int emr2; /* 0x8C || 0xBC */
- unsigned char res2[0x14];
- unsigned int rfr_ctrl; /* 0x84 || 0xD4 */
- unsigned int manual; /* 0xA8 || 0xD8 */
- unsigned char res3[0x4];
-} sdrc_cs_t;
-
-typedef struct sdrc_actim {
- unsigned int ctrla; /* 0x9C || 0xC4 */
- unsigned int ctrlb; /* 0xA0 || 0xC8 */
-} sdrc_actim_t;
-
-typedef struct sdrc {
- unsigned char res1[0x10];
- unsigned int sysconfig; /* 0x10 */
- unsigned int status; /* 0x14 */
- unsigned char res2[0x28];
- unsigned int cs_cfg; /* 0x40 */
- unsigned int sharing; /* 0x44 */
- unsigned char res3[0x18];
- unsigned int dlla_ctrl; /* 0x60 */
- unsigned int dlla_status; /* 0x64 */
- unsigned int dllb_ctrl; /* 0x68 */
- unsigned int dllb_status; /* 0x6C */
- unsigned int power; /* 0x70 */
- unsigned char res4[0xC];
- sdrc_cs_t cs[2]; /* 0x80 || 0xB0 */
-} sdrc_t;
+struct sdrc_cs {
+ u32 mcfg; /* 0x80 || 0xB0 */
+ u32 mr; /* 0x84 || 0xB4 */
+ u8 res1[0x4];
+ u32 emr2; /* 0x8C || 0xBC */
+ u8 res2[0x14];
+ u32 rfr_ctrl; /* 0x84 || 0xD4 */
+ u32 manual; /* 0xA8 || 0xD8 */
+ u8 res3[0x4];
+};
+
+struct sdrc_actim {
+ u32 ctrla; /* 0x9C || 0xC4 */
+ u32 ctrlb; /* 0xA0 || 0xC8 */
+};
+
+struct sdrc {
+ u8 res1[0x10];
+ u32 sysconfig; /* 0x10 */
+ u32 status; /* 0x14 */
+ u8 res2[0x28];
+ u32 cs_cfg; /* 0x40 */
+ u32 sharing; /* 0x44 */
+ u8 res3[0x18];
+ u32 dlla_ctrl; /* 0x60 */
+ u32 dlla_status; /* 0x64 */
+ u32 dllb_ctrl; /* 0x68 */
+ u32 dllb_status; /* 0x6C */
+ u32 power; /* 0x70 */
+ u8 res4[0xC];
+ struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */
+};
#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
#define DLLPHASE_90 (0x1 << 1)
#define LOADDLL (0x1 << 2)
@@ -244,39 +254,43 @@ typedef struct sdrc {
/* timer regs offsets (32 bit regs) */
+#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-typedef struct gptimer {
- unsigned int tidr; /* 0x00 r */
- unsigned char res[0xc];
- unsigned int tiocp_cfg; /* 0x10 rw */
- unsigned int tistat; /* 0x14 r */
- unsigned int tisr; /* 0x18 rw */
- unsigned int tier; /* 0x1c rw */
- unsigned int twer; /* 0x20 rw */
- unsigned int tclr; /* 0x24 rw */
- unsigned int tcrr; /* 0x28 rw */
- unsigned int tldr; /* 0x2c rw */
- unsigned int ttgr; /* 0x30 rw */
- unsigned int twpc; /* 0x34 r*/
- unsigned int tmar; /* 0x38 rw*/
- unsigned int tcar1; /* 0x3c r */
- unsigned int tcicr; /* 0x40 rw */
- unsigned int tcar2; /* 0x44 r */
-} gptimer_t;
+struct gptimer {
+ u32 tidr; /* 0x00 r */
+ u8 res[0xc];
+ u32 tiocp_cfg; /* 0x10 rw */
+ u32 tistat; /* 0x14 r */
+ u32 tisr; /* 0x18 rw */
+ u32 tier; /* 0x1c rw */
+ u32 twer; /* 0x20 rw */
+ u32 tclr; /* 0x24 rw */
+ u32 tcrr; /* 0x28 rw */
+ u32 tldr; /* 0x2c rw */
+ u32 ttgr; /* 0x30 rw */
+ u32 twpc; /* 0x34 r*/
+ u32 tmar; /* 0x38 rw*/
+ u32 tcar1; /* 0x3c r */
+ u32 tcicr; /* 0x40 rw */
+ u32 tcar2; /* 0x44 r */
+};
#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
/* enable sys_clk NO-prescale /1 */
#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
/* Watchdog */
+#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-typedef struct watchdog {
- unsigned char res1[0x34];
- unsigned int wwps; /* 0x34 r */
- unsigned char res2[0x10];
- unsigned int wspr; /* 0x48 rw */
-} watchdog_t;
+struct watchdog {
+ u8 res1[0x34];
+ u32 wwps; /* 0x34 r */
+ u8 res2[0x10];
+ u32 wspr; /* 0x48 rw */
+};
#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
#define WD_UNLOCK1 0xAAAA
#define WD_UNLOCK2 0x5555
@@ -284,72 +298,73 @@ typedef struct watchdog {
/* PRCM */
#define PRCM_BASE 0x48004000
+#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-typedef struct prcm {
- unsigned int fclken_iva2; /* 0x00 */
- unsigned int clken_pll_iva2; /* 0x04 */
- unsigned char res1[0x1c];
- unsigned int idlest_pll_iva2; /* 0x24 */
- unsigned char res2[0x18];
- unsigned int clksel1_pll_iva2 ; /* 0x40 */
- unsigned int clksel2_pll_iva2; /* 0x44 */
- unsigned char res3[0x8bc];
- unsigned int clken_pll_mpu; /* 0x904 */
- unsigned char res4[0x1c];
- unsigned int idlest_pll_mpu; /* 0x924 */
- unsigned char res5[0x18];
- unsigned int clksel1_pll_mpu; /* 0x940 */
- unsigned int clksel2_pll_mpu; /* 0x944 */
- unsigned char res6[0xb8];
- unsigned int fclken1_core; /* 0xa00 */
- unsigned char res7[0xc];
- unsigned int iclken1_core; /* 0xa10 */
- unsigned int iclken2_core; /* 0xa14 */
- unsigned char res8[0x28];
- unsigned int clksel_core; /* 0xa40 */
- unsigned char res9[0xbc];
- unsigned int fclken_gfx; /* 0xb00 */
- unsigned char res10[0xc];
- unsigned int iclken_gfx; /* 0xb10 */
- unsigned char res11[0x2c];
- unsigned int clksel_gfx; /* 0xb40 */
- unsigned char res12[0xbc];
- unsigned int fclken_wkup; /* 0xc00 */
- unsigned char res13[0xc];
- unsigned int iclken_wkup; /* 0xc10 */
- unsigned char res14[0xc];
- unsigned int idlest_wkup; /* 0xc20 */
- unsigned char res15[0x1c];
- unsigned int clksel_wkup; /* 0xc40 */
- unsigned char res16[0xbc];
- unsigned int clken_pll; /* 0xd00 */
- unsigned char res17[0x1c];
- unsigned int idlest_ckgen; /* 0xd20 */
- unsigned char res18[0x1c];
- unsigned int clksel1_pll; /* 0xd40 */
- unsigned int clksel2_pll; /* 0xd44 */
- unsigned int clksel3_pll; /* 0xd48 */
- unsigned char res19[0xb4];
- unsigned int fclken_dss; /* 0xe00 */
- unsigned char res20[0xc];
- unsigned int iclken_dss; /* 0xe10 */
- unsigned char res21[0x2c];
- unsigned int clksel_dss; /* 0xe40 */
- unsigned char res22[0xbc];
- unsigned int fclken_cam; /* 0xf00 */
- unsigned char res23[0xc];
- unsigned int iclken_cam; /* 0xf10 */
- unsigned char res24[0x2c];
- unsigned int clksel_cam; /* 0xf40 */
- unsigned char res25[0xbc];
- unsigned int fclken_per; /* 0x1000 */
- unsigned char res26[0xc];
- unsigned int iclken_per; /* 0x1010 */
- unsigned char res27[0x2c];
- unsigned int clksel_per; /* 0x1040 */
- unsigned char res28[0xfc];
- unsigned int clksel1_emu; /* 0x1140 */
-} prcm_t;
+struct prcm {
+ u32 fclken_iva2; /* 0x00 */
+ u32 clken_pll_iva2; /* 0x04 */
+ u8 res1[0x1c];
+ u32 idlest_pll_iva2; /* 0x24 */
+ u8 res2[0x18];
+ u32 clksel1_pll_iva2 ; /* 0x40 */
+ u32 clksel2_pll_iva2; /* 0x44 */
+ u8 res3[0x8bc];
+ u32 clken_pll_mpu; /* 0x904 */
+ u8 res4[0x1c];
+ u32 idlest_pll_mpu; /* 0x924 */
+ u8 res5[0x18];
+ u32 clksel1_pll_mpu; /* 0x940 */
+ u32 clksel2_pll_mpu; /* 0x944 */
+ u8 res6[0xb8];
+ u32 fclken1_core; /* 0xa00 */
+ u8 res7[0xc];
+ u32 iclken1_core; /* 0xa10 */
+ u32 iclken2_core; /* 0xa14 */
+ u8 res8[0x28];
+ u32 clksel_core; /* 0xa40 */
+ u8 res9[0xbc];
+ u32 fclken_gfx; /* 0xb00 */
+ u8 res10[0xc];
+ u32 iclken_gfx; /* 0xb10 */
+ u8 res11[0x2c];
+ u32 clksel_gfx; /* 0xb40 */
+ u8 res12[0xbc];
+ u32 fclken_wkup; /* 0xc00 */
+ u8 res13[0xc];
+ u32 iclken_wkup; /* 0xc10 */
+ u8 res14[0xc];
+ u32 idlest_wkup; /* 0xc20 */
+ u8 res15[0x1c];
+ u32 clksel_wkup; /* 0xc40 */
+ u8 res16[0xbc];
+ u32 clken_pll; /* 0xd00 */
+ u8 res17[0x1c];
+ u32 idlest_ckgen; /* 0xd20 */
+ u8 res18[0x1c];
+ u32 clksel1_pll; /* 0xd40 */
+ u32 clksel2_pll; /* 0xd44 */
+ u32 clksel3_pll; /* 0xd48 */
+ u8 res19[0xb4];
+ u32 fclken_dss; /* 0xe00 */
+ u8 res20[0xc];
+ u32 iclken_dss; /* 0xe10 */
+ u8 res21[0x2c];
+ u32 clksel_dss; /* 0xe40 */
+ u8 res22[0xbc];
+ u32 fclken_cam; /* 0xf00 */
+ u8 res23[0xc];
+ u32 iclken_cam; /* 0xf10 */
+ u8 res24[0x2c];
+ u32 clksel_cam; /* 0xf40 */
+ u8 res25[0xbc];
+ u32 fclken_per; /* 0x1000 */
+ u8 res26[0xc];
+ u32 iclken_per; /* 0x1010 */
+ u8 res27[0x2c];
+ u32 clksel_per; /* 0x1040 */
+ u8 res28[0xfc];
+ u32 clksel1_emu; /* 0x1140 */
+};
#else /* __ASSEMBLY__ */
#define CM_CLKSEL_CORE 0x48004a40
#define CM_CLKSEL_GFX 0x48004b40
@@ -358,21 +373,24 @@ typedef struct prcm {
#define CM_CLKSEL1_PLL 0x48004d40
#define CM_CLKSEL1_EMU 0x48005140
#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
#define PRM_BASE 0x48306000
+#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-typedef struct prm {
- unsigned char res1[0xd40];
- unsigned int clksel; /* 0xd40 */
- unsigned char res2[0x50c];
- unsigned int rstctrl; /* 0x1250 */
- unsigned char res3[0x1c];
- unsigned int clksrc_ctrl; /* 0x1270 */
-} prm_t;
+struct prm {
+ u8 res1[0xd40];
+ u32 clksel; /* 0xd40 */
+ u8 res2[0x50c];
+ u32 rstctrl; /* 0x1250 */
+ u8 res3[0x1c];
+ u32 clksrc_ctrl; /* 0x1270 */
+};
#else /* __ASSEMBLY__ */
#define PRM_RSTCTRL 0x48307250
#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
#define SYSCLKDIV_1 (0x1 << 6)
#define SYSCLKDIV_2 (0x1 << 7)
@@ -404,22 +422,24 @@ typedef struct prm {
#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
+#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-typedef struct pm {
- unsigned char res1[0x48];
- unsigned int req_info_permission_0; /* 0x48 */
- unsigned char res2[0x4];
- unsigned int read_permission_0; /* 0x50 */
- unsigned char res3[0x4];
- unsigned int wirte_permission_0; /* 0x58 */
- unsigned char res4[0x4];
- unsigned int addr_match_1; /* 0x58 */
- unsigned char res5[0x4];
- unsigned int req_info_permission_1; /* 0x68 */
- unsigned char res6[0x14];
- unsigned int addr_match_2; /* 0x80 */
-} pm_t;
+struct pm {
+ u8 res1[0x48];
+ u32 req_info_permission_0; /* 0x48 */
+ u8 res2[0x4];
+ u32 read_permission_0; /* 0x50 */
+ u8 res3[0x4];
+ u32 wirte_permission_0; /* 0x58 */
+ u8 res4[0x4];
+ u32 addr_match_1; /* 0x58 */
+ u8 res5[0x4];
+ u32 req_info_permission_1; /* 0x68 */
+ u8 res6[0x14];
+ u32 addr_match_2; /* 0x80 */
+};
#endif /*__ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
/* Permission values for registers -Full fledged permissions to all */
#define UNLOCK_1 0xFFFFFFFF
diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
index 6f0f90b60..5b9ac753e 100644
--- a/include/asm-arm/arch-omap3/mem.h
+++ b/include/asm-arm/arch-omap3/mem.h
@@ -29,12 +29,12 @@
#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
#ifndef __ASSEMBLY__
-typedef enum {
+enum {
STACKED = 0,
IP_DDR = 1,
COMBO_DDR = 2,
IP_SDR = 3,
-} mem_t;
+};
#endif /* __ASSEMBLY__ */
#define EARLY_INIT 1
diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h
index fa8f46d7f..6459d992b 100644
--- a/include/asm-arm/arch-omap3/omap3.h
+++ b/include/asm-arm/arch-omap3/omap3.h
@@ -79,10 +79,10 @@
#ifndef __ASSEMBLY__
-typedef struct s32ktimer {
+struct s32ktimer {
unsigned char res[0x10];
unsigned int s32k_cr; /* 0x10 */
-} s32ktimer_t;
+};
#endif /* __ASSEMBLY__ */
@@ -95,14 +95,14 @@ typedef struct s32ktimer {
#define OMAP34XX_GPIO6_BASE 0x49058000
#ifndef __ASSEMBLY__
-typedef struct gpio {
+struct gpio {
unsigned char res1[0x34];
unsigned int oe; /* 0x34 */
unsigned int datain; /* 0x38 */
unsigned char res2[0x54];
unsigned int cleardataout; /* 0x90 */
unsigned int setdataout; /* 0x94 */
-} gpio_t;
+};
#endif /* __ASSEMBLY__ */
#define GPIO0 (0x1 << 0)
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 2a723dcea..f34af1972 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1217,7 +1217,7 @@ typedef void (*ExcpHndlr) (void) ;
#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
#define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3)
-#define GCDR(x) __REG2(0x40300420, ((x) & 0x60) >> 3)
+#define GCDR(x) __REG2(0x40E00420, ((x) & 0x60) >> 3)
/* Multi-funktion Pin Registers, uncomplete, only:
* - GPIO
diff --git a/include/asm-m68k/coldfire/dspi.h b/include/asm-m68k/coldfire/dspi.h
index 4b7d61e0f..02d140961 100644
--- a/include/asm-m68k/coldfire/dspi.h
+++ b/include/asm-m68k/coldfire/dspi.h
@@ -26,140 +26,133 @@
#ifndef __DSPI_H__
#define __DSPI_H__
-/*********************************************************************
-* DMA Serial Peripheral Interface (DSPI)
-*********************************************************************/
-
+/* DMA Serial Peripheral Interface (DSPI) */
typedef struct dspi {
- u32 dmcr;
- u8 resv0[0x4];
- u32 dtcr;
- u32 dctar0;
- u32 dctar1;
- u32 dctar2;
- u32 dctar3;
- u32 dctar4;
- u32 dctar5;
- u32 dctar6;
- u32 dctar7;
- u32 dsr;
- u32 dirsr;
- u32 dtfr;
- u32 drfr;
+ u32 mcr; /* 0x00 */
+ u32 resv0; /* 0x04 */
+ u32 tcr; /* 0x08 */
+ u32 ctar[8]; /* 0x0C - 0x28 */
+ u32 sr; /* 0x2C */
+ u32 irsr; /* 0x30 */
+ u32 tfr; /* 0x34 - PUSHR */
+ u16 resv1; /* 0x38 */
+ u16 rfr; /* 0x3A - POPR */
#ifdef CONFIG_MCF547x_8x
- u32 dtfdr[4];
- u8 resv1[0x30];
- u32 drfdr[4];
+ u32 tfdr[4]; /* 0x3C */
+ u8 resv2[0x30]; /* 0x40 */
+ u32 rfdr[4]; /* 0x7C */
#else
- u32 dtfdr[16];
- u32 drfdr[16];
+ u32 tfdr[16]; /* 0x3C */
+ u32 rfdr[16]; /* 0x7C */
#endif
} dspi_t;
-/* Bit definitions and macros for DMCR */
-#define DSPI_DMCR_HALT (0x00000001)
-#define DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8)
-#define DSPI_DMCR_CRXF (0x00000400)
-#define DSPI_DMCR_CTXF (0x00000800)
-#define DSPI_DMCR_DRXF (0x00001000)
-#define DSPI_DMCR_DTXF (0x00002000)
-#define DSPI_DMCR_MDIS (0x00004000)
-#define DSPI_DMCR_CSIS0 (0x00010000)
-#define DSPI_DMCR_CSIS1 (0x00020000)
-#define DSPI_DMCR_CSIS2 (0x00040000)
-#define DSPI_DMCR_CSIS3 (0x00080000)
-#define DSPI_DMCR_CSIS4 (0x00100000)
-#define DSPI_DMCR_CSIS5 (0x00200000)
-#define DSPI_DMCR_CSIS6 (0x00400000)
-#define DSPI_DMCR_CSIS7 (0x00800000)
-#define DSPI_DMCR_ROOE (0x01000000)
-#define DSPI_DMCR_PCSSE (0x02000000)
-#define DSPI_DMCR_MTFE (0x04000000)
-#define DSPI_DMCR_FRZ (0x08000000)
-#define DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
-#define DSPI_DMCR_CSCK (0x40000000)
-#define DSPI_DMCR_MSTR (0x80000000)
+/* Module configuration */
+#define DSPI_MCR_MSTR (0x80000000)
+#define DSPI_MCR_CSCK (0x40000000)
+#define DSPI_MCR_DCONF(x) (((x)&0x03)<<28)
+#define DSPI_MCR_FRZ (0x08000000)
+#define DSPI_MCR_MTFE (0x04000000)
+#define DSPI_MCR_PCSSE (0x02000000)
+#define DSPI_MCR_ROOE (0x01000000)
+#define DSPI_MCR_CSIS7 (0x00800000)
+#define DSPI_MCR_CSIS6 (0x00400000)
+#define DSPI_MCR_CSIS5 (0x00200000)
+#define DSPI_MCR_CSIS4 (0x00100000)
+#define DSPI_MCR_CSIS3 (0x00080000)
+#define DSPI_MCR_CSIS2 (0x00040000)
+#define DSPI_MCR_CSIS1 (0x00020000)
+#define DSPI_MCR_CSIS0 (0x00010000)
+#define DSPI_MCR_MDIS (0x00004000)
+#define DSPI_MCR_DTXF (0x00002000)
+#define DSPI_MCR_DRXF (0x00001000)
+#define DSPI_MCR_CTXF (0x00000800)
+#define DSPI_MCR_CRXF (0x00000400)
+#define DSPI_MCR_SMPL_PT(x) (((x)&0x03)<<8)
+#define DSPI_MCR_HALT (0x00000001)
+
+/* Transfer count */
+#define DSPI_TCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
-/* Bit definitions and macros for DTCR */
-#define DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
+/* Clock and transfer attributes */
+#define DSPI_CTAR_DBR (0x80000000)
+#define DSPI_CTAR_TRSZ(x) (((x)&0x0F)<<27)
+#define DSPI_CTAR_CPOL (0x04000000)
+#define DSPI_CTAR_CPHA (0x02000000)
+#define DSPI_CTAR_LSBFE (0x01000000)
+#define DSPI_CTAR_PCSSCK(x) (((x)&0x03)<<22)
+#define DSPI_CTAR_PCSSCK_7CLK (0x00A00000)
+#define DSPI_CTAR_PCSSCK_5CLK (0x00800000)
+#define DSPI_CTAR_PCSSCK_3CLK (0x00400000)
+#define DSPI_CTAR_PCSSCK_1CLK (0x00000000)
+#define DSPI_CTAR_PASC(x) (((x)&0x03)<<20)
+#define DSPI_CTAR_PASC_7CLK (0x00300000)
+#define DSPI_CTAR_PASC_5CLK (0x00200000)
+#define DSPI_CTAR_PASC_3CLK (0x00100000)
+#define DSPI_CTAR_PASC_1CLK (0x00000000)
+#define DSPI_CTAR_PDT(x) (((x)&0x03)<<18)
+#define DSPI_CTAR_PDT_7CLK (0x000A0000)
+#define DSPI_CTAR_PDT_5CLK (0x00080000)
+#define DSPI_CTAR_PDT_3CLK (0x00040000)
+#define DSPI_CTAR_PDT_1CLK (0x00000000)
+#define DSPI_CTAR_PBR(x) (((x)&0x03)<<16)
+#define DSPI_CTAR_PBR_7CLK (0x00030000)
+#define DSPI_CTAR_PBR_5CLK (0x00020000)
+#define DSPI_CTAR_PBR_3CLK (0x00010000)
+#define DSPI_CTAR_PBR_1CLK (0x00000000)
+#define DSPI_CTAR_CSSCK(x) (((x)&0x0F)<<12)
+#define DSPI_CTAR_ASC(x) (((x)&0x0F)<<8)
+#define DSPI_CTAR_DT(x) (((x)&0x0F)<<4)
+#define DSPI_CTAR_BR(x) (((x)&0x0F))
-/* Bit definitions and macros for DCTAR group */
-#define DSPI_DCTAR_BR(x) (((x)&0x0000000F))
-#define DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4)
-#define DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8)
-#define DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12)
-#define DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16)
-#define DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18)
-#define DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20)
-#define DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22)
-#define DSPI_DCTAR_LSBFE (0x01000000)
-#define DSPI_DCTAR_CPHA (0x02000000)
-#define DSPI_DCTAR_CPOL (0x04000000)
-#define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27)
-#define DSPI_DCTAR_DBR (0x80000000)
-#define DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
-#define DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
-#define DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
-#define DSPI_DCTAR_PCSSCK_7CLK (0x00A00000)
-#define DSPI_DCTAR_PASC_1CLK (0x00000000)
-#define DSPI_DCTAR_PASC_3CLK (0x00100000)
-#define DSPI_DCTAR_PASC_5CLK (0x00200000)
-#define DSPI_DCTAR_PASC_7CLK (0x00300000)
-#define DSPI_DCTAR_PDT_1CLK (0x00000000)
-#define DSPI_DCTAR_PDT_3CLK (0x00040000)
-#define DSPI_DCTAR_PDT_5CLK (0x00080000)
-#define DSPI_DCTAR_PDT_7CLK (0x000A0000)
-#define DSPI_DCTAR_PBR_1CLK (0x00000000)
-#define DSPI_DCTAR_PBR_3CLK (0x00010000)
-#define DSPI_DCTAR_PBR_5CLK (0x00020000)
-#define DSPI_DCTAR_PBR_7CLK (0x00030000)
+/* Status */
+#define DSPI_SR_TCF (0x80000000)
+#define DSPI_SR_TXRXS (0x40000000)
+#define DSPI_SR_EOQF (0x10000000)
+#define DSPI_SR_TFUF (0x08000000)
+#define DSPI_SR_TFFF (0x02000000)
+#define DSPI_SR_RFOF (0x00080000)
+#define DSPI_SR_RFDF (0x00020000)
+#define DSPI_SR_TXCTR(x) (((x)&0x0F)<<12)
+#define DSPI_SR_TXPTR(x) (((x)&0x0F)<<8)
+#define DSPI_SR_RXCTR(x) (((x)&0x0F)<<4)
+#define DSPI_SR_RXPTR(x) (((x)&0x0F))
-/* Bit definitions and macros for DSR */
-#define DSPI_DSR_RXPTR(x) (((x)&0x0000000F))
-#define DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
-#define DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
-#define DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
-#define DSPI_DSR_RFDF (0x00020000)
-#define DSPI_DSR_RFOF (0x00080000)
-#define DSPI_DSR_TFFF (0x02000000)
-#define DSPI_DSR_TFUF (0x08000000)
-#define DSPI_DSR_EOQF (0x10000000)
-#define DSPI_DSR_TXRXS (0x40000000)
-#define DSPI_DSR_TCF (0x80000000)
+/* DMA/interrupt request selct and enable */
+#define DSPI_IRSR_TCFE (0x80000000)
+#define DSPI_IRSR_EOQFE (0x10000000)
+#define DSPI_IRSR_TFUFE (0x08000000)
+#define DSPI_IRSR_TFFFE (0x02000000)
+#define DSPI_IRSR_TFFFS (0x01000000)
+#define DSPI_IRSR_RFOFE (0x00080000)
+#define DSPI_IRSR_RFDFE (0x00020000)
+#define DSPI_IRSR_RFDFS (0x00010000)
-/* Bit definitions and macros for DIRSR */
-#define DSPI_DIRSR_RFDFS (0x00010000)
-#define DSPI_DIRSR_RFDFE (0x00020000)
-#define DSPI_DIRSR_RFOFE (0x00080000)
-#define DSPI_DIRSR_TFFFS (0x01000000)
-#define DSPI_DIRSR_TFFFE (0x02000000)
-#define DSPI_DIRSR_TFUFE (0x08000000)
-#define DSPI_DIRSR_EOQFE (0x10000000)
-#define DSPI_DIRSR_TCFE (0x80000000)
+/* Transfer control - 32-bit access */
+#define DSPI_TFR_CONT (0x80000000)
+#define DSPI_TFR_CTAS(x) (((x)&0x07)<<12)
+#define DSPI_TFR_EOQ (0x08000000)
+#define DSPI_TFR_CTCNT (0x04000000)
+#define DSPI_TFR_CS7 (0x00800000)
+#define DSPI_TFR_CS6 (0x00400000)
+#define DSPI_TFR_CS5 (0x00200000)
+#define DSPI_TFR_CS4 (0x00100000)
+#define DSPI_TFR_CS3 (0x00080000)
+#define DSPI_TFR_CS2 (0x00040000)
+#define DSPI_TFR_CS1 (0x00020000)
+#define DSPI_TFR_CS0 (0x00010000)
-/* Bit definitions and macros for DTFR */
-#define DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF))
-#define DSPI_DTFR_CS0 (0x00010000)
-#define DSPI_DTFR_CS2 (0x00040000)
-#define DSPI_DTFR_CS3 (0x00080000)
-#define DSPI_DTFR_CS5 (0x00200000)
-#define DSPI_DTFR_CTCNT (0x04000000)
-#define DSPI_DTFR_EOQ (0x08000000)
-#define DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
-#define DSPI_DTFR_CONT (0x80000000)
+/* Transfer Fifo */
+#define DSPI_TFR_TXDATA(x) (((x)&0xFFFF))
/* Bit definitions and macros for DRFR */
-#define DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF))
+#define DSPI_RFR_RXDATA(x) (((x)&0xFFFF))
/* Bit definitions and macros for DTFDR group */
-#define DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF))
-#define DSPI_DTFDR_TXCMD(x) (((x)&0x0000FFFF)<<16)
+#define DSPI_TFDR_TXDATA(x) (((x)&0x0000FFFF))
+#define DSPI_TFDR_TXCMD(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for DRFDR group */
-#define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF))
-
-void dspi_init(void);
-void dspi_tx(int chipsel, u8 attrib, u16 data);
-u16 dspi_rx(void);
+#define DSPI_RFDR_RXDATA(x) (((x)&0x0000FFFF))
#endif /* __DSPI_H__ */
diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h
index 6a3ef0328..e83ce08d5 100644
--- a/include/asm-m68k/immap.h
+++ b/include/asm-m68k/immap.h
@@ -26,6 +26,35 @@
#ifndef __IMMAP_H
#define __IMMAP_H
+#if defined(CONFIG_MCF520x)
+#include <asm/immap_520x.h>
+#include <asm/m520x.h>
+
+#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI (6)
+#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE (6)
+#endif
+
+#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS (128)
+#endif /* CONFIG_M520x */
+
#ifdef CONFIG_M52277
#include <asm/immap_5227x.h>
#include <asm/m5227x.h>
diff --git a/include/asm-m68k/immap_520x.h b/include/asm-m68k/immap_520x.h
new file mode 100644
index 000000000..08bc1090c
--- /dev/null
+++ b/include/asm-m68k/immap_520x.h
@@ -0,0 +1,212 @@
+/*
+ * MCF520x Internal Memory Map
+ *
+ * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_520X__
+#define __IMMAP_520X__
+
+#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
+#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
+#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000)
+#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000)
+#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
+#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
+#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000)
+#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
+#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x0005C000)
+#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
+#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
+#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
+#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
+#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
+#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
+#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
+#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
+#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
+#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00088000)
+#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x0008C000)
+#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00090000)
+#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
+#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
+#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
+#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000A8000)
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/qspi.h>
+
+/* System Controller Module */
+typedef struct scm1 {
+ u32 mpr; /* 0x00 Master Privilege */
+ u32 rsvd1[7];
+ u32 pacra; /* 0x20 Peripheral Access Ctrl A */
+ u32 pacrb; /* 0x24 Peripheral Access Ctrl B */
+ u32 pacrc; /* 0x28 Peripheral Access Ctrl C */
+ u32 pacrd; /* 0x2C Peripheral Access Ctrl D */
+ u32 rsvd2[4];
+ u32 pacre; /* 0x40 Peripheral Access Ctrl E */
+ u32 pacrf; /* 0x44 Peripheral Access Ctrl F */
+ u32 rsvd3[3];
+ u32 bmt; /* 0x50 bus monitor */
+} scm1_t;
+
+typedef struct scm2 {
+ u8 rsvd1[19]; /* 0x00 - 0x12 */
+ u8 wcr; /* 0x13 */
+ u16 rsvd2; /* 0x14 - 0x15 */
+ u16 cwcr; /* 0x16 */
+ u8 rsvd3[3]; /* 0x18 - 0x1A */
+ u8 cwsr; /* 0x1B */
+ u8 rsvd4[3]; /* 0x1C - 0x1E */
+ u8 scmisr; /* 0x1F */
+ u8 rsvd5[79]; /* 0x20 - 0x6F */
+ u32 cfadr; /* 0x70 */
+ u8 rsvd7; /* 0x74 */
+ u8 cfier; /* 0x75 */
+ u8 cfloc; /* 0x76 */
+ u8 cfatr; /* 0x77 */
+ u32 rsvd8; /* 0x78 - 0x7B */
+ u32 cfdtr; /* 0x7C */
+} scm2_t;
+
+/* Chip configuration module */
+typedef struct rcm {
+ u8 rcr;
+ u8 rsr;
+} rcm_t;
+
+typedef struct ccm_ctrl {
+ u16 ccr; /* 0x00 Chip Cfg */
+ u16 res1; /* 0x02 */
+ u16 rcon; /* 0x04 Reset Cfg */
+ u16 cir; /* 0x06 Chip ID */
+} ccm_t;
+
+/* GPIO port */
+typedef struct gpio_ctrl {
+ /* Port Output Data */
+ u8 podr_busctl; /* 0x00 */
+ u8 podr_be; /* 0x01 */
+ u8 podr_cs; /* 0x02 */
+ u8 podr_feci2c; /* 0x03 */
+ u8 podr_qspi; /* 0x04 */
+ u8 podr_timer; /* 0x05 */
+ u8 podr_uart; /* 0x06 */
+ u8 podr_fech; /* 0x07 */
+ u8 podr_fecl; /* 0x08 */
+ u8 res01[3]; /* 0x9 - 0x0B */
+
+ /* Port Data Direction */
+ u8 pddr_busctl; /* 0x0C */
+ u8 pddr_be; /* 0x0D */
+ u8 pddr_cs; /* 0x0E */
+ u8 pddr_feci2c; /* 0x0F */
+ u8 pddr_qspi; /* 0x10*/
+ u8 pddr_timer; /* 0x11 */
+ u8 pddr_uart; /* 0x12 */
+ u8 pddr_fech; /* 0x13 */
+ u8 pddr_fecl; /* 0x14 */
+ u8 res02[5]; /* 0x15 - 0x19 */
+
+ /* Port Data Direction */
+ u8 ppdr_cs; /* 0x1A */
+ u8 ppdr_feci2c; /* 0x1B */
+ u8 ppdr_qspi; /* 0x1C */
+ u8 ppdr_timer; /* 0x1D */
+ u8 ppdr_uart; /* 0x1E */
+ u8 ppdr_fech; /* 0x1F */
+ u8 ppdr_fecl; /* 0x20 */
+ u8 res03[3]; /* 0x21 - 0x23 */
+
+ /* Port Clear Output Data */
+ u8 pclrr_busctl; /* 0x24 */
+ u8 pclrr_be; /* 0x25 */
+ u8 pclrr_cs; /* 0x26 */
+ u8 pclrr_feci2c; /* 0x27 */
+ u8 pclrr_qspi; /* 0x28 */
+ u8 pclrr_timer; /* 0x29 */
+ u8 pclrr_uart; /* 0x2A */
+ u8 pclrr_fech; /* 0x2B */
+ u8 pclrr_fecl; /* 0x2C */
+ u8 res04[3]; /* 0x2D - 0x2F */
+
+ /* Pin Assignment */
+ u8 par_busctl; /* 0x30 */
+ u8 par_be; /* 0x31 */
+ u8 par_cs; /* 0x32 */
+ u8 par_feci2c; /* 0x33 */
+ u8 par_qspi; /* 0x34 */
+ u8 par_timer; /* 0x35 */
+ u16 par_uart; /* 0x36 */
+ u8 par_fec; /* 0x38 */
+ u8 par_irq; /* 0x39 */
+
+ /* Mode Select Control */
+ /* Drive Strength Control */
+ u8 mscr_fb; /* 0x3A */
+ u8 mscr_sdram; /* 0x3B */
+
+ u8 dscr_i2c; /* 0x3C */
+ u8 dscr_misc; /* 0x3D */
+ u8 dscr_fec; /* 0x3E */
+ u8 dscr_uart; /* 0x3F */
+ u8 dscr_qspi; /* 0x40 */
+} gpio_t;
+
+/* SDRAM controller */
+typedef struct sdram_ctrl {
+ u32 mode; /* 0x00 Mode/Extended Mode */
+ u32 ctrl; /* 0x04 Ctrl */
+ u32 cfg1; /* 0x08 Cfg 1 */
+ u32 cfg2; /* 0x0C Cfg 2 */
+ u32 res1[64]; /* 0x10 - 0x10F */
+ u32 cs0; /* 0x110 Chip Select 0 Cfg */
+ u32 cs1; /* 0x114 Chip Select 1 Cfg */
+} sdram_t;
+
+/* Clock Module */
+typedef struct pll_ctrl {
+ u8 odr; /* 0x00 Output divider */
+ u8 rsvd1;
+ u8 cr; /* 0x02 Control */
+ u8 rsvd2;
+ u8 mdr; /* 0x04 Modulation Divider */
+ u8 rsvd3;
+ u8 fdr; /* 0x06 Feedback Divider */
+ u8 rsvd4;
+} pll_t;
+
+/* Watchdog registers */
+typedef struct wdog_ctrl {
+ u16 cr; /* 0x00 Control */
+ u16 mr; /* 0x02 Modulus */
+ u16 cntr; /* 0x04 Count */
+ u16 sr; /* 0x06 Service */
+} wdog_t;
+
+#endif /* __IMMAP_520X__ */
diff --git a/include/asm-m68k/m520x.h b/include/asm-m68k/m520x.h
new file mode 100644
index 000000000..267bfd994
--- /dev/null
+++ b/include/asm-m68k/m520x.h
@@ -0,0 +1,358 @@
+/*
+ * m520x.h -- Definitions for Freescale Coldfire 520x
+ *
+ * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __M520X__
+#define __M520X__
+
+/* *** System Control Module (SCM) *** */
+#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28)
+#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24)
+#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20)
+#define MPROT_MTR 4
+#define MPROT_MTW 2
+#define MPROT_MPL 1
+
+#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28)
+#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24)
+#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20)
+
+#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12)
+
+#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28)
+#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24)
+#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20)
+#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8)
+#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4)
+#define SCM_PACRC_PACR23(x) ((x) & 0x0F)
+
+#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28)
+#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24)
+#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20)
+#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12)
+#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8)
+#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4)
+#define SCM_PACRD_PACR31(x) ((x) & 0x0F)
+
+#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28)
+#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24)
+#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20)
+#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16)
+#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12)
+
+#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28)
+#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24)
+#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20)
+
+#define PACR_SP 4
+#define PACR_WP 2
+#define PACR_TP 1
+
+#define SCM_BMT_BME (0x00000008)
+#define SCM_BMT_BMT_MASK (0x07)
+#define SCM_BMT_BMT(x) ((x) & 0x07)
+#define SCM_BMT_BMT1024 (0x0000)
+#define SCM_BMT_BMT512 (0x0001)
+#define SCM_BMT_BMT256 (0x0002)
+#define SCM_BMT_BMT128 (0x0003)
+#define SCM_BMT_BMT64 (0x0004)
+#define SCM_BMT_BMT32 (0x0005)
+#define SCM_BMT_BMT16 (0x0006)
+#define SCM_BMT_BMT8 (0x0007)
+
+#define SCM_CWCR_RO (0x8000)
+#define SCM_CWCR_CWR_WH (0x0100)
+#define SCM_CWCR_CWE (0x0080)
+#define SCM_CWRI_WINDOW (0x0060)
+#define SCM_CWRI_RESET (0x0040)
+#define SCM_CWRI_INT_RESET (0x0020)
+#define SCM_CWRI_INT (0x0000)
+#define SCM_CWCR_CWT(x) (((x) & 0x001F))
+
+#define SCM_ISR_CFEI (0x02)
+#define SCM_ISR_CWIC (0x01)
+
+#define SCM_CFIER_ECFEI (0x01)
+
+#define SCM_CFLOC_LOC (0x80)
+
+#define SCM_CFATR_WRITE (0x80)
+#define SCM_CFATR_SZ32 (0x20)
+#define SCM_CFATR_SZ16 (0x10)
+#define SCM_CFATR_SZ08 (0x00)
+#define SCM_CFATR_CACHE (0x08)
+#define SCM_CFATR_MODE (0x02)
+#define SCM_CFATR_TYPE (0x01)
+
+/* *** Interrupt Controller (INTC) *** */
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT_F1 (1)
+#define INT0_LO_EPORT_F4 (2)
+#define INT0_LO_EPORT_F7 (3)
+#define INT1_LO_PIT0 (4)
+#define INT1_LO_PIT1 (5)
+/* 6 - 7 rsvd */
+#define INT0_LO_EDMA_00 (8)
+#define INT0_LO_EDMA_01 (9)
+#define INT0_LO_EDMA_02 (10)
+#define INT0_LO_EDMA_03 (11)
+#define INT0_LO_EDMA_04 (12)
+#define INT0_LO_EDMA_05 (13)
+#define INT0_LO_EDMA_06 (14)
+#define INT0_LO_EDMA_07 (15)
+#define INT0_LO_EDMA_08 (16)
+#define INT0_LO_EDMA_09 (17)
+#define INT0_LO_EDMA_10 (18)
+#define INT0_LO_EDMA_11 (19)
+#define INT0_LO_EDMA_12 (20)
+#define INT0_LO_EDMA_13 (21)
+#define INT0_LO_EDMA_14 (22)
+#define INT0_LO_EDMA_15 (23)
+#define INT0_LO_EDMA_ERR (24)
+#define INT0_LO_SCM_CWIC (25)
+#define INT0_LO_UART0 (26)
+#define INT0_LO_UART1 (27)
+#define INT0_LO_UART2 (28)
+/* 29 rsvd */
+#define INT0_LO_I2C (30)
+#define INT0_LO_QSPI (31)
+
+#define INT0_HI_DTMR0 (32)
+#define INT0_HI_DTMR1 (33)
+#define INT0_HI_DTMR2 (34)
+#define INT0_HI_DTMR3 (35)
+#define INT0_HI_FEC0_TXF (36)
+#define INT0_HI_FEC0_TXB (37)
+#define INT0_HI_FEC0_UN (38)
+#define INT0_HI_FEC0_RL (39)
+#define INT0_HI_FEC0_RXF (40)
+#define INT0_HI_FEC0_RXB (41)
+#define INT0_HI_FEC0_MII (42)
+#define INT0_HI_FEC0_LC (43)
+#define INT0_HI_FEC0_HBERR (44)
+#define INT0_HI_FEC0_GRA (45)
+#define INT0_HI_FEC0_EBERR (46)
+#define INT0_HI_FEC0_BABT (47)
+#define INT0_HI_FEC0_BABR (48)
+/* 49 - 61 rsvd */
+#define INT0_HI_SCMISR_CFEI (62)
+
+/* *** Reset Controller Module (RCM) *** */
+#define RCM_RCR_SOFTRST (0x80)
+#define RCM_RCR_FRCRSTOUT (0x40)
+
+#define RCM_RSR_SOFT (0x20)
+#define RCM_RSR_WDOG (0x10)
+#define RCM_RSR_POR (0x08)
+#define RCM_RSR_EXT (0x04)
+#define RCM_RSR_WDR_CORE (0x02)
+#define RCM_RSR_LOL (0x01)
+
+/* *** Chip Configuration Module (CCM) *** */
+#define CCM_CCR_CSC (0x0200)
+#define CCM_CCR_OSCFREQ (0x0080)
+#define CCM_CCR_LIMP (0x0040)
+#define CCM_CCR_LOAD (0x0020)
+#define CCM_CCR_BOOTPS(x) (((x) & 0x0003) << 3)
+#define CCM_CCR_OSC_MODE (0x0004)
+#define CCM_CCR_PLL_MODE (0x0002)
+#define CCM_CCR_RESERVED (0x0001)
+
+#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6)
+#define CCM_CIR_PRN(x) ((x) & 0x003F)
+
+/* *** General Purpose I/O (GPIO) *** */
+#define GPIO_PDR_BUSCTL(x) ((x) & 0x0F)
+#define GPIO_PDR_BE(x) ((x) & 0x0F)
+#define GPIO_PDR_CS(x) (((x) & 0x07) << 1)
+#define GPIO_PDR_FECI2C(x) ((x) & 0x0F)
+#define GPIO_PDR_QSPI(x) ((x) & 0x0F)
+#define GPIO_PDR_TIMER(x) ((x) & 0x0F)
+#define GPIO_PDR_UART(x) ((x) & 0xFF)
+#define GPIO_PDR_FECH(x) ((x) & 0xFF)
+#define GPIO_PDR_FECL(x) ((x) & 0xFF)
+
+#define GPIO_PAR_FBCTL_OE (0x10)
+#define GPIO_PAR_FBCTL_TA (0x08)
+#define GPIO_PAR_FBCTL_RWB (0x04)
+#define GPIO_PAR_FBCTL_TS_MASK (0xFC)
+#define GPIO_PAR_FBCTL_TS_TS (0x03)
+#define GPIO_PAR_FBCTL_TS_DMA (0x02)
+
+#define GPIO_PAR_BE3 (0x08)
+#define GPIO_PAR_BE2 (0x04)
+#define GPIO_PAR_BE1 (0x02)
+#define GPIO_PAR_BE0 (0x01)
+
+#define GPIO_PAR_CS3 (0x08)
+#define GPIO_PAR_CS2 (0x04)
+#define GPIO_PAR_CS1_MASK (0xFC)
+#define GPIO_PAR_CS1_CS1 (0x03)
+#define GPIO_PAR_CS1_SDCS1 (0x02)
+
+#define GPIO_PAR_FECI2C_RMII_MASK (0x0F)
+#define GPIO_PAR_FECI2C_MDC_MASK (0x3F)
+#define GPIO_PAR_FECI2C_MDC_MDC (0xC0)
+#define GPIO_PAR_FECI2C_MDC_SCL (0x80)
+#define GPIO_PAR_FECI2C_MDC_U2TXD (0x40)
+#define GPIO_PAR_FECI2C_MDIO_MASK (0xCF)
+#define GPIO_PAR_FECI2C_MDIO_MDIO (0x30)
+#define GPIO_PAR_FECI2C_MDIO_SDA (0x20)
+#define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10)
+#define GPIO_PAR_FECI2C_I2C_MASK (0xF0)
+#define GPIO_PAR_FECI2C_SCL_MASK (0xF3)
+#define GPIO_PAR_FECI2C_SCL_SCL (0x0C)
+#define GPIO_PAR_FECI2C_SCL_U2RXD (0x04)
+#define GPIO_PAR_FECI2C_SDA_MASK (0xFC)
+#define GPIO_PAR_FECI2C_SDA_SDA (0x03)
+#define GPIO_PAR_FECI2C_SDA_U2TXD (0x01)
+
+#define GPIO_PAR_QSPI_PCS2_MASK (0x3F)
+#define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0)
+#define GPIO_PAR_QSPI_PCS2_DACK0 (0x80)
+#define GPIO_PAR_QSPI_PCS2_U2RTS (0x40)
+#define GPIO_PAR_QSPI_DIN_MASK (0xCF)
+#define GPIO_PAR_QSPI_DIN_DIN (0x30)
+#define GPIO_PAR_QSPI_DIN_DREQ0 (0x20)
+#define GPIO_PAR_QSPI_DIN_U2CTS (0x10)
+#define GPIO_PAR_QSPI_DOUT_MASK (0xF3)
+#define GPIO_PAR_QSPI_DOUT_DOUT (0x0C)
+#define GPIO_PAR_QSPI_DOUT_SDA (0x08)
+#define GPIO_PAR_QSPI_SCK_MASK (0xFC)
+#define GPIO_PAR_QSPI_SCK_SCK (0x03)
+#define GPIO_PAR_QSPI_SCK_SCL (0x02)
+
+#define GPIO_PAR_TMR_TIN3(x) (((x) & 0x03) << 6)
+#define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4)
+#define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2)
+#define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03)
+#define GPIO_PAR_TMR_TIN3_MASK (0x3F)
+#define GPIO_PAR_TMR_TIN3_TIN3 (0xC0)
+#define GPIO_PAR_TMR_TIN3_TOUT3 (0x80)
+#define GPIO_PAR_TMR_TIN3_U2CTS (0x40)
+#define GPIO_PAR_TMR_TIN2_MASK (0xCF)
+#define GPIO_PAR_TMR_TIN2_TIN2 (0x30)
+#define GPIO_PAR_TMR_TIN2_TOUT2 (0x20)
+#define GPIO_PAR_TMR_TIN2_U2RTS (0x10)
+#define GPIO_PAR_TMR_TIN1_MASK (0xF3)
+#define GPIO_PAR_TMR_TIN1_TIN1 (0x0C)
+#define GPIO_PAR_TMR_TIN1_TOUT1 (0x08)
+#define GPIO_PAR_TMR_TIN1_U2RXD (0x04)
+#define GPIO_PAR_TMR_TIN0_MASK (0xFC)
+#define GPIO_PAR_TMR_TIN0_TIN0 (0x03)
+#define GPIO_PAR_TMR_TIN0_TOUT0 (0x02)
+#define GPIO_PAR_TMR_TIN0_U2TXD (0x01)
+
+#define GPIO_PAR_UART1_MASK (0xF03F)
+#define GPIO_PAR_UART0_MASK (0xFFC0)
+#define GPIO_PAR_UART_U1CTS_MASK (0xF3FF)
+#define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00)
+#define GPIO_PAR_UART_U1CTS_TIN1 (0x0800)
+#define GPIO_PAR_UART_U1CTS_PCS1 (0x0400)
+#define GPIO_PAR_UART_U1RTS_MASK (0xFCFF)
+#define GPIO_PAR_UART_U1RTS_U1RTS (0x0300)
+#define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200)
+#define GPIO_PAR_UART_U1RTS_PCS1 (0x0100)
+#define GPIO_PAR_UART_U1TXD (0x0080)
+#define GPIO_PAR_UART_U1RXD (0x0040)
+#define GPIO_PAR_UART_U0CTS_MASK (0xFFCF)
+#define GPIO_PAR_UART_U0CTS_U0CTS (0x0030)
+#define GPIO_PAR_UART_U0CTS_TIN0 (0x0020)
+#define GPIO_PAR_UART_U0CTS_PCS0 (0x0010)
+#define GPIO_PAR_UART_U0RTS_MASK (0xFFF3)
+#define GPIO_PAR_UART_U0RTS_U0RTS (0x000C)
+#define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008)
+#define GPIO_PAR_UART_U0RTS_PCS0 (0x0004)
+#define GPIO_PAR_UART_U0TXD (0x0002)
+#define GPIO_PAR_UART_U0RXD (0x0001)
+
+#define GPIO_PAR_FEC_7W_MASK (0xF3)
+#define GPIO_PAR_FEC_7W_FEC (0x0C)
+#define GPIO_PAR_FEC_7W_U1RTS (0x04)
+#define GPIO_PAR_FEC_MII_MASK (0xFC)
+#define GPIO_PAR_FEC_MII_FEC (0x03)
+#define GPIO_PAR_FEC_MII_UnCTS (0x01)
+
+#define GPIO_PAR_IRQ_IRQ4 (0x01)
+
+#define GPIO_MSCR_FB_FBCLK(x) (((x) & 0x03) << 6)
+#define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4)
+#define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2)
+#define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03)
+#define GPIO_MSCR_FB_FBCLK_MASK (0x3F)
+#define GPIO_MSCR_FB_DUP_MASK (0xCF)
+#define GPIO_MSCR_FB_DLO_MASK (0xF3)
+#define GPIO_MSCR_FB_ADRCTL_MASK (0xFC)
+
+#define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4)
+#define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2)
+#define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03)
+#define GPIO_MSCR_SDR_SDCLKB_MASK (0xCF)
+#define GPIO_MSCR_SDR_SDCLK_MASK (0xF3)
+#define GPIO_MSCR_SDR_SDRAM_MASK (0xFC)
+
+#define MSCR_25VDDR (0x03)
+#define MSCR_18VDDR_FULL (0x02)
+#define MSCR_OPENDRAIN (0x01)
+#define MSCR_18VDDR_HALF (0x00)
+
+#define GPIO_DSCR_I2C(x) ((x) & 0x03)
+#define GPIO_DSCR_I2C_MASK (0xFC)
+
+#define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4)
+#define GPIO_DSCR_MISC_DBG_MASK (0xCF)
+#define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2)
+#define GPIO_DSCR_MISC_RSTOUT_MASK (0xF3)
+#define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03)
+#define GPIO_DSCR_MISC_TIMER_MASK (0xFC)
+
+#define GPIO_DSCR_FEC(x) ((x) & 0x03)
+#define GPIO_DSCR_FEC_MASK (0xFC)
+
+#define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4)
+#define GPIO_DSCR_UART_UART1_MASK (0xCF)
+#define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2)
+#define GPIO_DSCR_UART_UART0_MASK (0xF3)
+#define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03)
+#define GPIO_DSCR_UART_IRQ_MASK (0xFC)
+
+#define GPIO_DSCR_QSPI(x) ((x) & 0x03)
+#define GPIO_DSCR_QSPI_MASK (0xFC)
+
+#define DSCR_50PF (0x03)
+#define DSCR_30PF (0x02)
+#define DSCR_20PF (0x01)
+#define DSCR_10PF (0x00)
+
+/* *** Phase Locked Loop (PLL) *** */
+#define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4)
+#define PLL_PODR_CPUDIV_MASK (0x0F)
+#define PLL_PODR_BUSDIV(x) ((x) & 0x0F)
+#define PLL_PODR_BUSDIV_MASK (0xF0)
+
+#define PLL_PCR_DITHEN (0x80)
+#define PLL_PCR_DITHDEV(x) ((x) & 0x07)
+#define PLL_PCR_DITHDEV_MASK (0xF8)
+
+#endif /* __M520X__ */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 2c0c0cee4..284110451 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -883,8 +883,10 @@
#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */
#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */
#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */
+#define PVR_460EX_RB 0x130218A4 /* 460EX rev B with and without Sec Eng*/
#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */
#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */
+#define PVR_460GT_RB 0x130218A5 /* 460GT rev B with and without Sec Eng*/
#define PVR_460SX_RA 0x13541800 /* 460SX rev A */
#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
#define PVR_460GX_RA 0x13541802 /* 460GX rev A */
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
new file mode 100644
index 000000000..32123d2f5
--- /dev/null
+++ b/include/configs/M5208EVBE.h
@@ -0,0 +1,223 @@
+/*
+ * Configuation settings for the Freescale MCF5208EVBe.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _M5208EVBE_H
+#define _M5208EVBE_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF520x /* define processor family */
+#define CONFIG_M5208 /* define processor type */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT (0)
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 5000
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#undef CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CONFIG_MII_INIT 1
+# define CONFIG_SYS_DISCOVER_PHY
+# define CONFIG_SYS_RX_ETH_BUFFER 8
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# define CONFIG_HAS_ETH1
+
+# define CONFIG_SYS_FEC0_PINMUX 0
+# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CONFIG_SYS_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SPEED 80000
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x58000
+#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
+
+#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* CONFIG_MCFFEC */
+
+#define CONFIG_HOSTNAME M5208EVBe
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=40010000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off 0 3ffff;" \
+ "era 0 3ffff;" \
+ "cp.b ${loadaddr} 0 ${filesize};" \
+ "save\0" \
+ ""
+
+#define CONFIG_PRAM 512 /* 512 KB */
+#define CONFIG_SYS_PROMPT "-> "
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
+#define CONFIG_SYS_LOAD_ADDR 0x40010000
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
+#define CONFIG_SYS_PLL_ODR 0x36
+#define CONFIG_SYS_PLL_FDR 0x7D
+
+#define CONFIG_SYS_MBAR 0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/* Definitions for initial stack pointer and data area (in DPRAM) */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
+#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL 0x221
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1 0x43711630
+#define CONFIG_SYS_SDRAM_CFG2 0x56670000
+#define CONFIG_SYS_SDRAM_CTRL 0xE1002000
+#define CONFIG_SYS_SDRAM_EMOD 0x80010000
+#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
+#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
+
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+# define CONFIG_FLASH_CFI_DRIVER 1
+# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */
+# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+#endif
+
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+
+/*
+ * Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CONFIG_ENV_OFFSET 0x2000
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_ENV_SECT_SIZE 0x2000
+#define CONFIG_ENV_IS_IN_FLASH 1
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE 16
+
+/* Chipselect bank definitions */
+/*
+ * CS0 - NOR Flash
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CONFIG_SYS_CS0_BASE 0
+#define CONFIG_SYS_CS0_MASK 0x007F0001
+#define CONFIG_SYS_CS0_CTRL 0x00001FA0
+
+#endif /* _M5208EVBE_H */
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 053a914eb..e7db0cc10 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -154,26 +154,22 @@
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* DSPI and Serial Flash */
+#define CONFIG_CF_SPI
#define CONFIG_CF_DSPI
#define CONFIG_HARD_SPI
-#define CONFIG_SYS_SER_FLASH_BASE 0x01000000
#define CONFIG_SYS_SBFHDR_SIZE 0x7
#ifdef CONFIG_CMD_SPI
# define CONFIG_SYS_DSPI_CS2
# define CONFIG_SPI_FLASH
# define CONFIG_SPI_FLASH_STMICRO
-# define CONFIG_SYS_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \
- DSPI_DCTAR_CPOL | \
- DSPI_DCTAR_CPHA | \
- DSPI_DCTAR_PCSSCK_1CLK | \
- DSPI_DCTAR_PASC(0) | \
- DSPI_DCTAR_PDT(0) | \
- DSPI_DCTAR_CSSCK(0) | \
- DSPI_DCTAR_ASC(0) | \
- DSPI_DCTAR_PBR(0) | \
- DSPI_DCTAR_DT(1) | \
- DSPI_DCTAR_BR(1))
+# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
+ DSPI_CTAR_PCSSCK_1CLK | \
+ DSPI_CTAR_PASC(0) | \
+ DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(0) | \
+ DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(1))
#endif
/* Input, PCI, Flexbus, and VCO */
@@ -265,9 +261,7 @@
* FLASH organization
*/
#ifdef CONFIG_SYS_STMICRO_BOOT
-# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SER_FLASH_BASE
-# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_SER_FLASH_BASE
-# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS0_BASE
+# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
# define CONFIG_ENV_OFFSET 0x30000
# define CONFIG_ENV_SIZE 0x1000
# define CONFIG_ENV_SECT_SIZE 0x10000
@@ -283,6 +277,8 @@
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_FLASH_CFI_DRIVER 1
+# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+# define CONFIG_FLASH_SPANSION_S29WS_N 1
# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 07c85c4f5..30855bdaa 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -77,6 +77,9 @@
# define CONFIG_SYS_FEC1_PINMUX 0
# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
# define MCFFEC_TOUT_LOOP 50000
+
+# define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2"
+
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
@@ -204,7 +207,9 @@
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_FLASH_CFI_DRIVER 1
-# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+# define CONFIG_FLASH_SPANSION_S29WS_N 1
+# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 45f701652..fa444c39e 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -70,6 +70,7 @@
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SPI
@@ -93,7 +94,7 @@
# define MCFFEC_TOUT_LOOP 50000
# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
-# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
+# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_ETHPRIME "FEC0"
# define CONFIG_IPADDR 192.162.1.2
@@ -163,35 +164,33 @@
#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x58000
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
+#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* DSPI and Serial Flash */
+#define CONFIG_CF_SPI
#define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH
#define CONFIG_HARD_SPI
-#define CONFIG_SYS_SER_FLASH_BASE 0x01000000
#define CONFIG_SYS_SBFHDR_SIZE 0x7
#ifdef CONFIG_CMD_SPI
# define CONFIG_SPI_FLASH
# define CONFIG_SPI_FLASH_STMICRO
-# define CONFIG_SYS_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \
- DSPI_DCTAR_CPOL | \
- DSPI_DCTAR_CPHA | \
- DSPI_DCTAR_PCSSCK_1CLK | \
- DSPI_DCTAR_PASC(0) | \
- DSPI_DCTAR_PDT(0) | \
- DSPI_DCTAR_CSSCK(0) | \
- DSPI_DCTAR_ASC(0) | \
- DSPI_DCTAR_PBR(0) | \
- DSPI_DCTAR_DT(1) | \
- DSPI_DCTAR_BR(1))
+# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
+ DSPI_CTAR_PCSSCK_1CLK | \
+ DSPI_CTAR_PASC(0) | \
+ DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(0) | \
+ DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(1))
+# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
+# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
#endif
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
-#define CONFIG_PRAM 2048 /* 2048 KB */
+#define CONFIG_PRAM 2048 /* 2048 KB */
#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
@@ -209,7 +208,7 @@
#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_MBAR 0xFC000000
+#define CONFIG_SYS_MBAR 0xFC000000
/*
* Low Level Configuration Settings
@@ -265,7 +264,7 @@
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SYS_STMICRO_BOOT)
# define CONFIG_ENV_IS_IN_SPI_FLASH 1
# define CONFIG_ENV_SPI_CS 1
# define CONFIG_ENV_OFFSET 0x20000
@@ -273,30 +272,21 @@
# define CONFIG_ENV_SECT_SIZE 0x10000
#else
# define CONFIG_ENV_IS_IN_FLASH 1
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
-# define CONFIG_ENV_SECT_SIZE 0x2000
+# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000)
+# define CONFIG_ENV_SIZE 0x2000
+# define CONFIG_ENV_SECT_SIZE 0x8000
#endif
#undef CONFIG_ENV_OVERWRITE
#undef CONFIG_ENV_IS_EMBEDDED
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#ifdef CONFIG_SYS_STMICRO_BOOT
-# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SER_FLASH_BASE
-# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_SER_FLASH_BASE
-# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS0_BASE
-#endif
-#ifdef CONFIG_SYS_SPANSION_BOOT
-# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_SER_FLASH_BASE
-#endif
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_FLASH_CFI_DRIVER 1
+# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
@@ -311,27 +301,20 @@
* This is setting for JFFS2 support in u-boot.
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/
-#ifdef CONFIG_SYS_SPANSION_BOOT
-# define CONFIG_JFFS2_DEV "nor0"
-# define CONFIG_JFFS2_PART_SIZE 0x01000000
-# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
-#endif
-#ifdef CONFIG_SYS_STMICRO_BOOT
+#ifdef CONFIG_CMD_JFFS2
# define CONFIG_JFFS2_DEV "nor0"
# define CONFIG_JFFS2_PART_SIZE 0x01000000
# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
+/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
/*
- * CS0 - NOR Flash 8MB
+ * CS0 - NOR Flash 16MB
* CS1 - Available
* CS2 - Available
* CS3 - Available
@@ -339,10 +322,10 @@
* CS5 - Available
*/
- /* SPANSION Flash */
+ /* Flash */
#define CONFIG_SYS_CS0_BASE 0x00000000
-#define CONFIG_SYS_CS0_MASK 0x007F0001
-#define CONFIG_SYS_CS0_CTRL 0x00001180
+#define CONFIG_SYS_CS0_MASK 0x00FF0001
+#define CONFIG_SYS_CS0_CTRL 0x00004D80
#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 87f3a73ae..14d98d69c 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -200,25 +200,21 @@
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* DSPI and Serial Flash */
+#define CONFIG_CF_SPI
#define CONFIG_CF_DSPI
#define CONFIG_HARD_SPI
-#define CONFIG_SYS_SER_FLASH_BASE 0x01000000
#define CONFIG_SYS_SBFHDR_SIZE 0x13
#ifdef CONFIG_CMD_SPI
# define CONFIG_SPI_FLASH
# define CONFIG_SPI_FLASH_STMICRO
-# define CONFIG_SYS_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \
- DSPI_DCTAR_CPOL | \
- DSPI_DCTAR_CPHA | \
- DSPI_DCTAR_PCSSCK_1CLK | \
- DSPI_DCTAR_PASC(0) | \
- DSPI_DCTAR_PDT(0) | \
- DSPI_DCTAR_CSSCK(0) | \
- DSPI_DCTAR_ASC(0) | \
- DSPI_DCTAR_PBR(0) | \
- DSPI_DCTAR_DT(1) | \
- DSPI_DCTAR_BR(1))
+# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
+ DSPI_CTAR_PCSSCK_1CLK | \
+ DSPI_CTAR_PASC(0) | \
+ DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(0) | \
+ DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(1))
#endif
/* PCI */
@@ -342,10 +338,8 @@
* FLASH organization
*/
#ifdef CONFIG_SYS_STMICRO_BOOT
-# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SER_FLASH_BASE
-# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_SER_FLASH_BASE
-# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH2_BASE CONFIG_SYS_CS1_BASE
+# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE
# define CONFIG_ENV_OFFSET 0x30000
# define CONFIG_ENV_SIZE 0x2000
# define CONFIG_ENV_SECT_SIZE 0x10000
@@ -370,6 +364,7 @@
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_FLASH_CFI_DRIVER 1
+# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 0aaab4a4a..9d2b8600c 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -534,7 +534,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_NET
#endif
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 2de313931..0caf45603 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -433,7 +433,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
- #define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_NET
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_EXT2
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 64f5c4b75..d0933bae9 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -585,7 +585,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_NET
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_EXT2
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 5c2c5cb32..ad24e0c88 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -614,7 +614,6 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_NET
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_EXT2
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 3b733c03e..a2b7ee8cf 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -137,10 +137,11 @@
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the 40x Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/*
* Internal Definitions
@@ -214,9 +215,9 @@
" console=" xstr(CONFIG_USE_TTY) ",${baudrate}\0" \
CONFIG_ADDMISC \
"initrd_high=30000000\0" \
- "kernel_addr_r=400000\0" \
- "fdt_addr_r=800000\0" \
- "ramdisk_addr_r=C00000\0" \
+ "kernel_addr_r=1000000\0" \
+ "fdt_addr_r=1800000\0" \
+ "ramdisk_addr_r=1900000\0" \
"hostname=" xstr(CONFIG_HOSTNAME) "\0" \
"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index 2017b666a..590c69a19 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -45,11 +45,6 @@
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index 58ec94a84..b4f075ebc 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -56,11 +56,6 @@
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index 80559bf19..be478b24e 100644
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -44,11 +44,6 @@
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index 7a5769696..f4fd808e4 100644
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -45,11 +45,6 @@
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index 6ccebfaf8..2bdaaace3 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -114,29 +114,109 @@
#undef CONFIG_BOOTARGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "console=ttyPSC0\0" \
- "kernel_addr_r=400000\0" \
- "fdt_addr_r=600000\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:"\
- "${netmask}:${hostname}:${netdev}:off panic=1\0" \
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fw_image=digsyMPC.img\0" \
+ "mtcb_start=mtc led diag orange; run mtcb_1\0" \
+ "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; " \
+ "do mtc led $x; done\0" \
+ "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; " \
+ "else run mtcb_fw; fi\0" \
+ "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; " \
+ "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0" \
+ "mtcb_update=mtc led user1 orange;" \
+ "while mtc key; do ; done; run mtcb_2;\0" \
+ "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0" \
+ "mtcb_usb1=if fatload usb 0 400000 script.img; " \
+ "then run mtcb_doscript; else run mtcb_usb2; fi\0" \
+ "mtcb_usb2=if fatload usb 0 400000 $fw_image; " \
+ "then run mtcb_dousb; else run mtcb_ide; fi\0" \
+ "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; " \
+ "run mtcb_wait_flickr mtcb_ds_1;\0" \
+ "mtcb_ds_1=if imi 400000; then mtc led usbbusy; " \
+ "source 400000; else run mtcb_error; fi\0" \
+ "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0" \
+ "mtcb_du_1=if imi 400000; then run mtcb_du_2; " \
+ "else run mtcb_error; fi\0" \
+ "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; " \
+ "run mtcb_checkfw\0" \
+ "mtcb_checkfw=if imi ff000000; then run mtcb_success; " \
+ "else run mtcb_error; fi\0" \
+ "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
+ "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0" \
+ "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
+ "mtcb_uledflckr=mtc led user1 orange 11\0" \
+ "mtcb_error=mtc led user1 red\0" \
+ "mtcb_clear=erase ff000000 ff0fffff\0" \
+ "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0" \
+ "mtcb_success=mtc led user1 green\0" \
+ "mtcb_ide=if fatload ide 0 400000 $fw_image;" \
+ "then run mtcb_doide; else run mtcb_error; fi\0" \
+ "mtcb_doide=mtc led user2 green 1;" \
+ "run mtcb_wait_flickr mtcb_di_1;\0" \
+ "mtcb_di_1=if imi 400000; then run mtcb_di_2;" \
+ "else run mtcb_error; fi\0" \
+ "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0" \
+ "ramdisk_num_sector=16\0" \
+ "flash_base=ff000000\0" \
+ "flashdisk_size=e00000\0" \
+ "env_sector=fff60000\0" \
+ "flashdisk_start=ff100000\0" \
+ "load_cmd=tftp 400000 digsyMPC.img\0" \
+ "clear_cmd=erase ff000000 ff0fffff\0" \
+ "flash_cmd=cp.b 400000 ff000000 ${filesize}\0" \
+ "update_cmd=run load_cmd; " \
+ "iminfo 400000; " \
+ "run clear_cmd flash_cmd; " \
+ "iminfo ff000000\0" \
+ "spi_driver=yes\0" \
+ "spi_watchdog=no\0" \
+ "ftps_start=yes\0" \
+ "ftps_user1=admin\0" \
+ "ftps_pass1=admin\0" \
+ "ftps_base1=/\0" \
+ "ftps_home1=/\0" \
+ "plc_sio_srv=no\0" \
+ "plc_sio_baud=57600\0" \
+ "plc_sio_parity=no\0" \
+ "plc_sio_stop=1\0" \
+ "plc_sio_com=2\0" \
+ "plc_eth_srv=yes\0" \
+ "plc_eth_port=1200\0" \
+ "plc_root=/ide/\0" \
+ "diag_level=0\0" \
+ "webvisu=no\0" \
+ "plc_can1_routing=no\0" \
+ "plc_can1_baudrate=250\0" \
+ "plc_can2_routing=no\0" \
+ "plc_can2_baudrate=250\0" \
+ "plc_can3_routing=no\0" \
+ "plc_can3_baudrate=250\0" \
+ "plc_can4_routing=no\0" \
+ "plc_can4_baudrate=250\0" \
+ "netdev=eth0\0" \
+ "console=ttyPSC0\0" \
+ "kernel_addr_r=400000\0" \
+ "fdt_addr_r=600000\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off panic=1\0" \
"addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
- "rootpath=/opt/eldk/ppc_6xx\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
- "tftp ${fdt_addr_r} ${fdt_file};" \
- "run nfsargs addip addcons;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "load=tftp 200000 ${u-boot}\0" \
- "update=protect off FFF00000 +${filesize};" \
- "erase FFF00000 +${filesize};" \
- "cp.b 200000 FFF00000 ${filesize};" \
- "protect on FFF00000 +${filesize}\0" \
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${fdt_addr_r} ${fdt_file};" \
+ "run nfsargs addip addcons;" \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=protect off FFF00000 +${filesize};" \
+ "erase FFF00000 +${filesize};" \
+ "cp.b 200000 FFF00000 ${filesize};" \
+ "protect on FFF00000 +${filesize}\0" \
""
+#define CONFIG_BOOTCOMMAND "run mtcb_start"
+
/*
* SPI configuration
*/
diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h
index 32a8194a2..5c066426c 100644
--- a/include/configs/m501sk.h
+++ b/include/configs/m501sk.h
@@ -46,11 +46,6 @@
*/
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
index ac678d0b6..0c2ee6057 100644
--- a/include/configs/mp2usb.h
+++ b/include/configs/mp2usb.h
@@ -49,11 +49,6 @@
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 8fc6fb26c..61629f8c4 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -300,8 +300,7 @@
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__
-extern gpmc_csx_t *nand_cs_base;
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 809198b0f..9f0f34bd8 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -292,8 +292,7 @@
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__
-extern gpmc_csx_t *nand_cs_base;
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index c359c60b1..07a031bc8 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -285,8 +285,7 @@
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__
-extern gpmc_csx_t *nand_cs_base;
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index d7b1cc189..1cfd7e969 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -289,8 +289,7 @@
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__
-extern gpmc_csx_t *nand_cs_base;
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 676b42547..61a41e725 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -297,8 +297,7 @@
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__
-extern gpmc_csx_t *nand_cs_base;
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index 3f6f5451a..03f92f58e 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -252,8 +252,7 @@
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
#ifndef __ASSEMBLY__
-extern gpmc_csx_t *nand_cs_base;
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index fc401a8f8..1f95a3ced 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -107,6 +107,7 @@
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
#define NAND_ALLOW_ERASE_ALL 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/*
diff --git a/include/exports.h b/include/exports.h
index 0620e9eb8..16ea03a6b 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -33,6 +33,7 @@ void forceenv (char *varname, char *varvalue);
int i2c_write (uchar, uint, int , uchar* , int);
int i2c_read (uchar, uint, int , uchar* , int);
#endif
+#include <spi.h>
void app_startup(char **);
@@ -46,7 +47,7 @@ enum {
XF_MAX
};
-#define XF_VERSION 4
+#define XF_VERSION 5
#if defined(CONFIG_I386)
extern gd_t *global_data;
diff --git a/include/miiphy.h b/include/miiphy.h
index 32f0a6140..fa33ec7f7 100644
--- a/include/miiphy.h
+++ b/include/miiphy.h
@@ -1,4 +1,6 @@
/*----------------------------------------------------------------------------+
+| This source code is dual-licensed. You may use it under the terms of the
+| GNU General Public License version 2, or under the license below.
|
| This source code has been made available to you by IBM on an AS-IS
| basis. Anyone receiving this source is licensed under IBM
diff --git a/include/net.h b/include/net.h
index 4a03717ae..4873000c0 100644
--- a/include/net.h
+++ b/include/net.h
@@ -119,10 +119,10 @@ extern struct eth_device *eth_get_dev(void); /* get the current device MAC */
extern struct eth_device *eth_get_dev_by_name(char *devname); /* get device */
extern struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index */
extern int eth_get_dev_index (void); /* get the device index */
-extern void eth_set_enetaddr(int num, char* a); /* Set new MAC address */
extern void eth_parse_enetaddr(const char *addr, uchar *enetaddr);
extern int eth_getenv_enetaddr(char *name, uchar *enetaddr);
extern int eth_setenv_enetaddr(char *name, const uchar *enetaddr);
+extern int eth_getenv_enetaddr_by_index(int index, uchar *enetaddr);
extern int eth_init(bd_t *bis); /* Initialize the device */
extern int eth_send(volatile void *packet, int length); /* Send a packet */
diff --git a/include/netdev.h b/include/netdev.h
index 3e66586b4..50329a3f5 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -51,6 +51,7 @@ int eepro100_initialize(bd_t *bis);
int eth_3com_initialize (bd_t * bis);
int fec_initialize (bd_t *bis);
int fecmxc_initialize (bd_t *bis);
+int ftmac100_initialize(bd_t *bits);
int greth_initialize(bd_t *bis);
void gt6426x_eth_initialize(bd_t *bis);
int inca_switch_initialize(bd_t *bis);
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 400c540cb..d783c5b1a 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -1834,6 +1834,28 @@
#define PCI_DEVICE_ID_INTEL_82562ET 0x1031
+#define PCI_DEVICE_ID_INTEL_82571EB_COPPER 0x105E
+#define PCI_DEVICE_ID_INTEL_82571EB_FIBER 0x105F
+#define PCI_DEVICE_ID_INTEL_82571EB_SERDES 0x1060
+#define PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER 0x10A4
+#define PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER 0x10D5
+#define PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER 0x10A5
+#define PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
+#define PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL 0x10D9
+#define PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD 0x10DA
+#define PCI_DEVICE_ID_INTEL_82572EI_COPPER 0x107D
+#define PCI_DEVICE_ID_INTEL_82572EI_FIBER 0x107E
+#define PCI_DEVICE_ID_INTEL_82572EI_SERDES 0x107F
+#define PCI_DEVICE_ID_INTEL_82572EI 0x10B9
+#define PCI_DEVICE_ID_INTEL_82573E 0x108B
+#define PCI_DEVICE_ID_INTEL_82573E_IAMT 0x108C
+#define PCI_DEVICE_ID_INTEL_82573L 0x109A
+#define PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3 0x10B5
+#define PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT 0x1096
+#define PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT 0x1098
+#define PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT 0x10BA
+#define PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT 0x10BB
+
#define PCI_DEVICE_ID_INTEL_82815_MC 0x1130
#define PCI_DEVICE_ID_INTEL_82559ER 0x1209
diff --git a/include/ppc405.h b/include/ppc405.h
index a17dd3595..55649e474 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -1,4 +1,6 @@
/*----------------------------------------------------------------------------+
+| This source code is dual-licensed. You may use it under the terms of the
+| GNU General Public License version 2, or under the license below.
|
| This source code has been made available to you by IBM on an AS-IS
| basis. Anyone receiving this source is licensed under IBM
diff --git a/include/ppc440.h b/include/ppc440.h
index 6ce53a6ef..7f34fda8c 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1,4 +1,6 @@
/*----------------------------------------------------------------------------+
+| This source code is dual-licensed. You may use it under the terms of the
+| GNU General Public License version 2, or under the license below.
|
| This source code has been made available to you by IBM on an AS-IS
| basis. Anyone receiving this source is licensed under IBM
@@ -1156,6 +1158,11 @@
#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
+#define SDR0_ECID0 0x0080
+#define SDR0_ECID1 0x0081
+#define SDR0_ECID2 0x0082
+#define SDR0_ECID3 0x0083
+
/* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */
#define SDR0_ETH_PLL 0x4102
#define SDR0_ETH_PLL_PLLLOCK 0x80000000 /*Ethernet PLL lock indication*/
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index 55ff32353..a9954aa3d 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -1,4 +1,6 @@
/*----------------------------------------------------------------------------+
+| This source code is dual-licensed. You may use it under the terms of
+| the GNU General Public License version 2, or under the license below.
|
| This source code has been made available to you by IBM on an AS-IS
| basis. Anyone receiving this source is licensed under IBM
diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index 3e10883f9..7588e93ce 100644
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -1,4 +1,6 @@
/*----------------------------------------------------------------------------+
+| This source code is dual-licensed. You may use it under the terms of the
+| GNU General Public License version 2, or under the license below.
|
| This source code has been made available to you by IBM on an AS-IS
| basis. Anyone receiving this source is licensed under IBM
diff --git a/lib_arm/_ashldi3.S b/lib_arm/_ashldi3.S
index de4403d63..834ddc254 100644
--- a/lib_arm/_ashldi3.S
+++ b/lib_arm/_ashldi3.S
@@ -35,7 +35,9 @@ Boston, MA 02110-1301, USA. */
#endif
.globl __ashldi3
+.globl __aeabi_llsl
__ashldi3:
+__aeabi_llsl:
subs r3, r2, #32
rsb ip, r2, #32
diff --git a/lib_arm/_ashrdi3.S b/lib_arm/_ashrdi3.S
index 5edbcb3ae..671ac87a2 100644
--- a/lib_arm/_ashrdi3.S
+++ b/lib_arm/_ashrdi3.S
@@ -35,7 +35,9 @@ Boston, MA 02110-1301, USA. */
#endif
.globl __ashrdi3
+.globl __aeabi_lasr
__ashrdi3:
+__aeabi_lasr:
subs r3, r2, #32
rsb ip, r2, #32
diff --git a/lib_arm/_divsi3.S b/lib_arm/_divsi3.S
index 9dc15f6d6..cfbadb2ab 100644
--- a/lib_arm/_divsi3.S
+++ b/lib_arm/_divsi3.S
@@ -96,7 +96,9 @@
.align 5
.globl __divsi3
+.globl __aeabi_idiv
__divsi3:
+__aeabi_idiv:
cmp r1, #0
eor ip, r0, r1 @ save the sign of the result.
beq Ldiv0
diff --git a/lib_arm/_lshrdi3.S b/lib_arm/_lshrdi3.S
index fabfd9f0c..e7fa79938 100644
--- a/lib_arm/_lshrdi3.S
+++ b/lib_arm/_lshrdi3.S
@@ -35,7 +35,9 @@ Boston, MA 02110-1301, USA. */
#endif
.globl __lshrdi3
+.globl __aeabi_llsr
__lshrdi3:
+__aeabi_llsr:
subs r3, r2, #32
rsb ip, r2, #32
diff --git a/lib_arm/_udivsi3.S b/lib_arm/_udivsi3.S
index a3f9b5961..130980261 100644
--- a/lib_arm/_udivsi3.S
+++ b/lib_arm/_udivsi3.S
@@ -11,9 +11,12 @@ curbit .req r3
/* pc .req r15 */
.text
.globl __udivsi3
- .type __udivsi3 ,function
+ .type __udivsi3 ,function
+ .globl __aeabi_uidiv
+ .type __aeabi_uidiv ,function
.align 0
- __udivsi3 :
+ __udivsi3:
+ __aeabi_uidiv:
cmp divisor, #0
beq Ldiv0
mov curbit, #1
@@ -68,10 +71,23 @@ Ldiv0:
mov r0, #0 @ about as wrong as it could be
ldmia sp!, {pc}
.size __udivsi3 , . - __udivsi3
-/* # 235 "libgcc1.S" */
-/* # 320 "libgcc1.S" */
-/* # 421 "libgcc1.S" */
-/* # 433 "libgcc1.S" */
-/* # 456 "libgcc1.S" */
-/* # 500 "libgcc1.S" */
-/* # 580 "libgcc1.S" */
+
+.globl __aeabi_uidivmod
+__aeabi_uidivmod:
+
+ stmfd sp!, {r0, r1, ip, lr}
+ bl __aeabi_uidiv
+ ldmfd sp!, {r1, r2, ip, lr}
+ mul r3, r0, r2
+ sub r1, r1, r3
+ mov pc, lr
+
+.globl __aeabi_idivmod
+__aeabi_idivmod:
+
+ stmfd sp!, {r0, r1, ip, lr}
+ bl __aeabi_idiv
+ ldmfd sp!, {r1, r2, ip, lr}
+ mul r3, r0, r2
+ sub r1, r1, r3
+ mov pc, lr
diff --git a/lib_generic/lzma/LzmaDec.c b/lib_generic/lzma/LzmaDec.c
index acffb14aa..f941da27d 100644
--- a/lib_generic/lzma/LzmaDec.c
+++ b/lib_generic/lzma/LzmaDec.c
@@ -6,7 +6,7 @@
#include <watchdog.h>
#include "LzmaDec.h"
-#include <string.h>
+#include <linux/string.h>
#define kNumTopBits 24
#define kTopValue ((UInt32)1 << kNumTopBits)
diff --git a/lib_generic/lzma/LzmaTools.c b/lib_generic/lzma/LzmaTools.c
index 88ba399c7..408b577f1 100644
--- a/lib_generic/lzma/LzmaTools.c
+++ b/lib_generic/lzma/LzmaTools.c
@@ -61,7 +61,6 @@ int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize,
ISzAlloc g_Alloc;
SizeT outSizeFull = 0xFFFFFFFF; /* 4GBytes limit */
- SizeT inProcessed;
SizeT outProcessed;
SizeT outSize;
SizeT outSizeHigh;
diff --git a/lib_generic/lzma/Makefile b/lib_generic/lzma/Makefile
index 2916f215b..57f03b0cd 100644
--- a/lib_generic/lzma/Makefile
+++ b/lib_generic/lzma/Makefile
@@ -30,7 +30,7 @@ LIB = $(obj)liblzma.a
SOBJS =
-CFLAGS += -D_LZMA_PROB32 -I$(TOPDIR)/include/linux
+CFLAGS += -D_LZMA_PROB32
COBJS-$(CONFIG_LZMA) += LzmaDec.o LzmaTools.o
diff --git a/lib_m68k/board.c b/lib_m68k/board.c
index f73a46cce..483c9b6df 100644
--- a/lib_m68k/board.c
+++ b/lib_m68k/board.c
@@ -535,7 +535,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
*/
s = getenv ("flashchecksum");
if (s && (*s == 'y')) {
- printf (" CRC: %08lX",
+ printf (" CRC: %08X",
crc32 (0,
(const unsigned char *) CONFIG_SYS_FLASH_BASE,
flash_size)
diff --git a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c
index 371bbb394..ed1888ceb 100644
--- a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c
+++ b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2008
+ * (C) Copyright 2008-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -26,6 +26,17 @@
#include <asm/io.h>
#include <asm/processor.h>
+/*
+ * This code can configure those two Crucial SODIMM's:
+ *
+ * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
+ * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
+ *
+ */
+
+#define TEST_ADDR 0x10000000
+#define TEST_MAGIC 0x11223344
+
static void wait_init_complete(void)
{
u32 val;
@@ -35,7 +46,13 @@ static void wait_init_complete(void)
} while (!(val & 0x80000000));
}
-phys_size_t initdram(int board_type)
+static void ddr_start(void)
+{
+ mtsdram(SDRAM_MCOPT2, 0x28000000);
+ wait_init_complete();
+}
+
+static void ddr_init_common(void)
{
/*
* Reset the DDR-SDRAM controller.
@@ -49,17 +66,12 @@ phys_size_t initdram(int board_type)
* enabled. This will only work for the same memory
* configuration as used here:
*
- * Crucial CT6464AC667.8FB - 512MB SO-DIMM
- *
*/
mtsdram(SDRAM_MCOPT2, 0x00000000);
- mtsdram(SDRAM_MCOPT1, 0x05122000);
mtsdram(SDRAM_MODT0, 0x01000000);
- mtsdram(SDRAM_CODT, 0x02800021);
mtsdram(SDRAM_WRDTR, 0x82000823);
mtsdram(SDRAM_CLKTR, 0x40000000);
mtsdram(SDRAM_MB0CF, 0x00000201);
- mtsdram(SDRAM_MB1CF, 0x00000201);
mtsdram(SDRAM_RTR, 0x06180000);
mtsdram(SDRAM_SDTR1, 0x80201000);
mtsdram(SDRAM_SDTR2, 0x42103243);
@@ -82,17 +94,56 @@ phys_size_t initdram(int board_type)
mtsdram(SDRAM_INITPLR13, 0x80810040);
mtsdram(SDRAM_INITPLR14, 0x00000000);
mtsdram(SDRAM_INITPLR15, 0x00000000);
-
- mtsdram(SDRAM_MCOPT2, 0x28000000);
-
- wait_init_complete();
+ mtsdram(SDRAM_RDCC, 0x40000000);
+ mtsdram(SDRAM_RQDC, 0x80000038);
+ mtsdram(SDRAM_RFDC, 0x00000257);
mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */
mtdcr(SDRAM_R1BAS, 0x0400F800); /* MQ0_B1BAS */
+}
- mtsdram(SDRAM_RDCC, 0x40000000);
- mtsdram(SDRAM_RQDC, 0x80000038);
- mtsdram(SDRAM_RFDC, 0x00000257);
+phys_size_t initdram(int board_type)
+{
+ /*
+ * First try init for this module:
+ *
+ * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
+ */
+
+ ddr_init_common();
+
+ /*
+ * Crucial CT6464AC667.8FB - 512MB SO-DIMM
+ */
+ mtdcr(SDRAM_R0BAS, 0x0000F800);
+ mtdcr(SDRAM_R1BAS, 0x0400F800);
+ mtsdram(SDRAM_MCOPT1, 0x05122000);
+ mtsdram(SDRAM_CODT, 0x02800021);
+ mtsdram(SDRAM_MB1CF, 0x00000201);
+
+ ddr_start();
+
+ /*
+ * Now test if the dual-ranked module is really installed
+ * by checking an address in the upper 256MByte region
+ */
+ out_be32((void *)TEST_ADDR, TEST_MAGIC);
+ if (in_be32((void *)TEST_ADDR) != TEST_MAGIC) {
+ /*
+ * The test failed, so we assume that the single
+ * ranked module is installed:
+ *
+ * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
+ */
+
+ ddr_init_common();
+
+ mtdcr(SDRAM_R0BAS, 0x0000F000);
+ mtsdram(SDRAM_MCOPT1, 0x05322000);
+ mtsdram(SDRAM_CODT, 0x00800021);
+
+ ddr_start();
+ }
return CONFIG_SYS_MBYTES_SDRAM << 20;
}
diff --git a/net/Makefile b/net/Makefile
index 835a04af4..ff87d87e4 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -23,7 +23,7 @@
include $(TOPDIR)/config.mk
-# CFLAGS += -DET_DEBUG -DDEBUG
+# CFLAGS += -DDEBUG
LIB = $(obj)libnet.a
diff --git a/net/bootp.c b/net/bootp.c
index d5f9c4be6..0799ae2b0 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -8,17 +8,6 @@
* Copyright 2000-2004 Wolfgang Denk, wd@denx.de
*/
-#if 0
-#define DEBUG 1 /* general debug */
-#define DEBUG_BOOTP_EXT 1 /* Debug received vendor fields */
-#endif
-
-#ifdef DEBUG_BOOTP_EXT
-#define debug_ext(fmt,args...) printf (fmt ,##args)
-#else
-#define debug_ext(fmt,args...)
-#endif
-
#include <common.h>
#include <command.h>
#include <net.h>
@@ -107,7 +96,7 @@ static int BootpCheckPkt(uchar *pkt, unsigned dest, unsigned src, unsigned len)
retval = -6;
}
- debug ("Filtering pkt = %d\n", retval);
+ debug("Filtering pkt = %d\n", retval);
return retval;
}
@@ -129,7 +118,7 @@ static void BootpCopyNetParams(Bootp_t *bp)
if (strlen(bp->bp_file) > 0)
copy_filename (BootFile, bp->bp_file, sizeof(BootFile));
- debug ("Bootfile: %s\n", BootFile);
+ debug("Bootfile: %s\n", BootFile);
/* Propagate to environment:
* don't delete exising entry when BOOTP / DHCP reply does
@@ -156,7 +145,7 @@ static void BootpVendorFieldProcess (u8 * ext)
{
int size = *(ext + 1);
- debug_ext ("[BOOTP] Processing extension %d... (%d bytes)\n", *ext,
+ debug("[BOOTP] Processing extension %d... (%d bytes)\n", *ext,
*(ext + 1));
NetBootFileSize = 0;
@@ -255,7 +244,7 @@ static void BootpVendorProcess (u8 * ext, int size)
{
u8 *end = ext + size;
- debug_ext ("[BOOTP] Checking extension (%d bytes)...\n", size);
+ debug("[BOOTP] Checking extension (%d bytes)...\n", size);
while ((ext < end) && (*ext != 0xff)) {
if (*ext == 0) {
@@ -269,34 +258,27 @@ static void BootpVendorProcess (u8 * ext, int size)
}
}
-#ifdef DEBUG_BOOTP_EXT
- puts ("[BOOTP] Received fields: \n");
+ debug("[BOOTP] Received fields: \n");
if (NetOurSubnetMask)
- printf ("NetOurSubnetMask : %pI4\n", &NetOurSubnetMask);
+ debug("NetOurSubnetMask : %pI4\n", &NetOurSubnetMask);
if (NetOurGatewayIP)
- printf ("NetOurGatewayIP : %pI4", &NetOurGatewayIP);
+ debug("NetOurGatewayIP : %pI4", &NetOurGatewayIP);
- if (NetBootFileSize) {
- printf ("NetBootFileSize : %d\n", NetBootFileSize);
- }
+ if (NetBootFileSize)
+ debug("NetBootFileSize : %d\n", NetBootFileSize);
- if (NetOurHostName[0]) {
- printf ("NetOurHostName : %s\n", NetOurHostName);
- }
+ if (NetOurHostName[0])
+ debug("NetOurHostName : %s\n", NetOurHostName);
- if (NetOurRootPath[0]) {
- printf ("NetOurRootPath : %s\n", NetOurRootPath);
- }
+ if (NetOurRootPath[0])
+ debug("NetOurRootPath : %s\n", NetOurRootPath);
- if (NetOurNISDomain[0]) {
- printf ("NetOurNISDomain : %s\n", NetOurNISDomain);
- }
+ if (NetOurNISDomain[0])
+ debug("NetOurNISDomain : %s\n", NetOurNISDomain);
- if (NetBootFileSize) {
- printf ("NetBootFileSize: %d\n", NetBootFileSize);
- }
-#endif /* DEBUG_BOOTP_EXT */
+ if (NetBootFileSize)
+ debug("NetBootFileSize: %d\n", NetBootFileSize);
}
/*
* Handle a BOOTP received packet.
@@ -307,7 +289,7 @@ BootpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len)
Bootp_t *bp;
char *s;
- debug ("got BOOTP packet (src=%d, dst=%d, len=%d want_len=%zu)\n",
+ debug("got BOOTP packet (src=%d, dst=%d, len=%d want_len=%zu)\n",
src, dest, len, sizeof (Bootp_t));
bp = (Bootp_t *)pkt;
@@ -330,7 +312,7 @@ BootpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len)
NetSetTimeout(0, (thand_f *)0);
- debug ("Got good BOOTP\n");
+ debug("Got good BOOTP\n");
if ((s = getenv("autoload")) != NULL) {
if (*s == 'n') {
@@ -579,14 +561,9 @@ BootpRequest (void)
/* get our mac */
eth_getenv_enetaddr("ethaddr", bi_enetaddr);
-#ifdef DEBUG
- puts ("BootpRequest => Our Mac: ");
- for (reg=0; reg<6; reg++) {
- printf ("%x%c",
- bi_enetaddr[reg],
- reg==5 ? '\n' : ':');
- }
-#endif /* DEBUG */
+ debug("BootpRequest => Our Mac: ");
+ for (reg=0; reg<6; reg++)
+ debug("%x%c", bi_enetaddr[reg], reg==5 ? '\n' : ':');
/* Mac-Manipulation 2 get seed1 */
tst1=0;
@@ -820,7 +797,7 @@ static void DhcpSendRequestPkt(Bootp_t *bp_offer)
int pktlen, iplen, extlen;
IPaddr_t OfferedIP;
- debug ("DhcpSendRequestPkt: Sending DHCPREQUEST\n");
+ debug("DhcpSendRequestPkt: Sending DHCPREQUEST\n");
pkt = NetTxPacket;
memset ((void*)pkt, 0, PKTSIZE);
@@ -864,7 +841,7 @@ static void DhcpSendRequestPkt(Bootp_t *bp_offer)
iplen = BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + extlen;
NetSetIP(iphdr, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC, iplen);
- debug ("Transmitting DHCPREQUEST packet: len = %d\n", pktlen);
+ debug("Transmitting DHCPREQUEST packet: len = %d\n", pktlen);
#ifdef CONFIG_BOOTP_DHCP_REQUEST_DELAY
udelay(CONFIG_BOOTP_DHCP_REQUEST_DELAY);
#endif /* CONFIG_BOOTP_DHCP_REQUEST_DELAY */
@@ -879,13 +856,13 @@ DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len)
{
Bootp_t *bp = (Bootp_t *)pkt;
- debug ("DHCPHandler: got packet: (src=%d, dst=%d, len=%d) state: %d\n",
+ debug("DHCPHandler: got packet: (src=%d, dst=%d, len=%d) state: %d\n",
src, dest, len, dhcp_state);
if (BootpCheckPkt(pkt, dest, src, len)) /* Filter out pkts we don't want */
return;
- debug ("DHCPHandler: got DHCP packet: (src=%d, dst=%d, len=%d) state: %d\n",
+ debug("DHCPHandler: got DHCP packet: (src=%d, dst=%d, len=%d) state: %d\n",
src, dest, len, dhcp_state);
switch (dhcp_state) {
@@ -896,14 +873,14 @@ DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len)
* If filename is in format we recognize, assume it is a valid
* OFFER from a server we want.
*/
- debug ("DHCP: state=SELECTING bp_file: \"%s\"\n", bp->bp_file);
+ debug("DHCP: state=SELECTING bp_file: \"%s\"\n", bp->bp_file);
#ifdef CONFIG_SYS_BOOTFILE_PREFIX
if (strncmp(bp->bp_file,
CONFIG_SYS_BOOTFILE_PREFIX,
strlen(CONFIG_SYS_BOOTFILE_PREFIX)) == 0 ) {
#endif /* CONFIG_SYS_BOOTFILE_PREFIX */
- debug ("TRANSITIONING TO REQUESTING STATE\n");
+ debug("TRANSITIONING TO REQUESTING STATE\n");
dhcp_state = REQUESTING;
if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC))
@@ -918,7 +895,7 @@ DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len)
return;
break;
case REQUESTING:
- debug ("DHCP State: REQUESTING\n");
+ debug("DHCP State: REQUESTING\n");
if ( DhcpMessageType((u8 *)bp->bp_vend) == DHCP_ACK ) {
char *s;
diff --git a/net/eth.c b/net/eth.c
index 8e1d6921c..9b503124f 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -53,6 +53,13 @@ int eth_setenv_enetaddr(char *name, const uchar *enetaddr)
return setenv(name, buf);
}
+
+int eth_getenv_enetaddr_by_index(int index, uchar *enetaddr)
+{
+ char enetvar[32];
+ sprintf(enetvar, index ? "eth%daddr" : "ethaddr", index);
+ return eth_getenv_enetaddr(enetvar, enetaddr);
+}
#endif
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
@@ -180,7 +187,6 @@ int eth_register(struct eth_device* dev)
int eth_initialize(bd_t *bis)
{
- char enetvar[32];
unsigned char env_enetaddr[6];
int eth_number = 0;
@@ -221,8 +227,7 @@ int eth_initialize(bd_t *bis)
puts (" [PRIME]");
}
- sprintf(enetvar, eth_number ? "eth%daddr" : "ethaddr", eth_number);
- eth_getenv_enetaddr(enetvar, env_enetaddr);
+ eth_getenv_enetaddr_by_index(eth_number, env_enetaddr);
if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) {
if (memcmp(dev->enetaddr, "\0\0\0\0\0\0", 6) &&
@@ -259,31 +264,6 @@ int eth_initialize(bd_t *bis)
return eth_number;
}
-void eth_set_enetaddr(int num, char *addr) {
- struct eth_device *dev;
- unsigned char enetaddr[6];
-
- debug ("eth_set_enetaddr(num=%d, addr=%s)\n", num, addr);
-
- if (!eth_devices)
- return;
-
- eth_parse_enetaddr(addr, enetaddr);
-
- dev = eth_devices;
- while(num-- > 0) {
- dev = dev->next;
-
- if (dev == eth_devices)
- return;
- }
-
- debug ( "Setting new HW address on %s\n"
- "New Address is %pM\n",
- dev->name, enetaddr);
-
- memcpy(dev->enetaddr, enetaddr, 6);
-}
#ifdef CONFIG_MCAST_TFTP
/* Multicast.
* mcast_addr: multicast ipaddr from which multicast Mac is made
@@ -332,23 +312,37 @@ u32 ether_crc (size_t len, unsigned char const *p)
int eth_init(bd_t *bis)
{
- struct eth_device* old_current;
+ int eth_number;
+ struct eth_device *old_current, *dev;
if (!eth_current) {
puts ("No ethernet found.\n");
return -1;
}
+ /* Sync environment with network devices */
+ eth_number = 0;
+ dev = eth_devices;
+ do {
+ uchar env_enetaddr[6];
+
+ if (eth_getenv_enetaddr_by_index(eth_number, env_enetaddr))
+ memcpy(dev->enetaddr, env_enetaddr, 6);
+
+ ++eth_number;
+ dev = dev->next;
+ } while (dev != eth_devices);
+
old_current = eth_current;
do {
- debug ("Trying %s\n", eth_current->name);
+ debug("Trying %s\n", eth_current->name);
if (eth_current->init(eth_current,bis) >= 0) {
eth_current->state = ETH_STATE_ACTIVE;
return 0;
}
- debug ("FAIL\n");
+ debug("FAIL\n");
eth_try_another(0);
} while (old_current != eth_current);
diff --git a/net/net.c b/net/net.c
index 641c37cb8..d1cc9b2e9 100644
--- a/net/net.c
+++ b/net/net.c
@@ -113,10 +113,6 @@ DECLARE_GLOBAL_DATA_PTR;
# define ARP_TIMEOUT_COUNT CONFIG_NET_RETRY_COUNT
#endif
-#if 0
-#define ET_DEBUG
-#endif
-
/** BOOTP EXTENTIONS **/
IPaddr_t NetOurSubnetMask=0; /* Our subnet mask (0=unknown) */
@@ -218,9 +214,8 @@ void ArpRequest (void)
volatile uchar *pkt;
ARP_t *arp;
-#ifdef ET_DEBUG
- printf ("ARP broadcast %d\n", NetArpWaitTry);
-#endif
+ debug("ARP broadcast %d\n", NetArpWaitTry);
+
pkt = NetTxPacket;
pkt += NetSetEther (pkt, NetBcastAddr, PROT_ARP);
@@ -644,9 +639,8 @@ NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, int sport, int len)
/* if MAC address was not discovered yet, save the packet and do an ARP request */
if (memcmp(ether, NetEtherNullAddr, 6) == 0) {
-#ifdef ET_DEBUG
- printf("sending ARP for %08lx\n", dest);
-#endif
+ debug("sending ARP for %08lx\n", dest);
+
NetArpWaitPacketIP = dest;
NetArpWaitPacketMAC = ether;
@@ -666,9 +660,7 @@ NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, int sport, int len)
return 1; /* waiting */
}
-#ifdef ET_DEBUG
- printf("sending UDP to %08lx/%pM\n", dest, ether);
-#endif
+ debug("sending UDP to %08lx/%pM\n", dest, ether);
pkt = (uchar *)NetTxPacket;
pkt += NetSetEther (pkt, ether, PROT_IP);
@@ -692,9 +684,7 @@ int PingSend(void)
memcpy(mac, NetEtherNullAddr, 6);
-#ifdef ET_DEBUG
- printf("sending ARP for %08lx\n", NetPingIP);
-#endif
+ debug("sending ARP for %08lx\n", NetPingIP);
NetArpWaitPacketIP = NetPingIP;
NetArpWaitPacketMAC = mac;
@@ -1132,9 +1122,7 @@ NetReceive(volatile uchar * inpkt, int len)
#endif
ushort cti = 0, vlanid = VLAN_NONE, myvlanid, mynvlanid;
-#ifdef ET_DEBUG
- printf("packet received\n");
-#endif
+ debug("packet received\n");
NetRxPacket = inpkt;
NetRxPacketLen = len;
@@ -1165,9 +1153,7 @@ NetReceive(volatile uchar * inpkt, int len)
x = ntohs(et->et_protlen);
-#ifdef ET_DEBUG
- printf("packet received\n");
-#endif
+ debug("packet received\n");
if (x < 1514) {
/*
@@ -1185,9 +1171,8 @@ NetReceive(volatile uchar * inpkt, int len)
} else { /* VLAN packet */
VLAN_Ethernet_t *vet = (VLAN_Ethernet_t *)et;
-#ifdef ET_DEBUG
- printf("VLAN packet received\n");
-#endif
+ debug("VLAN packet received\n");
+
/* too small packet? */
if (len < VLAN_ETHER_HDR_SIZE)
return;
@@ -1208,9 +1193,7 @@ NetReceive(volatile uchar * inpkt, int len)
len -= VLAN_ETHER_HDR_SIZE;
}
-#ifdef ET_DEBUG
- printf("Receive from protocol 0x%x\n", x);
-#endif
+ debug("Receive from protocol 0x%x\n", x);
#if defined(CONFIG_CMD_CDP)
if (iscdp) {
@@ -1239,9 +1222,8 @@ NetReceive(volatile uchar * inpkt, int len)
* address; so if we receive such a packet, we set
* the server ethernet address
*/
-#ifdef ET_DEBUG
- puts ("Got ARP\n");
-#endif
+ debug("Got ARP\n");
+
arp = (ARP_t *)ip;
if (len < ARP_HDR_SIZE) {
printf("bad length %d < %d\n", len, ARP_HDR_SIZE);
@@ -1270,9 +1252,7 @@ NetReceive(volatile uchar * inpkt, int len)
switch (ntohs(arp->ar_op)) {
case ARPOP_REQUEST: /* reply with our IP address */
-#ifdef ET_DEBUG
- puts ("Got ARP REQUEST, return our IP\n");
-#endif
+ debug("Got ARP REQUEST, return our IP\n");
pkt = (uchar *)et;
pkt += NetSetEther(pkt, et->et_src, PROT_ARP);
arp->ar_op = htons(ARPOP_REPLY);
@@ -1296,18 +1276,14 @@ NetReceive(volatile uchar * inpkt, int len)
}
#endif
-#ifdef ET_DEBUG
- printf("Got ARP REPLY, set server/gtwy eth addr (%pM)\n",
+ debug("Got ARP REPLY, set server/gtwy eth addr (%pM)\n",
arp->ar_data);
-#endif
tmp = NetReadIP(&arp->ar_data[6]);
/* matched waiting packet's address */
if (tmp == NetArpWaitReplyIP) {
-#ifdef ET_DEBUG
- puts ("Got it\n");
-#endif
+ debug("Got it\n");
/* save address for later use */
memcpy(NetArpWaitPacketMAC, &arp->ar_data[0], 6);
@@ -1326,17 +1302,13 @@ NetReceive(volatile uchar * inpkt, int len)
}
return;
default:
-#ifdef ET_DEBUG
- printf("Unexpected ARP opcode 0x%x\n", ntohs(arp->ar_op));
-#endif
+ debug("Unexpected ARP opcode 0x%x\n", ntohs(arp->ar_op));
return;
}
break;
case PROT_RARP:
-#ifdef ET_DEBUG
- puts ("Got RARP\n");
-#endif
+ debug("Got RARP\n");
arp = (ARP_t *)ip;
if (len < ARP_HDR_SIZE) {
printf("bad length %d < %d\n", len, ARP_HDR_SIZE);
@@ -1360,11 +1332,9 @@ NetReceive(volatile uchar * inpkt, int len)
break;
case PROT_IP:
-#ifdef ET_DEBUG
- puts ("Got IP\n");
-#endif
+ debug("Got IP\n");
if (len < IP_HDR_SIZE) {
- debug ("len bad %d < %lu\n", len, (ulong)IP_HDR_SIZE);
+ debug("len bad %d < %lu\n", len, (ulong)IP_HDR_SIZE);
return;
}
if (len < ntohs(ip->ip_len)) {
@@ -1372,9 +1342,8 @@ NetReceive(volatile uchar * inpkt, int len)
return;
}
len = ntohs(ip->ip_len);
-#ifdef ET_DEBUG
- printf("len=%d, v=%02x\n", len, ip->ip_hl_v & 0xff);
-#endif
+ debug("len=%d, v=%02x\n", len, ip->ip_hl_v & 0xff);
+
if ((ip->ip_hl_v & 0xf0) != 0x40) {
return;
}
@@ -1432,10 +1401,9 @@ NetReceive(volatile uchar * inpkt, int len)
(*packetHandler)((uchar *)ip, 0, 0, 0);
return;
case ICMP_ECHO_REQUEST:
-#ifdef ET_DEBUG
- printf ("Got ICMP ECHO REQUEST, return %d bytes \n",
+ debug("Got ICMP ECHO REQUEST, return %d bytes \n",
ETHER_HDR_SIZE + len);
-#endif
+
memcpy (&et->et_dest[0], &et->et_src[0], 6);
memcpy (&et->et_src[ 0], NetOurEther, 6);
diff --git a/net/nfs.c b/net/nfs.c
index 010162902..27395fbf2 100644
--- a/net/nfs.c
+++ b/net/nfs.c
@@ -29,8 +29,6 @@
#include "nfs.h"
#include "bootp.h"
-/*#define NFS_DEBUG*/
-
#if defined(CONFIG_CMD_NET) && defined(CONFIG_CMD_NFS)
#define HASHES_PER_LINE 65 /* Number of "loading" hashes per line */
@@ -357,9 +355,7 @@ RPC request dispatcher
static void
NfsSend (void)
{
-#ifdef NFS_DEBUG
- printf ("%s\n", __FUNCTION__);
-#endif
+ debug("%s\n", __func__);
switch (NfsState) {
case STATE_PRCLOOKUP_PROG_MOUNT_REQ:
@@ -397,9 +393,7 @@ rpc_lookup_reply (int prog, uchar *pkt, unsigned len)
memcpy ((unsigned char *)&rpc_pkt, pkt, len);
-#ifdef NFS_DEBUG
- printf ("%s\n", __FUNCTION__);
-#endif
+ debug("%s\n", __func__);
if (ntohl(rpc_pkt.u.reply.id) != rpc_id)
return -1;
@@ -427,9 +421,7 @@ nfs_mount_reply (uchar *pkt, unsigned len)
{
struct rpc_t rpc_pkt;
-#ifdef NFS_DEBUG
- printf ("%s\n", __FUNCTION__);
-#endif
+ debug("%s\n", __func__);
memcpy ((unsigned char *)&rpc_pkt, pkt, len);
@@ -454,9 +446,7 @@ nfs_umountall_reply (uchar *pkt, unsigned len)
{
struct rpc_t rpc_pkt;
-#ifdef NFS_DEBUG
- printf ("%s\n", __FUNCTION__);
-#endif
+ debug("%s\n", __func__);
memcpy ((unsigned char *)&rpc_pkt, pkt, len);
@@ -480,9 +470,7 @@ nfs_lookup_reply (uchar *pkt, unsigned len)
{
struct rpc_t rpc_pkt;
-#ifdef NFS_DEBUG
- printf ("%s\n", __FUNCTION__);
-#endif
+ debug("%s\n", __func__);
memcpy ((unsigned char *)&rpc_pkt, pkt, len);
@@ -507,9 +495,7 @@ nfs_readlink_reply (uchar *pkt, unsigned len)
struct rpc_t rpc_pkt;
int rlen;
-#ifdef NFS_DEBUG
- printf ("%s\n", __FUNCTION__);
-#endif
+ debug("%s\n", __func__);
memcpy ((unsigned char *)&rpc_pkt, pkt, len);
@@ -544,9 +530,7 @@ nfs_read_reply (uchar *pkt, unsigned len)
struct rpc_t rpc_pkt;
int rlen;
-#ifdef NFS_DEBUG_nop
- printf ("%s\n", __FUNCTION__);
-#endif
+ debug("%s\n", __func__);
memcpy ((uchar *)&rpc_pkt, pkt, sizeof(rpc_pkt.u.reply));
@@ -601,9 +585,7 @@ NfsHandler (uchar *pkt, unsigned dest, unsigned src, unsigned len)
{
int rlen;
-#ifdef NFS_DEBUG
- printf ("%s\n", __FUNCTION__);
-#endif
+ debug("%s\n", __func__);
if (dest != NfsOurPort) return;
@@ -661,9 +643,7 @@ NfsHandler (uchar *pkt, unsigned dest, unsigned src, unsigned len)
NfsState = STATE_UMOUNT_REQ;
NfsSend ();
} else {
-#ifdef NFS_DEBUG
- printf ("Symlink --> %s\n", nfs_path);
-#endif
+ debug("Symlink --> %s\n", nfs_path);
nfs_filename = basename (nfs_path);
nfs_path = dirname (nfs_path);
@@ -696,9 +676,7 @@ NfsHandler (uchar *pkt, unsigned dest, unsigned src, unsigned len)
void
NfsStart (void)
{
-#ifdef NFS_DEBUG
- printf ("%s\n", __FUNCTION__);
-#endif
+ debug("%s\n", __func__);
NfsDownloadState = NETLOOP_FAIL;
NfsServerIP = NetServerIP;
diff --git a/net/rarp.c b/net/rarp.c
index 710569626..d37981bfc 100644
--- a/net/rarp.c
+++ b/net/rarp.c
@@ -48,9 +48,7 @@ static void
RarpHandler(uchar * dummi0, unsigned dummi1, unsigned dummi2, unsigned dummi3)
{
char *s;
-#ifdef DEBUG
- puts ("Got good RARP\n");
-#endif
+ debug("Got good RARP\n");
if ((s = getenv("autoload")) != NULL) {
if (*s == 'n') {
/*
diff --git a/net/sntp.c b/net/sntp.c
index 404587e80..76c10ecd3 100644
--- a/net/sntp.c
+++ b/net/sntp.c
@@ -23,7 +23,7 @@ SntpSend (void)
int pktlen = SNTP_PACKET_LEN;
int sport;
- debug ("%s\n", __FUNCTION__);
+ debug("%s\n", __func__);
memset (&pkt, 0, sizeof(pkt));
@@ -54,7 +54,7 @@ SntpHandler (uchar *pkt, unsigned dest, unsigned src, unsigned len)
struct rtc_time tm;
ulong seconds;
- debug ("%s\n", __FUNCTION__);
+ debug("%s\n", __func__);
if (dest != SntpOurPort) return;
@@ -78,7 +78,7 @@ SntpHandler (uchar *pkt, unsigned dest, unsigned src, unsigned len)
void
SntpStart (void)
{
- debug ("%s\n", __FUNCTION__);
+ debug("%s\n", __func__);
NetSetTimeout (SNTP_TIMEOUT, SntpTimeout);
NetSetHandler(SntpHandler);
diff --git a/net/tftp.c b/net/tftp.c
index b0f1cca0b..fb98a346e 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -10,8 +10,6 @@
#include "tftp.h"
#include "bootp.h"
-#undef ET_DEBUG
-
#if defined(CONFIG_CMD_NET)
#define WELL_KNOWN_PORT 69 /* Well known TFTP port # */
@@ -196,9 +194,7 @@ TftpSend (void)
strcpy ((char *)pkt, "timeout");
pkt += 7 /*strlen("timeout")*/ + 1;
sprintf((char *)pkt, "%lu", TIMEOUT / 1000);
-#ifdef ET_DEBUG
- printf("send option \"timeout %s\"\n", (char *)pkt);
-#endif
+ debug("send option \"timeout %s\"\n", (char *)pkt);
pkt += strlen((char *)pkt) + 1;
/* try for more effic. blk size */
pkt += sprintf((char *)pkt,"blksize%c%d%c",
@@ -295,9 +291,9 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len)
break;
case TFTP_OACK:
-#ifdef ET_DEBUG
- printf("Got OACK: %s %s\n", pkt, pkt+strlen(pkt)+1);
-#endif
+ debug("Got OACK: %s %s\n",
+ pkt,
+ pkt + strlen((char *)pkt) + 1);
TftpState = STATE_OACK;
TftpServerPort = src;
/*
@@ -309,10 +305,8 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len)
if (strcmp ((char*)pkt+i,"blksize") == 0) {
TftpBlkSize = (unsigned short)
simple_strtoul((char*)pkt+i+8,NULL,10);
-#ifdef ET_DEBUG
- printf ("Blocksize ack: %s, %d\n",
+ debug("Blocksize ack: %s, %d\n",
(char*)pkt+i+8,TftpBlkSize);
-#endif
break;
}
}
@@ -348,11 +342,8 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len)
}
}
-#ifdef ET_DEBUG
- if (TftpState == STATE_RRQ) {
- puts ("Server did not acknowledge timeout option!\n");
- }
-#endif
+ if (TftpState == STATE_RRQ)
+ debug("Server did not acknowledge timeout option!\n");
if (TftpState == STATE_RRQ || TftpState == STATE_OACK) {
/* first block received */