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authorDave Liu <daveliu@freescale.com>2008-12-02 11:48:51 +0800
committerScott Wood <scottwood@freescale.com>2009-01-23 10:32:50 -0600
commitc70564e6b1bd08f3230182392238907f3531a87e (patch)
tree08210e54577641c2567a0bcf3ad981855df43dea /nand_spl/nand_boot_fsl_elbc.c
parent50657c273278f74378e1ac39b41d612b92fdffa0 (diff)
downloadu-boot-linaro-stable-c70564e6b1bd08f3230182392238907f3531a87e.tar.gz
NAND: Fix cache and memory inconsistency issue
We load the secondary stage u-boot image from NAND to system memory by nand_load, but we did not flush d-cache to memory, nor invalidate i-cache before we jump to RAM. When the system has cache enabled and the TLB/page attribute of system memory is cacheable, it will cause issues. - 83xx family is using the d-cache lock, so all of d-cache access is cache-inhibited. so you can't see the issue. - 85xx family is using d-cache, i-cache enable, partial cache lock. you will see the issue. This patch fixes the cache issue. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'nand_spl/nand_boot_fsl_elbc.c')
-rw-r--r--nand_spl/nand_boot_fsl_elbc.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c
index 4a961ea7b..0d0c44e1e 100644
--- a/nand_spl/nand_boot_fsl_elbc.c
+++ b/nand_spl/nand_boot_fsl_elbc.c
@@ -143,6 +143,11 @@ void nand_boot(void)
* Jump to U-Boot image
*/
puts("transfering control\n");
+ /*
+ * Clean d-cache and invalidate i-cache, to
+ * make sure that no stale data is executed.
+ */
+ flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
uboot();
}