diff options
| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2011-02-01 15:55:58 +0000 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-03-29 07:41:37 -0500 |
| commit | b03a466d6ceb9dbfd1a1638f355e9c8b4833259f (patch) | |
| tree | 5969f3c69be00b44b0fdf7c00c1d180d414e4b09 /include | |
| parent | 2d7534a344412409d03e4a341614e4320c48879b (diff) | |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe. Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/pci.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/pci.h b/include/pci.h index c6b264bdb..1284c427b 100644 --- a/include/pci.h +++ b/include/pci.h @@ -306,6 +306,7 @@ #define PCI_DCR 0x54 /* PCIe Device Control Register */ #define PCI_DSR 0x56 /* PCIe Device Status Register */ #define PCI_LSR 0x5e /* PCIe Link Status Register */ +#define PCI_LCR 0x5c /* PCIe Link Control Register */ #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ #define PCI_LTSSM_L0 0x16 /* L0 state */ |