diff options
| author | Wolfgang Denk <wd@denx.de> | 2009-08-16 23:40:13 +0200 |
|---|---|---|
| committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-08-17 23:53:41 +0200 |
| commit | 4af34177b657e91263919a307fd0b0865a299e52 (patch) | |
| tree | 9f2ed36884ee3efe14983b679ad342d3dd7bd783 /include | |
| parent | 7dedefdf749ff02c1086f7ddb8cb83a77b00d030 (diff) | |
Monahans: avoid floating point calculations
Current code for the Monahans CPU defined OSCR_CLK_FREQ as 3.250 (MHz)
which caused floating point operations to be used. This resulted in
unresolved references to some FP related libgcc functions when using
U-Boot's private libgcc functions.
Change the code to use fixed point math only.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-pxa/pxa-regs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index f34af1972..a25d4c512 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1094,7 +1094,7 @@ typedef void (*ExcpHndlr) (void) ; #define OMCR10 __REG(0x40A000D8) /* OS Match Control Register 10 */ #define OMCR11 __REG(0x40A000DC) /* OS Match Control Register 11 */ -#define OSCR_CLK_FREQ 3.250 /* MHz */ +#define OSCR_CLK_FREQ 3250 /* kHz = 3.25 MHz */ #endif /* CONFIG_CPU_MONAHANS */ #define OSSR_M4 (1 << 4) /* Match status channel 4 */ |