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authorWolfgang Denk <wd@denx.de>2009-03-09 00:41:48 +0100
committerWolfgang Denk <wd@denx.de>2009-03-09 00:41:48 +0100
commit014c595f12d4f7e14cb10188f856465b2d41718f (patch)
tree9130a01fbb5499975530a20a559dbaba9a1f2a89 /include
parent9c2d63ec0e9520948b6d598ea32e9aa4e0de847f (diff)
parentf70fd13e2fe4cf58e251271c27f9c06e141d7f9a (diff)
downloadu-boot-linaro-stable-014c595f12d4f7e14cb10188f856465b2d41718f.tar.gz
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
Conflicts: lib_ppc/board.c Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'include')
-rw-r--r--include/configs/MPC8349ITX.h5
-rw-r--r--include/configs/keymile-common.h7
-rw-r--r--include/configs/kmeter1.h120
3 files changed, 92 insertions, 40 deletions
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 5e1ddaedd..38a7386d0 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -99,6 +99,7 @@
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
+#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
@@ -168,6 +169,9 @@
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
+
#ifdef CONFIG_HARD_I2C
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
#endif
@@ -457,6 +461,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SDRAM
#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114)
diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h
index d70bc4808..c7f6ba34d 100644
--- a/include/configs/keymile-common.h
+++ b/include/configs/keymile-common.h
@@ -42,13 +42,9 @@
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
-
-/* should go away, if kmeter I2C support is enabled */
-#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD)
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
-#endif
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
@@ -73,10 +69,7 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-/* should go away, if kmeter I2C support is enabled */
-#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD)
#define CONFIG_HUSH_INIT_VAR 1
-#endif
#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index b86c61d5f..49a801f63 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -28,10 +28,12 @@
#define CONFIG_MPC83XX 1 /* MPC83XX family */
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
#define CONFIG_KMETER1 1 /* KMETER1 board specific */
+#define CONFIG_HOSTNAME kmeter1
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
+#define CONFIG_MISC_INIT_R 1
/*
* System Clock Setup
*/
@@ -51,10 +53,11 @@
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_CORE_ENABLE | \
HRCWH_FROM_0X00000100 | \
- HRCWH_BOOTSEQ_NORMAL | \
+ HRCWH_BOOTSEQ_DISABLE | \
HRCWH_SW_WATCHDOG_DISABLE | \
HRCWH_ROM_LOC_LOCAL_16BIT | \
HRCWH_BIG_ENDIAN | \
+ HRCWH_LALE_EARLY | \
HRCWH_LDP_CLEAR )
/*
@@ -91,8 +94,8 @@
* Manually set up DDR parameters
*/
#define CONFIG_DDR_II
-#define CONFIG_SYS_DDR_SIZE 256 /* MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
+#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
CSCONFIG_ROW_BIT_13 | \
CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
@@ -101,11 +104,12 @@
SDRAM_CFG_SREN)
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL ((0x100 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
- (0x406 << SDRAM_INTERVAL_REFINT_SHIFT))
+#define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+ (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
-#define CONFIG_SYS_DDR_MODE 0x04440242
-#define CONFIG_SYS_DDR_MODE2 0x00800000
+#define CONFIG_SYS_DDRCDR 0x40000001
+#define CONFIG_SYS_DDR_MODE 0x47860452
+#define CONFIG_SYS_DDR_MODE2 0x8080c000
#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
@@ -116,22 +120,22 @@
(0 << TIMING_CFG0_WRT_SHIFT) | \
(0 << TIMING_CFG0_RWT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_40) | \
+#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_50) | \
( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
- ( 1 << TIMING_CFG1_ACTTOACT_SHIFT) | \
- ( 2 << TIMING_CFG1_WRREC_SHIFT) | \
- ( 2 << TIMING_CFG1_REFREC_SHIFT) | \
- ( 2 << TIMING_CFG1_ACTTORW_SHIFT) | \
- ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
- ( 2 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2 ((5 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+ ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+ ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
+ ( 7 << TIMING_CFG1_REFREC_SHIFT) | \
+ ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+ ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+ ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
- (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
- (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+ (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
- (4 << TIMING_CFG2_CPO_SHIFT))
+ (5 << TIMING_CFG2_CPO_SHIFT))
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
@@ -141,9 +145,10 @@
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CONFIG_SYS_FLASH_BASE 0xF0000000
#define CONFIG_SYS_FLASH_BASE_1 0xF2000000
-#define CONFIG_SYS_PIGGY_BASE 0x80000000
+#define CONFIG_SYS_PIGGY_BASE 0xE8000000
+#define CONFIG_SYS_PIGGY_SIZE 128
#define CONFIG_SYS_PAXE_BASE 0xA0000000
-#define CONFIG_SYS_PAXE_SIZE 256
+#define CONFIG_SYS_PAXE_SIZE 512
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
@@ -151,7 +156,7 @@
#undef CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
@@ -174,8 +179,8 @@
* Bank Bus Machine PortSz Size Device
* ---- --- ------- ------ ----- ------
* 0 Local GPCM 16 bit 256MB FLASH
- * 1 Local GPCM 8 bit 256KB GPIO/PIGGY
- * 3 Local GPCM 8 bit 256MB PAXE
+ * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
+ * 3 Local GPCM 8 bit 512MB PAXE
*
*/
/*
@@ -209,12 +214,12 @@
* PRIO1/PIGGY on the local bus CS1
*/
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x80000011 /* 256KB window size */
+#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \
(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
BR_V)
-#define CONFIG_SYS_OR1_PRELIM (0xfffc0000 | /* 256KB */ \
+#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX | OR_GPCM_EAD)
@@ -223,7 +228,7 @@
* PAXE on the local bus CS3
*/
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */
-#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001b /* 256MB window size */
+#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \
(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
@@ -296,10 +301,42 @@
#else /* CFG_RAMBOOT */
#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
-#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif /* CFG_RAMBOOT */
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_I2C_MULTI_BUS 1
+#define CONFIG_I2C_CMD_TREE 1
+#define CONFIG_SYS_MAX_I2C_BUS 2
+#define CONFIG_I2C_MUX 1
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* Support the IVM EEprom */
+#define CONFIG_SYS_IVM_EEPROM_ADR 0x50
+#define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400
+#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible) */
+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
+#define CONFIG_SYS_DTT_MAX_TEMP 70
+#define CONFIG_SYS_DTT_LOW_TEMP -30
+#define CONFIG_SYS_DTT_HYSTERESIS 3
+#define CONFIG_SYS_DTT_BUS_NUM (2)
+
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
@@ -345,7 +382,7 @@
/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
@@ -365,7 +402,7 @@
/* PAXE: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
@@ -401,16 +438,25 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define BOOTFLASH_START F0000000
+
+#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
+
+#define MTDIDS_DEFAULT "nor0=app"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=app:256k(u-boot),128k(env),128k(envred)," \
+ "1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)"
+
/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_UEC_ETH)
-#define CONFIG_HAS_ETH0
+#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV "km-common=empty\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_DEF_ENV \
"netdev=eth0\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
@@ -452,6 +498,14 @@
"loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
"loadkernel=tftp ${kernel_addr_r} ${boot_file}\0" \
"unlock=yes\0" \
+ "EEprom_ivm=pca9547:70:9\0" \
+ "dtt_bus=pca9547:70:a\0" \
+ "mtdids=nor0=app \0" \
+ "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \
""
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
+#endif
+
#endif /* __CONFIG_H */