Merge with /home/wd/git/u-boot/masterLABEL_2005_08_12_0050

3 files changed, 250 insertions, 166 deletions

diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 88bbadfc2..64ea6bef9 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -32,11 +32,18 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_BAMBOO		1	/* Board is BAMBOO              */
 #define CONFIG_440EP		1	/* Specific PPC440EP support    */
-
 #define CONFIG_4xx		1	/* ... PPC4xx family	        */
-#define CONFIG_BOARD_EARLY_INIT_F 	1   /* Call board_early_init_f	*/
 #define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
 
+#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
+
+/*
+ * Please note that, if NAND support is enabled, the 2nd ethernet port
+ * can't be used because of pin multiplexing. So, if you want to use the
+ * 2nd ethernet port you have to "undef" the following define.
+ */
+#define CONFIG_BAMBOO_NAND      1       /* enable nand flash support    */
+
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
@@ -58,13 +65,15 @@
 
 #define CFG_USB_DEVICE          0x50000000
 #define CFG_NVRAM_BASE_ADDR     0x80000000
-#define CFG_BCSR_BASE	        (CFG_NVRAM_BASE_ADDR | 0x2000)
+#define CFG_BOOT_BASE_ADDR      0xf0000000
+#define CFG_NAND_ADDR           0x90000000
+#define CFG_NAND2_ADDR          0x94000000
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR	0xf0000000		/* DCache       */
-#define CFG_INIT_RAM_END	0x1000
+#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
+#define CFG_INIT_RAM_END	(8 << 10)
 #define CFG_GBL_DATA_SIZE	256		    	/* num bytes initial data	*/
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
@@ -88,7 +97,7 @@
  * The DS1558 code assumes this condition
  *
  *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE	    (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
+#define CFG_NVRAM_SIZE	        (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs     */
 #define CONFIG_RTC_DS1556	1		         /* DS1556 RTC		*/
 
 /*-----------------------------------------------------------------------
@@ -118,22 +127,81 @@
 #define CFG_FLASH_ADDR1         0x2aa
 #define CFG_FLASH_WORD_SIZE     unsigned char
 
-#define CFG_FLASH_2ND_16BIT_DEV 1         /* bamboo has 8 and 16bit device     */
-#define CFG_FLASH_2ND_ADDR      0x87800000  /* bamboo has 8 and 16bit device     */
+#define CFG_FLASH_2ND_16BIT_DEV 1         /* bamboo has 8 and 16bit device      */
+#define CFG_FLASH_2ND_ADDR      0x87800000  /* bamboo has 8 and 16bit device    */
 
 #ifdef CFG_ENV_IS_IN_FLASH
 #define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
-#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
-#if 0 /* test-only */
 /* Address and size of Redundant Environment Sector	*/
 #define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
-#endif
 #endif /* CFG_ENV_IS_IN_FLASH */
 
 /*-----------------------------------------------------------------------
+ * NAND-FLASH related
+ *----------------------------------------------------------------------*/
+#define NAND_CMD_REG   (0x00) /* NandFlash Command Register */
+#define NAND_ADDR_REG  (0x04) /* NandFlash Address Register */
+#define NAND_DATA_REG  (0x08) /* NandFlash Data Register */
+#define NAND_ECC0_REG  (0x10) /* NandFlash ECC Register0 */
+#define NAND_ECC1_REG  (0x14) /* NandFlash ECC Register1 */
+#define NAND_ECC2_REG  (0x18) /* NandFlash ECC Register2 */
+#define NAND_ECC3_REG  (0x1C) /* NandFlash ECC Register3 */
+#define NAND_ECC4_REG  (0x20) /* NandFlash ECC Register4 */
+#define NAND_ECC5_REG  (0x24) /* NandFlash ECC Register5 */
+#define NAND_ECC6_REG  (0x28) /* NandFlash ECC Register6 */
+#define NAND_ECC7_REG  (0x2C) /* NandFlash ECC Register7 */
+#define NAND_CR0_REG   (0x30) /* NandFlash Device Bank0 Config Register */
+#define NAND_CR1_REG   (0x34) /* NandFlash Device Bank1 Config Register */
+#define NAND_CR2_REG   (0x38) /* NandFlash Device Bank2 Config Register */
+#define NAND_CR3_REG   (0x3C) /* NandFlash Device Bank3 Config Register */
+#define NAND_CCR_REG   (0x40) /* NandFlash Core Configuration Register */
+#define NAND_STAT_REG  (0x44) /* NandFlash Device Status Register */
+#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */
+#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */
+
+/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */
+#define NAND0_CMD_READ1_HALF1     0x00     /* Starting addr for 1rst half of registers */
+#define NAND0_CMD_READ1_HALF2     0x01     /* Starting addr for 2nd half of registers */
+#define NAND0_CMD_READ2           0x50
+#define NAND0_CMD_READ_ID         0x90
+#define NAND0_CMD_READ_STATUS     0x70
+#define NAND0_CMD_RESET           0xFF
+#define NAND0_CMD_PAGE_PROG       0x80
+#define NAND0_CMD_PAGE_PROG_TRUE  0x10
+#define NAND0_CMD_PAGE_PROG_DUMMY 0x11
+#define NAND0_CMD_BLOCK_ERASE     0x60
+#define NAND0_CMD_BLOCK_ERASE_END 0xD0
+
+#define CFG_MAX_NAND_DEVICE     1	/* Max number of NAND devices */
+#define SECTORSIZE              512
+
+#define ADDR_COLUMN             1
+#define ADDR_PAGE               2
+#define ADDR_COLUMN_PAGE        3
+
+#define NAND_ChipID_UNKNOWN     0x00
+#define NAND_MAX_FLOORS         1
+#define NAND_MAX_CHIPS          1
+
+#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0)
+#define WRITE_NAND(d, adr)      do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0)
+#define READ_NAND(adr)          (*(volatile u8 *)((ulong)adr+NAND_DATA_REG))
+#define NAND_WAIT_READY(nand)   while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01))
+
+/* not needed with 440EP NAND controller */
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+#define NAND_DISABLE_CE(nand)
+#define NAND_ENABLE_CE(nand)
+
+/*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------------- */
 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
@@ -206,10 +274,14 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_NET_MULTI        1       /* required for netconsole      */
 #define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
+
+#ifndef CONFIG_BAMBOO_NAND
+#define CONFIG_NET_MULTI        1       /* required for netconsole      */
 #define CONFIG_PHY1_ADDR        1
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#endif /* CONFIG_BAMBOO_NAND */
+
 #define CONFIG_NO_PHY_RESET     1       /* no PHY reset on bamboo!!!    */
 
 #define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
@@ -228,8 +300,15 @@
 #define USB_2_0_DEVICE
 #endif /*CONFIG_440EP*/
 
+#ifdef CONFIG_BAMBOO_NAND
+#define _CFG_CMD_NAND CFG_CMD_NAND
+#else
+#define _CFG_CMD_NAND 0
+#endif /* CONFIG_BAMBOO_NAND */
+
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
 				CFG_CMD_ASKENV	| \
+				CFG_CMD_EEPROM	| \
 				CFG_CMD_DATE	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_DIAG	| \
@@ -244,6 +323,7 @@
 				CFG_CMD_REGINFO	| \
 				CFG_CMD_SDRAM	| \
 				CFG_CMD_USB	| \
+				_CFG_CMD_NAND	| \
 				CFG_CMD_SNTP	)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -253,42 +333,42 @@
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
 
 #define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		    1	/* To use extended board_into (bd_t) */
-#define CONFIG_LYNXKDI          1   /* support kdi files */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI          1       /* support kdi files            */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
  */
 /* General PCI */
-#define CONFIG_PCI			            /* include pci support	        */
-#undef  CONFIG_PCI_PNP			        /* do (not) pci plug-and-play         */
+#define CONFIG_PCI			/* include pci support	        */
+#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-#define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 
 /* Board-specific PCI */
 #define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
 #define CFG_PCI_TARGET_INIT
 #define CFG_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x1014  /* IBM */
-#define CFG_PCI_SUBSYS_ID 0xcafe        /* Whatever */
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */
 
 /*
  * For booting Linux, the board info and command line data
@@ -300,7 +380,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		32768	/* For IBM 440 CPUs			*/
+#define CFG_DCACHE_SIZE		(32<<10) /* For IBM 440 CPUs			*/
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index c7451959a..bc5aaf893 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -127,6 +127,10 @@
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define	CONFIG_PHY_ADDR		1	/* PHY address			*/
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	2	/* EMAC1 PHY address		*/
+#define CONFIG_NET_MULTI	1
+#define CFG_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
 
 #define CONFIG_RTC_DS174x	1	/* use DS1743 RTC in Bubinga	*/
 
@@ -199,8 +203,6 @@
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	  /* Number of ethernet rx buffers & descriptors */
-
 /*-----------------------------------------------------------------------
  * I2C stuff
  *-----------------------------------------------------------------------
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index ddc916985..4ac930b42 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -1,4 +1,6 @@
 /*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -28,56 +30,53 @@
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
-#define CONFIG_YOSEMITE				1	/* Board is BAMBOO	     */
-#define CONFIG_440EP				1	/* Specific PPC440EP support */
-
-#define CONFIG_4xx					1	/* ... PPC4xx family	*/
-#define CONFIG_BOARD_EARLY_INIT_F	1   /* Call board_early_init_f	*/
-#undef	CFG_DRAM_TEST					/* disable - takes long time! */
+#define CONFIG_YOSEMITE		1	/* Board is Yosemite            */
+#define CONFIG_440EP		1	/* Specific PPC440EP support    */
+#define CONFIG_4xx		1	/* ... PPC4xx family	        */
 #define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/
 
+#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		    */
-#define CFG_FLASH_BASE	    0xfe000000	    /* start of FLASH		*/
-#define CFG_MONITOR_BASE    TEXT_BASE	    /* start of monitor		*/
-#define CFG_PCI_MEMBASE	    0xa0000000	    /* mapped pci memory	*/
-#define CFG_PCI_MEMBASE1    CFG_PCI_MEMBASE  + 0x10000000
-#define CFG_PCI_MEMBASE2    CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3    CFG_PCI_MEMBASE2 + 0x10000000
-
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
+#define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
+#define CFG_FLASH_BASE	        0xfc000000	    /* start of FLASH	*/
+#define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
+#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
+#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
 
 /*Don't change either of these*/
-#define CFG_PERIPHERAL_BASE 0xef600000	    /* internal peripherals	*/
-#define CFG_PCI_BASE	    0xe0000000	    /* internal PCI regs	*/
+#define CFG_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
+#define CFG_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
 /*Don't change either of these*/
 
-#define CFG_USB_DEVICE 0x50000000
-#define CFG_NVRAM_BASE_ADDR 0x80000000
-#define CFG_BCSR_BASE	    (CFG_NVRAM_BASE_ADDR | 0x2000)
+#define CFG_USB_DEVICE          0x50000000
+#define CFG_NVRAM_BASE_ADDR     0x80000000
+#define CFG_BCSR_BASE	        (CFG_NVRAM_BASE_ADDR | 0x2000)
+#define CFG_BOOT_BASE_ADDR      0xf0000000
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR	  0xf0000000		/* DCache */
-#define CFG_INIT_RAM_END	0x2000
-#define CFG_GBL_DATA_SIZE	256			/* num bytes initial data	*/
+#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
+#define CFG_INIT_RAM_END	(8 << 10)
+#define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
-#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
-#define CFG_KBYTES_SDRAM	( 128 * 1024)	/* 128MB		     */
-#define CFG_SDRAM_BANKS	    (2)
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CFG_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
-#define CONFIG_BAUDRATE			9600
-#define CONFIG_SERIAL_MULTI   1
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI     1
 /*define this if you want console on UART1*/
 #undef CONFIG_UART1_CONSOLE
 
@@ -85,26 +84,21 @@
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 /*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
- * The DS1558 code assumes this condition
- *
+ * Environment
  *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE	    (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
-#define CONFIG_RTC_DS1556	1			 /* DS1556 RTC		*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
+#endif
 
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#if 1 /* test-only */
-#define CFG_MAX_FLASH_BANKS	1		    /* number of banks	    */
-#define CFG_MAX_FLASH_SECT	256		    /* sectors per device   */
-
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	120000	    /* Timeout for Flash Write (in ms)	*/
-#else
 #define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
 #define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
 #define CFG_FLASH_CFI_AMD_RESET 1		/* AMD RESET for STM 29W320DB!	*/
@@ -116,12 +110,24 @@
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
 #undef CONFIG_SPD_EEPROM	       /* Don't use SPD EEPROM for setup    */
+#define CFG_KBYTES_SDRAM        (128 * 1024)    /* 128MB		    */
+#define CFG_SDRAM_BANKS	        (2)
+
 
 /*-----------------------------------------------------------------------
  * I2C
@@ -131,44 +137,70 @@
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
 
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#undef	CFG_ENV_IS_IN_NVRAM		    /*No NVRAM on board*/
-#undef	CFG_ENV_IS_IN_FLASH		    /* ... not in flash		*/
-#define CFG_ENV_IS_IN_EEPROM 1
-
-/* Define to allow the user to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
 #define CFG_I2C_MULTI_EEPROMS
-#define CFG_ENV_SIZE		0x200	    /* Size of Environment vars */
-#define CFG_ENV_OFFSET		0x0
 #define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
 #define CFG_I2C_EEPROM_ADDR_LEN 1
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 
-#define CONFIG_BOOTCOMMAND	"bootm 0xfe000000"    /* autoboot command */
-#define CONFIG_BOOTDELAY	3		    /* disable autoboot */
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE		0x200	    /* Size of Environment vars */
+#define CFG_ENV_OFFSET		0x0
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=yosemite\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/yosemite/uImage\0"				\
+	"kernel_addr=fc000000\0"					\
+	"ramdisk_addr=fc100000\0"					\
+	"load=tftp 100000 /tftpboot/yosemite/u-boot.bin\0"		\
+	"update=protect off fff80000 ffffffff;era fff80000 ffffffff;"	\
+		"cp.b 100000 fff80000 80000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
 
-#define CONFIG_LOADS_ECHO		1	/* echo on for serial download	*/
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
-#define CONFIG_MII			1	/* MII PHY management		*/
-#define CONFIG_NET_MULTI    1	/* required for netconsole  */
-#define CONFIG_PHY1_ADDR    3
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_NET_MULTI        1	/* required for netconsole      */
+#define CONFIG_PHY1_ADDR        3
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
 #define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		10.0.4.251
-#define CONFIG_ETHADDR		00:10:EC:00:12:34
-#define CONFIG_ETH1ADDR		00:10:EC:00:12:35
 
 #define CFG_RX_ETH_BUFFER	32	  /* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SERVERIP		10.0.4.115
 
 /* Partitions */
 #define CONFIG_MAC_PARTITION
@@ -190,53 +222,21 @@
 #define CONFIG_HW_WATCHDOG			/* watchdog */
 #endif
 
-#ifdef CONFIG_440EP
-	/* Need to define POST */
-#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL | \
-			CFG_CMD_DATE	|   \
-			CFG_CMD_DHCP	|   \
-			CFG_CMD_DIAG	|   \
-			CFG_CMD_ECHO	|   \
-			CFG_CMD_EEPROM	|   \
-			CFG_CMD_ELF	|   \
-    /*	    CFG_CMD_EXT2    |*/ \
-	/*		CFG_CMD_FAT		|*/	\
-			CFG_CMD_I2C	|	\
-	/*		CFG_CMD_IDE		|*/	\
-			CFG_CMD_IRQ	|	\
-    /*		CFG_CMD_KGDB	|*/	\
-			CFG_CMD_MII	|   \
-			CFG_CMD_PCI		|	\
-			CFG_CMD_PING	|	\
-			CFG_CMD_REGINFO |	\
-			CFG_CMD_SDRAM	|   \
-			CFG_CMD_FLASH	|   \
-	/*		CFG_CMD_SPI		|*/	\
-			CFG_CMD_USB	|	\
-			0 ) & ~CFG_CMD_IMLS)
-#else
-#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL | \
-			CFG_CMD_DATE	|   \
-			CFG_CMD_DHCP	|   \
-			CFG_CMD_DIAG	|   \
-			CFG_CMD_ECHO	|   \
-			CFG_CMD_EEPROM	|   \
-			CFG_CMD_ELF	|   \
-    /*	    CFG_CMD_EXT2    |*/ \
-	/*		CFG_CMD_FAT		|*/	\
-			CFG_CMD_I2C	|	\
-	/*		CFG_CMD_IDE		|*/	\
-			CFG_CMD_IRQ	|	\
-    /*		CFG_CMD_KGDB	|*/	\
-			CFG_CMD_MII	|   \
-			CFG_CMD_PCI		|	\
-			CFG_CMD_PING	|	\
-			CFG_CMD_REGINFO |	\
-			CFG_CMD_SDRAM	|   \
-			CFG_CMD_FLASH	|   \
-	/*		CFG_CMD_SPI		|*/	\
-			0 ) & ~CFG_CMD_IMLS)
-#endif
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_USB	)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -245,42 +245,42 @@
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
 
 #define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		    1	/* To use extended board_into (bd_t) */
-#define CONFIG_LYNXKDI		1   /* support kdi files */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI          1       /* support kdi files            */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
  */
 /* General PCI */
-#define CONFIG_PCI				    /* include pci support		*/
-#undef	CONFIG_PCI_PNP				/* do (not) pci plug-and-play	      */
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CONFIG_PCI			/* include pci support	        */
+#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
+#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
 #define CFG_PCI_TARGET_INIT
 #define CFG_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
-#define CFG_PCI_SUBSYS_ID 0xcafe	/* Whatever */
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */
 
 /*
  * For booting Linux, the board info and command line data
@@ -288,10 +288,11 @@
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		8192	/* For IBM 405 CPUs			*/
+#define CFG_DCACHE_SIZE		(32<<10) /* For IBM 440 CPUs			*/
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
@@ -309,4 +310,5 @@
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
+
 #endif	/* __CONFIG_H */