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author | Troy Kisky <troy.kisky@boundarydevices.com> | 2011-12-22 08:42:06 +0100 |
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committer | John Rigby <john.rigby@linaro.org> | 2012-01-19 17:08:51 -0700 |
commit | ba5ee185ad76cb41f028e5816f7f1d0e4e5ef724 (patch) | |
tree | eea18644bc7ad14734149a4e8c5e46c4632fedfc /drivers/mmc/fsl_esdhc.c | |
parent | 85fe4bf4ae2e1eed20979445030354b3e491b907 (diff) |
mx6qsabrelite: enet: force master, maximize tx clock delay
Register 0x106 is tx data delay register.
With this patch, gigabit mode still does not work reliably.
Ping shows about a 10% packet loss on large packets.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Diffstat (limited to 'drivers/mmc/fsl_esdhc.c')
0 files changed, 0 insertions, 0 deletions