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authorWolfgang Denk <wd@denx.de>2010-06-30 01:02:11 +0200
committerWolfgang Denk <wd@denx.de>2010-06-30 01:02:11 +0200
commit0a9463e93537a68e7246714f43fb69eca0b7b214 (patch)
treecec01ecc6502a65cbbbda406dfac23b93c093899 /board
parent955ea6fc2749a4305395758fc797cf8c11dcbed7 (diff)
parentbde3892edac99bf974e5b9809a112a6ce530be03 (diff)
downloadu-boot-linaro-stable-0a9463e93537a68e7246714f43fb69eca0b7b214.tar.gz
Merge branch 'master' into next
Diffstat (limited to 'board')
-rw-r--r--board/evb64260/mpsc.c2
-rw-r--r--board/freescale/p1_p2_rdb/ddr.c2
-rw-r--r--board/freescale/p1_p2_rdb/p1_p2_rdb.c16
3 files changed, 15 insertions, 5 deletions
diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c
index bee04fd53..f3dc20b29 100644
--- a/board/evb64260/mpsc.c
+++ b/board/evb64260/mpsc.c
@@ -88,7 +88,7 @@ static void galsdma_enable_rx(void);
/* GT64240A errata: cant read MPSC/BRG registers... so make mirrors in ram for read/modify write */
-#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->mirror_hack))
+#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->mirror_hack[0]))
#define GT_REG_WRITE_MIRROR_G(a,d) {MIRROR_HACK->a ## _M = d; GT_REG_WRITE(a,d);}
#define GTREGREAD_MIRROR_G(a) (MIRROR_HACK->a ## _M)
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index fccc4f8f5..15b46b0da 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -76,7 +76,7 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
#define CONFIG_SYS_DDR_TIMING_0_667 0x55770802
#define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543
#define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1
-#define CONFIG_SYS_DDR_CLK_CTRL_667 0x02800000
+#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
#define CONFIG_SYS_DDR_MODE_1_667 0x00040852
#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 31cdf9ae4..fae31f28c 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -54,6 +54,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define BOARDREV_MASK 0x10100000
#define BOARDREV_B 0x10100000
#define BOARDREV_C 0x00100000
+#define BOARDREV_D 0x00000000
#define SYSCLK_66 66666666
#define SYSCLK_50 50000000
@@ -64,7 +65,7 @@ unsigned long get_board_sys_clk(ulong dummy)
volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
u32 val_gpdat, sysclk_gpio, board_rev_gpio;
- val_gpdat = pgpio->gpdat;
+ val_gpdat = in_be32(&pgpio->gpdat);
sysclk_gpio = val_gpdat & SYSCLK_MASK;
board_rev_gpio = val_gpdat & BOARDREV_MASK;
if (board_rev_gpio == BOARDREV_C) {
@@ -77,6 +78,11 @@ unsigned long get_board_sys_clk(ulong dummy)
return SYSCLK_66;
else
return SYSCLK_50;
+ } else if (board_rev_gpio == BOARDREV_D) {
+ if(sysclk_gpio == 0)
+ return SYSCLK_66;
+ else
+ return SYSCLK_100;
}
return 0;
}
@@ -100,12 +106,14 @@ int checkboard (void)
char board_rev = 0;
struct cpu_type *cpu;
- val_gpdat = pgpio->gpdat;
+ val_gpdat = in_be32(&pgpio->gpdat);
board_rev_gpio = val_gpdat & BOARDREV_MASK;
if (board_rev_gpio == BOARDREV_C)
board_rev = 'C';
else if (board_rev_gpio == BOARDREV_B)
board_rev = 'B';
+ else if (board_rev_gpio == BOARDREV_D)
+ board_rev = 'D';
else
panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
@@ -159,6 +167,7 @@ int board_eth_init(bd_t *bis)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int num = 0;
char *tmp;
+ u32 pordevsr;
unsigned int vscfw_addr;
#ifdef CONFIG_TSEC1
@@ -171,7 +180,8 @@ int board_eth_init(bd_t *bis)
#endif
#ifdef CONFIG_TSEC3
SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+ pordevsr = in_be32(&gur->pordevsr);
+ if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
tsec_info[num].flags |= TSEC_SGMII;
num++;
#endif