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authorWolfgang Denk <wd@denx.de>2009-02-24 22:56:00 +0100
committerWolfgang Denk <wd@denx.de>2009-02-24 22:56:00 +0100
commit7fe2a9839423a619b5e232646f93ad915ac2029e (patch)
tree99542fc4ed267e373a8620b6d2c685c1a6050dfe /board/imx31_phycore/imx31_phycore.c
parent89e372cd3d520ed20fab543f2cbba2dbb9490cf8 (diff)
parenta2bb7105a79af8f2ffa9f87256fce6c1cbcbd8e1 (diff)
downloadu-boot-linaro-stable-7fe2a9839423a619b5e232646f93ad915ac2029e.tar.gz
Merge branch 'master' of git://git.denx.de/u-boot-video
Diffstat (limited to 'board/imx31_phycore/imx31_phycore.c')
-rw-r--r--board/imx31_phycore/imx31_phycore.c57
1 files changed, 57 insertions, 0 deletions
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
index ae93444a1..93a5c40d7 100644
--- a/board/imx31_phycore/imx31_phycore.c
+++ b/board/imx31_phycore/imx31_phycore.c
@@ -23,6 +23,7 @@
#include <common.h>
+#include <s6e63d6.h>
#include <asm/arch/mx31.h>
#include <asm/arch/mx31-regs.h>
@@ -66,6 +67,62 @@ int board_init (void)
return 0;
}
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_S6E63D6
+ struct s6e63d6 data = {
+ /*
+ * See comment in mxc_spi.c::decode_cs() for .cs field format.
+ * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
+ * 2 of the SPI controller #1, since it is unused.
+ */
+ .cs = 2 | (57 << 8),
+ .bus = 0,
+ .id = 0,
+ };
+ int ret;
+
+ /* SPI1 */
+ mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
+ mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
+ mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
+ mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
+ mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
+ mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
+ mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
+
+ /* start SPI1 clock */
+ __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
+
+ /* GPIO 57 */
+ /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
+ mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
+
+ /* SPI1 CS2 is free */
+ ret = s6e63d6_init(&data);
+ if (ret)
+ return ret;
+
+ /*
+ * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
+ * OLED display connected to a S6E63D6 SPI display controller in the
+ * 18 bit RGB mode
+ */
+ s6e63d6_index(&data, 2);
+ s6e63d6_param(&data, 0x0182);
+ s6e63d6_index(&data, 3);
+ s6e63d6_param(&data, 0x8130);
+ s6e63d6_index(&data, 0x10);
+ s6e63d6_param(&data, 0x0000);
+ s6e63d6_index(&data, 5);
+ s6e63d6_param(&data, 0x0001);
+ s6e63d6_index(&data, 0x22);
+#endif
+ return 0;
+}
+#endif
+
int checkboard (void)
{
printf("Board: Phytec phyCore i.MX31\n");