diff options
| author | Wolfgang Denk <wd@denx.de> | 2009-03-09 00:41:48 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-03-09 00:41:48 +0100 |
| commit | 014c595f12d4f7e14cb10188f856465b2d41718f (patch) | |
| tree | 9130a01fbb5499975530a20a559dbaba9a1f2a89 /board/freescale | |
| parent | 9c2d63ec0e9520948b6d598ea32e9aa4e0de847f (diff) | |
| parent | f70fd13e2fe4cf58e251271c27f9c06e141d7f9a (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
Conflicts:
lib_ppc/board.c
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/mpc837xemds/pci.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c index 31116b31c..29de2e77f 100644 --- a/board/freescale/mpc837xemds/pci.c +++ b/board/freescale/mpc837xemds/pci.c @@ -115,6 +115,13 @@ skip_pci: if (PARTID_NO_E(spridr) == SPR_8379) return; + if (pex2) + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + else + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + /* Configure the clock for PCIE controller */ clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); @@ -132,13 +139,6 @@ skip_pci: out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); - if (pex2) - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - else - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg, 0); } |