path: root/arch
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authorJohn Rigby <john.rigby@linaro.org>2011-09-22 21:55:14 -0600
committerJohn Rigby <john.rigby@linaro.org>2012-12-06 12:16:44 -0700
commita895321ff9d640f3881625f435f0aa4b1c7643b0 (patch)
treee6d088cf91f0b2a0821126ae18980635352d9aa2 /arch
parentc2232c71a01a2483f966b3618b30477583e75c71 (diff)
SAUCE: HACK: move omap spl base address
Move NON_SECURE_SRAM_START from 0x40304000 to 0x40303000 and move u-boot-spl load address from 0x40304350 to 0x40303080. This allows it to stay under 0x4030c000 which is what the TRM says it must do. SRAM actually starts at 0x40300000 on GP devices but was set to 0x40304000 to be the same as Secure devices so this breaks that. Signed-off-by: John Rigby <john.rigby@linaro.org>
Diffstat (limited to 'arch')
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index d4b507610..a7e97eb12 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -167,7 +167,7 @@ struct control_lpddr2io_regs {
* Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
* at 0x40304000(EMU base) so that our code works for both EMU and GP
-#define NON_SECURE_SRAM_START 0x40304000
+#define NON_SECURE_SRAM_START 0x40303000
#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4030D000