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authorJeong-Hyeon Kim <jhkim@insignal.co.kr>2012-08-29 12:28:26 +0900
committerJohn Rigby <john.rigby@linaro.org>2012-12-06 13:51:42 -0700
commit4a703be87762dfd8753ad77af235f2db252592e3 (patch)
treef5eae01e95873ac50c9c41b03738b137a0dec5e8 /arch
parentcd191553c40ab35703847ea2bb1f4c360fc3a49e (diff)
downloadu-boot-linaro-stable-4a703be87762dfd8753ad77af235f2db252592e3.tar.gz
EXYNOS: additional Exynos4 SoC series support
- Fixed MPLL register address It's different between Exynos4210 and Exynos4412. - Added pinmux functions for Exynos4 - Added extended gpios for Exynos4412 Exynos4412 has more gpios than Exynos4210. Signed-off-by: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/exynos/clock.c67
-rw-r--r--arch/arm/cpu/armv7/exynos/pinmux.c241
-rw-r--r--arch/arm/include/asm/arch-exynos/clock.h240
-rw-r--r--arch/arm/include/asm/arch-exynos/cpu.h14
-rw-r--r--arch/arm/include/asm/arch-exynos/gpio.h21
5 files changed, 578 insertions, 5 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 680aeeb4d..002a49390 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -92,6 +92,70 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
return fout;
}
+/* exynos4: return pll clock frequency */
+static unsigned long exynos4412_get_pll_clk(int pllreg)
+{
+ struct exynos4412_clock *clk =
+ (struct exynos4412_clock *)samsung_get_base_clock();
+ unsigned long r, m, p, s, k = 0, mask, fout;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con0);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con0);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con0);
+ k = readl(&clk->epll_con1);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con0);
+ k = readl(&clk->vpll_con1);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ /*
+ * APLL_CON: MIDV [25:16]
+ * MPLL_CON: MIDV [25:16]
+ * EPLL_CON: MIDV [24:16]
+ * VPLL_CON: MIDV [24:16]
+ */
+ if (pllreg == APLL || pllreg == MPLL)
+ mask = 0x3ff;
+ else
+ mask = 0x1ff;
+
+ m = (r >> 16) & mask;
+
+ /* PDIV [13:8] */
+ p = (r >> 8) & 0x3f;
+ /* SDIV [2:0] */
+ s = r & 0x7;
+
+ freq = CONFIG_SYS_CLK_FREQ;
+
+ if (pllreg == EPLL) {
+ k = k & 0xffff;
+ /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
+ fout = (m + k / 65536) * (freq / (p * (1 << s)));
+ } else if (pllreg == VPLL) {
+ k = k & 0xffff;
+ /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
+ fout = (m + k / 65536) * (freq / (p * (1 << s)));
+ } else {
+ /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+ fout = m * (freq / (p * (1 << s)));
+ }
+
+ return fout;
+}
+
/* exynos5: return pll clock frequency */
static unsigned long exynos5_get_pll_clk(int pllreg)
{
@@ -745,6 +809,9 @@ unsigned long get_pll_clk(int pllreg)
if (cpu_is_exynos5())
return exynos5_get_pll_clk(pllreg);
else
+ if (cpu_is_exynos4412())
+ return exynos4412_get_pll_clk(pllreg);
+ else
return exynos4_get_pll_clk(pllreg);
}
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index 7776add9d..0746878a2 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -26,6 +26,245 @@
#include <asm/arch/pinmux.h>
#include <asm/arch/sromc.h>
+static void exynos4_uart_config(int peripheral)
+{
+ struct exynos4_gpio_part1 *gpio1 =
+ (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
+ struct s5p_gpio_bank *bank;
+ int i, start, count;
+
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ bank = &gpio1->a0;
+ start = 0;
+ count = 4;
+ break;
+ case PERIPH_ID_UART1:
+ bank = &gpio1->a0;
+ start = 4;
+ count = 4;
+ break;
+ case PERIPH_ID_UART2:
+ bank = &gpio1->a1;
+ start = 0;
+ count = 4;
+ break;
+ case PERIPH_ID_UART3:
+ bank = &gpio1->a1;
+ start = 4;
+ count = 2;
+ break;
+ }
+ for (i = start; i < start + count; i++) {
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ }
+}
+
+static int exynos4_mmc_config(int peripheral, int flags)
+{
+ struct exynos4_gpio_part2 *gpio2 =
+ (struct exynos4_gpio_part2 *) samsung_get_base_gpio_part2();
+ struct s5p_gpio_bank *bank, *bank_ext;
+ int i, start = 0, gpio_func = 0;
+
+ switch (peripheral) {
+ case PERIPH_ID_SDMMC0:
+ bank = &gpio2->k0;
+ bank_ext = &gpio2->k1;
+ start = 3;
+ gpio_func = GPIO_FUNC(0x2);
+ break;
+ case PERIPH_ID_SDMMC1:
+ bank = &gpio2->k1;
+ bank_ext = NULL;
+ break;
+ case PERIPH_ID_SDMMC2:
+ bank = &gpio2->k2;
+ bank_ext = &gpio2->k3;
+ start = 3;
+ gpio_func = GPIO_FUNC(0x3);
+ break;
+ case PERIPH_ID_SDMMC3:
+ bank = &gpio2->k3;
+ bank_ext = NULL;
+ break;
+ }
+ if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+ debug("SDMMC device %d does not support 8bit mode",
+ peripheral);
+ return -1;
+ }
+ if (flags & PINMUX_FLAG_8BIT_MODE) {
+ for (i = start; i <= (start + 3); i++) {
+ s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
+ s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
+ s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+ }
+ }
+ for (i = 0; i < 2; i++) {
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+ s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ }
+ for (i = 3; i <= 6; i++) {
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
+ s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ }
+ return 0;
+}
+
+static void exynos4_sromc_config(int flags)
+{
+ struct exynos4_gpio_part2 *gpio2 =
+ (struct exynos4_gpio_part2 *) samsung_get_base_gpio_part2();
+ int i;
+
+ /*
+ * SROM:CS1 and EBI
+ *
+ * GPY0[0] SROM_CSn[0]
+ * GPY0[1] SROM_CSn[1](2)
+ * GPY0[2] SROM_CSn[2]
+ * GPY0[3] SROM_CSn[3]
+ * GPY0[4] EBI_OEn(2)
+ * GPY0[5] EBI_EEn(2)
+ *
+ * GPY1[0] EBI_BEn[0](2)
+ * GPY1[1] EBI_BEn[1](2)
+ * GPY1[2] SROM_WAIT(2)
+ * GPY1[3] EBI_DATA_RDn(2)
+ */
+ s5p_gpio_cfg_pin(&gpio2->y0, (flags & PINMUX_FLAG_BANK),
+ GPIO_FUNC(2));
+ s5p_gpio_cfg_pin(&gpio2->y0, 4, GPIO_FUNC(2));
+ s5p_gpio_cfg_pin(&gpio2->y0, 5, GPIO_FUNC(2));
+
+ for (i = 0; i < 4; i++)
+ s5p_gpio_cfg_pin(&gpio2->y1, i, GPIO_FUNC(2));
+
+ /*
+ * EBI: 8 Addrss Lines
+ *
+ * GPY3[0] EBI_ADDR[0](2)
+ * GPY3[1] EBI_ADDR[1](2)
+ * GPY3[2] EBI_ADDR[2](2)
+ * GPY3[3] EBI_ADDR[3](2)
+ * GPY3[4] EBI_ADDR[4](2)
+ * GPY3[5] EBI_ADDR[5](2)
+ * GPY3[6] EBI_ADDR[6](2)
+ * GPY3[7] EBI_ADDR[7](2)
+ *
+ * EBI: 16 Data Lines
+ *
+ * GPY5[0] EBI_DATA[0](2)
+ * GPY5[1] EBI_DATA[1](2)
+ * GPY5[2] EBI_DATA[2](2)
+ * GPY5[3] EBI_DATA[3](2)
+ * GPY5[4] EBI_DATA[4](2)
+ * GPY5[5] EBI_DATA[5](2)
+ * GPY5[6] EBI_DATA[6](2)
+ * GPY5[7] EBI_DATA[7](2)
+ *
+ * GPY6[0] EBI_DATA[8](2)
+ * GPY6[1] EBI_DATA[9](2)
+ * GPY6[2] EBI_DATA[10](2)
+ * GPY6[3] EBI_DATA[11](2)
+ * GPY6[4] EBI_DATA[12](2)
+ * GPY6[5] EBI_DATA[13](2)
+ * GPY6[6] EBI_DATA[14](2)
+ * GPY6[7] EBI_DATA[15](2)
+ */
+ for (i = 0; i < 8; i++) {
+ s5p_gpio_cfg_pin(&gpio2->y3, i, GPIO_FUNC(2));
+ s5p_gpio_set_pull(&gpio2->y3, i, GPIO_PULL_UP);
+
+ s5p_gpio_cfg_pin(&gpio2->y5, i, GPIO_FUNC(2));
+ s5p_gpio_set_pull(&gpio2->y5, i, GPIO_PULL_UP);
+
+ s5p_gpio_cfg_pin(&gpio2->y6, i, GPIO_FUNC(2));
+ s5p_gpio_set_pull(&gpio2->y6, i, GPIO_PULL_UP);
+ }
+}
+
+static void exynos4_i2c_config(int peripheral, int flags)
+{
+
+ struct exynos4_gpio_part1 *gpio1 =
+ (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
+
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C1:
+ s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C2:
+ s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C3:
+ s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C4:
+ s5p_gpio_cfg_pin(&gpio1->b, 0, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b, 1, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C5:
+ s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C6:
+ s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
+ break;
+ case PERIPH_ID_I2C7:
+ s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
+ break;
+ }
+}
+
+static int exynos4_pinmux_config(int peripheral, int flags)
+{
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ exynos4_uart_config(peripheral);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC3:
+ return exynos4_mmc_config(peripheral, flags);
+ case PERIPH_ID_SROMC:
+ exynos4_sromc_config(flags);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ exynos4_i2c_config(peripheral, flags);
+ break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ }
+
+ return 0;
+}
+
static void exynos5_uart_config(int peripheral)
{
struct exynos5_gpio_part1 *gpio1 =
@@ -269,6 +508,8 @@ int exynos_pinmux_config(int peripheral, int flags)
{
if (cpu_is_exynos5())
return exynos5_pinmux_config(peripheral, flags);
+ else if (cpu_is_exynos4())
+ return exynos4_pinmux_config(peripheral, flags);
else {
debug("pinmux functionality not supported\n");
return -1;
diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
index fce38efbb..77760f25b 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -251,6 +251,246 @@ struct exynos4_clock {
unsigned int div_iem_l1;
};
+struct exynos4412_clock {
+ unsigned char res1[0x4200];
+ unsigned int src_leftbus;
+ unsigned char res2[0x1fc];
+ unsigned int mux_stat_leftbus;
+ unsigned char res3[0xfc];
+ unsigned int div_leftbus;
+ unsigned char res4[0xfc];
+ unsigned int div_stat_leftbus;
+ unsigned char res5[0x1fc];
+ unsigned int gate_ip_leftbus;
+ unsigned char res6[0x12c];
+ unsigned int gate_ip_image;
+ unsigned char res7[0xcc];
+ unsigned int clkout_cmu_leftbus;
+ unsigned int clkout_cmu_leftbus_div_stat;
+ unsigned char res8[0x37f8];
+ unsigned int src_rightbus;
+ unsigned char res9[0x1fc];
+ unsigned int mux_stat_rightbus;
+ unsigned char res10[0xfc];
+ unsigned int div_rightbus;
+ unsigned char res11[0xfc];
+ unsigned int div_stat_rightbus;
+ unsigned char res12[0x1fc];
+ unsigned int gate_ip_rightbus;
+ unsigned char res13[0x15c];
+ unsigned int gate_ip_perir;
+ unsigned char res14[0x9c];
+ unsigned int clkout_cmu_rightbus;
+ unsigned int clkout_cmu_rightbus_div_stat;
+ unsigned char res15[0x3608];
+ unsigned int epll_lock;
+ unsigned char res16[0xc];
+ unsigned int vpll_lock;
+ unsigned char res17[0xec];
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned int epll_con2;
+ unsigned char res18[0x4];
+ unsigned int vpll_con0;
+ unsigned int vpll_con1;
+ unsigned int vpll_con2;
+ unsigned char res19[0xe4];
+ unsigned int src_top0;
+ unsigned int src_top1;
+ unsigned char res20[0x8];
+ unsigned int src_cam0;
+ unsigned int src_tv;
+ unsigned int src_mfc;
+ unsigned int src_g3d;
+ unsigned char res21[0x4];
+ unsigned int src_lcd0;
+ unsigned int src_isp;
+ unsigned int src_maudio;
+ unsigned int src_fsys;
+ unsigned char res22[0xc];
+ unsigned int src_peril0;
+ unsigned int src_peril1;
+ unsigned int src_cam1;
+ unsigned char res23[0xc4];
+ unsigned int src_mask_cam0;
+ unsigned int src_mask_tv;
+ unsigned char res24[0xc];
+ unsigned int src_mask_lcd;
+ unsigned int src_mask_isp;
+ unsigned int src_mask_maudio;
+ unsigned int src_mask_fsys;
+ unsigned char res25[0xc];
+ unsigned int src_mask_peril0;
+ unsigned int src_mask_peril1;
+ unsigned char res26[0xb8];
+ unsigned int mux_stat_top;
+ unsigned int mux_stat_top1;
+ unsigned char res27[0x10];
+ unsigned int mux_stat_mfc;
+ unsigned int mux_stat_g3d;
+ unsigned char res28[0x28];
+ unsigned int mux_stat_cam1;
+ unsigned char res29[0xb4];
+ unsigned int div_top;
+ unsigned char res30[0xc];
+ unsigned int div_cam0;
+ unsigned int div_tv;
+ unsigned int div_mfc;
+ unsigned int div_g3d;
+ unsigned char res31[0x4];
+ unsigned int div_lcd;
+ unsigned int div_isp;
+ unsigned int div_maudio;
+ unsigned int div_fsys0;
+ unsigned int div_fsys1;
+ unsigned int div_fsys2;
+ unsigned int div_fsys3;
+ unsigned int div_peril0;
+ unsigned int div_peril1;
+ unsigned int div_peril2;
+ unsigned int div_peril3;
+ unsigned int div_peril4;
+ unsigned int div_peril5;
+ unsigned int div_cam1;
+ unsigned char res32[0x14];
+ unsigned int div2_ratio;
+ unsigned char res33[0x8c];
+ unsigned int div_stat_top;
+ unsigned char res34[0xc];
+ unsigned int div_stat_cam0;
+ unsigned int div_stat_tv;
+ unsigned int div_stat_mfc;
+ unsigned int div_stat_g3d;
+ unsigned char res35[0x4];
+ unsigned int div_stat_lcd;
+ unsigned int div_stat_isp;
+ unsigned int div_stat_maudio;
+ unsigned int div_stat_fsys0;
+ unsigned int div_stat_fsys1;
+ unsigned int div_stat_fsys2;
+ unsigned int div_stat_fsys3;
+ unsigned int div_stat_peril0;
+ unsigned int div_stat_peril1;
+ unsigned int div_stat_peril2;
+ unsigned int div_stat_peril3;
+ unsigned int div_stat_peril4;
+ unsigned int div_stat_peril5;
+ unsigned int div_stat_cam1;
+ unsigned char res36[0x14];
+ unsigned int div2_stat;
+ unsigned char res37[0xc0];
+ unsigned int gate_bus_fsys1;
+ unsigned char res38[0x1d8];
+ unsigned int gate_ip_cam;
+ unsigned int gate_ip_tv;
+ unsigned int gate_ip_mfc;
+ unsigned int gate_ip_g3d;
+ unsigned char res39[0x4];
+ unsigned int gate_ip_lcd;
+ unsigned int gate_ip_isp;
+ unsigned char res40[0x4];
+ unsigned int gate_ip_fsys;
+ unsigned char res41[0x8];
+ unsigned int gate_ip_gps;
+ unsigned int gate_ip_peril;
+ unsigned char res42[0x1c];
+ unsigned int gate_block;
+ unsigned char res43[0x8c];
+ unsigned int clkout_cmu_top;
+ unsigned int clkout_cmu_top_div_stat;
+ unsigned char res44[0x3600];
+ unsigned int mpll_lock;
+ unsigned char res45[0xfc];
+ unsigned int mpll_con0;
+ unsigned int mpll_con1;
+ unsigned char res46[0xf0];
+ unsigned int src_dmc;
+ unsigned char res47[0xfc];
+ unsigned int src_mask_dmc;
+ unsigned char res48[0xfc];
+ unsigned int mux_stat_dmc;
+ unsigned char res49[0xfc];
+ unsigned int div_dmc0;
+ unsigned int div_dmc1;
+ unsigned char res50[0xf8];
+ unsigned int div_stat_dmc0;
+ unsigned int div_stat_dmc1;
+ unsigned char res51[0x2f8];
+ unsigned int gate_ip_dmc;
+ unsigned int gate_ip_dmc1;
+ unsigned char res52[0xf8];
+ unsigned int clkout_cmu_dmc;
+ unsigned int clkout_cmu_dmc_div_stat;
+ unsigned char res53[0x5f8];
+ unsigned int dcgidx_map0;
+ unsigned int dcgidx_map1;
+ unsigned int dcgidx_map2;
+ unsigned char res54[0x14];
+ unsigned int dcgperf_map0;
+ unsigned int dcgperf_map1;
+ unsigned char res55[0x18];
+ unsigned int dvcidx_map;
+ unsigned char res56[0x1c];
+ unsigned int freq_cpu;
+ unsigned int freq_dpm;
+ unsigned char res57[0x18];
+ unsigned int dvsemclk_en;
+ unsigned int maxperf;
+ unsigned char res58[0xc];
+ unsigned int dmc_puause_ctrl;
+ unsigned int ddrphy_lock_ctrl;
+ unsigned int c2c_state;
+ unsigned char res59[0x2f60];
+ unsigned int apll_lock;
+ unsigned char res60[0xfc];
+ unsigned int apll_con0;
+ unsigned int apll_con1;
+ unsigned char res61[0xf8];
+ unsigned int src_cpu;
+ unsigned char res62[0x1fc];
+ unsigned int mux_stat_cpu;
+ unsigned char res63[0xfc];
+ unsigned int div_cpu0;
+ unsigned int div_cpu1;
+ unsigned char res64[0xf8];
+ unsigned int div_stat_cpu0;
+ unsigned int div_stat_cpu1;
+ unsigned char res65[0x2f8];
+ unsigned int gate_ip_cpu;
+ unsigned char res66[0xfc];
+ unsigned int clkout_cmu_cpu;
+ unsigned int clkout_cmu_cpu_div_stat;
+ unsigned char res67[0x5f8];
+ unsigned int armclk_stopctrl;
+ unsigned int atclk_stopctrl;
+ unsigned char res68[0x18];
+ unsigned int pwr_ctrl;
+ unsigned int pwr_ctrl2;
+ unsigned char res69[0x3d8];
+ unsigned int l2_status;
+ unsigned char res70[0xc];
+ unsigned int cpu_status;
+ unsigned char res71[0xc];
+ unsigned int ptm_status;
+ unsigned char res72[0x2edc];
+ unsigned int clk_div_isp0;
+ unsigned int clk_div_isp1;
+ unsigned char res73[0xf8];
+ unsigned int clk_div_stat_isp0;
+ unsigned int clk_div_stat_isp1;
+ unsigned char res74[0x3f8];
+ unsigned int gate_ip_isp0;
+ unsigned int gate_ip_isp1;
+ unsigned char res75[0x1f8];
+ unsigned int clkout_cmu_isp;
+ unsigned int clkout_cmu_isp_stat;
+ unsigned char res76[0xf8];
+ unsigned int clkout_cmu_spare0;
+ unsigned int clkout_cmu_spare1;
+ unsigned int clkout_cmu_spare2;
+ unsigned int clkout_cmu_spare3;
+};
+
struct exynos5_clock {
unsigned int apll_lock;
unsigned char res1[0xfc];
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 2cd4ae152..58c7de60b 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -58,6 +58,10 @@
#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4412_DMC0_BASE 0x10600000
+#define EXYNOS4412_DMC1_BASE 0x10610000
+#define EXYNOS4412_GPIO_PART4_BASE 0x106E0000
+
/* EXYNOS5 */
#define EXYNOS5_I2C_SPACING 0x10000
@@ -130,14 +134,16 @@ static inline char *s5p_get_cpu_name(void)
return EXYNOS_CPU_NAME;
}
-#define IS_SAMSUNG_TYPE(type, id) \
+#define IS_SAMSUNG_TYPE(type, id, shift) \
static inline int cpu_is_##type(void) \
{ \
- return (s5p_cpu_id >> 12) == id; \
+ return (s5p_cpu_id >> shift) == id; \
}
-IS_SAMSUNG_TYPE(exynos4, 0x4)
-IS_SAMSUNG_TYPE(exynos5, 0x5)
+IS_SAMSUNG_TYPE(exynos4, 0x4, 12)
+IS_SAMSUNG_TYPE(exynos4210, 0x4210, 0)
+IS_SAMSUNG_TYPE(exynos4412, 0x4412, 0)
+IS_SAMSUNG_TYPE(exynos5, 0x5, 12)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int samsung_get_base_##device(void) \
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index 4db8fd640..09286451f 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -49,6 +49,9 @@ struct exynos4_gpio_part1 {
struct s5p_gpio_bank f1;
struct s5p_gpio_bank f2;
struct s5p_gpio_bank f3;
+ struct s5p_gpio_bank res1[2];
+ struct s5p_gpio_bank j0;
+ struct s5p_gpio_bank j1;
};
struct exynos4_gpio_part2 {
@@ -68,7 +71,13 @@ struct exynos4_gpio_part2 {
struct s5p_gpio_bank y4;
struct s5p_gpio_bank y5;
struct s5p_gpio_bank y6;
- struct s5p_gpio_bank res1[80];
+ struct s5p_gpio_bank res1[3];
+ struct s5p_gpio_bank m0;
+ struct s5p_gpio_bank m1;
+ struct s5p_gpio_bank m2;
+ struct s5p_gpio_bank m3;
+ struct s5p_gpio_bank m4;
+ struct s5p_gpio_bank res2[72];
struct s5p_gpio_bank x0;
struct s5p_gpio_bank x1;
struct s5p_gpio_bank x2;
@@ -79,6 +88,16 @@ struct exynos4_gpio_part3 {
struct s5p_gpio_bank z;
};
+struct exynos4_gpio_part4 {
+ struct s5p_gpio_bank v0;
+ struct s5p_gpio_bank v1;
+ struct s5p_gpio_bank res1[1];
+ struct s5p_gpio_bank v2;
+ struct s5p_gpio_bank v3;
+ struct s5p_gpio_bank res2[1];
+ struct s5p_gpio_bank v4;
+};
+
struct exynos5_gpio_part1 {
struct s5p_gpio_bank a0;
struct s5p_gpio_bank a1;