diff options
| author | York Sun <yorksun@freescale.com> | 2011-03-17 11:18:12 -0700 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-03-24 09:20:50 -0500 |
| commit | 4ca31929466b2804eac74d04ec7bf656c568250e (patch) | |
| tree | a4cef3565ed35aa6144d3d73ca425337e990b229 /arch | |
| parent | 634bc5542959f9ab53961642a1106c4acd2757f3 (diff) | |
powerpc/mpc8xxx: disable rcw_en bit for non-DDR3
rcw_en bit is only available for DDR3 controllers. It is a reserved bit on
DDR1 and DDR2 controllers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 8ef6ca8c1..cefabe769 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -682,7 +682,9 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, | ((obc_cfg & 0x1) << 6) | ((ap_en & 0x1) << 5) | ((d_init & 0x1) << 4) +#ifdef CONFIG_FSL_DDR3 | ((rcw_en & 0x1) << 2) +#endif | ((md_en & 0x1) << 0) ); debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); |