aboutsummaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
authorSteve Sakoman <steve@sakoman.com>2010-08-17 14:39:34 -0700
committerSandeep Paulraj <s-paulraj@ti.com>2010-09-08 14:50:52 -0400
commitb2b9169f0bc860ac34d7828df8730744394d8f6e (patch)
treea267e19c62fbfc5794fd39da8d36c0b8952bef01 /arch
parentba9a11e4ea27d43bfc3d9f1787117fe4826b3ce7 (diff)
downloadu-boot-linaro-stable-b2b9169f0bc860ac34d7828df8730744394d8f6e.tar.gz
ARMV7: OMAP3: Update CPU type detection for AM35XX/OMAP36XX/37XX
TI has added new processors to the OMAP3 family. This patch enhances the code in sysinfo.c to detect which family member is present. Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/omap3/sys_info.c147
-rw-r--r--arch/arm/include/asm/arch-omap3/cpu.h14
-rw-r--r--arch/arm/include/asm/arch-omap3/omap3.h32
-rw-r--r--arch/arm/include/asm/arch-omap3/sys_proto.h2
4 files changed, 161 insertions, 34 deletions
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
index 1df4401d4..549ac1918 100644
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ b/arch/arm/cpu/armv7/omap3/sys_info.c
@@ -38,7 +38,10 @@ static char *rev_s[CPU_3XX_MAX_REV] = {
"2.0",
"2.1",
"3.0",
- "3.1"};
+ "3.1",
+ "UNKNOWN",
+ "UNKNOWN",
+ "3.1.2"};
/*****************************************************************
* dieid_num_r(void) - read and set die ID
@@ -75,32 +78,81 @@ u32 get_cpu_type(void)
}
/******************************************
- * get_cpu_rev(void) - extract version info
+ * get_cpu_id(void) - extract cpu id
+ * returns 0 for ES1.0, cpuid otherwise
******************************************/
-u32 get_cpu_rev(void)
+u32 get_cpu_id(void)
{
- u32 cpuid = 0;
struct ctrl_id *id_base;
+ u32 cpuid = 0;
/*
* On ES1.0 the IDCODE register is not exposed on L4
* so using CPU ID to differentiate between ES1.0 and > ES1.0.
*/
__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
- if ((cpuid & 0xf) == 0x0)
- return CPU_3XX_ES10;
- else {
+ if ((cpuid & 0xf) == 0x0) {
+ return 0;
+ } else {
/* Decode the IDs on > ES1.0 */
id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
- cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf;
+ cpuid = readl(&id_base->idcode);
+ }
- /* Some early ES2.0 seem to report ID 0, fix this */
- if(cpuid == 0)
- cpuid = CPU_3XX_ES20;
+ return cpuid;
+}
- return cpuid;
+/******************************************
+ * get_cpu_family(void) - extract cpu info
+ ******************************************/
+u32 get_cpu_family(void)
+{
+ u16 hawkeye;
+ u32 cpu_family;
+ u32 cpuid = get_cpu_id();
+
+ if (cpuid == 0)
+ return CPU_OMAP34XX;
+
+ hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
+ switch (hawkeye) {
+ case HAWKEYE_OMAP34XX:
+ cpu_family = CPU_OMAP34XX;
+ break;
+ case HAWKEYE_AM35XX:
+ cpu_family = CPU_AM35XX;
+ break;
+ case HAWKEYE_OMAP36XX:
+ cpu_family = CPU_OMAP36XX;
+ break;
+ default:
+ cpu_family = CPU_OMAP34XX;
}
+
+ return cpu_family;
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+ u32 cpuid = get_cpu_id();
+
+ if (cpuid == 0)
+ return CPU_3XX_ES10;
+ else
+ return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
+}
+
+/*****************************************************************
+ * get_sku_id(void) - read sku_id to get info on max clock rate
+ *****************************************************************/
+u32 get_sku_id(void)
+{
+ struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
+ return readl(&id_base->sku_id) & SKUID_CLK_MASK;
}
/***************************************************************************
@@ -213,24 +265,66 @@ u32 get_device_type(void)
*/
int print_cpuinfo (void)
{
- char *cpu_s, *sec_s;
+ char *cpu_family_s, *cpu_s, *sec_s, *max_clk;
+
+ switch (get_cpu_family()) {
+ case CPU_OMAP34XX:
+ cpu_family_s = "OMAP";
+ switch (get_cpu_type()) {
+ case OMAP3503:
+ cpu_s = "3503";
+ break;
+ case OMAP3515:
+ cpu_s = "3515";
+ break;
+ case OMAP3525:
+ cpu_s = "3525";
+ break;
+ case OMAP3530:
+ cpu_s = "3530";
+ break;
+ default:
+ cpu_s = "35XX";
+ break;
+ }
+ if ((get_cpu_rev() >= CPU_3XX_ES31) &&
+ (get_sku_id() == SKUID_CLK_720MHZ))
+ max_clk = "720 mHz";
+ else
+ max_clk = "600 mHz";
- switch (get_cpu_type()) {
- case OMAP3503:
- cpu_s = "3503";
break;
- case OMAP3515:
- cpu_s = "3515";
+ case CPU_AM35XX:
+ cpu_family_s = "AM";
+ switch (get_cpu_type()) {
+ case AM3505:
+ cpu_s = "3505";
+ break;
+ case AM3517:
+ cpu_s = "3517";
+ break;
+ default:
+ cpu_s = "35XX";
+ break;
+ }
+ max_clk = "600 Mhz";
break;
- case OMAP3525:
- cpu_s = "3525";
- break;
- case OMAP3530:
- cpu_s = "3530";
+ case CPU_OMAP36XX:
+ cpu_family_s = "OMAP";
+ switch (get_cpu_type()) {
+ case OMAP3730:
+ cpu_s = "3630/3730";
+ break;
+ default:
+ cpu_s = "36XX/37XX";
+ break;
+ }
+ max_clk = "1 Ghz";
break;
default:
+ cpu_family_s = "OMAP";
cpu_s = "35XX";
- break;
+ max_clk = "600 Mhz";
}
switch (get_device_type()) {
@@ -250,8 +344,9 @@ int print_cpuinfo (void)
sec_s = "?";
}
- printf("OMAP%s-%s ES%s, CPU-OPP2 L3-165MHz\n",
- cpu_s, sec_s, rev_s[get_cpu_rev()]);
+ printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
+ cpu_family_s, cpu_s, sec_s,
+ rev_s[get_cpu_rev()], max_clk);
return 0;
}
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index 390b00794..99da756bc 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -60,19 +60,14 @@ struct ctrl {
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
-/* cpu type */
-#define OMAP3503 0x5c00
-#define OMAP3515 0x1c00
-#define OMAP3525 0x4c00
-#define OMAP3530 0x0c00
-
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct ctrl_id {
u8 res1[0x4];
u32 idcode; /* 0x04 */
u32 prod_id; /* 0x08 */
- u8 res2[0x0C];
+ u32 sku_id; /* 0x0c */
+ u8 res2[0x08];
u32 die_id_0; /* 0x18 */
u32 die_id_1; /* 0x1C */
u32 die_id_2; /* 0x20 */
@@ -89,6 +84,11 @@ struct ctrl_id {
#define HS_DEVICE 0x2
#define GP_DEVICE 0x3
+/* device speed */
+#define SKUID_CLK_MASK 0xf
+#define SKUID_CLK_600MHZ 0x0
+#define SKUID_CLK_720MHZ 0x8
+
#define GPMC_BASE (OMAP34XX_GPMC_BASE)
#define GPMC_CONFIG_CS0 0x60
#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h
index 12815f694..3957c796f 100644
--- a/arch/arm/include/asm/arch-omap3/omap3.h
+++ b/arch/arm/include/asm/arch-omap3/omap3.h
@@ -176,11 +176,41 @@ struct gpio {
#define CPU_3XX_ES21 2
#define CPU_3XX_ES30 3
#define CPU_3XX_ES31 4
-#define CPU_3XX_MAX_REV (CPU_3XX_ES31 + 1)
+#define CPU_3XX_ES312 7
+#define CPU_3XX_MAX_REV 8
#define CPU_3XX_ID_SHIFT 28
#define WIDTH_8BIT 0x0000
#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
+/*
+ * Hawkeye values
+ */
+#define HAWKEYE_OMAP34XX 0xb7ae
+#define HAWKEYE_AM35XX 0xb868
+#define HAWKEYE_OMAP36XX 0xb891
+
+#define HAWKEYE_SHIFT 12
+
+/*
+ * Define CPU families
+ */
+#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */
+#define CPU_AM35XX 0x3500 /* AM35xx devices */
+#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */
+
+/*
+ * Control status register values corresponding to cpu variants
+ */
+#define OMAP3503 0x5c00
+#define OMAP3515 0x1c00
+#define OMAP3525 0x4c00
+#define OMAP3530 0x0c00
+
+#define AM3505 0x5c00
+#define AM3517 0x1c00
+
+#define OMAP3730 0x0c00
+
#endif
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index db7b42aed..4a28ba1c4 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -41,7 +41,9 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
void watchdog_init(void);
void set_muxconf_regs(void);
+u32 get_cpu_family(void);
u32 get_cpu_rev(void);
+u32 get_sku_id(void);
u32 get_mem_type(void);
u32 get_sysboot_value(void);
u32 is_gpmc_muxed(void);