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authorKumar Gala <galak@kernel.crashing.org>2010-09-23 14:50:37 -0500
committerKumar Gala <galak@kernel.crashing.org>2010-10-07 09:49:47 -0500
commit3c6a22b962e4dd86637a9d49fe46c5bcc69cbe5a (patch)
tree63780f58791fb2b53cdd926f68fb6e76ca55794d /arch/powerpc
parent1bf8e9fd7498da3f9b109944b0551c589402d643 (diff)
downloadu-boot-linaro-stable-3c6a22b962e4dd86637a9d49fe46c5bcc69cbe5a.tar.gz
powerpc/p4080: Add new CPC register - HDBCR0
Manual was updated to add a new register for disabling CDQ speculation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 3dd2b7f53..30c64ebb1 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1589,7 +1589,9 @@ typedef struct cpc_corenet {
u32 cpcerreaddr; /* error extended address */
u32 cpcerraddr; /* error address */
u32 cpcerrctl; /* error control */
- u32 res9[105]; /* pad out to 4k */
+ u32 res9[41]; /* pad out to 4k */
+ u32 cpchdbcr0; /* hardware debug control register 0 */
+ u32 res10[63]; /* pad out to 4k */
} cpc_corenet_t;
#define CPC_CSR0_CE 0x80000000 /* Cache Enable */
@@ -1616,6 +1618,7 @@ typedef struct cpc_corenet {
#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
#define CPC_SRCR0_SRAMEN 0x00000001
#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
+#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
#endif /* CONFIG_SYS_FSL_CPC */
/* Global Utilities Block */