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authorWolfgang Denk <wd@denx.de>2010-07-24 20:34:13 +0200
committerWolfgang Denk <wd@denx.de>2010-07-24 20:34:13 +0200
commit96623171423a94092cde80642328fda58a92c894 (patch)
treee5e98dc33dc17399ad16d85d6df1c36d44e22889 /arch/powerpc/include
parent47ec10c5975f0ce8f4a748c7b76c45c0fb60c0ac (diff)
parent1ffcb86ce06a252ff6f4620691eb347c8ab47b61 (diff)
downloadu-boot-linaro-stable-96623171423a94092cde80642328fda58a92c894.tar.gz
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/ppc4xx-sdram.h10
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h
index d9506e27c..4ec1ef866 100644
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ b/arch/powerpc/include/asm/ppc4xx-sdram.h
@@ -63,6 +63,8 @@
#define SDRAM_CFG0 0x20 /* memory controller options 0 */
#define SDRAM_CFG1 0x21 /* memory controller options 1 */
+#define SDRAM0_BESR0 0x0000 /* bus error status reg 0 */
+#define SDRAM0_BESR1 0x0008 /* bus error status reg 1 */
#define SDRAM0_BEAR 0x0010 /* bus error address reg */
#define SDRAM0_SLIO 0x0018 /* ddr sdram slave interface options */
#define SDRAM0_CFG0 0x0020 /* ddr sdram options 0 */
@@ -363,6 +365,7 @@
/*
* Memory controller registers
*/
+#ifdef CONFIG_405EX
#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */
#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */
#define SDRAM_BEARL 0x02 /* PLB bus error address low */
@@ -371,11 +374,10 @@
#define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */
#define SDRAM_PLBOPT 0x08 /* PLB slave options */
#define SDRAM_PUABA 0x09 /* PLB upper address base */
-#ifndef CONFIG_405EX
-#define SDRAM_MCSTAT 0x14 /* memory controller status */
-#else
#define SDRAM_MCSTAT 0x1F /* memory controller status */
-#endif
+#else /* CONFIG_405EX */
+#define SDRAM_MCSTAT 0x14 /* memory controller status */
+#endif /* CONFIG_405EX */
#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */