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authorSrikanth Srinivasan <srikanth.srinivasan@freescale.com>2010-02-10 17:32:43 +0800
committerKumar Gala <galak@kernel.crashing.org>2010-04-26 22:37:51 -0500
commitab48ca1a661b9ab8e3fee9fe2df65432b09ed073 (patch)
tree6ba670c47296df3430c06dd3f80482e808bc0325 /arch/powerpc/include/asm
parent1749c3da8d8445cdf78d70120a803e3e9553113c (diff)
downloadu-boot-linaro-stable-ab48ca1a661b9ab8e3fee9fe2df65432b09ed073.tar.gz
ppc/p4080: Fix synchronous frequency calculations
When DDR is in synchronous mode, the existing code assigns sysclk frequency to DDR frequency. It should be synchronous with the platform frequency. CPU frequency is based on platform frequency in synchronous mode. Also fix: * Fixes the bit mask for DDR_SYNC (RCWSR5[184]) * Corrects the detection of synchronous mode. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm')
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 957ad76a7..dd28e3239 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1697,8 +1697,8 @@ typedef struct ccsr_gur {
u8 res17[24];
u32 rcwsr[16]; /* Reset control word status */
#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
-#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000
-#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15
+#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
+#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000