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authorYork Sun <yorksun@freescale.com>2010-05-07 09:12:01 -0500
committerKumar Gala <galak@kernel.crashing.org>2010-05-12 04:54:30 -0500
commitbcb6c2bb84705bfd73eed5c9a31e9ff24833ee8c (patch)
treebb4f46357fba0cf1dd5a89871215f71c98ae5eca /arch/powerpc/cpu/mpc8xxx
parentf54fe87acedbbad7d29ad18cab31d2b323717514 (diff)
downloadu-boot-linaro-stable-bcb6c2bb84705bfd73eed5c9a31e9ff24833ee8c.tar.gz
Enabled support for Rev 1.3 SPD for DDR2 DIMMs
SPD has minor change from Rev 1.2 to 1.3. This patch enables Rev 1.3. The difference has ben examined and the code is compatible. Speed bins is not verified on hardware for CL7 at this moment. This patch also enables SPD Rev 1.x where x is up to "F". According to SPD spec, the lower nibble is optionally used to determine which additinal bytes or attribute bits have been defined. Software can safely use defaults. However, the upper nibble should always be checked. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx')
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
index d9d0fa70e..dcb37cea1 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
@@ -175,8 +175,8 @@ determine_refresh_rate_ps(const unsigned int spd_refresh)
* ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3
* Not certain if any good value exists for CL=2
*/
- /* CL2 CL3 CL4 CL5 CL6 */
-unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500 };
+ /* CL2 CL3 CL4 CL5 CL6 CL7*/
+unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500, 1875 };
unsigned int
compute_derated_DDR2_CAS_latency(unsigned int mclk_ps)