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authorMichal Simek <monstr@monstr.eu>2010-04-16 12:56:33 +0200
committerMichal Simek <monstr@monstr.eu>2010-04-16 12:56:33 +0200
commit8ff972c6e99938f1a033e5500dccc9a37ce3406f (patch)
tree59fb5422f385e27d04ce3ee6b90cab665ed21626 /arch/microblaze/cpu
parent9b4d90569028604bc491ea419187c31e4467bdca (diff)
downloadu-boot-linaro-stable-8ff972c6e99938f1a033e5500dccc9a37ce3406f.tar.gz
microblaze: Consolidate cache code
Merge cpu and lib cache code. Flush cache before disabling. Signed-off-by: Michal Simek <monstr@monstr.eu>
Diffstat (limited to 'arch/microblaze/cpu')
-rw-r--r--arch/microblaze/cpu/cache.c28
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index 3b7c4d4f7..d258a6938 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -50,6 +50,8 @@ void icache_enable (void) {
}
void icache_disable(void) {
+ /* we are not generate ICACHE size -> flush whole cache */
+ flush_cache(0, 32768);
MSRCLR(0x20);
}
@@ -58,5 +60,31 @@ void dcache_enable (void) {
}
void dcache_disable(void) {
+#ifdef XILINX_USE_DCACHE
+#ifdef XILINX_DCACHE_BYTE_SIZE
+ flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
+#else
+#warning please rebuild BSPs and update configuration
+ flush_cache(0, 32768);
+#endif
+#endif
MSRCLR(0x80);
}
+
+void flush_cache (ulong addr, ulong size)
+{
+ int i;
+ for (i = 0; i < size; i += 4)
+ asm volatile (
+#ifdef CONFIG_ICACHE
+ "wic %0, r0;"
+#endif
+ "nop;"
+#ifdef CONFIG_DCACHE
+ "wdc.flush %0, r0;"
+#endif
+ "nop;"
+ :
+ : "r" (addr + i)
+ : "memory");
+}